Method and apparatus for facilitating alignment of semiconductor devices in integrated circuit package

Abstract

In one embodiment, an apparatus includes a package substrate including a core having a first surface along a first plane and a second surface along a second plane; a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third plane being substantially parallel to the first plane; a first dielectric material disposed on the first surface of the core, the first dielectric material extending into the opening to fill a first gap between a wall of the opening and a side surface of the semiconductor device; and a second dielectric material disposed on the second surface of the core, the second dielectric material extending into the opening to fill a second gap between the second plane and the fourth plane.

Description

Technical Field

[0001] The present disclosure generally relates to semiconductor manufacturing, and more particularly, to methods and apparatuses for facilitating alignment of semiconductor devices in an integrated circuit package. Background Art

[0002] Semiconductor manufacturing is the process used to create integrated circuits, central processing units (CPUs), and many other types of electronic components. Semiconductor manufacturing includes precise control and placement of components within an integrated circuit (IC) package. Brief Description of the Drawings

[0003] Figure 1 An example integrated circuit (IC) package constructed in accordance with the teachings disclosed herein is shown.

[0004] Figure 2 The construction is shown Figure 1 of a first example stage of the construction process of the IC package.

[0005] Figure 3 The construction is shown Figure 1 of a second example stage of the construction process of the IC package.

[0006] Figure 4 The construction is shown Figure 1 of a third example stage of the construction process of the IC package.

[0007] Figure 5 The construction is shown Figure 1 of a fourth example stage of the construction process of the IC package.

[0008] Figure 6 The construction is shown Figure 1 of a fifth example stage of the construction process of the IC package.

[0009] Figure 7 The first example stage of Figure 2 is shown with a first alternative construction configuration.

[0010] Figure 8 The fifth example stage of Figure 6 is shown with a first alternative construction configuration.

[0011] Figure 9 The first example stage of Figure 2 is shown with a second alternative construction configuration.

[0012] Figure 10 The fifth example stage of Figure 6 is shown with a second alternative construction configuration.

[0013] Figure 11is a flowchart showing example operations that may be performed to fabricate an Figure 1 IC package in accordance with the examples disclosed herein.

[0014] Figure 12 is a top view of a wafer including die that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0015] Figure 13 is a cross-sectional side view of an IC device that may be included in an IC package constructed in accordance with the teachings disclosed herein.

[0016] Figure 14 is a cross-sectional side view of an IC device assembly that may include an IC package constructed in accordance with the teachings disclosed herein.

[0017] Figure 15 is a block diagram of an example electrical device that may include an IC package constructed in accordance with the teachings disclosed herein.

[0018] Generally, the same reference numerals will be used throughout the drawings and the accompanying written description to refer to the same or like parts. The drawings are not necessarily to scale. Instead, the thickness of layers or regions may be enlarged in the drawings. Although the drawings show layers and regions with clean lines and boundaries, some or all of these lines and / or boundaries may be idealized. In reality, the boundaries and / or lines may be unobservable, blended, and / or irregular. Detailed Description

[0019] Figure 1 illustrates an example integrated circuit (IC) package 100 constructed in accordance with the teachings disclosed herein. In the illustrated example, the IC package 100 is electrically coupled to a circuit board 102 via an array of contact pads or lands 104 on the mounting surface 105 (e.g., bottom surface) of the package. In some examples, in addition to or instead of the contact pads 104, the IC package 100 may include balls, pins, and / or pads to enable the package 100 to be electrically coupled to the circuit board 102. In this example, the package 100 includes two semiconductor (e.g., silicon) dies 106, 108 (sometimes also referred to as chips or chiplets) that are mounted to a package substrate 110 and enclosed by a package lid or molding compound 112. Thus, the package substrate 110 is an example unit for supporting the semiconductor dies. Although Figure 1 the example IC package 100 includes two dies 106, 108, in other examples, the package 100 may have only one die or more than two dies. In some examples, one of the dies 106, 108 (or a separate die) is embedded in the package substrate 110. The dies 106, 108 may provide any suitable type of functionality (e.g., data processing, memory storage, etc.).

[0020] As shown in the illustrated example, each of die 106, 108 is electrically and mechanically coupled to substrate 110 via an array of corresponding interconnects 114. In Figure 1 it, the interconnects are shown as bumps. However, interconnects 114 can be any other type of electrical connection (e.g., balls, pins, pads, wire bonds, etc.) in addition to or instead of the illustrated bumps. The electrical connection (e.g., interconnect 114) between die 106, 108 and substrate 110 is sometimes referred to as a first-level interconnect. In contrast, the electrical connection (e.g., pad 104) between IC package 100 and circuit board 102 is sometimes referred to as a second-level interconnect. In some examples, one or both of die 106, 108 can be stacked on top of one or more other dies and / or interposers. In such an example, die 106, 108 are coupled to the underlying die and / or interposer via a first set of first-level interconnects, and the underlying die and / or interposer can be connected to package substrate 110 via a separate set of first-level interconnects associated with the underlying die and / or interposer. Thus, as used herein, a first-level interconnect refers to an interconnect (e.g., ball, bump, pin, pad, wire bond, etc.) between a die and a package substrate or between a die and an underlying die and / or interposer.

[0021] As Figure 1 shown, interconnects 114 of the first-level interconnects include two different types of bumps corresponding to core bumps 116 and bridge bumps 118. As used herein, a core bump 116 is a bump on die 106, 108 through which electrical signals are passed between die 106, 108 and components external to IC package 100. More specifically, as shown in the illustrated example, when die 106, 108 are mounted to package substrate 110, core bumps 116 are physically connected and electrically coupled to contact pads 120 on the inner surface 122 of substrate 110. Contact pads 120 on the inner surface 122 of package substrate 110 are electrically coupled via internal interconnects 124 within substrate 110 to pads 104 on the bottom (outer) surface 105 of substrate 110 (e.g., the surface opposite inner surface 122). As a result, there is a continuous electrical signal path between interconnects 114 of die 106, 108 and pads 104 mounted to circuit board 102, and this continuous electrical signal path passes through contact pads 120 and interconnects 124 disposed therebetween.

[0022] As used herein, a bridging bump 118 is a bump on dies 106, 108 through which electrical signals are transferred between different dies among dies 106, 108 within the package 100. Thus, as shown in the illustrated example, the bridging bump 118 of the first die 106 is electrically coupled to the bridging bump 118 of the second die 108 via an interconnect bridge 126 embedded in the package substrate 110. As Figure 1 shown, the die bumps 116 are generally larger than the bridging bumps 118. In some examples, the interconnect bridge 126 and associated bridging bumps 118 are omitted.

[0023] For illustrative purposes, the internal interconnect 124 is shown as a straight line extending directly between the pad 104 on the bottom surface 105 and the contact pad on the inner surface 122. However, in some examples, the internal interconnect 124 is defined by traces or wirings in separate conductive (e.g., metal) layers within a build-up region 128 on one or both sides of a substrate core 130 in the package substrate 110. In such examples, the build-up region 128 includes dielectric layers to separate different conductive layers. In such examples, the traces or wirings in different conductive layers are electrically coupled (to define the complete circuit path of the internal interconnect 124) by conductive (e.g., metal) vias extending between the different conductive layers. Additionally, in some examples, the internal interconnect 124 includes vias extending through the substrate core 130.

[0024] In some examples, the substrate core 130 is an organic substrate or core (e.g., an epoxy-based prepreg layer). In other examples, the substrate core 130 is a glass substrate or core. In some examples, the glass substrate (e.g., glass core 130) includes quartz, fused silica, and / or borosilicate glass. In some examples, the glass substrate (e.g., glass core 130) includes at least 20% (by weight) of each of silicon (Si) and oxygen (O). In other examples, the glass substrate (e.g., glass core 130) includes a greater amount of at least one of silicon or oxygen (e.g., at least 25 wt%, at least 30 wt%, at least 35 wt%, at least 40 wt%, etc.). In some examples, the glass substrate (e.g., glass core 130) includes at least 5% (by weight) of aluminum (Al). According to the present disclosure, the glass substrate (e.g., glass core 130) includes at least one glass layer and does not include epoxy resin and does not include glass fibers (e.g., does not include an epoxy-based prepreg layer having a glass fabric). In some examples, the glass substrate (e.g., glass core 130) corresponds to a monolithic glass extending across the entire height / thickness of the core. In some examples, the glass core 130 has a rectangular shape that substantially coextends in a plan view with the layers above and below the core (e.g., substantially coextends with the stacking region 128). The substrate core 130 (whether an organic core or a glass core) provides stiffness and mechanical support or strength to the encapsulation substrate 110 and the remainder of the package 100. Thus, the substrate core 130 is an example unit for strengthening the encapsulation substrate. In some examples, the thickness of the core 130 is driven by the size (e.g., footprint) of the package 100. For example, in some cases, the larger package 100 includes a substrate 110 having a larger (e.g., thicker) core 130 compared to a smaller package 100 where the core does not need to be as thick.

[0025] As shown in the illustrated example, the substrate core 130 includes a cavity 132, and a semiconductor device 134 is embedded in the cavity 132. In some examples, the semiconductor device 134 is a passive semiconductor die (e.g., a die that does not include transistors). In this example, the semiconductor device 134 is a deep trench capacitor die (also simply referred to herein as a deep trench capacitor). In some such examples, the deep trench capacitor is used to achieve efficient power delivery to a fully integrated voltage regulator within the first die 106 in the IC package 100. In other examples, other types of semiconductor devices may be embedded in the cavity 132 of the substrate core 130 in addition to or instead of the deep trench capacitor. In some examples, more than one semiconductor device 134 may be embedded in the cavity 132 of the substrate core 130. In some examples, the substrate core 130 may include multiple cavities, each cavity containing one or more individual semiconductor devices 134.

[0026] As described above, in this example, the semiconductor device 134 is a deep trench capacitor and will continue to be referred to as such. As shown in the illustrated example, the deep trench capacitor 134 is electrically coupled to the first die 106. In some examples, the deep trench capacitor 134 is positioned adjacent to the first die 106 (e.g., within the substrate core 130 rather than being spaced further apart as in the case of a bond pad side capacitor) to reduce inductance and parasitic effects, thereby increasing the effectiveness of the deep trench capacitor 134 (and / or achieving a given capacitance with a smaller sized capacitor). However, the challenge of embedding the deep trench capacitor 134 within the core 130 of the substrate stems from the thickness mismatch between the deep trench capacitor 134 and the core 130. In this example, the deep trench capacitor 134 is constructed from a semiconductor (e.g., silicon) wafer through wafer-level processing. Due to the nature of this wafer-level processing, the deep trench capacitor 134 has a thickness 136 that is limited to be less than or equal to approximately 800 micrometers (μm) or less (e.g., less than or equal to approximately 700μm, less than or equal to approximately 650μm, less than or equal to approximately 600μm, etc.). In contrast, the substrate core 130 can be much thicker, especially for larger packages as described above. For example, in some examples, the core 130 has a thickness 138 that is at least 20% or more greater than the thickness 136 of the deep trench capacitor 134 (e.g., at least 25% greater, at least 30% greater, at least 50% greater, at least 75% greater, at least twice as great, etc.). More specifically, in some examples, the thickness 138 of the core 130 is greater than approximately 800μm or more (e.g., greater than or equal to approximately 1 millimeter (mm) (e.g., 1000μm), greater than or equal to approximately 1.2mm, greater than or equal to approximately 1.4mm, greater than or equal to approximately 1.5mm, etc.). Thus, as Figure 1 shown, the thickness 136 of the deep trench capacitor 134 is less than the thickness 138 of the core 130.

[0027] The mismatch between the thicknesses 136, 138 of the deep trench capacitor 134 and the core 130 presents challenges in positioning the deep trench capacitor 134 within the cavity 132 of the core 130. Specifically, due to the difficulty of fixing the deep trench capacitor in place, the relatively small size of the deep trench capacitor 134 may result in misalignment and / or rotational displacement or tilt in any of the x, y, and z axes. In particular, it may be difficult to hold the deep trench capacitor 134 in place using adhesives and / or sealants because of the large space within the cavity 132 that needs to be filled, which may take time to solidify or cure during which the deep trench capacitor 134 may shift, rotate, or otherwise move. As a result, the contact surface 140 of the deep trench capacitor 134 (e.g., the surface containing the contacts by which the deep trench capacitor 134 is electrically coupled to (and faces) the first die 106) may not be aligned (e.g., flush) with the corresponding surface 142 of the substrate core 130 (which also faces the first die 106). Such misalignment may negatively impact the ability of the deep trench capacitor 134 to make electrical connections to the interconnections within the stacking region 128 above the core 130. Additionally, non-uniformity of the materials within the cavity 132 (e.g., the deep trench capacitor 134 and a relatively large volume of adhesive and / or sealant) may create processing challenges downstream and / or increase the risk of warping and / or mechanical stress in the packaged substrate 110.

[0028] The examples disclosed herein overcome the above challenges by providing spacers, pedestals, or other structures to fill most of the space within the cavity 132 and support the deep trench capacitor at a suitable height and in a suitable position relative to the substrate core 130. The examples disclosed herein allow for the removal of the spacers, pedestals, or other structures after the deep trench capacitor 134 has been placed / aligned relative to the substrate core 130. That is, in some examples, the spacer or pedestal is a temporary structure used during the manufacture of the integrated circuit package and is subsequently removed once the deep trench capacitor 134 has been fixed in place by other means (e.g., an adhesive or molding material that at least partially surrounds the deep trench capacitor 134).

[0029] Figure 2 A first example stage 200 of the build process of the IC package 100 is shown. The first example stage 200 includes Figure 1 a deep trench capacitor 134 that is positioned on a carrier 210 having a pedestal 220 (e.g., a spacer, a platform, etc.). In Figure 1 the Figure 2In the example, the base 220 is on the carrier 210, and the deep trench capacitor 134 abuts the base 220. In some examples disclosed herein, the base 220 is an integral extension of the carrier 210 or a protrusion on the carrier 210 (e.g., the base 220 is integrally coupled to the carrier 210). In other examples, the base 220 is different from the carrier and is attached to the carrier (e.g., via an adhesive).

[0030] In the examples disclosed herein, the carrier 210 is made of glass, silicon (Si), metal (e.g., aluminum, steel, etc.), ceramic, or any combination or derivative thereof. In some examples, the base 220 is made of the same material as the carrier 210. In other examples, the base 220 is made of a material different from the carrier 210. The base 220 is designed / sized to support the deep trench capacitor 134 to facilitate alignment of the deep trench capacitor 134 with Figure 1 other components in the IC package 100. More specifically, as disclosed herein, the base 220 facilitates alignment of the deep trench capacitor 134 with other components within the IC package 100 to reduce or eliminate misalignment caused by manual or imprecise placement of semiconductor devices within the IC package 100. Specifically, as discussed further below, the deep trench capacitor 134 may be placed on or supported by the base 220, which is sized (e.g., has a thickness) such that a first semiconductor device surface 240 (e.g., facing outward) of the deep trench capacitor 134 is aligned with a corresponding (e.g., adjacent) surface of the substrate core 130.

[0031] Figure 2 The deep trench capacitor 134 includes one or more contact pads 230 on the first semiconductor device surface 240. In some examples, the (one or more) contact pads 230 are included on the deep trench capacitor 134 to enable an electrical connection between the first die 106 (or in some examples, the second die 108) and the deep trench capacitor 134 (as discussed in connection with Figure 1 ). In Figure 2 the illustrated example, the (one or more) contact pads 230 are embedded within the deep trench capacitor 134 such that an outward-facing surface of the (one or more) contact pads is substantially flush with the first semiconductor device surface 240. In some examples, the (one or more) contact pads 230 are recessed relative to the first semiconductor device surface 240. In some examples, the (one or more) contact pads 230 protrude outward from the first semiconductor device surface 240. In Figure 2 the example, the deep trench capacitor 134 includes two contact pads 230, but it should be understood that the deep trench capacitor 134 may include any suitable number of contact pads 230.

[0032] Figure 2The deep trench capacitor 134 includes a second semiconductor device surface 250 opposite the first semiconductor device surface 240. The first semiconductor device surface 240 includes (one or more) contact pads 230 and faces the dies 106, 108 (e.g., once the IC package 100 is fully assembled). The first semiconductor device surface 240 defines a first semiconductor device plane 241.

[0033] The second semiconductor device surface 250 faces the base 220 (e.g., during assembly and prior to subsequent removal of the base 220). The second semiconductor device surface 250 defines a second semiconductor device plane 251. In some examples, the first semiconductor device plane 241 is substantially parallel to the second semiconductor device plane 251. As used herein, substantially parallel means within 5 degrees of exact parallelism.

[0034] The base 220 includes a first base surface 252 and side base surfaces 254. In Figure 2 an example, the base 220 includes two side base surfaces 254, each opposite to the other. The second semiconductor device surface 250 docks with the first base surface 252. In some examples, the first base surface 252 extends laterally beyond the second semiconductor device surface 250. In other examples, the first base surface 252 extends laterally up to or less than the boundary or perimeter of the second semiconductor device surface 252.

[0035] In some examples, the second semiconductor device surface 250 is coupled to the base 220 via a debonding film 260 to enable subsequent separation of the base 220 from the deep trench capacitor 134. The debonding film 260 can include, but is not limited to, epoxy resin, dry film, benzocyclobutene (BCB), polyimide, and UV curable compounds. In some examples, the debonding film 260 is positioned on the deep trench capacitor 134 or any additional structure via spin coating, and / or deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD). In some examples, the debonding film 260 is positioned simultaneously along the entire exposed surface of the carrier 210 and the base 220. For example, the debonding film 260 is placed along the first base surface 252, the side base surfaces 254, and the top carrier surface 262. In other examples, the debonding film 260 is positioned to cover components (e.g., the deep trench capacitor 134) located on the carrier 210 and / or the base 220. In such examples, the debonding film 260 will be positioned to the width of the second semiconductor device surface 250 on the first base surface 252.

[0036] Figure 2 The deep trench capacitor 134 further includes a side surface 270. As Figure 2As shown in the example of, the deep trench capacitor 134 includes two side surfaces 270 that face each other. The side surfaces 270 are substantially perpendicular to the first semiconductor device plane 241 and / or the second semiconductor device plane 251. As used herein, substantially perpendicular means within 5 degrees of exact perpendicularity.

[0037] The deep trench capacitor 134 has a capacitor (cap) thickness 280 defined by the first semiconductor device surface 240 and the second semiconductor device surface 250.

[0038] Figure 3 The construction is shown Figure 1 of a second example stage 300 of the construction process of the IC package 100. In Figure 3 the example of, the substrate core 130 is positioned on the carrier 210 such that the pedestal 220 and the deep trench capacitor 134 are positioned within the cavity 132 of the substrate core 130.

[0039] The substrate core 130 includes a first core surface 310 and a second core surface 320. The first core surface 310 faces the dies 106, 108 (e.g., once the IC package 100 is fully assembled). The first core surface 310 defines a first core plane 311 that is substantially parallel to the first semiconductor device plane 241. In some examples, the first core surface 310 is substantially flush with the first semiconductor device surface 240. As used herein, substantially flush means within an angular offset of 5 degrees and / or within a misalignment of 25 microns.

[0040] In some examples, the pedestal 220 is sized to place the first core surface 310 in substantially coplanar alignment with the first semiconductor device surface 240. As used herein, substantially coplanar alignment means substantially parallel and within a linear offset of 25 microns or less (e.g., within 20 microns, within 15 microns, within 10 microns, within 5 microns, etc.).

[0041] The second die surface 320 faces the carrier 210. The second die surface 320 defines a second die plane 321 that is substantially parallel to the second semiconductor device plane 251. In some examples, the second die surface 320 is coupled to the carrier 210 via a release film 260. In some examples, different portions of the release film 260 are deposited on the carrier 210 at different times, which correspond to when different components are positioned on the carrier 210. For example, in some examples, when the deep trench capacitor 134 is positioned and adhered to the base 220, a first portion of the release film 260 is added to the first base surface 252, and when the substrate die 130 is positioned and adhered to the carrier 210, a second portion of the release film 260 is added to the second die surface. In some such examples, the second portion of the release film 260 is limited to the width, footprint, or area of the substrate die 130 along the first carrier surface 262. In some examples, a final portion of the release film 260 can then be placed on the remaining surfaces of the carrier 210 and / or the base 220 (e.g., from the edge of the substrate die 130 along the first carrier surface 262, along the side base surface 254, and along the first base surface 252 to the edge of the deep trench capacitor 134). Thus, in some examples, the release film 260 can be positioned in three stages: a first release film stage corresponding to positioning the deep trench capacitor 134, a second release film stage corresponding to positioning the substrate die 130, and a third release film stage corresponding to positioning the release film 260 on the remaining surfaces of the carrier 210 and the base 220. In the above example, the deep trench capacitor 134 is positioned on the base 220 before the substrate die 130 is positioned on the carrier 210. However, in other examples, the substrate die 130 can be positioned on the carrier 210 before the deep trench capacitor 134 is positioned on the base 220.

[0042] In Figure 3 examples, the substrate die 130 includes a wall 330 corresponding to the cavity 132. The wall 330 faces the base 220 and the side surface 270 of the deep trench capacitor 134.

[0043] In some examples, corresponding to the second example stage 300, the IC package 100 includes a first distance 340 between the side surface 270 and the wall 330 and a second distance 350 between the wall 330 and the side base surface 254. In some examples, the first distance 340 and the second distance 350 are the same. In Figure 3 examples, the first distance 340 and the second distance 350 are different such that the first distance 340 is greater than the second distance 350. In some examples, the base 220 and / or the deep trench capacitor 134 are not centered within the cavity 132 such that the first distance 340 and the second distance 350 are different on different sides of the base 220 and / or the deep trench capacitor 134.

[0044] The first distance 340 defines a first gap 360. The first gap 360 includes portions of the IC package 100 that extend horizontally from the wall 330 of the substrate core 130 to the side surface 270 of the deep trench capacitor 134 and vertically from the first semiconductor device plane 241 (or the first core plane 311) to the second semiconductor device plane 251 (or the first pedestal surface 252).

[0045] The second distance 350 defines a second gap 370. The second gap 370 includes portions of the IC package 100 that extend horizontally from the wall 330 of the substrate core 130 to the side pedestal surface 254 and vertically from the second semiconductor device plane 251 (or the first pedestal surface 252) to the second core plane 321.

[0046] The substrate core 130 has a core thickness 380 defined by a first core surface 310 and a second core surface 320. In some examples, the core thickness 380 is greater than the capacitor thickness 280.

[0047] Figure 4 A construction is shown Figure 1 of a third example stage 400 of the construction process of the IC package 100. In the third example stage, a first dielectric material 410 is disposed on the first surface 310 of the substrate core 130.

[0048] In Figure 4 the example, the first dielectric material 410 is made of a molding compound (sealant), an organic epoxy build-up film, a photoimageable dielectric (PID), silicon dioxide (SiO2), hafnium silicate (HfSiO4), zirconium silicate, or any other suitable dielectric material for encapsulating semiconductor components.

[0049] The first dielectric material 410 is disposed to fill the first gap 360 and the second gap 370. In some examples, the first dielectric material 410 does not completely fill the second gap 370, but partially fills the second gap 370. In some examples, the first dielectric material does not extend into the second gap (e.g., the first dielectric material fills the first gap 360 but not the second gap 370). In some examples, the first dielectric material 410 does not completely fill the first gap 360, but partially fills the first gap 370. In Figure 4In the illustrated example, the first dielectric material 410 has a first lateral thickness equal to the first distance 340 at the first gap 360. The first dielectric material 410 has a second lateral thickness equal to the second distance 350 at the second gap 370. In some examples, the first dielectric material 410 is provided all at once (e.g., continuously). In other examples, the first dielectric material 410 is provided at intervals to form a layer (e.g., provide a first layer, wait for the first layer to dry / cure, and then provide a second / subsequent layer). The first dielectric material 410 is provided to encapsulate the substrate core 130 and / or the deep trench capacitor 134. In some examples, the first dielectric material 410 also defines a first dielectric layer in one of the build-up regions 128 on the first side of the substrate core 130.

[0050] Figure 5 illustrates a construction Figure 1 of a fourth example stage 500 of the build process of the IC package 100. In Figure 5 the example, the pedestal 220 and the carrier 210 are removed from the substrate core 130 and the deep trench capacitor 134. In this example, the first dielectric material 410 holds the position of the deep trench capacitor 134 relative to the substrate core 130. Thus, in some examples, the carrier 210 and the pedestal 220 are not removed until the first dielectric material 410 has solidified, hardened, or cured.

[0051] In some examples, in the case where the release film 260 is used to bond the deep trench capacitor 134 to the pedestal 220 and bond the substrate core 130 to the carrier 210, a release process is required to remove the release film to facilitate the removal of the pedestal 220 and the carrier 210. Examples of release processes that can be used herein to remove the release film 260 include, but are not limited to, a heat source, a laser source, an ultraviolet light source, or a solvent that reacts with the release film to release the film. In some examples, in the case where the release film 260 is not used, no release process is required to remove the pedestal 220 and the carrier 210.

[0052] Figure 6 illustrates a construction Figure 1 of a fifth example stage 600 of the build process of the IC package 100. In Figure 6In the example, the second dielectric material 610 is disposed in the space previously occupied by the carrier 210 and the base 220 to fill the remaining open space in the cavity. Additionally, in some examples, the second dielectric material 610 also defines a first dielectric layer in the stacking region 128 on the second side of the substrate core 130 (opposite to the first stacking region 128 defined by the first dielectric material 410). The second dielectric material 610 may include any of the materials listed above for the first dielectric material 410. In some examples, the second dielectric material 610 is the same material as the first dielectric material 410. In other examples, the second dielectric material 610 is a different material from the first dielectric material 410.

[0053] In Figure 6 the example, the first dielectric material 410 contacts the second dielectric material 610 at an interface 615 corresponding to the position of the surface of the carrier 210 and the base 220 before their removal. In some examples, at least a portion of the interface 615 between the first dielectric material 410 and the second dielectric material 610 extends transversely to the first core surface 310 and the second core surface 320. In some examples, the interface is not observable. In some examples, at least a portion of the interface 615 is substantially coplanar with the second semiconductor device surface 250 of the deep trench capacitor 134.

[0054] In some examples, one or more conductive (e.g., metal) vias 620 are positioned to extend through the first dielectric material 410 to contact the (one or more) contact pads 230 on the deep trench capacitor 134. The conductive vias 620 facilitate connecting the deep trench capacitor 134 to the internal interconnect 124 within the stacking region 128 to achieve electrical coupling with the contact pads 120 and the first die 106, as Figure 1 shown. Although the conductive vias 620 are disclosed in connection with Figure 6 here, the conductive vias 620 can also be added in connection with Figure 4 and / or Figure 5 the example manufacturing stages shown (e.g., the third example stage 400 and / or the fourth example stage 500).

[0055] Figure 7 Illustrates Figure 2 a first alternative build configuration 700 of the first example stage 200 of Figure 7 In the example, the base 220 includes a first base surface 252 and a side base surface 254. The deep trench capacitor 134 includes a first semiconductor device surface 240, a second semiconductor device surface 250, and a side surface 270.

[0056] As Figure 7As shown, the side base surface 254 is aligned with the side surface 270. Accordingly, the width of the base 220 (e.g., the distance from the first base surface 252 to the side base surface 254) is substantially equal to (e.g., within an equal 50 μm) the width of the deep trench capacitor 134 (e.g., the distance from the first semiconductor device surface 240 or the second semiconductor device surface 250 to the side surface 270).

[0057] Figure 8 illustrates Figure 6 a first alternative construction configuration 800 of a fifth exemplary stage 600 of Figure 8 In an example of

[0058] As Figure 8 shown in an example of

[0059] Figure 9 illustrates Figure 2 a second alternative construction configuration 900 of a first exemplary stage 200 of Figure 9 In an example of

[0060] As Figure 9 shown, the side surface 270 of the deep trench capacitor 134 extends laterally beyond the side base surface 254. Accordingly, the width of the base 220 is less than the width of the deep trench capacitor 134.

[0061] Figure 10 illustrates Figure 6 a second alternative construction configuration 1000 of a fifth exemplary stage 600 of Figure 10 In an example of

[0062] As Figure 10 shown in an example of

[0063] In accordance with the teachings of the present disclosure, Figure 2-6 、 Figure 7 and Figure 8 and Figure 9 and Figure 10 the examples shown in Figure 2-10shows alternative configurations that may be required based on the dimensions or operability requirements of the stacking region 128, substrate core 130, or any other component within the IC package 100 based on Figure 1 . Figure 1 Although an example manner of manufacturing the example IC package 100 is shown in ,

[0064] , one or more of the components, processes, and / or apparatuses shown in Figure 11 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner.

[0064] Although Figure 11 an example manner of manufacturing Figure 1 is shown in Figure 11 , Figure 1 , one or more of the components, processes, and / or apparatuses shown in Figure 11 may be combined, divided, rearranged, omitted, eliminated, and / or implemented in any other manner. Figure 11 is a flowchart of an example operation 1100 that may be performed to manufacture the IC package 100 in accordance with the examples disclosed herein. The example operation 1100 of Figure 1 begins at block 1110, where a carrier 210 and a base 220 are provided. In some examples, the carrier 210 and the base 220 are manufactured together and provided as a single piece for aligning semiconductor devices (e.g., deep trench capacitor 134).

[0065] Figure 11 Once the carrier 210 and the base 220 are provided, the substrate core 130 is positioned on the carrier 210 (block 1120). In some examples, the substrate core 130 is positioned first because the substrate core 130 includes an opening / gap (e.g., cavity 132) within which the semiconductor device is positioned. In some examples, a release film 260 is placed at this stage to bond the substrate core 130 to the carrier 210. Figure 1 Once the substrate core 130 is positioned on the carrier 210, the semiconductor device is positioned on the base 220 within the opening / gap in the substrate core 130 (block 1130). In some examples, the semiconductor device is positioned before the substrate core 130. In some examples, a release film 260 is placed at this stage to bond the semiconductor device to the base 220. Figure 11 Once the carrier 210 and the base 220 are provided, the substrate core 130 is positioned on the carrier 210. (block 1120). In some examples, the substrate core 130 is positioned first because the substrate core 130 includes an opening / gap (e.g., cavity 132) within which the semiconductor device is positioned. In some examples, a release film 260 is placed at this stage to bond the substrate core 130 to the carrier 210.

[0066] Once the substrate core 130 is positioned on the carrier 210, the semiconductor device is positioned on the base 220 within the opening / gap in the substrate core 130. (block 1130). In some examples, the semiconductor device is positioned before the substrate core 130. In some examples, a release film 260 is placed at this stage to bond the semiconductor device to the base 220.

[0067] Once the substrate core 130 is positioned on the carrier 210, the semiconductor device is positioned on the base 220 within the opening / gap in the substrate core 130. (block 1130). In some examples, the semiconductor device is positioned before the substrate core 130. In some examples, a release film 260 is placed at this stage to bond the semiconductor device to the base 220.

[0068] Once the substrate core 130 and the semiconductor device have been positioned on the carrier 210 and the pedestal 220, respectively, a first dielectric material 410 is disposed on a first side of the substrate core 130 opposite the carrier 210 (e.g., the first core surface 310). (Block 1140). In some examples, the first dielectric material 410 is disposed to encapsulate the substrate core 130 and the semiconductor device. In some examples, the first dielectric material 410 encapsulates the semiconductor device without encapsulating the substrate core 130. In some examples, the first dielectric material 410 is disposed to serve as a dielectric layer in the build-up region 128 adjacent to the substrate core 130. As disclosed herein, the first dielectric material 410 fills some or all of the first gap 360 and some or all of the second gap 370.

[0069] Once the first dielectric material 410 is disposed, the carrier 210 and the pedestal 220 are removed. (Block 1150). In some examples, when a release film 260 is used, a release process is required to remove the release film 260 to allow removal of the carrier 210 and the pedestal 220. As disclosed above, examples of the release process include a heat source or an ultraviolet light source.

[0070] Once the carrier 210 and the pedestal 220 are removed, a second dielectric material 610 is disposed on a second side of the substrate core exposed by removing the carrier 210 and the pedestal 220 (e.g., the second core surface 320). (Block 1160). In some examples, the second dielectric material 610 is disposed to serve as a dielectric layer within the build-up region 128 on the second side of the substrate core 130. In some examples, the second dielectric material 610 is the same material as the first dielectric material 410. In other examples, the second dielectric material 610 is different from the first dielectric material 410.

[0071] The example IC package 100 disclosed herein can be included in any suitable electronic component. Figure 12-15 Various examples of devices that can include or be included in the IC package 100 disclosed herein are shown.

[0072] Figure 12 can be included in Figure 1Top view of the wafer 1200 and die 1202 (e.g., as any suitable die among die 106, 108) in the IC package 100. The wafer 1200 may be composed of semiconductor material and may include one or more die 1202 having circuitry. Each of the die 1202 may be a repeating unit of a semiconductor product. After the manufacture of the semiconductor product is completed, the wafer 1200 may undergo a singulation process, in which the die 1202 are separated from each other to provide discrete "chips". The die 1202 may include one or more transistors (e.g., some of the Figure 13 transistors 1340 discussed below), support circuitry for transmitting electrical signals to the transistors, passive components (e.g., traces, resistors, capacitors, inductors, and / or other circuitry), and / or any other components. In some examples, the die 1202 may include and / or implement memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive-bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuitry. Multiple of these devices may be combined on a single die 1202. For example, a memory array formed of multiple memory circuits may be formed on the same die 1202 as programmable circuitry (e.g., Figure 15 the processor circuitry 1502) or other logic circuitry. Such memory may store information for use by the programmable circuitry. The example IC package 100 disclosed herein may be manufactured using die-to-wafer assembly techniques, in which some die are attached to a wafer 1200 including other die, and the wafer 1200 is then singulated.

[0073] Figure 13 is a cross-sectional side view of an IC device 1300 (e.g., as any suitable die among die 106, 108) that may be included in the Figure 1 IC package 100. One or more of the IC devices in the IC device 1300 may be included in one or more die 1202 ( Figure 12 ). The IC device 1300 may be formed on a die substrate 1302 (e.g., Figure 12 the wafer 1200), and may be included in a die (e.g., Figure 12into the die 1202). The die substrate 1302 can be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1302 can include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some examples, the die substrate 1302 can be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Other materials classified as Group II-VI, III-V, or IV can also be used to form the die substrate 1302. Although several examples of materials that can form the die substrate 1302 are described herein, any material that can serve as the basis for the IC device 1300 can be used. The die substrate 1302 can be a singulated die (e.g., Figure 12 the die 1202) or a portion of a wafer (e.g., Figure 12 the wafer 1200).

[0074] The IC device 1300 can include one or more device layers 1304 disposed on or above the die substrate 1302. The device layer 1304 can include features of one or more transistors 1340 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1302. The device layer 1304 can include, for example, one or more source and / or drain (S / D) regions 1320, a gate 1322 for controlling the current flow between the S / D regions 1320, and one or more S / D contacts 1324 for transmitting electrical signals to / from the S / D regions 1320. The transistor 1340 can include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1340 is not limited to Figure 13 the type and configuration shown, and can include a wide variety of other types and / or configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors can include FinFET transistors (e.g., double-gate or triple-gate transistors), and surround or all-around gate transistors (e.g., nanoribbon and nanowire transistors).

[0075] Each transistor 1340 may include a gate 1322 formed of at least two layers (a gate dielectric and a gate electrode). The gate dielectric may include one or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, when a high-k material is used, an annealing process may be performed on the gate dielectric to improve its quality.

[0076] The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1340 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some embodiments, the gate electrode may be composed of a stack of two or more metal layers, where one or more of the metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes. For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to NMOS transistors (e.g., for work function adjustment). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to PMOS transistors (e.g., for work function adjustment).

[0077] In some examples, when viewing a cross-section of the transistor 1340 along the source-channel-drain direction, the gate electrode may be composed of a U-shaped structure that includes a bottom portion that is substantially parallel to the surface of the die substrate 1302 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1302. In other examples, at least one of the metal layers forming the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1302 and does not include sidewall portions that are substantially perpendicular to the top surface of the die substrate 1302. In other examples, the gate electrode may be composed of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may be composed of one or more U-shaped metal layers formed on top of one or more planar non-U-shaped layers.

[0078] In some examples, a pair of sidewall spacers that enclose the gate stack may be formed on opposite sides of the gate stack. The sidewall spacers may be formed of materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming the sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, multiple pairs of spacers may be used; for example, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0079] The S / D regions 1320 may be formed in the die substrate 1302 adjacent to the gates 1322 of each transistor 1340. The S / D regions 1320 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopant ions such as boron, aluminum, antimony, phosphorus, or arsenic may be implanted into the die substrate 1302 to form the S / D regions 1320. The ion implantation process may be followed by an annealing process to activate the dopants and cause them to further diffuse into the die substrate 1302. In the latter process, the die substrate 1302 may first be etched to form a recess at the location of the S / D regions 1320. Then, an epitaxial deposition process may be performed to fill the recess with the material used to fabricate the S / D regions 1320. In some embodiments, the S / D regions 1320 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be in-situ doped with a dopant such as boron, arsenic, or phosphorus. In some examples, the S / D regions 1320 may be formed using one or more alternative semiconductor materials, such as germanium or III-V materials or alloys. In further examples, the S / D regions 1320 may be formed using one or more layers of metal and / or metal alloy.

[0080] Electrical signals such as power and / or input / output (I / O) signals may be transmitted to and / or from the devices (e.g., transistors 1340) of the device layer 1304 via one or more interconnect layers (shown as interconnect layers 1306 - 1310 in Figure 13 ). For example, the conductive features (e.g., gates 1322 and S / D contacts 1324) of the device layer 1304 may be electrically coupled to the interconnect structures 1328 of the interconnect layers 1306 - 1310. One or more interconnect layers 1306 - 1310 may form the metallization stack (also referred to as the "ILD stack") 1319 of the IC device 1300.

[0081] The interconnect structures 1328 may be arranged within the interconnect layers 1306 - 1310 to transmit electrical signals according to various designs (in particular, the arrangement is not limited to Figure 13 the specific configuration of the interconnect structures 1328 shown in Figure 13A specific number of interconnect layers 1306 - 1310 are shown, but examples of the present disclosure include IC devices having more or fewer interconnect layers than shown.

[0082] In some examples, the interconnect structure 1328 may include wires 1328a and / or vias 1328b filled with a conductive material such as metal. The wires 1328a may be arranged to transmit electrical signals in a direction substantially parallel to the plane of the surface of the die substrate 1302 on which the device layer 1304 is formed. For example, the wires 1328a may transmit electrical signals in a direction in and out of the page from Figure 13 the perspective shown. The vias 1328b may be arranged to transmit electrical signals in a direction substantially perpendicular to the plane of the surface of the die substrate 1302 on which the device layer 1304 is formed. In some examples, the vias 1328b may electrically couple the wires 1328a of different interconnect layers 1306 - 1310 together.

[0083] The interconnect layers 1306 - 1310 may include a dielectric material 1326 disposed between the interconnect structures 1328, as Figure 13 shown. In some examples, the dielectric material 1326 disposed between the interconnect structures 1328 in different interconnect layers within the interconnect layers 1306 - 1310 may have different compositions; in other examples, the composition of the dielectric material 1326 between the different interconnect layers 1306 - 1310 may be the same.

[0084] The first interconnect layer 1306 (referred to as metal 1 or “M1”) may be formed directly on the device layer 1304. In some examples, the first interconnect layer 1306 may include wires 1328a and / or vias 1328b, as shown. The wires 1328a of the first interconnect layer 1306 may be coupled to the contacts (e.g., S / D contacts 1324) of the device layer 1304.

[0085] The second interconnect layer 1308 (referred to as metal 2 or “M2”) may be formed directly on the first interconnect layer 1306. In some examples, the second interconnect layer 1308 may include vias 1328b to couple the wires 1328a of the second interconnect layer 1308 to the wires 1328a of the first interconnect layer 1306. Although, for clarity, the wires 1328a and vias 1328b are depicted as wires within each interconnect layer (e.g., within the second interconnect layer 1308), in some examples, the wires 1328a and vias 1328b may be structurally and / or materially continuous (e.g., filled simultaneously during a dual - damascene process).

[0086] In accordance with similar techniques and configurations described in connection with the second interconnect layer 1308 or the first interconnect layer 1306, a third interconnect layer 1310 (referred to as metal 3 or “M3”) (and additional interconnect layers as needed) can be successively formed on the second interconnect layer 1308. In some examples, the “higher” (i.e., further from the device layer 1304) interconnect layers in the metallization stack 1319 in the IC device 1300 can be thicker.

[0087] The IC device 1300 can include a solder mask material 1334 (such as polyimide or a similar material) and one or more conductive contacts 1336 formed on the interconnect layers 1306 - 1310. In Figure 13 the, the conductive contacts 1336 are shown in the form of bond pads. The conductive contacts 1336 can be electrically coupled to the interconnect structure 1328 and are configured to transfer electrical signals of the (one or more) transistors 1340 to other external devices. For example, solder joints can be formed on one or more conductive contacts 1336 to mechanically and / or electrically couple the chip including the IC device 1300 to another component (such as a circuit board). The IC device 1300 can include additional or alternative structures to transfer electrical signals from the interconnect layers 1306 - 1310; for example, the conductive contacts 1336 can include other similar features (such as pillars) that transfer electrical signals to external components.

[0088] Figure 14 is a cross-sectional side view of an IC device assembly 1400 that can include the IC package 100 disclosed herein. In some examples, the IC device assembly corresponds to the IC package 100. The IC device assembly 1400 includes a plurality of components disposed on a circuit board 1402 (which can be, for example, a motherboard). The IC device assembly 1400 includes components disposed on a first side 1440 of the circuit board 1402 and an opposite second side 1442 of the circuit board 1402; generally, components can be disposed on one or both sides 1440 and 1442. Any IC package discussed below with reference to the IC device assembly 1400 can take the form of Figure 1 the example IC package 100.

[0089] In some examples, the circuit board 1402 can be a printed circuit board (PCB) including a plurality of metal layers separated from each other by dielectric material layers and interconnected by conductive vias. Any one or more of the metal layers can be formed in a desired circuit pattern to transfer electrical signals (optionally in combination with other metal layers) between components coupled to the circuit board 1402. In other examples, the circuit board 1402 can be a non-PCB substrate.

[0090] Figure 14The IC device component 1400 shown in [description] includes a package-on-interposer structure 1436 coupled to the first surface 1440 of the circuit board 1402 through a coupling component 1416. The coupling component 1416 can electrically and mechanically couple the package-on-interposer structure 1436 to the circuit board 1402 and can include solder balls (such as Figure 14 shown), protruding and recessed parts of the socket, adhesives, underfill materials, and / or any other suitable electrical and / or mechanical coupling structures.

[0091] The package-on-interposer structure 1436 can include an IC package 1420 coupled to the interposer 1404 through a coupling component 1418. The coupling component 1418 can take any appropriate form for the application, such as the form discussed above with reference to the coupling component 1416. Although Figure 14 a single IC package 1420 is shown, multiple IC packages can be coupled to the interposer 1404; in fact, additional interposers can be coupled to the interposer 1404. The interposer 1404 can provide an intermediate substrate for bridging the circuit board 1402 and the IC package 1420. The IC package 1420 can be or include, for example, a die ( Figure 12 die 1202), an IC device (e.g., Figure 13 IC device 1300), or any other suitable component. Generally, the interposer 1404 can extend the connections to a wider pitch or re-route the connections to different connections. For example, the interposer 1404 can couple the IC package 1420 (e.g., a die) to a set of BGA conductive contacts of the coupling component 1416 for coupling to the circuit board 1402. In Figure 14 the example shown, the IC package 1420 and the circuit board 1402 are attached to opposite sides of the interposer 1404; in other examples, the IC package 1420 and the circuit board 1402 can be attached to the same side of the interposer 1404. In some examples, three or more components can be interconnected through the interposer 1404.

[0092] In some examples, the interposer 1404 can be formed as a PCB, including multiple metal layers separated from each other by dielectric material layers and interconnected by conductive vias. In some examples, the interposer 1404 can be formed of epoxy resin, fiberglass-reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic materials, or polymer materials such as polyimide. In some examples, the interposer 1404 can be formed of alternating rigid or flexible materials, which can include the same materials as those used for semiconductor substrates above, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1404 can include metal interconnects 1408, as well as vias 1410, including but not limited to through-silicon vias (TSVs) 1406. The interposer 1404 can further include embedded devices 1414, including both passive and active devices. These devices can include but are not limited to capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices can also be formed on the interposer 1404. The package-on-interposer structure 1436 can take the form of any package-on-interposer structure known in the art.

[0093] The IC device assembly 1400 can include an IC package 1424 coupled to the first face 1440 of the circuit board 1402 through a coupling component 1422. The coupling component 1422 can take the form of any example discussed above with reference to the coupling component 1416, and the IC package 1424 can take the form of any example discussed above with reference to the IC package 1420.

[0094] Figure 14 The IC device assembly 1400 shown in includes a package-on-package structure 1434 coupled to the second face 1442 of the circuit board 1402 through a coupling component 1428. The package-on-package structure 1434 can include a first IC package 1426 and a second IC package 1432 coupled together through a coupling component 1430, such that the first IC package 1426 is disposed between the circuit board 1402 and the second IC package 1432. The coupling components 1428, 1430 can take the form of any example of the coupling component 1416 discussed above, and the IC packages 1426, 1432 can take the form of any example of the IC package 1420 discussed above. The package-on-package structure 1434 can be configured according to any package-on-package structure known in the art.

[0095] Figure 15is a block diagram of an example electrical device 1500 that may include one or more example IC packages 100. For example, any suitable components of the components of the electrical device 1500 may include one or more of the device components 1400, IC devices 1300, or dies 1202 disclosed herein and may be arranged in the example IC package 100. Multiple components are shown in Figure 15 as being included in the electrical device 1500, but any one or more of these components may be omitted or duplicated to suit the application. In some examples, some or all of the components included in the electrical device 1500 may be attached to one or more motherboards. In some examples, some or all of these components are fabricated on a single system-on-chip (SoC) die.

[0096] Additionally, in various examples, the electrical device 1500 may not include Figure 15 one or more of the components shown in, but the electrical device 1500 may include interface circuitry for coupling to one or more components. For example, the electrical device 1500 may not include the display 1506, but may include display interface circuitry (e.g., connectors and driver circuitry) to which the display 1506 may be coupled. In another set of examples, the electrical device 1500 may not include the audio input device 1518 (e.g., microphone) or the audio output device 1508 (e.g., speaker, headphones, earbuds, etc.), but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1518 or the audio output device 1508 may be coupled.

[0097] The electrical device 1500 may include programmable circuitry 1502 (e.g., one or more processing devices). The programmable circuitry 1502 may include one or more digital signal processors (DSPs), application specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptographic processors (specialized processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing device. The electrical device 1500 may include a memory 1504, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or hard disk drives. In some examples, the memory 1504 may include a memory that shares a die with the programmable circuitry 1502. This memory may be used as a cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).

[0098] In some examples, the electrical device 1500 may include a communication chip 1512 (e.g., one or more communication chips). For example, the communication chip 1512 may be configured to manage wireless communication for transmitting data to and from the electrical device 1500. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc. that can communicate data by using modulated electromagnetic radiation via a non-solid medium. The term does not mean that the associated devices do not contain any wires, although in some examples they may not contain any wires.

[0099] The communication chip 1512 may implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), Long Term Evolution (LTE) project, and any revisions, updates, and / or amendments thereof (e.g., LTE-Advanced project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks that are compatible with IEEE 802.16 are commonly referred to as WiMAX networks (which is an acronym for Worldwide Interoperability for Microwave Access), and the WiMAX network is a certification mark for products that have passed the compliance and interoperability tests of the IEEE 802.16 standard. The communication chip 1512 may operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1512 may operate according to Enhanced Data GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1512 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO) and its derivatives, and any other wireless protocols designated as 3G, 4G, 5G, and above. In other examples, the communication chip 1512 may operate according to other wireless protocols. The electrical device 1500 may include an antenna 1522 to facilitate wireless communication and / or receive other wireless communications (e.g., AM or FM radio transmissions).

[0100] In some examples, the communication chip 1512 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 1512 may include multiple communication chips. For example, a first communication chip 1512 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1512 may be dedicated to long-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, the first communication chip 1512 may be dedicated to wireless communications, and the second communication chip 1512 may be dedicated to wired communications.

[0101] The electrical device 1500 may include a battery / power circuitry 1514. The battery / power circuitry 1514 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1500 to an energy source (e.g., AC line power) separate from the electrical device 1500.

[0102] The electrical device 1500 may include a display 1506 (or corresponding interface circuitry, as discussed above). The display 1506 may include any visual indicator, such as a heads-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0103] The electrical device 1500 may include an audio output device 1508 (or corresponding interface circuitry, as discussed above). The audio output device 1508 may include any device that generates an audible indicator, such as a speaker, headphones, or earbuds.

[0104] The electrical device 1500 may include an audio input device 1518 (or corresponding interface circuitry, as discussed above). The audio input device 1518 may include any device that produces a signal representative of sound, such as a microphone, microphone array, or digital musical instrument (e.g., an instrument having a Musical Instrument Digital Interface (MIDI) output).

[0105] The electrical device 1500 may include a GPS circuitry 1516. The GPS circuitry 1516 may communicate with a satellite-based system and may receive the location of the electrical device 1500, as is known in the art.

[0106] The electrical device 1500 may include any other output device 1510 (or corresponding interface circuitry, as discussed above). Examples of other output devices 1510 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0107] The electrical device 1500 may include any other input device 1520 (or corresponding interface circuitry, as discussed above). Examples of other input devices 1520 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0108] The electrical device 1500 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a cellular phone, a smartphone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a ultrabook computer, a personal digital assistant (PDA), a ultra-mobile personal computer, etc.), a desktop electrical device, a server, or other networked computing components, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1500 may be any other electronic device that processes data.

[0109] "Including" and "comprising" (and all of their forms and tenses) are used herein as open-ended terms. Thus, whenever a claim employs any form of "include" or "comprise" (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within any kind of claim recitation, it should be understood that additional elements, terms, etc. may exist without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase "at least" is used as a transitional term in, for example, the preamble of a claim, it is open-ended in the same manner as the terms "comprising" and "including" are open-ended. When used in the form of, for example, A, B, and / or C, the term "and / or" means any combination or subset of A, B, C, such as (1) A alone, (2) B alone, (3) C alone, (4) A and B, (5) A and C, (6) B and C, or (7) A and B and C. As used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A and B" is intended to refer to embodiments that include any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing a structure, component, item, object, and / or thing, the phrase "at least one of A or B" is intended to refer to embodiments that include any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A and B" is intended to refer to embodiments that include any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of a process, instruction, action, activity, etc., the phrase "at least one of A or B" is intended to refer to embodiments that include any one of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0110] As used herein, singular references (e.g., "a", "an", "first", "second", etc.) do not exclude a plurality. As used herein, the term "a" or "an" object refers to one or more of such objects. The terms "a" (or "an"), "one or more", and "at least one" are used interchangeably herein. Additionally, although listed separately, multiple units, elements, or acts may be implemented by, for example, the same entity or object. Further, although individual features may be included in different examples or claims, these features may be combined, and inclusion in different examples or claims does not imply that the combination of features is not feasible and / or not advantageous.

[0111] As used herein, unless otherwise specified, the term "above" describes the relationship of two parts relative to the ground. If there is at least one part between the second part and the ground and the first part, the first part is above the second part. Similarly, as used herein, when the first part is closer to the ground than the second part, the first part is "below" the second part. As described above, in one or more cases where there are other parts therebetween, no other parts therebetween, the first and second parts are in contact, or the first and second parts are not in direct contact with each other, the first part may be above or below the second part.

[0112] Notwithstanding this, in the context of manufacturing or fabricating a semiconductor device (e.g., a transistor), a semiconductor die containing the semiconductor device, and / or an integrated circuit (IC) package containing the semiconductor die, "above" is not referenced to the ground, but to the underlying substrate on which the relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein, and unless the context otherwise indicates or implies, when a first component (e.g., a transistor or other semiconductor device) within a semiconductor die is further from the substrate (e.g., a semiconductor wafer) on which the two components are fabricated or otherwise provided during production / fabrication than a second component within the semiconductor die, the first component is "above" the second component. Similarly, unless the context otherwise indicates or implies, during fabrication, when a first component (e.g., a semiconductor die) within an IC package is further from the printed circuit board (PCB) to which the IC package is to be mounted or attached, the first component is "above" the second component within the IC package. It should be understood that semiconductor devices are typically used in an orientation different from their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing the semiconductor device, and / or an integrated circuit (IC) package during use, the definition of "above" in the previous paragraph (i.e., the term "above" describes the relationship of two parts relative to the ground) will likely be determined based on the context of use.

[0113] As used in this patent, stating that any part (e.g., a layer, film, region, zone, or plate) is on another part in any way (e.g., positioned on another part, located on another part, disposed on another part, or formed on another part, etc.) indicates that the part so mentioned is in contact with the other part, or that the part so mentioned is above the other part, with one or more intermediate parts therebetween.

[0114] As used herein, unless otherwise specified, connection references (e.g., attach, couple, connect, and join) can include intermediate members between the elements referenced by the connection reference and / or relative movement between these elements. Thus, a connection reference does not necessarily infer that the two elements are directly connected and / or in a fixed relationship with each other. As used herein, a statement that any part is "in contact" with another part is defined to mean that there is no intermediate part between the two parts.

[0115] Unless otherwise specifically stated, descriptors such as "first", "second", "third", etc. used herein do not import or otherwise indicate any meaning of priority, physical order, arrangement in a list, and / or ordering in any way, but are merely used as labels and / or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor "first" may be used to refer to an element in a detailed description, while the same element may be referred to by a different descriptor such as "second" or "third" in the claims. In such cases, it should be understood that such descriptors are only used to clearly identify those elements within the context of the discussion (e.g., within the claims), where the elements may, for example, otherwise share the same name.

[0116] As used herein, the phrase "communicate" (including its variants) encompasses direct communication and / or indirect communication through one or more intermediate components, and does not require direct physical (e.g., wired) communication and / or constant communication, but additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and / or one-time events.

[0117] As used herein, "programmable circuitry" is defined to include (i) one or more dedicated circuits (e.g., application specific integrated circuits (ASICs)) that are configured to perform one or more specific operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and / or (ii) one or more general-purpose semiconductor-based circuits that can be programmed with instructions to perform one or more specific functions and / or operations and include one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as a central processing unit (CPU) that can execute a first instruction to perform one or more operations and / or functions; a field programmable gate array (FPGA) that can be programmed with a second instruction to cause the configuration and / or fabric of the FPGA to instantiate one or more operations and / or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations and / or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations and / or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations and / or functions; and / or an integrated circuit such as an application specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and / or any combination thereof), and an orchestration technique (e.g., one or more application programming interfaces (APIs)) that can allocate one or more computing tasks to one or more programmable circuitry of the multiple types of programmable circuitry that are suitable and available to perform the one or more computing tasks.

[0118] As used herein, an integrated circuit / circuitry is defined as one or more semiconductor packages that contain one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate that couples multiple circuit elements, a system on a chip (SoC), etc.

[0119] From the foregoing, it will be appreciated that example systems, devices, articles, and methods for improving semiconductor device alignment in integrated circuit packages have been disclosed. The disclosed systems, devices, articles, and methods provide for reducing or eliminating misalignment of semiconductor devices within an IC package to improve performance and consistency in the manufacture of the IC package.

[0120] This disclosure relates to example methods, apparatuses, systems, and articles for facilitating alignment of semiconductor devices in integrated circuit packages. Further examples and combinations thereof include the following:

[0121] Example 1 includes a package substrate that includes: a core having a first surface along a first plane and a second surface along a second plane, the second surface being opposite the first surface; a semiconductor device disposed within an opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third surface being opposite the fourth surface, the third plane being substantially parallel to the first plane; a first dielectric material disposed on the first surface of the core, the first dielectric material extending into the opening to fill a first gap between the walls of the opening and a side surface of the semiconductor device; and a second dielectric material disposed on the second surface of the core, the second dielectric material extending into the opening to fill a second gap between the second plane and the fourth plane.

[0122] Example 2 includes the package substrate of Example 1, wherein the semiconductor device includes a deep trench capacitor.

[0123] Example 3 includes the package substrate of Example 1, wherein the first dielectric material contacts the second dielectric material.

[0124] Example 4 includes the package substrate of Example 1, wherein a first portion of the first dielectric material extends a first distance between the first plane and the second plane, and a second portion of the first dielectric material extends a second distance between the first plane and the second plane, the second distance being less than the first distance.

[0125] Example 5 includes the package substrate of Example 4, wherein the first portion of the first dielectric material extends along the walls of the opening, and the second portion of the first dielectric material extends along the side surface of the semiconductor device.

[0126] Example 6 includes the package substrate of Example 5, wherein the first distance extends from the first plane to the second plane, and the second distance extends from the first plane to the fourth plane.

[0127] Example 7 includes the package substrate of Example 1, wherein the fourth plane is between the first plane and the second plane, and the first dielectric material extends into the opening beyond the fourth plane by a distance.

[0128] Example 8 includes the encapsulated substrate of Example 7, wherein the first dielectric material has a first lateral thickness between the first plane and the fourth plane and a second lateral thickness between the second plane and the fourth plane, and the second lateral thickness is equal to or greater than the first lateral thickness.

[0129] Example 9 includes the encapsulated substrate of Example 1, wherein the first dielectric material and the second dielectric material are the same material.

[0130] Example 10 includes the encapsulated substrate of Example 1, wherein the first dielectric material is different from the second dielectric material.

[0131] Example 11 includes an integrated circuit package, comprising a core having a first thickness defined by a first surface and a second surface of the core; a deep trench capacitor disposed in an opening in the core, the deep trench capacitor having a second thickness defined by a third surface and a fourth surface of the deep trench capacitor, the second thickness being less than the first thickness, the third surface of the deep trench capacitor being substantially flush with the first surface of the core; and a first dielectric material disposed on the first surface of the core and the third surface of the deep trench capacitor, the first dielectric material extending along a side surface of the deep trench capacitor into the opening, the first dielectric material for mechanically coupling the deep trench capacitor to the core.

[0132] Example 12 includes the integrated circuit package of Example 11, further comprising a second dielectric material disposed on the second surface of the core and the fourth surface of the deep trench capacitor.

[0133] Example 13 includes the integrated circuit package of Example 12, wherein the first dielectric material contacts the second dielectric material.

[0134] Example 14 includes the integrated circuit package of Example 13, wherein the first dielectric material contacts the second dielectric material along an interface, and a first portion of the interface extends in a first direction transverse to the first surface and the second surface of the core.

[0135] Example 15 includes the integrated circuit package of Example 14, wherein a second portion of the interface extends in a second direction substantially coplanar with the fourth surface of the deep trench capacitor.

[0136] Example 16 includes a method comprising: positioning a core on a carrier, the carrier including a base extending into an opening in the core, the core having a first surface facing away from the carrier and a second surface facing the carrier; positioning a semiconductor device on the base, the semiconductor device having a third surface facing away from the base and a fourth surface facing the base, the base sized to place the third surface of the semiconductor device in substantially coplanar alignment with the first surface of the core; depositing a first dielectric material on the first surface of the core and the third surface of the semiconductor device, the first dielectric material extending into the opening to at least partially cover side surfaces of the semiconductor device and contact the base; and removing the carrier and the base, after removing the carrier and the base, the first dielectric material maintaining the semiconductor device in place relative to the core.

[0137] Example 17 includes the method of Example 16, further comprising depositing a second dielectric material on the second surface of the core, the second dielectric material extending into a gap in the opening, the gap created by removing the base from within the opening.

[0138] Example 18 includes the method of Example 16, further comprising providing release films between the carrier and the core and between the base and the semiconductor device, the release films facilitating removal of the carrier and the base.

[0139] Example 19 includes the method of Example 18, further comprising providing a release film on a surface of at least one of the carrier or the base that is exposed within the opening and spaced apart from the semiconductor device.

[0140] Example 20 includes the method of Example 16, wherein the base is an integral extension of the carrier.

[0141] Example 21 includes the method of Example 16, wherein positioning of the semiconductor device on the base is completed before the core is positioned on the carrier.

[0142] The appended claims are hereby incorporated by reference into this detailed description. Although certain example systems, devices, articles of manufacture, and methods have been disclosed herein, the scope of this patent is not limited thereto. On the contrary, this patent covers all systems, devices, articles of manufacture, and methods that fall entirely within the scope of the claims of this patent.

Claims

1. A packaging substrate, comprising: a core having a first surface along a first plane and a second surface along a second plane, the second surface being opposite to the first surface; a semiconductor device disposed within the opening in the core, the semiconductor device having a third surface along a third plane and a fourth surface along a fourth plane, the third surface being opposite the fourth surface, the third plane being substantially parallel to the first plane; a first dielectric material disposed on the first surface of the core, the first dielectric material extending into the opening to fill a first gap between a wall of the opening and a side surface of the semiconductor device; as well as A second dielectric material is disposed on the second surface of the core, the second dielectric material extending into the opening to fill a second gap between the second plane and the fourth plane.

2. The packaging substrate according to claim 1, wherein: The semiconductor device includes a deep trench capacitor.

3. The packaging substrate according to claim 1, wherein: The first dielectric material is in contact with the second dielectric material.

4. The packaging substrate according to claim 1, wherein: A first portion of the first dielectric material extends a first distance between the first plane and the second plane, and a second portion of the first dielectric material extends a second distance between the first plane and the second plane, the second distance being less than the first distance.

5. The packaging substrate according to claim 4, wherein: The first portion of the first dielectric material extends along a wall of the opening, and the second portion of the first dielectric material extends along the side surface of the semiconductor device.

6. The packaging substrate according to claim 5, wherein: The first distance extends from the first plane to the second plane, and the second distance extends from the first plane to the fourth plane.

7. A packaging substrate according to any preceding claim, wherein: The fourth plane is between the first plane and the second plane, and the first dielectric material extends into the opening a distance beyond the fourth plane.

8. The packaging substrate according to claim 7, wherein: The first dielectric material has a first lateral thickness between the first plane and the fourth plane and a second lateral thickness between the second plane and the fourth plane, the second lateral thickness being equal to or greater than the first lateral thickness.

9. The packaging substrate according to any one of claims 1 to 6, wherein: The first dielectric material and the second dielectric material are the same material.

10. The packaging substrate according to any one of claims 1 to 6, wherein: The first dielectric material is different from the second dielectric material.

11. An integrated circuit package, comprising: a core having a first thickness defined by a first surface and a second surface of the core; a deep trench capacitor disposed within the opening in the core, the deep trench capacitor having a second thickness defined by a third surface and a fourth surface of the deep trench capacitor, the second thickness being less than the first thickness, the third surface of the deep trench capacitor being substantially flush with the first surface of the core; as well as A first dielectric material is disposed on the first surface of the core and the third surface of the deep trench capacitor, the first dielectric material extends into the opening along a side surface of the deep trench capacitor, and the first dielectric material is used to mechanically couple the deep trench capacitor to the core.

12. The integrated circuit package of claim 11, further comprising a second dielectric material disposed on the second surface of the core and the fourth surface of the deep trench capacitor.

13. The integrated circuit package of claim 12, wherein: The first dielectric material is in contact with the second dielectric material.

14. The integrated circuit package of claim 13, wherein: The first dielectric material contacts the second dielectric material along an interface, a first portion of the interface extending in a first direction transverse to the first and second surfaces of the core.

15. The integrated circuit package of claim 14, wherein: A second portion of the interface extends in a second direction that is substantially coplanar with the fourth surface of the deep trench capacitor.

16. A method comprising: positioning a core on a carrier, the carrier comprising a base extending into an opening in the core, the core having a first surface facing away from the carrier and a second surface facing the carrier; positioning a semiconductor device on the pedestal, the semiconductor device having a third surface facing away from the pedestal and a fourth surface facing the pedestal, the pedestal being sized to place the third surface of the semiconductor device in substantially coplanar alignment with the first surface of the core; depositing a first dielectric material on the first surface of the core and the third surface of the semiconductor device, the first dielectric material extending into the opening to at least partially cover side surfaces of the semiconductor device and contact the pedestal; as well as The carrier and the pedestal are removed, the first dielectric material holding the semiconductor device in place relative to the core after the carrier and the pedestal are removed.

17. The method of claim 16, further comprising depositing a second dielectric material on the second surface of the core, the second dielectric material extending into a gap in the opening, the gap created by removing the pedestal from within the opening. 18 . The method of claim 16 , further comprising providing a release film between the carrier and the core and between the pedestal and the semiconductor device, the release film facilitating removal of the carrier and the pedestal. 19 . The method of claim 18 , further comprising providing the release film on a surface of at least one of the carrier or the base that is exposed within the opening and spaced apart from the semiconductor device.

20. The method according to any one of claims 16 to 19, wherein: The base is an integral extension of the carrier.

21. The method according to any one of claims 16 to 19, wherein: Positioning of the semiconductor device on the base is completed before positioning of the core on the carrier.

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