Battery cell layout structure and battery pack

Abstract

The invention relates to a battery cell layout structure and a battery pack. The battery cell layout structure and the battery pack can be formed with lower cost, fewer communication nodes and lower energy consumption. The battery cell layout structure comprises N battery cells, the N battery cells are arranged in a row in a series connection mode, and N is an even number larger than 4; the data acquisition chip is used for acquiring data of the battery cells so as to monitor the battery cells, and in the N battery cells, under the state that the first battery cell and the last battery cell, namely the Nth battery cell, at the two ends of the battery cell queue are excluded, the data of the battery cells are acquired; the other N-2 battery cells are sequentially grouped in a manner of taking two adjacent battery cells as one group, each group forms one battery cell system, and one data acquisition chip is arranged for each battery cell system.

Description

Technical Field

[0001] The present disclosure relates to a battery cell layout structure and a battery pack, belonging to the technical field of batteries. Background Art

[0002] With the rapid development of the new energy industry, intelligent battery cell technology has become a key area for improving battery performance and safety. In the field of electric vehicles, intelligent battery cells can achieve precise monitoring and control of battery states, improve the accuracy of driving range and the service life of batteries, and optimize the power performance and safety of vehicles.

[0003] However, current intelligent battery cell solutions have some significant drawbacks. For existing intelligent battery cells, each is served by a chip subsystem (1 chip and its sensors), which means that in large-scale applications, such as in electric vehicle battery packs or large-scale energy storage systems, a large number of chip subsystems are required, resulting in a high cost for realizing battery cell intelligence in the whole pack, increasing the production cost of products and the difficulty of market promotion. In addition, since each battery cell corresponds to a chip, there are too many communication nodes, and problems such as signal interference and transmission delay are likely to occur during data transmission, affecting communication performance and reducing the timeliness and accuracy of feedback of battery cell state information. Moreover, too many monitoring chips continuously in the working or standby state will increase the standby power consumption of the battery and shorten the power holding time of the battery in the non-use state. Especially for devices that need to be in the standby state for a long time (such as backup power supplies, etc.), it significantly affects the user experience of the device and the overall life of the battery. Summary of the Invention

[0004] In order to adapt to the trend of intelligent development and solve the above technical problems of existing intelligent battery cells, the present disclosure proposes a battery cell layout structure and a battery pack applying the battery cell layout structure, which can be formed with a lower cost, fewer communication nodes and lower energy consumption.

[0005] Specifically, in a first aspect of the present disclosure, a battery cell layout structure is provided, including:

[0006] At least N battery cells, where the N battery cells are arranged in a row in a series connection manner, and N is an even number greater than or equal to 4; and

[0007] A data acquisition chip, which is used to acquire data of the battery cells so as to monitor the battery cells,

[0008] Wherein, among the N battery cells, excluding the first battery cell and the last battery cell, i.e., the Nth battery cell, at both ends of the battery cell queue, the remaining N - 2 battery cells are sequentially grouped in a manner that every two adjacent battery cells form a group, and each group forms a battery cell subsystem, and

[0009] For each of the battery cell subsystems, one of the data acquisition chips is provided.

[0010] According to the battery cell layout structure with the above configuration, first, the cost can be significantly reduced. Compared with the traditional solution where one chip is provided for each battery cell, in the battery cell layout structure of the present disclosure, two battery cells form a group to constitute a battery cell subsystem, and only one chip needs to be equipped for each subsystem. Taking N battery cells (N is an even number greater than or equal to 4) as an example, after excluding the first and last 2 battery cells that need to be processed by the traditional solution at both ends of the queue, the middle N - 2 battery cells can form (N - 2) / 2 battery cell subsystems, and only (N - 2) / 2 chips are required. Compared with the traditional solution with N - 2 chips, the number of chips used is significantly reduced, thereby reducing the chip procurement cost, the related circuit design cost, and the overall hardware cost, and significantly reducing the cost of making the entire battery pack intelligent. For example, for a battery cell group with N = 100, the number of chips is reduced from 100 to 51 (the battery cells at both ends are monitored independently), and the cost is reduced by nearly 50%.

[0011] Secondly, according to the battery cell layout structure with the above configuration, since the number of chips is reduced, the communication nodes are correspondingly reduced. During the data transmission process, problems such as signal interference and transmission delay are alleviated. For example, when the battery system conducts data communication, fewer communication nodes make the data transmission path more concise, ensuring the stability and timeliness of data transmission, which helps to obtain the parameter information of the battery cell subsystem more efficiently and provides a good communication foundation for the real-time monitoring and precise control of the battery cell state, thereby improving the operation efficiency and reliability of the entire battery system.

[0012] Furthermore, according to the battery cell layout structure with the above configuration, since the number of chips is reduced, the number of chips in the standby state is reduced, thereby reducing the power consumption of the battery in the non-working state. For devices that need to standby for a long time, such as backup power supplies, etc., the battery power holding time can be effectively extended, unnecessary energy loss of the battery can be reduced, and the overall service life of the battery and the usage experience of the device can be improved.

[0013] In addition, according to the battery cell layout structure with the above configuration, by grouping and managing the battery cells and arranging the chips and collecting data in units of subsystems, the system architecture becomes more regular and modular. During the assembly, debugging, and maintenance processes of the battery system, operating in units of battery cell subsystems is more systematic and convenient compared to managing each battery cell one by one, which is beneficial to improving the integration and maintainability of the system.

[0014] Preferably, in the battery cell layout structure of the first aspect, it further includes: a plurality of busbars. Among them, N battery cells are arranged in such a way that the polarities of the pole columns of adjacent battery cells alternate with each other. The busbars connect the pole columns with different polarities of two adjacent battery cells, so that the N battery cells are connected in series with each other. And one pole column of the first battery cell and one pole column of the Nth battery cell become the total pole columns. And wherein, on the opposite side of the side where the total pole columns are located, the data acquisition chip is connected between two adjacent busbars, so as to be electrically connected and communicatively connected with the corresponding battery cell subsystem.

[0015] According to the battery cell layout structure with the above configuration, N battery cells are arranged in such a way that the polarities of the pole columns of adjacent battery cells alternate with each other. By connecting the pole columns with different polarities of two adjacent battery cells through busbars, the battery cells are connected in series with each other, ensuring the stable transmission of current between the battery cells, forming a stable series circuit, guaranteeing the power output of the entire battery system, enabling the battery to output a voltage level that meets the requirements of the device, and meeting the power requirements of different application scenarios. Setting one pole column of the first battery cell and one pole column of the Nth battery cell as the total pole columns provides a clear power output interface for the entire battery system, making the connection between the battery system and external devices clearer and more convenient, facilitating the installation and use of the device, reducing the risk of connection errors, and improving the compatibility and usability of the system. In addition, the data acquisition chip is connected between two adjacent busbars on the opposite side of the side where the total pole columns are located, and is electrically connected and communicatively connected with the corresponding battery cell subsystem, thereby shortening the electrical distance between the data acquisition chip and the battery cell subsystem, reducing the loss and interference of signal transmission, and improving the accuracy and real-time performance of data acquisition. At the same time, the battery cell layout structure is also convenient for wiring and circuit design, making the structure of the entire battery system more compact and reasonable, and improving the integration and reliability of the system.

[0016] Preferably, in the battery cell layout structure of the first aspect, each of the battery cell subsystems is electrically connected to the corresponding data acquisition chip via a power supply line, and communicatively connected via a collection line. And the collection line includes a voltage collection line, so that each data acquisition chip collects the voltage of the corresponding battery cell subsystem via its voltage collection line, that is, the sum of the voltages of the two battery cells that make up the battery cell subsystem.

[0017] According to the battery cell layout structure with the above configuration, the battery cell subsystem is electrically connected to the data acquisition chip through a power supply line, providing power guarantee for the stable operation of the chip, ensuring that the chip is always in a working ready state, continuously monitoring the battery cell subsystem, avoiding monitoring interruption caused by abnormal power supply, and improving the stability of the entire monitoring system. In addition, a communication connection is established using the acquisition lines, especially the voltage acquisition lines among them, to build an efficient data transmission channel, which can quickly and accurately transmit the voltage data of the battery cell subsystem to the chip, reducing signal interference and transmission loss, and ensuring the timeliness and accuracy of the data. In this disclosure, compared with the traditional solution where each battery cell needs to be independently provided with a voltage acquisition line and a power supply line, each battery cell subsystem (two battery cells) only needs a set of voltage acquisition lines and a shared power supply line, and the number of power supply lines is reduced by about 50%, reducing the material cost and assembly complexity of the FPC wiring or the power supply line. At the same time, the data acquisition chip directly obtains the total voltage of the two battery cells through a single set of voltage acquisition lines, without the need to separately design a voltage sampling channel for each battery cell, and the number of sampling channels is halved, reducing the chip cost. Moreover, by connecting the busbars on both sides, the subsystem chip can directly measure the total voltage of the two battery cells, without the need to perform differential calculations on each single battery cell one by one, reducing the signal noise interference of the voltage sampling link and improving the sampling efficiency on the high-voltage side.

[0018] Preferably, in the battery cell layout structure of the first aspect, it further includes: a temperature sensor, the temperature sensor is disposed on the pole or near the pole of any one of the two battery cells of each battery cell subsystem on the opposite side, and the acquisition line further includes a temperature acquisition line, and each temperature sensor is communicatively connected to the data acquisition chip of the corresponding battery cell subsystem via its temperature acquisition line, so that the data acquisition chip can acquire the temperature of the corresponding battery cell subsystem.

[0019] According to the battery cell layout structure with the above configuration, a temperature sensor is disposed on the battery cell pole or near the pole of each battery cell subsystem, making the monitoring of the battery cell temperature by the system more targeted and accurate, and capable of quickly capturing the subtle temperature changes of the battery cell during operation. The addition of a temperature acquisition line to the acquisition line realizes the stable communication between the temperature sensor and the data acquisition chip, ensuring that the temperature data can be transmitted in real time and accurately, avoiding data delay or loss, and providing a reliable basis for subsequent processing and analysis by the chip. The data acquisition chip can acquire the temperature of the battery cell subsystem, and combined with other data such as voltage, a comprehensive evaluation of the battery cell state can be realized. For example, it can timely detect the degradation of battery cell performance and potential fault hazards caused by abnormal temperature, and then take measures, such as adjusting the charge and discharge strategy, effectively preventing battery thermal runaway, improving the safety of battery use, and extending the battery life. In addition, these accurate temperature data can also help the system optimize the thermal management strategy, enabling the battery cell to maintain a good working state under different ambient temperatures and improving the performance of the entire battery system.

[0020] Preferably, in the battery cell layout structure of the first aspect, the power supply line and the acquisition line are integrated into an FPC cable, and the data acquisition chip is configured as a PCBA or directly surface-mounted on the FPC.

[0021] According to the battery cell layout structure with the above configuration, the power supply line and the acquisition line are integrated into a thin, flexible FPC cable, which can be flexibly routed in a limited space, better adapt to the compact layout structure of the battery cells, effectively save the space inside the battery system, improve the space utilization rate, and contribute to the miniaturization and lightweight design of the battery system. Compared with traditional multiple independent lines, the FPC cable, as a whole, is simpler and more convenient to install during the installation process, reducing the complexity of wiring and the probability of errors. Installers do not need to connect numerous scattered power supply lines and acquisition lines one by one, greatly shortening the installation time, improving the production efficiency, and at the same time reducing the risk of system failures caused by incorrect line connections. Moreover, by configuring the data acquisition chip as a PCBA or directly surface-mounted on the FPC, the integration degree of the system is further improved; the PCBA form integrates the chip and related electronic components on a circuit board, while directly surface-mounting on the FPC simplifies the structure even more, reducing the connection links between the chip and other components, making the entire battery cell monitoring system more compact and integrated, which not only helps to improve the stability and reliability of the system, but also facilitates the maintenance and management of the entire system.

[0022] Preferably, in the battery cell layout structure of the first aspect, the data acquisition chip includes at least one of the following: an analog front end (AFE) chip; an equalization and wired transmission chip; a microcontroller unit (MCU) chip; a sensor chip; and an EIS measurement chip.

[0023] According to the battery cell layout structure with the above configuration, high-precision analog signal acquisition is achieved through the AFE chip to ensure the accuracy of data such as the voltage and current of the battery cells; the energy equalization and signal transmission efficiency between the battery cells are optimized through the equalization and wired transmission chip to improve the system stability and energy utilization rate; real-time data processing and control are achieved through the MCU chip to enhance the intelligent level of the system; the environmental parameters such as the temperature and pressure of the battery cells are monitored in real time through the sensor chip to improve the safety and reliability of the system; electrochemical impedance spectroscopy analysis is achieved through the EIS measurement chip to provide key data for the assessment of the health state of the battery cells. Using the above highly integrated battery cell layout structure, the cost and power consumption are reduced, the accuracy and real-time performance of data acquisition are improved, and at the same time the anti-interference ability and scalability of the system are enhanced.

[0024] Preferably, in the battery cell layout structure of the first aspect, the FPC cable is installed on the side of the opposite side of the queue of the battery cells and extends along the arrangement direction of the N battery cells.

[0025] According to the battery cell layout structure with the above configuration, by installing the FPC cable on the side of the battery cell queue, the edge space inside the battery pack can be fully utilized, avoiding spatial conflicts with the battery cell body or other components, making the overall structure of the battery pack more compact, improving the space utilization rate. In addition, the FPC cable extends along the battery cell arrangement direction, forming a continuous signal and power supply transmission path, reducing the complexity of multiple independent cables in traditional wiring, simplifying the wiring structure inside the battery pack, reducing the assembly difficulty and cost, and at the same time reducing the failure risk caused by messy wiring. Moreover, the FPC cable extending along the battery cell queue is also conducive to forming a modular design, facilitating installation, maintenance and replacement, and also supporting the expansion of the battery pack. Just by extending the FPC cable, more battery cells can be added, improving the flexibility and scalability of the system.

[0026] Preferably, in the battery cell layout structure of the first aspect, it further includes: a thin-film pressure sensor, and the thin-film pressure sensor is closely attached between two battery cells constituting each of the battery cell subsystems.

[0027] According to the battery cell layout structure with the above configuration, through the thin-film pressure sensor closely attached between two battery cells constituting each battery cell subsystem, the pressure change between the battery cells can be sensed in real time, and the pressure change caused by the internal chemical reaction of the battery cells during the charge and discharge process can be captured in a timely manner. When the pressure exceeds the normal range, an abnormal signal is quickly transmitted, prompting the system to take protection measures such as stopping the charge and discharge in a timely manner to avoid safety accidents. In addition, using the pressure data provided by the thin-film pressure sensor, the degree of battery cell aging, the stability of the electrode material, etc. can be inferred accordingly, helping to comprehensively evaluate the battery health and life, and also enabling the battery management system to optimize the charge and discharge control based on the pressure information, extending the battery service life. The thin-film pressure sensor is thin, light and flexible, closely attached between the battery cells without occupying too much space and not affecting the original structure design. Moreover, due to its simple installation, no complex process and additional fixing device are required, the production cost is reduced and the production efficiency is improved, which is conducive to large-scale application.

[0028] Preferably, in the battery cell layout structure of the first aspect, it further includes: a temperature and pressure sensor, and the temperature and pressure sensor is closely attached between two battery cells constituting each of the battery cell subsystems, or the temperature and pressure sensor is arranged inside the battery cell.

[0029] According to the cell layout structure with the above configuration, the temperature and pressure sensors can be flexibly installed, closely attached between two cells that make up each cell subsystem, or can also be set inside the cells. The temperature and pressure sensors are used to comprehensively and real-time monitor the pressure and temperature changes of the cells during the charging and discharging processes, providing key data for battery state assessment. When abnormal temperature and pressure are detected, signals can be transmitted to the battery management system in a timely manner, prompting the system to take effective measures to prevent safety accidents and ensure the safety of the battery system. At the same time, based on the temperature and pressure data, the battery health and life can be accurately evaluated, the charging and discharging control can be optimized, the battery service life can be extended, and the installation method will not have a great impact on the original structure, providing convenience for system upgrade and transformation.

[0030] The second aspect of the present disclosure provides a battery pack, which includes a plurality of cells, and the cells have the cell layout structure described in the first aspect.

[0031] Due to the adoption of the cell layout structure of the first aspect, the battery pack of the second aspect of the present disclosure can also achieve the various technical effects mentioned above.

[0032] The basic composition of the cell layout structure of the present disclosure and the battery pack applying this cell layout structure has been described above. Next, it will be described more clearly with reference to the drawings to facilitate better understanding. Description of the Drawings

[0033] The drawings are used to better understand the present invention and do not constitute an improper limitation to the present invention. Among them:

[0034] Figure 1 is a schematic diagram of a cell queue according to an embodiment of the present disclosure;

[0035] Figure 2 is a schematic diagram of a cell layout structure according to the first embodiment of the present disclosure;

[0036] Figure 3 is a schematic diagram of a cell layout structure according to the second embodiment of the present disclosure.

[0037] List of Reference Numerals

[0038] 1 Cell

[0039] 1A The 1st Cell

[0040] 1B The 2nd Cell

[0041] 1C The 3rd Cell

[0042] 1D The 4th Cell

[0043] 1E The 5th Cell

[0044] 1F The 6th Cell

[0045] 1BC Battery Cell Subsystem

[0046] 1DE Battery Cell Subsystem

[0047] 2 Pole

[0048] 3 Total Pole

[0049] 4 Bus Bar

[0050] 5 Power Supply Wire

[0051] 6 Data Acquisition Chip Detailed Implementation Manner

[0052] Hereinafter, the technical solution of the present invention will be more clearly described by describing the detailed implementation manner of the present invention with reference to the accompanying drawings.

[0053] It should be noted that the accompanying drawings of the present invention are only schematic diagrams simply shown for clearly showing the parts related to the solution of the present invention, and do not show some non-essential parts that may exist. Therefore, these drawings should not be construed as limiting the present invention, and they may be different from the actual structure during use. In addition, it should also be understood that the terms "upper", "lower", "left", "right", "front", "rear", etc. indicating orientation or position that may appear in the following description are for the purpose of convenient explanation only, rather than restrictive. Similarly, for the sake of clarity and conciseness, the description of well-known functions and structures is omitted below.

[0054] Figure 1 is a schematic diagram of a battery cell queue according to an embodiment of the present disclosure; Figure 2 is a schematic diagram of a battery cell layout structure according to the first embodiment of the present disclosure; Figure 3 is a schematic diagram of a battery cell layout structure according to the second embodiment of the present disclosure. As shown in the figure, in this embodiment, the battery cells are taken as square battery cells for illustration. However, this is only an example, and the battery cells can also be cylindrical battery cells or blade batteries, etc.

[0055] <First Embodiment>

[0056] As Figure 1 shown, the battery cell layout structure of this embodiment shows a battery cell queue in which 4 battery cells 1 are arranged in a row, and the 4 battery cells 1 are arranged in such a way that the polarities of the poles 2 of adjacent battery cells alternate with each other. Here, the first battery cell 1 is regarded as the 1st battery cell 1A, the second battery cell 1 is regarded as the 2nd battery cell 1B, the third battery cell 1 is regarded as the 3rd battery cell 1C, and the fourth and last battery cell is regarded as the 4th battery cell 1D.

[0057] See Figure 2, the cell layout structure of this embodiment includes a bus bar 4. The bus bar 4 is connected to the poles 2 with different polarities of two adjacent cells 1, so that the 4 cells 1 are connected in series with each other, and one pole 2 of the first cell 1, i.e., the first cell 1A, and one pole 2 of the fourth cell, i.e., the fourth cell 1D, become the total poles 3.

[0058] In this embodiment, in order to achieve intelligence, a data acquisition chip 6 is also provided for the cell 1 in the cell layout structure. The data acquisition chip 6 is used to collect data of the cell 1 so as to monitor the cell 1.

[0059] In the cell layout structure of this embodiment, the cell layout structure enables two cells 1 to form a cell subsystem as a group, and each subsystem is equipped with a data acquisition chip 8 to monitor the states of the two cells 1 in the cell subsystem. See Figure 2 , in this embodiment, the second cell 1, i.e., the second cell 1A, and the third cell 1, i.e., the third cell 1C, are configured to form a cell subsystem 1BC.

[0060] Compared with the traditional solution where one data acquisition chip is provided for each cell, the cell layout structure of the embodiment provides one data acquisition chip 6 for the cell subsystem 1BC. As Figure 2 shown, the cell queue is on the opposite side of the side where the total pole 3 is located, so that the data acquisition chip 6 is connected between two adjacent bus bars 4, thereby being electrically and communicatively connected to the corresponding cell subsystem 1BC.

[0061] Specifically, as Figure 2As shown, one end of a power supply line 5 is connected to the bus bar 4 between the first battery cell 1A and the second battery cell 1B, and the other end is connected to the data acquisition chip 6; one end of another power supply line 5 is connected to the bus bar 4 between the third battery cell 1C and the fourth battery cell 1D, and the other end is connected to the data acquisition chip 6. In the battery cell layout structure of this embodiment, in addition to the power supply line 5 for transmitting current for power supply, there is also a collection line (not shown) for transmitting signals for communication. That is, the data acquisition chip 6 is electrically connected and communicatively connected to the battery cell subsystem 1BC. For the electrical connection, the data acquisition chip 6 is powered by the battery cell subsystem 1BC via the bus bar 4 without an external power supply, which improves the system independence and reliability, realizes power supply self-consistency, electrically connects the battery cell subsystem and the data acquisition chip through the power supply line, provides power guarantee for the stable operation of the chip, ensures that the chip is always in a working ready state, continuously monitors the battery cell subsystem, avoids monitoring interruption caused by abnormal power supply, and improves the stability of the entire monitoring system. For the communication connection, data communication between the battery cell subsystem 1BC and the data acquisition chip 6 is realized via the collection line, the voltage data of the battery cell subsystem is quickly and accurately transmitted to the chip, signal interference and transmission loss are reduced, the timeliness and accuracy of the data are guaranteed, and the collected data can be uploaded through a communication interface (such as CAN, SPI). The BMS monitors the battery cell subsystem BC. The power supply line 5 and the collection line can be integrated into an FPC cable, and the data acquisition chip 6 is configured as a PCBA or directly surface-mounted on the FPC. The FPC cable can be installed on the side of the opposite side of the queue of the battery cells and extends along the arrangement direction of the 4 battery cells 1 in this embodiment.

[0062] The collection line includes a voltage collection line. Thus, the data acquisition chip 6 can directly collect and measure the voltage of the battery cell subsystem 1BC via the voltage collection line, that is, the sum of the voltages of the two battery cells 1B and 1C that make up the battery cell subsystem 1BC. By measuring the total voltage of the battery cell subsystem, the equalization control logic is simplified. For example, when actually arranging the battery cells, there will be many other battery cell subsystems such as the battery cell subsystem 1BC. When the voltage of a certain subsystem is detected to be abnormal, it can be directly located to a specific two-battery-cell group for equalization.

[0063] The battery cell layout structure of this embodiment also includes a temperature sensor such as an NTC (not shown). The temperature sensor can be disposed on the pole 2 of any one of the two battery cells 1B and 1C of the battery cell subsystem 1BC on the aforementioned opposite side. Correspondingly, the collection line also includes a temperature collection line. The temperature sensor is communicatively connected to the data acquisition chip 6 of the battery cell subsystem 1BC via its temperature collection line, so that the data acquisition chip 6 can collect the temperature of the battery cell subsystem 1BC. In addition, the temperature sensor can also be disposed near the aforementioned pole.

[0064] In this embodiment, functions such as power supply, voltage acquisition, temperature acquisition, and communication are realized through a single FPC, achieving high integration, reducing the number of power supply lines and the use of connectors, reducing failure rates, and saving space. The flexibility of the FPC can adapt to the slight expansion during the charge and discharge process of the battery cells (especially for square / soft-pack battery cells), avoiding the risk of breakage caused by deformation of the rigid PCB. The SMT process can directly mount chips on the FPC in batches, reducing the PCBA assembly link and lowering production costs. The FPC cable can be pre-processed into a standardized module to support rapid assembly and repair and replacement. Compared with traditional multiple independent lines, the FPC cable, as a whole, is simpler and more convenient during installation, reducing the complexity of wiring and the probability of errors. Installers do not need to connect numerous scattered power supply lines and acquisition lines one by one, greatly shortening the installation time, improving production efficiency, and at the same time reducing the risk of system failures caused by incorrect line connections. At the same time, it also supports the expansion of the battery pack. By simply extending the FPC cable, more battery cells can be added, improving the flexibility and scalability of the system.

[0065] The data acquisition chip 6 may include at least one of the following: an analog front end (AFE) chip; a balancing and wired transmission chip; a microcontroller unit (MCU) chip; a sensor chip; and an EIS measurement chip. In addition, it also includes flash, LDO, necessary resistors, inductors, capacitors, etc. It should be noted that if the EIS measurement chip is integrated into the MCU or AFE, it may not exist as a separate chip.

[0066] High-precision analog signal acquisition is achieved through the AFE chip to ensure the accuracy of data such as the voltage and current of the battery cells; the energy balance between the battery cells and the signal transmission efficiency are optimized through the balancing and wired transmission chip to improve the system stability and energy utilization rate; real-time data processing and control are achieved through the MCU chip to enhance the intelligent level of the system; the environmental parameters such as the temperature and pressure of the battery cells are monitored in real time through the sensor chip to improve the safety and reliability of the system; electrochemical impedance spectroscopy analysis is achieved through the EIS measurement chip to provide key data for the assessment of the health state of the battery cells. Using the above highly integrated battery cell layout structure, the cost and power consumption are reduced, the accuracy and real-time performance of data acquisition are improved, and at the same time, the anti-interference ability and scalability of the system are enhanced.

[0067] In the battery cell layout structure of this embodiment, there is also a thin-film pressure sensor (not shown), and the thin-film pressure sensor is closely attached between the two battery cells that make up the battery cell subsystem 1BC, namely the second battery cell 1B and the third battery cell 1C. In addition, the battery cell layout structure of this embodiment may also include a temperature and pressure sensor, and the temperature and pressure sensor may also be closely attached between the two battery cells that make up the battery cell subsystem 1BC, namely the second battery cell 1B and the third battery cell 1C. Figure 2There are gaps between the shown battery cells 1. This is only a schematic diagram drawn for the convenience of illustration. In actual situations, there is basically no gap between the battery cells 1. The thin-film pressure sensor and the pressure-temperature sensor are firmly pressed between the two battery cells. In addition, besides being arranged between the battery cells, the pressure-temperature sensor can also be arranged inside the battery cell.

[0068] Through the thin-film pressure sensor closely attached between the two battery cells 1 that make up the battery cell subsystem, the pressure change between the battery cells 1 can be sensed in real time, and the pressure change caused by the chemical reaction inside the battery cell during the charge and discharge process can be captured in a timely manner. When the pressure exceeds the normal range, an abnormal signal is quickly transmitted, prompting the system to take protection measures such as stopping the charge and discharge in a timely manner to avoid safety accidents. In addition, using the pressure data provided by the thin-film pressure sensor, the degree of battery cell aging, the stability of the electrode material, etc. can be inferred accordingly, helping to comprehensively evaluate the battery health and life, and also enabling the battery management system to optimize the charge and discharge control based on the pressure information, extending the battery service life. The thin-film pressure sensor is thin, light, and flexible, closely attached between the battery cells without occupying too much space and not affecting the original structural design. Also, due to its simple installation, no complex process and additional fixing device are required, the production cost is reduced, the production efficiency is improved, which is conducive to large-scale application.

[0069] The pressure-temperature sensor can be flexibly installed, can be closely attached between the two battery cells that make up each battery cell subsystem, or can also be arranged inside the battery cell. Using the pressure-temperature sensor to comprehensively and real-time monitor the pressure and temperature changes of the battery cell during the charge and discharge process, providing key data for the battery state assessment. When abnormal pressure-temperature is detected, a signal can be transmitted to the battery management system in a timely manner, prompting the system to take effective measures to prevent the occurrence of safety accidents and ensuring the safety of the battery system. At the same time, based on the pressure-temperature data, the battery health and life can be accurately evaluated, the charge and discharge control can be optimized, and the battery service life can be extended, and the installation method will not have a great impact on the original structure, providing convenience for system upgrade and transformation.

[0070] <Second Embodiment>

[0071] Figure 3 The second embodiment is shown. The second embodiment is basically the same as the first embodiment, except that the number of battery cells 1 increases from 4 to 6, that is, the 5th battery cell 1E and the 6th battery cell 1F are added.

[0072] Similar to the situation of the first embodiment, the 6 battery cells in the second embodiment are also alternately arranged in a battery cell queue in a way that the polarities are opposite to each other, and adjacent two battery cells 1 are connected by the bus bar 4. In the second embodiment, besides the battery cell subsystem 1BC, there is also a battery cell subsystem 1DE composed of the battery cell 1D and the battery cell 1E.

[0073] The cell subsystem 1DE, like the cell subsystem 1BC, has one data acquisition chip 6. This data acquisition chip 6 is connected to the busbars 4 of cells 1B and 1C and the busbars 4 of cells 1E and 1F through the power supply line 5 to supply power to the data acquisition chip 6. In addition, similar to the first embodiment, the cell subsystem 1DE of the second embodiment also has data lines for collecting voltage, temperature, etc. A thin-film pressure sensor is also provided between the 5th cell 1D and the 6th cell 1E, and a temperature and pressure sensor is also provided between the 5th cell 1D and the 6th cell 1E or inside each cell, which will not be elaborated here.

[0074] <Other embodiments>

[0075] Similar to the above second embodiment, according to the cell layout structure of the present disclosure, an even number of cells 1 can be continuously added, and two adjacent cells are sequentially grouped into a cell subsystem.

[0076] That is to say, the cell layout structure of the present disclosure may include: at least N cells, the N cells are arranged in a row in a series connection manner, and N is an even number greater than or equal to 4; and a data acquisition chip, the data acquisition chip is used to collect data of the cells so as to monitor the cells. Among the N cells, excluding the first cell and the last cell, i.e., the Nth cell, at both ends of the cell queue, the remaining N - 2 cells are sequentially grouped in a manner that two adjacent cells form a group, and each group forms a cell subsystem, and for each cell subsystem, one data acquisition chip is provided.

[0077] According to the cell layout structure with the above configuration, first of all, the cost can be significantly reduced. Compared with the traditional solution where one chip is provided for each cell, the cell layout structure of the present disclosure makes two cells form a group to constitute a cell subsystem, and only one cell chip needs to be equipped for each subsystem. Taking N cells (N is an even number greater than or equal to 4) as an example, after excluding the 2 cells that need to be processed by the traditional solution at both ends of the queue, the middle N - 2 cells can form (N - 2) / 2 cell subsystems, and only (N - 2) / 2 chips are needed. Compared with the traditional solution of N - 2 chips, the number of chips used is greatly reduced, thereby reducing the chip procurement cost, related circuit design cost, and overall hardware cost, and significantly reducing the cost of making the whole pack of cells intelligent. For example, for a cell group with N = 100, the number of chips is reduced from 100 to 51 (the cells at both ends are monitored independently), and the cost is reduced by nearly 50%.

[0078] Secondly, according to the battery cell layout structure with the above configuration, since the number of chips is reduced, the communication nodes are correspondingly reduced. During data transmission, problems such as signal interference and transmission delay are alleviated. For example, when the battery system conducts data communication, fewer communication nodes make the data transmission path more concise, ensuring the stability and timeliness of data transmission. This helps to obtain the parameter information of the battery cell subsystem more efficiently, providing a good communication foundation for the real-time monitoring and precise control of the battery cell state, and thus improving the operating efficiency and reliability of the entire battery system.

[0079] Furthermore, according to the battery cell layout structure with the above configuration, due to the reduction in the number of chips, the number of chips in the standby state is reduced, thereby reducing the power consumption of the battery in the non-working state. For devices that need to standby for a long time, such as backup power supplies, it can effectively extend the battery power retention time, reduce unnecessary energy loss of the battery, and improve the overall service life of the battery and the user experience of the device.

[0080] In addition, according to the battery cell layout structure with the above configuration, by grouping and managing the battery cells and arranging chips and collecting data in units of subsystems, the system architecture becomes more regular and modular. During the assembly, debugging, and maintenance of the battery system, operating in units of battery cell subsystems is more systematic and convenient compared to managing each single battery cell one by one, which is beneficial to improving the integration and maintainability of the system.

[0081] It should be noted that for the two battery cells at the head and tail of the battery cell queue, since they do not form a battery cell subsystem, a data acquisition chip can be configured for each of the two battery cells at the head and tail of the battery cell queue, and the data acquisition chip is connected to the positive and negative electrodes of the corresponding head and tail battery cells for sampling to conduct monitoring.

[0082] In addition, it should also be noted that although in this disclosure, 1 data acquisition chip is shared for the battery cell subsystem composed of two battery cells to monitor the battery cell subsystem, when single battery cell-level balancing is required, only the acquisition line needs to be added, which has good scalability. For example, redundant acquisition lines can be reserved in the FPC to support on-demand expansion of single battery cell measurement.

[0083] <Application Example>

[0084] For the battery cell layout structures in the above embodiments, they can be well applied to various energy storage devices, including but not limited to battery packs of vehicles (two-wheeled or three-wheeled vehicles such as cars and motorcycles), battery packs of drones, large-scale energy storage systems, and so on.

[0085] For the above application example, due to the adoption of the battery cell layout structure of this disclosure, it is significantly superior to the traditional single battery cell monitoring scheme in terms of cost control, space utilization, system reliability, etc., and supports flexible expansion.

[0086] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can occur depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A battery cell layout structure, characterized in that: include: At least N battery cells, the N battery cells are arranged in a row in a manner of being connected in series, and N is an even number greater than 4; and A data acquisition chip, wherein the data acquisition chip is used to collect data of the battery cell so as to monitor the battery cell, Among the N cells, excluding the first cell at both ends of the cell queue and the last cell, i.e., the Nth cell, the remaining N-2 cells are grouped in sequence with two adjacent cells as a group, and each group becomes a cell subsystem, and For each of the battery cell subsystems, one data acquisition chip is provided.

2. The battery cell layout structure according to claim 1, characterized in that: Also includes: Multiple bus bars, The N cells are arranged in such a way that the polarities of the poles of adjacent cells are alternated with each other, and the bus bar connects the poles of two adjacent cells with different polarities, so that the N cells are connected in series with each other, and one pole of the first cell and one pole of the Nth cell become the total pole, and Among them, on the side opposite to the side where the main pole is located, the data acquisition chip is connected between two adjacent bus bars, so as to be electrically and communicatively connected with the corresponding battery cell subsystem.

3. The battery cell layout structure according to claim 2, characterized in that: Each of the battery subsystems is electrically connected to the corresponding data acquisition chip via a power supply line and is communicatively connected via an acquisition line, and The acquisition lines include voltage acquisition lines, so that each of the data acquisition chips acquires the voltage of the corresponding battery cell subsystem via its voltage acquisition line, that is, the voltage sum of the two battery cells constituting the battery cell subsystem.

4. The battery cell layout structure according to claim 3, characterized in that: Also includes: a temperature sensor, the temperature sensor being arranged on the opposite side on or near the pole of any one of the two battery cells of each of the battery cell subsystems, and The acquisition line also includes a temperature acquisition line, Each of the temperature sensors is communicatively connected to a data acquisition chip of the corresponding battery cell subsystem via a temperature acquisition line, so that the data acquisition chip can acquire the temperature of the corresponding battery cell subsystem.

5. The battery cell arrangement structure according to claim 3 or 4, characterized in that: The power supply line and the collection line are integrated into an FPC cable, and The data acquisition chip is constructed as a PCBA or is directly surface mounted on an FPC.

6. The battery cell arrangement structure according to any one of claims 1 to 5, characterized in that: The data acquisition chip includes at least one of the following: Analog front end (AFE) chip; Equalization and wired transmission chip; Microcontroller unit (MCU) chip; sensor chip; and EIS measurement chip.

7. The battery cell arrangement structure according to any one of claims 5 or 6, characterized in that: The FPC cable is installed on the side surface of the opposite side of the array of the battery cells and extends along the arrangement direction of the N battery cells.

8. The battery cell arrangement structure according to any one of claims 1 to 7, characterized in that: Also includes: A thin film pressure sensor is tightly fitted between two battery cells constituting each of the battery cell subsystems.

9. The battery cell arrangement structure according to any one of claims 1 to 6, characterized in that: Also includes: A temperature and pressure sensor is tightly fitted between two battery cells constituting each of the battery cell subsystems, or the temperature and pressure sensor is arranged inside the battery cell.

10. A battery pack, the battery comprising a plurality of cells, characterized in that: The battery cell has a battery cell layout structure according to any one of claims 1-9.

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