A vertical cavity surface emitting semiconductor laser and a manufacturing method thereof

Abstract

This application relates to the technical field of semiconductor lasers, and in particular, to a vertical cavity surface emitting semiconductor laser and its manufacturing method, including a substrate, an N-side electrode, an N-type DBR layer, an N-type confinement layer, an active region, a P-type confinement layer, a P-type DBR layer, a confinement layer, a dielectric filling layer, a surface passivation layer, a P-side electrode, a P-type metal contact, and an ALD layer. A confinement hole is provided on the confinement layer, the material of the confinement layer includes Bi₂Se₃, and the confinement hole is a rotationally asymmetric structure. The bandwidth and relative intensity noise RIN of the laser are greatly improved, so that the laser prepared by the solution of this application can meet the high bandwidth and low noise requirements of a single-channel 100 Gbps link; innovatively use Bi₂Se₃ to manufacture the confinement layer of the VCSEL laser, simplify the preparation process of the VCSEL product, and improve the product bandwidth and process uniformity; innovatively use a rotationally asymmetric morphology to manufacture the confinement layer of the VCSEL laser, and optimize the relative intensity noise performance of the product.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor lasers, and particularly to a vertical cavity surface emitting semiconductor laser and a manufacturing method thereof. Background Art

[0002] Currently, for short-distance transmission links with a single-channel 100 Gbps rate, vertical cavity surface emitting lasers stand out among many semiconductor optical communication chips due to their advantages of high speed, high reliability, easy coupling, low power consumption, low cost, etc., and their compatibility with existing multimode fiber cabling systems, becoming the preferred optical chip solution for data centers and short-distance optical communication. Along with the increasing market demand, higher requirements are also put forward for the transmission rate of VCSEL optical chips.

[0003] For traditional oxidation-confined vertical cavity surface emitting lasers, reducing the confinement aperture and thus decreasing the mode volume is the main strategy to increase the bandwidth. However, it is quite challenging to achieve a confinement aperture smaller than 4 microns because of the strict requirements for high reliability and repeatability of devices in mass production. In addition, the oxide layer also imposes certain restrictions on the thermal diffusion of the device. Moreover, the design constraints brought by the process make it extremely difficult for oxide vertical cavity surface emitting lasers to achieve a bandwidth higher than 35 GHz.

[0004] It is very difficult to achieve the high bandwidth required for a single-channel 100 Gbps link through traditional oxidation-confined vertical cavity surface emitting laser technology. The limitations of the technology based on traditional oxidation-confined vertical cavity surface emitting laser (VCSEL) chips are becoming increasingly prominent. Summary of the Invention

[0005] To solve the above problems, this application provides a vertical cavity surface emitting semiconductor laser and a manufacturing method thereof.

[0006] One object of this application is to provide a vertical cavity surface emitting semiconductor laser, adopting the following technical solution:

[0007] A vertical cavity surface emitting semiconductor laser includes a substrate, an N-side electrode, an N-type DBR layer, an N-type confinement layer, an active region, a P-type confinement layer, a P-type DBR layer, a confinement layer, a dielectric filling layer, a surface passivation layer, a P-side electrode, a P-type metal contact, and an ALD layer. A confinement hole is opened on the confinement layer, and the material of the confinement layer includes Bi2Se3.

[0008] By adopting the above technical solution, the material of the confinement layer is grown through Bi2Se3. The current confinement of Bi2Se3 is determined by the intrinsic characteristics of the material, avoiding the pore diameter fluctuation caused by wet oxidation. The deviation of the traditional process is ±10%, while the process deviation of this application is <±2%. In addition, the confinement layer of Bi2Se3 has the effects of ultra-low resistance and efficient carrier injection. The surface state electron mobility of Bi2Se3 is as high as 10 4 ~10 5 cm² / (V·s), far exceeding that of GaAs bulk material (~8000 cm² / (V·s)), significantly reducing the series resistance and improving the AC performance of the laser. The confinement layer of Bi2Se3 also has high temperature stability and device reliability. The Bi2Se3 material remains stable below 300 °C, enabling the VCSEL to continuously operate in an environment of 150 °C. While the traditional oxide layer is prone to structural relaxation at >100 °C. The high thermal conductivity of the Bi2Se3 layer (the thermal conductivity of Bi2Se3 is ~2 W / m·K) improves the heat dissipation efficiency, and the device thermal resistance is reduced to 5 K / W (the traditional structure is 10 - 15 K / W). The Bi2Se3 layer also has the advantage of polarization controllable output. The spin-momentum locking characteristic of the Bi2Se3 surface state induces carrier spin polarization, making the output light have a specific polarization direction (extinction ratio > 30 dB).

[0009] Preferably, the confinement hole is a rotationally asymmetric structure.

[0010] By adopting the above technical solution, relative intensity noise (RIN) is the core index to measure the output light intensity stability of the laser, and it is defined as the ratio of the power spectral density of the light intensity fluctuation to the square of the average light intensity (RIN = ⟨ΔP²⟩ / ⟨P⟩²). In VCSELs, RIN mainly comes from the following mechanisms: 1) Carrier density fluctuations, relaxation oscillations caused by carrier-photon interactions. 2) Mode competition noise: Energy competition between multiple transverse modes or polarization modes leads to instantaneous power fluctuations. 3) Spatial hole burning effect: Local gain saturation caused by uneven carrier distribution. Due to symmetry limitations, traditional circular aperture VCSELs have a large RIN (poor performance). While the rotationally asymmetric aperture significantly suppresses RIN through the following physical mechanisms: 1) Carrier transport optimization: The asymmetric aperture restricts the diffusion of carriers in a specific direction, forming a directional carrier transport channel, reducing the spatial fluctuation of carrier density. The carrier density non-uniformity is reduced from 5% of the circular aperture to 1% of the asymmetric structure, corresponding to the RIN spectral width being compressed to 2 GHz (5 GHz for the circular aperture). 2) The rotationally asymmetric aperture changes the optical field distribution in the cavity through geometric anisotropy. The optical field localization in the long axis direction is stronger, resulting in lower loss of the fundamental transverse mode (LP 01 ), than that of the higher-order mode (LP 11etc.), suppressing multimode oscillation. The asymmetric structure breaks the polarization degeneracy, forcibly locks a single polarization state, and eliminates polarization mode competition noise. 3) The rotating asymmetric aperture disperses carrier consumption through a non-uniform optical field distribution, avoiding carrier depletion in the central region (i.e., "spatial hole burning") caused by the symmetric optical field in a circular aperture. Improvement in gain uniformity: The standard deviation of the light intensity distribution decreases from 30% for a circular aperture to 10% for the asymmetric structure, reducing the non-linear gain coefficient (ε) from 1×10⁻²³ m³ to 3×10⁻² 4 m³, and the RIN decreases by 4 dB in the region above the threshold. The rotating asymmetric aperture VCSEL reduces the RIN noise to below -148 dB / Hz through a triple mechanism of mode competition suppression, carrier localization, and thermal-optical coupling optimization, an improvement of 5 - 7 dB / Hz compared to the circular structure.

[0011] Preferably, a buffer layer is inserted into the confinement layer, and the buffer layer material is AlAs.

[0012] Preferably, an intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

[0013] By adopting the above technical solution, the buffer layer alleviates lattice mismatch (Bi2Se3 lattice constant 4.14 Å vs. GaAs 5.65 Å). Using hexagonal boron nitride as the intermediate layer, a low-defect interface is achieved through weak van der Waals force coupling, with a surface roughness <0.5 nm. The defect density can be reduced to 10¹ 0 cm⁻² or less. The Dirac surface state electrons of Bi2Se3 have spin-momentum locking characteristics, forming a high-mobility (>10 4 cm² / (V·s)) conductive channel, while the bulk remains insulating. In the VCSEL, the Bi2Se3 layer covers the mesa sidewall, and its bulk insulating property is used to laterally block the current, allowing current to be injected into the quantum well active region only through the top surface state, achieving self-aligned current confinement.

[0014] Another object of the present application is to provide a manufacturing method of a vertical cavity surface emitting semiconductor laser, adopting the following technical solution:

[0015] A manufacturing method of a vertical cavity surface emitting semiconductor laser for manufacturing the above vertical cavity surface emitting semiconductor laser, including,

[0016] S1. Use molecular beam epitaxy to grow an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer on a substrate respectively;

[0017] S2. Use molecular beam epitaxy to grow a confinement layer on the P-type confinement layer with Bi2Se3 as the material.

[0018] By adopting the above technical solution, using Bi2Se3 as the material to grow the confinement layer can simplify the process, eliminate the oxidation step (wet oxidation requires high-temperature steam treatment at 400 °C or above), reduce the process flow by 30%, and increase the yield to over 90%.

[0019] Preferably, in step S2, when growing the confinement layer, insert a 1.5 nm thick buffer layer of AlAs.

[0020] Preferably, in step S2, insert a buffer layer with hexagonal boron nitride as the intermediate layer.

[0021] Preferably, in step S2, use a step-and-repeat projection lithography machine to transfer the rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam for irradiation treatment to destroy the Dirac surface state and induce insulation to form confinement holes.

[0022] By adopting the above technical solution, it is very difficult to achieve rotationally asymmetric confinement holes with a major axis of 3.6 μm in the traditional wet oxidation process, and it cannot be compared with the solution mentioned in this application in terms of production yield and process uniformity.

[0023] Preferably, in step S2, the growth temperature is controlled at 200 - 300 °C.

[0024] By adopting the above technical solution, the growth temperature is controlled at 200 - 300 °C to avoid damaging the VCSEL quantum well structure.

[0025] Preferably, it further includes

[0026] S3. Use molecular beam epitaxy to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer;

[0027] S4. Use an evaporation process to fabricate a P-type electrode metal ring on the top of the device light-emitting area as the current injection area;

[0028] S5. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition to cover the device surface with a low-stress SiNx passivation protective film for passivation protection;

[0029] S6. Isolate the device through ion implantation process and reduce the parasitic capacitance;

[0030] S7. Use benzocyclobutene as the dielectric material to fill the positive and negative electrode areas of the chip to reduce the parasitic parameters of the chip itself;

[0031] S8. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition as the optical dielectric film for the chip light-emitting hole;

[0032] S9. Remove the dielectric film above the current injection region in S1 through a dry etching process, and use the metal of the current injection region in S1 as the seed gold to grow the P-type electrode by electroplating;

[0033] S10. Use an evaporation process to fabricate and grow the front N-type electrode;

[0034] S11. Use the ALD process to passivate the chip device area, protect the internal structure of the chip, and improve the reliability of the chip;

[0035] S12. Grind and thin the chip;

[0036] S13. Evaporate metal on the back side;

[0037] S14. Perform RTA treatment;

[0038] S15. Test and age;

[0039] S16. Cut and sort.

[0040] In summary, the present application includes at least one of the following beneficial technical effects:

[0041] 1. Under the condition of meeting the reliability requirements of commercial laser applications, the AC performance of the VCSEL laser product is greatly improved. In particular, the bandwidth and relative intensity noise RIN of the laser are greatly improved, so that the laser prepared by the preferred solution of this patent can meet the high-bandwidth and low-noise requirements of a single-channel 100Gbps link;

[0042] 2. Innovatively use Bi2Se3 to manufacture the confinement layer of the VCSEL laser, simplify the manufacturing process of the VCSEL product, and improve the product bandwidth and process uniformity;

[0043] 3. Innovatively use a rotationally asymmetric morphology to manufacture the confinement hole of the VCSEL laser, and optimize the relative intensity noise performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a schematic cross-sectional structure diagram of Embodiment 1;

[0045] Figure 2 is a schematic plan structure diagram of Embodiment 1;

[0046] Figure 3 is a test curve graph of the laser bandwidth in Embodiment 1;

[0047] Figure 4 is a test curve graph of the relative intensity noise of the laser in Embodiment 1;

[0048] Figure 5 is the eye diagram of the laser in Embodiment 1;

[0049] Figure 6 It is the laser reliability verification diagram in Embodiment 1;

[0050] Figure 7 It is the preparation process diagram of the confinement hole in S in Embodiment 2.

[0051] Explanation of reference numerals:

[0052] 1. Substrate; 2. N-side electrode; 3. N-type DBR layer; 4. N-type confinement layer; 5. Active region; 6. P-type confinement layer; 7. P-type DBR layer; 8. Confinement layer; 9. Dielectric filling layer; 10. Surface passivation layer; 11. P-side electrode; 12. P-type metal contact; 13. ALD layer; 14. Back N-type electrode; 15. Confinement hole. Detailed implementation manners

[0053] The following further elaborates on this application in conjunction with all the attached drawings.

[0054] Embodiment 1

[0055] This application embodiment discloses a vertical cavity surface emitting semiconductor laser. Referring to Figures 1 to 2 , it includes a substrate 1, an N-side electrode 2, an N-type DBR layer 3, an N-type confinement layer 4, an active region 5, a P-type confinement layer 6, a P-type DBR layer 7, a confinement layer 8, a dielectric filling layer 9, a surface passivation layer 10, a P-side electrode 11, a P-type metal contact 12, and an ALD layer 13. A back N-type electrode 14 is provided at the bottom of the substrate 1.

[0056] Referring to Figures 1 to 2 , the material of the N-type substrate 1 is GaAs; the material of the N-side electrode 2 is Au / Ge / Ni / Au. The material of the N-type DBR layer 3 is GaAs / AlAs, and AlAs is used as the heat dissipation layer, with relatively high reliability. The material of the N-type confinement layer 4 is AlGaAs; for the active region 5, the material is an InGaAs / AlGaAs strained quantum well structure. The material of the P-type confinement layer 6 is AlGaAs; for the P-type DBR layer 7, the material is GaAs / AlGaAs.

[0057] Referring to Figures 1 to 2 , the material of the confinement layer 8 is Bi2Se3. A confinement hole 15 with a rotationally asymmetric structure, such as a semi-circular shape, is formed in the confinement layer 8. A buffer layer is inserted into the confinement layer 8, the material of the buffer layer is AlAs, and an intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

[0058] Referring to Figures 1 to 2, the material of the dielectric filling layer 9 is BCB (benzocyclobutene), which reduces the external parasitic capacitance. The material of the surface passivation layer 10 is SiNx, which has a passivation and protection effect. The material of the P-side electrode 11 is Ti / Pt / Au. The material of the optical dielectric film is SiNx, and the refractive index can be changed by controlling the film thickness to adjust the optical properties. The material of the ALD layer 13 is Al2O3, which is the passivation layer of the laser, protecting the inside of the laser from water vapor erosion and improving the reliability of the product. The material of the back N-type electrode 14 is Au / Ge / Ni / Au. Designing an N-type electrode on the back of the laser is beneficial for the laser to adapt to different packaging scenarios at the application end and improve the compatibility of the laser at the application end.

[0059] Refer to Figure 3 , a vertical cavity surface emitting semiconductor laser in this application has a room temperature -3dB bandwidth as high as 35Ghz and a high temperature -3dB bandwidth as high as 30Ghz under the operating current, and its performance is superior to that of traditional lasers.

[0060] Refer to Figure 4 , the relative intensity noise at room temperature is lower than -148dB / Hz and the relative intensity noise at high temperature is lower than -145dB / Hz under the operating current, and its performance is superior to that of traditional lasers. It meets the index of the relative noise intensity of VCSEL products by IEEE802.3 (Institute of Electrical and Electronics Engineers) (<138dB / Hz).

[0061] Refer to Figure 5 , the eye diagram TDECQ at room temperature is 1.32dB and the eye diagram TDECQ at high temperature is 2.61dB under the operating current, meeting the index of the eye diagram TDECQ of VCSEL products by IEEE802.3 (Institute of Electrical and Electronics Engineers) (<3dB).

[0062] Refer to Figure 6 , it meets the reliability requirements of VCSEL for commercial data communication applications (under the use conditions of 8mA current and 75℃, the time to reach 1% device failure (TT1%F) is greater than 10 years).

[0063] Embodiment 2

[0064] This application embodiment discloses a manufacturing method of a vertical cavity surface emitting semiconductor laser, including,

[0065] S1. Use molecular beam epitaxy (MBE) process to form an epitaxial layer on one side surface of the substrate. The epitaxial layer includes an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer that are sequentially stacked.

[0066] S2. Use molecular beam epitaxy (MBE) to grow a confinement layer on the above epitaxial layer with Bi2Se3 as the material; during the growth process, a 1.5 nm AlAs buffer layer needs to be inserted to relieve lattice mismatch (lattice constant of Bi2Se3 is 4.14 Å vs. 5.65 Å of GaAs), and hexagonal boron nitride (h-BN) is used as the intermediate layer to achieve a low-defect interface through weak van der Waals coupling, with a surface roughness <0.5 nm. The defect density can be reduced to below 10¹ 0 cm⁻². The growth temperature is controlled at 200 - 300 °C to avoid damaging the VCSEL quantum well structure. Use a stepper to transfer the rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam (Ga⁺ ions) for irradiation treatment to destroy the Dirac surface states and induce insulation to form confinement holes (diameter controlled at 3.5 μm ± 0.1).

[0067] S3. Use molecular beam epitaxy (MBE) to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer.

[0068] Among them, the principle of using Bi2Se3 with hexagonal boron nitride (h-BN) as the intermediate layer and inserting a buffer layer (AlAs) as the confinement layer of the patented VCSEL laser is that the Dirac surface state electrons of Bi2Se3 have the characteristic of spin-momentum locking, forming a conductive channel with a high mobility (>10 4 cm² / (V·s)), while the bulk phase remains insulating. In the VCSEL, the Bi2Se3 layer covers the mesa sidewall, and its bulk phase insulation characteristic is used to block the current laterally, allowing only the current to be injected into the quantum well active region through the top surface state, realizing self-aligned current confinement.

[0069] The advantages of using Bi2Se3 with hexagonal boron nitride (h-BN) as the intermediate layer and inserting a buffer layer (AlAs) as the confinement layer of the patented VCSEL laser are as follows: 1. Process simplification: The oxidation step is omitted (wet oxidation requires high-temperature steam treatment above 400 °C), the process flow is reduced by 30%, and the yield is increased to over 90%. 2. Aperture uniformity: The current confinement of Bi2Se3 is determined by the intrinsic characteristics of the material, avoiding the aperture diameter fluctuation caused by wet oxidation (the deviation of the traditional process is ±10%, and the deviation of the process of this patent is <±2%). 3. Ultra-low resistance and efficient carrier injection: The electron mobility of the Bi2Se3 surface state is as high as 10 4 ~10 5cm² / (V·s), far exceeding that of bulk GaAs material (~8000 cm² / (V·s)), significantly reducing the series resistance and improving the AC performance of the laser. 4. High temperature stability and device reliability: The Bi2Se3 material remains stable below 300 °C, enabling the VCSEL to operate continuously in an environment of 150 °C (the traditional oxide layer is prone to structural relaxation at >100 °C). The high thermal conductivity of Bi2Se3 (the thermal conductivity of Bi2Se3 ~ 2 W / m·K) improves the heat dissipation efficiency, and the device thermal resistance is reduced to 5 K / W (the traditional structure is 10 - 15 K / W). 5. Polarization - controllable output: The spin - momentum locking property of the surface states of Bi2Se3 (Spin - Momentum Locking) induces the spin polarization of carriers, making the output light have a specific polarization direction (extinction ratio > 30 dB). 6. It is very difficult to achieve a rotation - asymmetric oxidation confinement layer (semicircular arc) with a major axis of 3.6 um by the traditional wet oxidation process, and it cannot be compared with the preferred solution mentioned in the patent in terms of production yield and process uniformity, etc.

[0070] The advantages of using a rotation - asymmetric (circular arc) as the confinement layer of the patented VCSEL laser are as follows: Relative intensity noise (RIN) is a core index to measure the stability of the output optical intensity of a laser, and its definition is the ratio of the power spectral density of the optical intensity fluctuation to the square of the average optical intensity (RIN = ⟨ΔP²⟩ / ⟨P⟩²). In a VCSEL, RIN mainly comes from the following mechanisms: 1. Carrier density fluctuations, relaxation oscillations (Relaxation Oscillation) caused by the carrier - photon interaction. 2. Mode competition noise: The energy competition between multiple transverse modes or polarization modes causes instantaneous power fluctuations. 3. Spatial hole - burning effect: Local gain saturation caused by non - uniform carrier distribution. Due to symmetry limitations, the RIN of traditional circular - aperture VCSELs is relatively large (poor performance).

[0071] The rotation - asymmetric aperture significantly suppresses RIN through the following physical mechanisms: 1. Carrier transport optimization: The asymmetric aperture restricts the diffusion of carriers in a specific direction, forming a directional carrier transport channel, reducing the spatial fluctuations of the carrier density. The non - uniformity of the carrier density is reduced from 5% of the circular aperture to 1% of the asymmetric structure, corresponding to the RIN spectral width being compressed to 2 GHz (5 GHz for the circular aperture). 2. The rotation - asymmetric aperture (such as an arc - type) changes the optical field distribution in the cavity through geometric anisotropy. The optical field localization in the major - axis direction is stronger, resulting in lower loss of the fundamental transverse mode (LP 01 ) than that of the higher - order mode (LP 11etc.), suppressing multimode oscillation. The asymmetric structure breaks the polarization degeneracy, forcibly locks a single polarization state, and eliminates polarization mode competition noise. 3. The rotating asymmetric aperture disperses carrier consumption through a non-uniform light field distribution, avoiding carrier depletion in the central region caused by the symmetric light field in the circular aperture (i.e., "spatial hole burning"). Improvement of gain uniformity: The standard deviation of the light intensity distribution decreases from 30% of the circular aperture to 10% of the asymmetric structure, reducing the nonlinear gain coefficient (ε) from 1×10⁻²³ m³ to 3×10⁻² 4 m³, and the RIN is reduced by 4 dB in the region above the threshold. The rotating asymmetric aperture VCSEL reduces the RIN noise to below -148 dB / Hz through three mechanisms: mode competition suppression, carrier localization, and thermal-optical coupling optimization, which is 5 - 7 dB / Hz higher than that of the circular structure.

[0072] S4. Using the evaporation process, a P-type electrode metal ring is fabricated on the top of the device light-emitting area as the current injection area.

[0073] S5. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition process, and cover the device surface with a low-stress SiNx passivation protective film for passivation protection.

[0074] S6. Isolate the device through ion implantation process and reduce the parasitic capacitance.

[0075] S7. Use benzocyclobutene as the dielectric material to fill the positive and negative electrode regions of the chip, reducing the parasitic parameters of the chip itself.

[0076] S8. Grow a layer of SiNx through plasma-enhanced chemical vapor deposition process as the optical dielectric film of the chip light-emitting hole.

[0077] S9. Remove the dielectric film above the current injection area in S1 through dry etching process, and use the metal of the current injection area in S1 as the seed gold to grow the P-type electrode by electroplating process.

[0078] S10. Use the evaporation process to fabricate and grow the front N-type electrode.

[0079] S11. Use the ALD process to passivate the chip device area, protect the internal structure of the chip, and improve the reliability of the chip.

[0080] S12. Grind and thin the chip.

[0081] S13. Evaporate metal on the back to form the back N-type electrode.

[0082] S14. RTA treatment.

[0083] S15. Test and age.

[0084] S16. Cut and sort.

[0085] The above are all preferred embodiments of this application, and do not limit the protection scope of this application accordingly. Therefore, all equivalent changes made according to the structure, shape, and principle of this application shall be covered within the protection scope of this application.

Claims

1. A vertical cavity surface emitting semiconductor laser, characterized in that: It includes a substrate (1), an N-side electrode (2), an N-type DBR layer (3), an N-type confinement layer (4), an active region (5), a P-type confinement layer (6), a P-type DBR layer (7), a confinement layer (8), a dielectric filling layer (9), a surface passivation layer (10), a P-side electrode (11), a P-type metal contact (12), and an ALD layer (13). A confinement hole (15) for light output is formed in the confinement layer (8), and the material of the confinement layer (8) includes Bi2Se3.

2. The vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: The confinement hole (15) has a rotationally asymmetric structure.

3. A vertical cavity surface emitting semiconductor laser according to claim 1, characterized in that: A buffer layer is inserted into the confinement layer (8), and the material of the buffer layer is AlAs.

4. A vertical cavity surface emitting semiconductor laser according to claim 3, characterized in that: An intermediate layer is inserted into the buffer layer, and the material of the intermediate layer is hexagonal boron nitride.

5. A manufacturing method of a vertical cavity surface emitting semiconductor laser, characterized in that: A method for manufacturing a vertical cavity surface emitting semiconductor laser as described in any one of claims 1-4 includes: S1. Using molecular beam epitaxy to grow an N-type DBR layer, an N-type confinement layer, an active region, a λ / 2 cavity, and a P-type confinement layer on the substrate respectively; S2. Using molecular beam epitaxy to grow a confinement layer on the P-type confinement layer with Bi2Se3 as the material.

6. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: In step S2, when growing the confinement layer, insert a 1.5 nm thick buffer layer of AlAs.

7. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 6, wherein: In step S2, insert hexagonal boron nitride as the intermediate layer into the buffer layer.

8. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, characterized in that: In step S2, use a step-and-repeat projection lithography machine to transfer a rotationally asymmetric conductive pattern onto the confinement layer, and then use a focused ion beam for irradiation treatment to destroy the Dirac surface state and induce insulation to form the confinement hole.

9. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, wherein: In step S2, control the growth temperature at 200-300 °C.

10. The manufacturing method of a vertical cavity surface emitting semiconductor laser according to claim 5, wherein: It further includes: S3. Using molecular beam epitaxy to perform secondary epitaxial growth on the confinement layer to complete the growth of the P-type DBR layer; S4. Using evaporation coating process to fabricate a P-type electrode metal ring on the top of the device light emitting area as the current injection area; S5. Growing a layer of SiNx by plasma enhanced chemical vapor deposition process to cover the device surface with a low-stress SiNx passivation protection film for passivation protection; S6. Isolating the device by ion implantation process and reducing the parasitic capacitance; S7. Using benzocyclobutene as the dielectric material to fill the positive and negative electrode regions of the chip to reduce the parasitic parameters of the chip itself; S8. Growing a layer of SiNx by plasma enhanced chemical vapor deposition process as the optical dielectric film of the chip light output hole; S9. Removing the dielectric film above the current injection area in S1 by dry etching process, and using the metal in the current injection area in S1 as the seed metal to grow the P-type electrode by electroplating process; S10. Using evaporation coating process to fabricate and grow the front N-type electrode; S11. Using ALD process to passivate the chip device area to protect the internal structure of the chip and improve the reliability of the chip; S12. Grinding and thinning the chip; S13. Backside metal evaporation coating; S14. RTA treatment; S15. Testing and aging; S16. Dicing and sorting.

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