Anti-interference bidirectional electrostatic protection circuit

Abstract

An anti-interference bidirectional electrostatic protection circuit provided by the present invention comprises a first electrostatic discharge path and a second electrostatic discharge path which are arranged in parallel, and the first electrostatic discharge path comprises a first electrostatic discharge unit and a second electrostatic discharge unit which are arranged in a stacked manner. The second electrostatic discharge path comprises a third electrostatic discharge unit and a fourth electrostatic discharge unit which are stacked, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, the capacitance value of the first electrostatic discharge unit is larger than that of the second electrostatic discharge unit, and the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit. The third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, the capacitance value of the third electrostatic discharge unit is larger than that of the fourth electrostatic discharge unit, and the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions. Through circuit structure and layout optimization, accumulated charges on an internal floating node can be discharged.

Description

Technical Field

[0001] The present invention relates to the field of electrostatic protection circuits, and particularly to an anti-interference bidirectional electrostatic protection circuit. Background Art

[0002] During the use of electronic devices, due to reasons such as friction, contact separation, etc., static electricity is easily generated on the human body, clothing, device surface, etc. When the static electricity accumulates to a certain extent, an electrostatic discharge phenomenon will occur, releasing high-energy charges. This electrostatic discharge can cause serious damage to sensitive components such as integrated circuits (ICs) inside the electronic device, resulting in a decline in device performance or even complete failure.

[0003] In some electronic devices, the signal swing of certain ports will have both positive and negative voltages at the same time. For these ports, a bidirectional electrostatic protection circuit needs to be provided: that is, it needs to have bidirectional voltage blocking ability when the chip is working normally; at the same time, when static electricity comes, it also needs to have bidirectional electrostatic discharge ability. In actual ESD protection projects, by adopting the method of connecting two unidirectional ESD devices in series "head-to-head" or "tail-to-tail", the bidirectional ESD protection requirements are met. At this time, in order to provide effective electrostatic protection, attention needs to be paid to the clamping voltage after the ESD circuit conducts, and it is usually required that it does not exceed the failure voltage of the protected circuit under a specific ESD excitation level.

[0004] Existing bidirectional stacked ESD circuits, such as Figure 1(a) - Figure 1(c) shown, for bidirectional voltage withstand I / O or power supply ports, usually connect zener diodes, BJTs (bipolar junction transistors) or MOSFETs in series "head-to-head" or "tail-to-tail", which is a common ESD protection circuit strategy. At this time, the internal node Ax is floating, x = 1, 2, 3. Resistors R1 and R2 are used to limit the base current to ensure that the transistor conducts under appropriate conditions; resistors R3 and R4 are used to limit the gate current to ensure that the MOSFET conducts under appropriate conditions.

[0005] However, for the chip ports adopting the above bidirectional stacked ESD circuit, sometimes the actual ESD protection level of the port is much lower than its design value. Research shows that this is usually due to the charge storage behavior of the internal floating nodes of the above bidirectional ESD circuit. When an ESD event occurs, the non-zero potential caused by these stored charges has a certain probability of being superimposed on the I-V characteristic curve of the ESD protection device, thus severely deteriorating its clamping voltage characteristics, and ultimately greatly reducing the ESD protection level of the port.

[0006] The I-V characteristics of the ESD circuit are affected by the floating potential of Ax as shown in Fig. 2(a). An external bias voltage represents the port voltage or the pre-charge phenomenon during ESD testing. As shown in Fig. 2(a), in a specific case, when the external bias voltage disappears, the Ax potential cannot be discharged to zero potential. As shown in Fig. 2(c), when the Ax potential is non-zero, the IV curve (two red broken lines) of the ESD circuit will drift to the right along the X-axis, thus significantly deteriorating the electrostatic protection effect of the ESD circuit, that is, the ESD robustness will be severely interfered by the Ax potential. Summary of the Invention

[0007] To solve the problems in the prior art, the present invention provides an anti-interference bidirectional electrostatic protection circuit. Through circuit structure and layout optimization, the accumulated charges on the floating nodes inside the circuit can be effectively and timely discharged, avoiding the interference of the non-zero potential on the floating nodes inside on the ESD protection effect.

[0008] The anti-interference bidirectional electrostatic protection circuit of the present invention includes a first electrostatic discharge path and a second electrostatic discharge path arranged in parallel. One end of the first electrostatic discharge path and the second electrostatic discharge path is connected to a first port, and the other end of the first electrostatic discharge path and the second electrostatic discharge path is connected to a second port. The first electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked. The second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked. Among them, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions. The capacitance value of the first electrostatic discharge unit is greater than that of the second electrostatic discharge unit. The third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions. The capacitance value of the third electrostatic discharge unit is greater than that of the fourth electrostatic discharge unit, and the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions.

[0009] Further, the first electrostatic discharge unit and the third electrostatic discharge unit are provided with m ESD components connected in parallel, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n ESD components connected in parallel, where m and n are both positive integers, and m > n.

[0010] In another improvement of the present invention, the first electrostatic discharge unit and the third electrostatic discharge unit are provided with m ESD components connected in parallel, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n ESD components connected in parallel, where m and n are both positive integers, and m = n. The first electrostatic discharge unit is connected in parallel with k capacitors, and the third electrostatic discharge unit is connected in parallel with k capacitors, and k is a positive integer.

[0011] Further, the ESD component includes a diode, a MOSFET, a bipolar junction transistor (BJT), or a thyristor.

[0012] Further, the number of stacked stages of the first electrostatic discharge path and the second electrostatic discharge path is equal, both being 2 or more. The number of the first electrostatic discharge units and the second electrostatic discharge units is each more than one, and the number of the second electrostatic discharge units and the third electrostatic discharge units is each more than one.

[0013] Further, the second electrostatic discharge path is replaced by a second electrostatic discharge unit and a first resistor connected in parallel across both ends of the first electrostatic discharge unit.

[0014] Further, a second resistor is connected in parallel across both ends of the second electrostatic discharge unit. The resistance values of the first resistor and the second resistor are determined by weighing the floating charge discharge duration and the static power consumption.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: Through circuit structure and layout optimization, the present invention changes the electrostatic discharge path from the same layout to a design with different capacitance ratios, which can effectively and timely discharge the accumulated charge on the floating node inside the series ESD protection circuit from one end of the small capacitor, avoiding the interference of the non-zero potential on the internal floating node to the ESD protection effect, thereby realizing the intrinsic ESD protection ability of the protection circuit; By setting the two electrostatic discharge paths with different capacitance value ratios and opposite directions, for the bidirectional port bias, there is always one path that can effectively conduct electrostatic protection, realizing the anti-interference of the ESD function. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] FIG. 1(a) is a circuit schematic diagram of the first embodiment of the prior art bidirectional stacked ESD circuit;

[0018] FIG. 1(b) is a circuit schematic diagram of the second embodiment of the prior art bidirectional stacked ESD circuit;

[0019] FIG. 1(c) is a circuit schematic diagram of the third embodiment of the prior art bidirectional stacked ESD circuit;

[0020] FIGS. 2(a) and 2(b) are schematic diagrams showing the influence of the Ax floating potential on the I-V characteristics of the prior art bidirectional stacked ESD circuit;

[0021] Figure 2(c) is a schematic diagram showing the rightward drift of the IV curve of the existing bidirectional stacked ESD circuit;

[0022] Figure 3(a) is the equivalent circuit diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0023] Figure 3(b) is the circuit network diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0024] Figure 3(c) is the layout diagram of the first embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0025] Figure 4(a) is the equivalent circuit diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0026] Figure 4(b) is the circuit network diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0027] Figure 4(c) is the layout diagram of the second embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0028] Figure 5 is the equivalent circuit diagram of the third embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0029] Figure 6 is the equivalent circuit diagram of the fourth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0030] Figure 7 is the equivalent circuit diagram of the fifth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention;

[0031] Figure 8 is the equivalent circuit diagram of the sixth embodiment of the anti-interference bidirectional electrostatic protection circuit of the present invention. Detailed implementation manners

[0032] Unless otherwise defined, all technical and scientific terms used in the present invention have the same meaning as commonly understood by those skilled in the technical field to which the present invention belongs; the terms used in the description of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusion. The terms "first", "second", etc. in the description and claims of the present invention or the above-mentioned drawings are used to distinguish different objects and are not used to describe a specific order.

[0033] References to "embodiments" in this invention mean that the specific features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the invention. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an exclusive, independent, or alternative embodiment to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described in this invention can be combined with other embodiments.

[0034] To enable those skilled in the art of this technology to better understand the solution of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below in conjunction with the accompanying drawings.

[0035] As Figure 3(a) - Figure 6 shown, the anti-interference bidirectional electrostatic protection circuit of this invention includes a first electrostatic discharge path and a second electrostatic discharge path arranged in parallel. One end of the first electrostatic discharge path and the second electrostatic discharge path is connected to a first port, and the other end of the first electrostatic discharge path and the second electrostatic discharge path is connected to a second port. The first electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit stacked, and the second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit stacked. Among them, the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, and the capacitance value of the first electrostatic discharge unit is greater than that of the second electrostatic discharge unit. The third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, and the capacitance value of the third electrostatic discharge unit is greater than that of the fourth electrostatic discharge unit. Moreover, the first electrostatic discharge unit and the third electrostatic discharge unit are arranged in opposite directions.

[0036] The first electrostatic discharge unit and the third electrostatic discharge unit are provided with m ESD components connected in parallel, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n ESD components connected in parallel. Among them, both m and n are positive integers. The ESD components in this example include diodes, MOSFETs, bipolar junction transistors (BJTs), or thyristors, etc. The connection method can refer to Figure 1(a) - Figure 1(c) the connection method, and the gates of MOSFETs, the bases of bipolar junction transistors (BJTs), and the control terminals of thyristors can also be set floating.

[0037] The following is described in conjunction with specific embodiments. The ESD components in this example are selected as diodes. The explanations of the reference numerals in the embodiments are as follows:

[0038] ● 100, 200, 300, 400, 500, 600 represent port 1;

[0039] ● 101, 201, 301, 401, 501, 601 represent port 2;

[0040] ● 110, 210, 310, 410 usually represent the "reverse ESD discharge path", indicating the current discharge from port 2 to port 1;

[0041] ● 111, 211, 311, 411 usually represent the "forward ESD discharge path", indicating the current discharge from port 2 to port 1;

[0042] ● 510, 610 usually represent the "bidirectional ESD discharge path", indicating that the current can be discharged either from port 2 to port 1 or from port 1 to port 2;

[0043] ● 120, 121, 130, 131, 220, 221, 230, 231, 120-1, 120-2, 120-N 11 、121-1, 121-2,

[0044] 121-N 21 、130-1, 130-2, 130-N 12 、131-1, 131-2, 131-N 22 、220-1, 220-2, 220-N 31 、

[0045] 221-1, 221-2, 221-N 41 、230-1, 230-2, 230-N 32 、231-1, 231-2, 231-N 42 、320,

[0046] 321, 330, 331, 420, 421, 430, 431, 520, 521, 620, 621 represent diodes;

[0047] ● 122, 123, 132, 133, 222, 223, 232, 233 represent diode layouts;

[0048] ● 340, 341, 441, 441 represent capacitors;

[0049] ● 550, 650, 651 represent resistors;

[0050] ● A1, A2, A3, B1, B2, C1, C2, D1, D2, E1, E2, F1, G1 represent the internal floating nodes of the bidirectional electrostatic protection circuit;

[0051] ● N 11 、N 12 、N 21 、N 22 、N 31 、N32 , N 41 , N 42 represents the number of parallel-connected ESD diodes.

[0052] As Figure 3(a) - Figure 3(c) shown, as the first embodiment of the present invention, this embodiment consists of two ESD bidirectional paths: on the reverse ESD discharge path 110, the area of diode 120 is smaller than that of diode 121, that is, the parasitic capacitance of diode 120 is smaller than that of diode 121. After the port 100 is negatively biased, this path can discharge the potential of the internal floating node B1 to zero, thus not affecting the ESD protection effect; on the forward ESD discharge path 111, the area of diode 130 is larger than that of diode 131, that is, the parasitic capacitance of diode 130 is larger than that of diode 131; after the port 100 is positively biased, this path can discharge the potential of B2 to zero, thus not affecting the ESD protection effect.

[0053] In summary, for the bidirectional port bias of the embodiment, there is always a path that can effectively perform electrostatic protection, realizing the anti-interference of the ESD function. It should be particularly noted that: the internal floating nodes B1 and B2 cannot be short-circuited. This embodiment takes the zener diode as an example and is also applicable to other ESD diodes or other ESD devices.

[0054] As shown in FIGS. 3(b) and 3(c), the total number of parallel-connected positive-biased diodes (N 11 +N 12 ) is equal to the total number of parallel-connected reverse-biased diodes (N 21 +N 22 ), that is, N 11 +N 12 =N 21 +N 22 . Therefore, the total layout area of the positive-biased diode and the reverse-biased diode is equal, which is consistent with the design common sense of this type of bidirectional ESD architecture. However, on different ESD discharge paths, the area ratio of the positive-biased diode to the reverse-biased diode is not the same, that is, N 11 <N 12 , N 21 >N 22 , so as to realize the regulation of the parasitic capacitance ratio, and finally realize the bidirectional floating charge discharge and effective ESD protection.

[0055] As Figure 4(a) - Figure 4(c)As shown in the figure, as the second embodiment of the present invention, based on the first embodiment, this example changes the series connection mode of diode 230 and diode 231: from "head-to-head" to "tail-to-tail". At this time, the reverse ESD discharge path 210 is a "head-to-head" type series connection, while the forward ESD discharge path 211 is a "tail-to-tail" type series connection. The advantage of this embodiment 2 is that this example is applicable to the situation where the overall layout space of the upper part is relatively small, such as Figure 4(b) and 4(c) shown, at this time the overall layout of the upper part is smaller than that of the lower part. This embodiment increases the degree of freedom in layout design.

[0056] such as Figure 5 shown, as the third embodiment of the present invention, this example further considers the ESD protection efficiency of forward and reverse components. Here, all diodes are made to be exactly the same size, that is, the parasitic capacitances are the same. In order to make their capacitance ratios different, this example uses the externally added capacitors 340 and 341 to adjust the capacitance ratios on the bidirectional paths respectively.

[0057] such as Figure 6 shown, as the fourth embodiment of the present invention, compared with the third embodiment, the present invention adjusts the directions of the diodes 430 and 431 on the second electrostatic discharge path, and then sets the externally added capacitors 440 and 441 in the lower part of the layout, so as to increase the degree of freedom in layout design.

[0058] such as Figure 7 shown, as the fifth embodiment of the present invention, the second electrostatic discharge path in this example is replaced by a second electrostatic discharge unit and a first resistor connected in parallel across both ends of the first electrostatic discharge unit. From the overall structure, there is only one ESD discharge path in this example, and at this time the capacitance of diode 520 is smaller than that of diode 521. This example is particularly applicable to the "full-chip ESD network based on the power rail". At this time, diode 520 can specifically refer to the "ESD diode" of the I / O port, and diode 521 specifically refers to the power clamp element. In this embodiment, by connecting a resistor in parallel with diode 521, the charge of the internal floating node F1 can be effectively discharged, so as to achieve an effective ESD protection effect. Of course, the value of resistor 550 in this example needs to be carefully balanced: that is, it should be able to discharge the charge of the floating node within a limited time and at the same time take into account the deterioration amplitude of the static leakage current.

[0059] such as Figure 8As shown, as the sixth embodiment of the present invention, on the basis of the fifth embodiment, the present invention can effectively discharge floating charges by adding a resistor network to a single ESD discharge path. The resistor network in this example includes a resistor 651 connected in parallel across the two ends of the diode 621, and a resistor 650 connected in parallel across the two ends of the diode 620. The resistance values of the resistors 650 and 651 in this example also need to be balanced between the "floating charge discharge duration" and the "static power consumption". The parasitic capacitances of the diode 620 and the diode 621 in this example can be different or can be set to be the same, and then the effective discharge of floating charges is achieved by adjusting the resistor network.

[0060] It is worth mentioning that the stacking level of all embodiments of the present invention is not limited to the stacking number of the existing embodiments, and can also be set to any stacking level.

[0061] As can be seen from the above, the present invention provides a robust two-way electrostatic protection solution. Through circuit structure and layout optimization, the accumulated charges on the floating nodes inside the series-type ESD protection circuit can be effectively and timely discharged, avoiding the interference of the non-zero potential on the internal floating nodes to the ESD protection effect, thereby realizing the intrinsic ESD protection ability of the protection circuit.

[0062] The above-described specific embodiments are the preferred embodiments of the present invention, and do not limit the specific implementation scope of the present invention. The scope of the present invention includes but is not limited to this specific embodiment, and all equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. An anti-interference bidirectional electrostatic protection circuit, characterized in that: It includes a first electrostatic discharge path and a second electrostatic discharge path arranged in parallel, wherein one end of the first electrostatic discharge path and the second electrostatic discharge path is connected to the first port, and the other end of the first electrostatic discharge path and the second electrostatic discharge path is connected to the second port, the first electrostatic discharge path includes a first electrostatic discharge unit and a second electrostatic discharge unit arranged in a stacked manner, and the second electrostatic discharge path includes a third electrostatic discharge unit and a fourth electrostatic discharge unit arranged in a stacked manner, wherein the first electrostatic discharge unit and the second electrostatic discharge unit are arranged in opposite directions, wherein the capacitance value of the first electrostatic discharge unit is greater than the capacitance value of the second electrostatic discharge unit, the third electrostatic discharge unit and the fourth electrostatic discharge unit are arranged in opposite directions, the capacitance value of the third electrostatic discharge unit is greater than the capacitance value of the fourth electrostatic discharge unit, and the first electrostatic discharge unit is arranged in opposite directions to the third electrostatic discharge unit.

2. The anti-interference bidirectional electrostatic protection circuit according to claim 1, characterized in that: The first electrostatic discharge unit and the third electrostatic discharge unit are provided with m parallel-connected ESD elements, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n parallel-connected ESD elements, wherein m and n are both positive integers, and m>n.

3. The anti-interference bidirectional electrostatic protection circuit according to claim 1, characterized in that: The first electrostatic discharge unit and the third electrostatic discharge unit are provided with m ESD elements connected in parallel, and the second electrostatic discharge unit and the fourth electrostatic discharge unit are provided with n ESD elements connected in parallel, wherein m and n are both positive integers, and m=n, the first electrostatic discharge unit is connected with k capacitors in parallel, and the third electrostatic discharge unit is connected with k capacitors in parallel, and k is a positive integer.

4. The anti-interference bidirectional electrostatic protection circuit according to claim 2 or 3, characterized in that: The ESD element includes a diode, a MOSFET tube, a bipolar junction transistor BJT or a thyristor.

5. The anti-interference bidirectional electrostatic protection circuit according to any one of claims 1 to 3, characterized in that: The stacking levels of the first electrostatic discharge path and the second electrostatic discharge path are equal, both are more than 2 levels, the number of the first electrostatic discharge unit and the second electrostatic discharge unit are more than one, and the number of the second electrostatic discharge unit and the third electrostatic discharge unit are more than one.

6. The anti-interference bidirectional electrostatic protection circuit according to any one of claims 1 to 3, characterized in that: The second electrostatic discharge path is replaced by a second electrostatic discharge unit and a first resistor connected in parallel at two ends of the first electrostatic discharge unit.

7. The anti-interference bidirectional electrostatic protection circuit according to claim 6, characterized in that: Two ends of the second electrostatic discharge unit are connected in parallel with a second resistor, and the resistance values ​​of the first resistor and the second resistor are determined by a trade-off between the floating charge discharge time and the static power consumption.

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