Anti-false-triggering electrostatic discharge clamping circuit

Abstract

The invention discloses an electrostatic discharge clamping circuit capable of preventing false triggering, which belongs to the technical field of electrostatic discharge protection of integrated circuits and comprises a control transistor, a PMOS (P-channel Metal Oxide Semiconductor) current mirror resistor branch, an NMOS (N-channel Metal Oxide Semiconductor) current mirror capacitor branch, an inverter and a clamping transistor, through feedback control and voltage division design, an RC structure formed by a PMOS current mirror resistor branch and an NMOS current mirror capacitor branch has different RC time constant numbers during an electrostatic discharge event and normal power-on or rapid power-on, and has a good anti-false-triggering characteristic; the small capacitor and the small resistor are amplified through two groups of current mirror structures, and the layout area occupied by the resistor and the capacitor is greatly reduced based on the equivalent large resistor and the large capacitor. According to the invention, the problems that the electrostatic discharge clamping tube in the existing integrated circuit is easy to trigger mistakenly and the resistor and the capacitor occupy a large layout area are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of strain measurement, and particularly relates to an electrostatic discharge clamping circuit that prevents mis-triggering. Background Art

[0002] Electrostatic Discharge (ESD) is an extremely common phenomenon in life. ESD can generate voltages of thousands of volts, which can produce extremely large currents in integrated circuits, causing problems such as gate oxide breakdown, metal interconnection fusing, and PN junction breakdown. Especially when integrated circuits enter the deep sub-micron era, integrated circuits can only withstand a breakdown voltage of a few volts to dozens of volts, and its potential destructiveness will become more obvious. Therefore, ESD protection is very important for integrated circuits, and currently almost all integrated circuits have ESD protection structures. In on-chip ESD protection, the ESD power clamping circuit is a very important part, and its main purpose is to achieve ESD protection between power pins, avoiding ESD current from damaging power pins and internal circuits.

[0003] Traditional RC-triggered clamping circuits are composed of an RC detection network, an inverter, and a clamping transistor. Among them, the RC detection branch is usually composed of a resistor and a capacitor, and different RC time constants can be set by adjusting parameters. The inverter usually serves as the driving circuit of the clamping transistor, pulling up or pulling down the level of the detection branch to control the turn-off and turn-on of the clamping transistor. When the clamping transistor is turned on, it can conduct a large current, thereby discharging ESD energy. However, the traditional RC detection branch with a fixed RC time constant is very easy to be confused with ESD events during the fast power-on detection process, and there is a great risk of mis-triggering; in addition, in some processes, due to the small resistance value per unit area or capacitance value per unit area, in order to set a sufficiently long RC time constant, a large layout area needs to be sacrificed, but this is not allowed in the integrated circuit design solutions that pursue good anti-mis-triggering characteristics, high integration, and low cost. Summary of the Invention

[0004] Aiming at the above deficiencies in the prior art, the present invention provides an electrostatic discharge clamping circuit that prevents mis-triggering, which solves the problem that the electrostatic discharge clamping tube in the existing integrated circuit is prone to mis-triggering.

[0005] In order to achieve the above invention purpose, the technical solution adopted by the present invention is as follows:

[0006] An electrostatic discharge clamping circuit that prevents mis-triggering provided by the present invention includes a control transistor, a PMOS current mirror resistor branch, an NMOS current mirror capacitor branch, an inverter, and a clamping transistor;

[0007] The control transistor is respectively connected to a PMOS current mirror resistor branch and an NMOS current mirror capacitor branch, and is externally connected to a power supply voltage VDD; the PMOS current mirror resistor branch is connected to the NMOS current mirror capacitor branch, and is externally connected to the power supply voltage VDD and the ground level VSS respectively; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to an inverter, and is externally grounded to the ground level VSS; the inverter is connected to a clamping transistor, and is externally connected to the power supply voltage VDD and the ground level VSS respectively; the clamping transistor is externally connected to the power supply voltage VDD and the ground level VSS respectively.

[0008] The beneficial effects of the present invention are as follows: in an electrostatic discharge clamping circuit for preventing mis-triggering provided by the present invention, an RC structure is formed by a PMOS current mirror resistor branch and an NMOS current mirror capacitor branch. The RC structure performs feedback control on the control transistor. Through feedback control and voltage division design, the RC structure formed by the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch has different RC time constants during electrostatic discharge events and normal power-on or fast power-on, and has good anti-mis-triggering characteristics; the present invention also realizes the equivalent amplification of capacitance and resistance based on two groups of current mirror structures by setting the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch. Based on the equivalent large resistance and large capacitance, the layout area occupied by the resistance and capacitance is greatly reduced.

[0009] Further, the control transistor adopts a PMOS transistor Mp0 with feedback control, which serves as the switching transistor of the PMOS current mirror resistor branch and also serves as the voltage dividing transistor for normal power-on and fast power-on;

[0010] The source and substrate of the PMOS transistor Mp0 are externally connected to the power supply voltage VDD; the gate of the PMOS transistor Mp0 is respectively connected to the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch to receive the detection signal V RC of the RC structure to form a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistor branch.

[0011] Further, the PMOS current mirror resistor branch includes a PMOS transistor Mp1, a PMOS transistor Mp2, and a resistor R;

[0012] The substrate of the PMOS transistor Mp1 is externally connected to the power supply voltage VDD; the source of the PMOS transistor Mp1 is connected to the drain of the PMOS transistor Mp0; the gate of the PMOS transistor Mp1 is respectively connected to the drain, one end of the resistor R, and the gate of the PMOS transistor Mp2; the other end of the resistor R is externally grounded to the ground level VSS; the source and substrate of the PMOS transistor Mp2 are both externally connected to the power supply voltage VDD; the drain of the PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch for generating the detection signal V of the RC structure RC 。

[0013] Further, the NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitive manner;

[0014] The source of the PMOS transistor Mp3 is respectively connected to the drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and the inverter for generating the detection signal V of the RC structure RC ; the gate of the PMOS transistor Mp3 is respectively connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0; the source and substrate of the NMOS transistor Mn0 are both externally grounded to the ground level VSS; the source and substrate of the NMOS transistor Mn1 are both externally grounded to the ground level VSS.

[0015] Further, the inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2;

[0016] The gate of the PMOS transistor Mp4 is respectively connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1; the source and substrate of the PMOS transistor Mp4 are externally connected to the power supply voltage VDD; the source and substrate of the NMOS transistor Mn2 are externally grounded to the ground level VSS; the drain of the PMOS transistor Mp4 is respectively connected to the drain of the NMOS transistor Mn2 and the clamping transistor for generating the driving voltage V G and inputting it to the clamping transistor.

[0017] Further, the clamping transistor uses an NMOS transistor Mn3;

[0018] The gate of the NMOS transistor Mn3 is respectively connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2 for receiving the driving voltage V G ; the drain of the NMOS transistor Mn3 is externally connected to the power supply voltage VDD; the source and substrate of the NMOS transistor Mn3 are both externally grounded to the ground level VSS.

[0019] Other advantages of the present invention will be analyzed in more detail in the subsequent embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other related drawings can also be obtained based on these drawings.

[0021] Figure 1 It is a block diagram of a mis-trigger prevention electrostatic discharge clamping circuit in an embodiment of the present invention.

[0022] Figure 2 It is a schematic diagram of a mis-trigger prevention electrostatic discharge clamping circuit in an embodiment of the present invention.

[0023] Figure 3 It is a schematic diagram of a traditional RC-triggered clamping circuit in an embodiment of the present invention.

[0024] Figure 4 It is a node voltage waveform diagram of the circuit of the present invention under electrostatic discharge event simulation in an embodiment of the present invention.

[0025] Figure 5 It is a waveform diagram of the ability of the clamping transistor of the circuit of the present invention and the traditional RC-triggered clamping circuit to discharge the electrostatic discharge current in an electrostatic discharge event in an embodiment of the present invention.

[0026] Figure 6 It is a node voltage waveform diagram of the circuit of the present invention and the traditional RC-triggered clamping circuit under normal power-on event simulation in an embodiment of the present invention.

[0027] Figure 7 It is a clamping transistor leakage waveform diagram of the circuit of the present invention and the traditional RC-triggered clamping circuit under normal power-on event simulation in an embodiment of the present invention.

[0028] Figure 8 It is a node voltage waveform diagram of the circuit of the present invention and the traditional RC-triggered clamping circuit under fast power-on event simulation in an embodiment of the present invention.

[0029] Figure 9 It is a size comparison diagram of the clamping circuit of the present invention and the traditional clamping circuit in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. The components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents the selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.

[0031] As Figure 1 shown, in an embodiment of the present invention, the present invention provides an anti-mis-trigger electrostatic discharge clamping circuit, including a control transistor, a PMOS current mirror resistor branch, an NMOS current mirror capacitor branch, an inverter, and a clamping transistor;

[0032] The control transistor is respectively connected to the PMOS current mirror resistor branch, the NMOS current mirror capacitor branch, and the inverter, and is externally connected to the power supply voltage VDD; the PMOS current mirror resistor branch is respectively connected to the NMOS current mirror capacitor branch and the inverter, and is respectively externally connected to the power supply voltage VDD and the ground level VSS; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to the inverter and is externally grounded to the ground level VSS; the inverter is connected to the clamping transistor and is respectively externally connected to the power supply voltage VDD and the ground level VSS; the clamping transistor is respectively externally connected to the power supply voltage VDD and the ground level VSS.

[0033] As Figure 2 shown, the control transistor uses a feedback-controlled PMOS transistor Mp0 as the switching transistor of the PMOS current mirror resistor branch and at the same time as the voltage-dividing transistor for normal power-on and fast power-on;

[0034] In this solution, when the PMOS transistor Mp0 is used as the switching transistor of the PMOS current mirror resistor branch, it can control the leakage current. When the PMOS transistor Mp0 is used as the voltage-dividing transistor for normal power-on and fast power-on, it can change the RC time constant to prevent mis-triggering; the RC structure refers to the resistor-capacitor structure formed by connecting the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch.

[0035] When the internal circuit of the integrated circuit is working normally, the detection signal V RC of the RC structure is at a high level, feeding back to control the gate voltage of the PMOS transistor Mp0, so that the PMOS transistor Mp0 is in an off state and controls the leakage current as the switching transistor of the PMOS current mirror resistor branch;

[0036] During normal power-on and fast power-on, since the PMOS transistor Mp0 acts as a voltage-dividing transistor, the PMOS transistor Mp1 will be in the subthreshold conduction state and the PMOS transistor Mp2 will be in the fully-conducted state. At this time, the on-resistance of the PMOS transistor Mp2 will form a new RC structure with the NMOS current mirror capacitor branch. Compared with the large RC time constant during an electrostatic discharge event, the time constant of the new RC structure is very small, within a few nanoseconds, and has a sensitive detection ability, which can accurately prevent false triggering.

[0037] The source and substrate of the PMOS transistor Mp0 are both externally connected to the power supply voltage VDD; the gate of the PMOS transistor Mp0 is respectively connected to the PMOS current mirror resistance branch and the NMOS current mirror capacitor branch for receiving the detection signal V of the RC structure RC to form a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistance branch.

[0038] The PMOS current mirror resistance branch includes a PMOS transistor Mp1, a PMOS transistor Mp2, and a resistor R;

[0039] The substrate of the PMOS transistor Mp1 is externally connected to the power supply voltage VDD; the source of the PMOS transistor Mp1 is connected to the drain of the PMOS transistor Mp0; the gate of the PMOS transistor Mp1 is respectively connected to the drain, one end of the resistor R, and the gate of the PMOS transistor Mp2; the other end of the resistor R is externally connected to the ground level VSS; the source and substrate of the PMOS transistor Mp2 are both externally connected to the power supply voltage VDD; the drain of the PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch for generating the detection signal V of the RC structure RC In this solution, V A is the node voltage between the PMOS transistor Mp0 and the PMOS transistor Mp1, and V B is the common gate voltage of the PMOS transistor Mp1 and the PMOS transistor Mp2 in the PMOS current mirror resistance branch.

[0040] In this solution, the resistance branch of the PMOS current mirror is equivalent to a large resistor, and its current is reduced by a factor of several times, and then the capacitor is charged. A group of current mirrors that amplify the resistor R in the resistance branch of the PMOS current mirror adopt a PMOS structure. Through the multiple relationship of the MOSFET width-to-length ratio, the large current flowing through the resistor is reduced by about 9 times after passing through the current mirror composed of PMOS transistor Mp1 and PMOS transistor Mp2, and then the capacitor is charged. Therefore, the capacitor needs a longer time to reach the threshold voltage for the inverter to invert. Therefore, the resistance branch of the PMOS current mirror provided by the present invention is equivalent to a large resistor. In addition, the present invention controls the leakage current of the resistance branch of the PMOS current mirror through PMOS transistor Mp0, and the gate of PMOS transistor Mp0 is connected to the middle node of the RC structure.

[0041] The NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitive manner;

[0042] The source of the PMOS transistor Mp3 is respectively connected to the drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and the inverter to generate a detection signal V of the RC structure RC ; the gate of the PMOS transistor Mp3 is respectively connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0; the source and the substrate of the NMOS transistor Mn0 are both externally grounded to the ground level VSS; the source and the substrate of the NMOS transistor Mn1 are both externally grounded to the ground level VSS.

[0043] In this solution, the NMOS current mirror capacitor branch can multiply the capacitance value of the PMOS transistor Mp3 connected in a capacitive manner and is equivalent to a large capacitor. The inverted ratio current mirror structure adopted by the NMOS current mirror capacitor branch to amplify the impedance of the capacitor realizes an impedance amplification of about 45 times through the multiple relationship of the MOSFET width-to-length ratio, effectively increasing the resistance value of the capacitor. In addition, since the inverted ratio current mirror structure is adopted in this solution, it can be found according to the relationship between the NMOS transistor current voltage and the width-to-length ratio that: under the same voltage, the smaller the width-to-length ratio of the NMOS transistor, the smaller the current, thus reducing the leakage current of the circuit.

[0044] The inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2;

[0045] The gate of the PMOS transistor Mp4 is connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1 respectively; the source and substrate of the PMOS transistor Mp4 are externally connected to the power supply voltage VDD; the source and substrate of the NMOS transistor Mn2 are externally grounded to the ground level VSS; the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn2 and the clamping transistor respectively, for generating the driving voltage V G and inputting it to the clamping transistor.

[0046] In this solution, the inverter is composed of the PMOS transistor Mp4 and the NMOS transistor Mn2 to generate the driving voltage V G and input it to the clamping transistor; in order to enable the PMOS transistor Mp4 to have sufficient driving ability, its size is selected as 1 / 20 of the clamping transistor, while the driving ability of the NMOS transistor Mn2 is better than that of the PMOS transistor Mp4 and further affects the circuit delay time, so in this solution, the size of the NMOS transistor Mn2 is selected as 1 / 4 of the PMOS transistor Mp4.

[0047] The clamping transistor uses the NMOS transistor Mn3;

[0048] The gate of the NMOS transistor Mn3 is connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2 respectively, for receiving the driving voltage V G ; the drain of the NMOS transistor Mn3 is externally connected to the power supply voltage VDD; the source and substrate of the NMOS transistor Mn3 are both externally grounded to the ground level VSS.

[0049] In this solution, the clamping transistor uses the large-size NMOS transistor Mn3, which is used to turn on during electrostatic discharge according to the driving voltage V G to discharge the electrostatic discharge energy; the size of the NMOS transistor Mn3 determines the protection level of the designed Human Body Model (HBM). In this embodiment, the width / length of the channel of the selected NMOS transistor Mn3 is 1000μm / 180nm, which can achieve a failure current tolerance of 1.8A, and its HBM protection level is about 2700V.

[0050] The circuit structure in this solution is illustrated by taking the 0.18-micron, 1.8V complementary metal oxide semiconductor process as an example. Among them, the resistor R uses the POLY resistor with the largest resistance value per unit area under this complementary metal oxide semiconductor process, and the capacitor uses the active MOSFET capacitor.

[0051] The working principle of the present invention is:

[0052] (1) When an electrostatic discharge event occurs, due to the very fast power-on speed, usually within 10 ns, and the voltage across the capacitor does not change abruptly, the node voltage of the large resistor and large capacitor RC structure composed of the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch, that is, the detection signal V RC cannot change rapidly with the power supply voltage VDD. Therefore, when an electrostatic discharge event occurs, the initial voltage of the detection signal V RC is at a low level, and the detection signal V RC of the RC structure also serves as the gate control voltage of the PMOS transistor Mp0, ensuring that the PMOS transistor Mp0 is fully turned on during the electrostatic discharge event, reducing the current of the PMOS current mirror resistor branch by several times, and transmitting it to the NMOS current mirror capacitor branch for charging. The detection signal V RC will form a voltage difference with the source voltage of the PMOS transistor Mp4, and the PMOS transistor Mp4 will thus be turned on, pulling up the drive voltage V G to the power supply voltage VDD, thereby turning on the NMOS transistor Mn3 to discharge the electrostatic discharge energy.

[0053] In an electrostatic discharge event, the power-on time is between 100 ps and 60 ns, while the HBM electrostatic discharge duration is usually between 500 ns and 1 μs. According to the requirements of the electrostatic discharge event for the discharge time and fast and accurate detection, the RC time constant is usually set to 500 ns, which requires relatively large resistors and capacitors. In some processes, due to the small resistance value and capacitance value per unit area, it will occupy a relatively large layout area. And the design of a single RC time constant often weakens the anti-mis-triggering performance during fast power-on. However, in the circuit of the present invention, the equivalent amplification of the resistor and capacitor is realized through the current mirror structure, and a relatively large RC time constant can be designed only with relatively small resistors and capacitors, making the selection of the RC time constant no longer limited to the selection of resistors and capacitors, effectively saving the layout area. Moreover, in this solution, by introducing a control transistor with feedback control to play a voltage-dividing role during normal power-on and fast power-on, a new RC structure with a small RC time constant is formed by the circuit during normal power-on and fast power-on, making the RC time constant within the range of several nanoseconds, having good anti-mis-triggering characteristics.

[0054] (2) During normal power-on, the power supply voltage VDD on the power supply line rises from 0 to the operating voltage within a relatively long time (usually from 1 μs to 1 ms). In this embodiment, taking the operating voltage of 1.8 V as an example. Due to the slow power-on speed, the node voltage of the large resistor and large capacitor RC network composed of the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch, that is, the detection signal V RC will change with the power supply voltage VDD. Therefore, the PMOS transistor Mp0 is in the off state, and the gate-source voltage V Bwill also be lower than its turn-on threshold, and the PMOS transistor Mp2 is in a fully conducting state. Its on-resistance will form a new small time constant RC structure with the NMOS current mirror capacitor branch. Since the source voltage and the gate voltage of the PMOS transistor Mp4 change synchronously, the maximum gate-source voltage is 0, and the PMOS transistor Mp4 is turned off. The NMOS transistor Mn2 is turned on as the gate voltage increases, and the driving voltage V G will be pulled down to 0, the NMOS transistor Mn3 is turned off, and the entire circuit is in the off state.

[0055] (3) When some other special fast power-on events occur, the power supply voltage VDD will rise from 0 to the operating voltage in a very short time (usually from dozens to hundreds of nanoseconds). The situation at this time is similar to that of an electrostatic discharge event, and there may be a situation of false triggering caused by confusion with the electrostatic discharge pulse. In the detection of fast power-on of the circuit of the present invention, the power supply voltage VDD is 1.8V. Due to the voltage division of the control transistor, the PMOS transistor Mp1, and the resistor R, the voltage difference between V A and V B is less than the turn-on threshold of the PMOS transistor Mp1, and the PMOS transistor Mp1 is in the sub-threshold conduction state. The gate voltage of the PMOS transistor Mp2 is only a few millivolts, and its source is externally connected to the power supply VDD, so it is fully conducting. At this time, a new RC structure is mainly composed of the fully conducting PMOS transistor Mp2 and the NMOS current mirror capacitor branch. Since the on-resistance of the PMOS transistor Mp2 is very small, it will make the overall RC time constant of the new RC result smaller, and the detection signal of the corresponding new RC structure will closely follow the power supply voltage VDD, resulting in the PMOS transistor Mp4 in the inverter not being turned on, and the NMOS transistor Mn2 being turned on, realizing the pull-down drive of the driving voltage V G , to turn off the NMOS transistor Mn3, so that the entire circuit is in the off state, and thus can effectively avoid false triggering in the case of fast power-on.

[0056] In a practical example of the present invention, the present invention performs characteristic simulation on the voltage and current of the node in the electrostatic discharge event based on the electrostatic discharge clamping circuit provided by the present invention for anti-false triggering, and conducts a comparative verification under the same conditions with the traditional RC-triggered clamping circuit.

[0057] As Figure 3 shown, the traditional RC-triggered clamping circuit includes an RC detection network, an inverter, and a clamping transistor;

[0058] The RC detection network includes a resistor R1 and a capacitor C1; one end of the resistor R1 is externally connected to a power supply VDD; the other end of the resistor R1 is respectively connected to one end of the capacitor C1 and an inverter, and a node RC0 is formed at the connection between the RC detection network and the directioner, and the corresponding node voltage is used as the detection signal V of the traditional RC-triggered clamping circuit RC0 ; the other end of the capacitor C1 is externally grounded to a ground level VSS; the inverter includes a PMOS transistor Mp10 and an NMOS transistor Mn10; the source and substrate of the PMOS transistor Mp10 are both externally connected to the power supply VDD; the gate of the PMOS transistor Mp10 is respectively connected to the other end of the resistor R1 and the gate of the NMOS transistor Mn10; the drain of the PMOS transistor Mp10 is respectively connected to the drain of the NMOS transistor Mn10 and a clamping transistor, and transmits a driving voltage V to the clamping transistor G0 ; the source and substrate of the NMOS transistor Mn10 are both externally grounded; the clamping transistor uses an NMOS transistor Mn11; the gate of the NMOS transistor Mn11 is connected to the drain of the NMOS transistor Mn10; the source and substrate of the NMOS transistor Mn11 are externally grounded to the ground level VSS; the drain of the NMOS transistor Mn11 is externally connected to the power supply VDD

[0059] As Figure 4 shown, during the simulation process, the rise time of the amplitude of the power supply voltage VDD rising from 0V to 4V is set to 10ns, and the detection signal V in the circuit of the present invention RC (V of the present invention RC ), the driving voltage V G (V of the present invention G ), the node voltage V between the PMOS transistor Mp0 and the PMOS transistor Mp1 A (V of the present invention A ), and the common gate voltage V of the PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistor branch B (V of the present invention B ) are simulated and observed: under an electrostatic discharge event, the PMOS transistor Mp0 is fully turned on, making V of the present invention A close to the power supply voltage VDD, and V of the present invention B remains at about 2.8V, ensuring that both can be fully turned on. V of the present invention RC can follow the change of the power supply voltage VDD in the first 1-2ns when the power supply voltage VDD is powered on. After V of the present invention RC rises to 1.2V, the power supply voltage VDD powers on at a faster speed, and V of the present invention RCIt cannot follow the change of the power supply voltage VDD, and a voltage difference appears between the two. The voltage difference changes from 2.8V to 0.4V. Among them, the duration greater than the threshold voltage of the PMOS transistor Mp4 during the change process is about 600ns, and the gate voltage V of the NMOS transistor Mn3 G changes from 3.6V to below 0.4V during this period, ensuring that the NMOS transistor Mn3 has enough time to discharge the electrostatic discharge energy.

[0060] As Figure 5 shown, under the simulation condition that the rise time of the amplitude of the power supply voltage VDD from 0V to 4V is 10ns, the traditional electrostatic discharge circuit can continuously discharge an electrostatic discharge current of about 1.8A, that is, the traditional i_clamp is about 1.8A. The circuit of the present invention can continuously discharge an electrostatic discharge current of about 1.6A under this condition, that is, the i_clamp of the present invention is about 1.6A.

[0061] In another practical example of the present invention, the circuit of the present invention is simulated under the condition of normal power-on of the integrated circuit, and compared and verified with the traditional RC-triggered clamping circuit under the same conditions.

[0062] As Figure 6 and Figure 7 shown, during the simulation process, the rise time of the amplitude of the power supply voltage VDD from 0V to 1.8V is set to 10ns, and the detection signal V in the circuit of the present invention RC (V of the present invention RC ), the node voltage V between the PMOS transistor Mp0 and the PMOS transistor Mp1 A (V of the present invention A ), the common gate voltage V of the PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistance branch B (V of the present invention B ), the electrostatic discharge current of the circuit of the present invention (i_clamp of the present invention), and the detection signal V of the traditional RC-triggered clamping circuit RC0 (traditional V RC0 ), the electrostatic discharge current discharged by the traditional discharge circuit (traditional i_clamp) are simulated and observed: during the entire power-on process, V of the present invention RC follows the change of the power supply voltage VDD more closely than the traditional V RC0 . The voltage difference between V of the present invention RC and the power supply voltage is always less than the turn-on threshold voltage of the PMOS transistor Mp0, controlling the transistor to be in the off state. V of the present invention A changes around 0.4V, and V of the present invention BChanging around 0V, the PMOS transistor Mp1 is in subthreshold conduction and the PMOS transistor Mp2 is turned on. The PMOS transistor Mp4 in the inverter is turned off and the NMOS transistor Mn2 is turned on. In the present invention, V G is pulled down to 0V, and when in the present invention V G is pulled down to 0V and the NMOS transistor Mn3 is not turned on, then the maximum value of i_clamp in the present invention is about 250 nA and stabilizes at about 70 nA.

[0063] In another practical example of the present invention, the circuit of the present invention is simulated under the condition of rapid power-on of the integrated circuit, and is verified by comparison under the same conditions with a traditional RC-triggered clamping circuit.

[0064] As Figure 8 shown, during the simulation, the rise time of the amplitude of the power supply voltage VDD from 0V to 1.8V is set to 100 ns, and the detection signal V RC in the circuit of the present invention (V RC of the present invention), the node voltage V A between the PMOS transistor Mp0 and the PMOS transistor Mp1 (V A of the present invention), the common gate voltage V B of the PMOS transistors Mp1 and Mp2 in the PMOS current mirror resistance branch (V B of the present invention), and the detection signal V RC0 of the traditional RC-triggered clamping circuit (V RC0 of the traditional) are simulated and observed: Compared with normal power-on, the power-on time of rapid power-on is very fast and it is very easy to be confused with electrostatic discharge events. In the present invention, under the condition of rapid power-on, due to the control of the PMOS transistor Mp0, V A of the present invention stabilizes at about 0.4V, V B of the present invention stabilizes at about 0V, the subthreshold conduction of the PMOS transistor Mp1 and the on-resistance of the PMOS transistor Mp2 are very small, and the overall equivalent RC time constant is also small, within the range of several nanoseconds, and it can better cope with rapid power-on events. V RC of the present invention follows the change of the power supply VDD more closely, and the voltage difference between the two is always below 0.4V, less than the turn-on threshold voltage of the transistor, and the NMOS transistor Mn3 is not turned on. While the V RC0 of the traditional RC-triggered clamping circuit cannot follow VDD closely under this simulation condition, and the voltage difference between the two is always greater than 0.4V within 1 µs after power-on starting from 0, that is, greater than the turn-on threshold voltage of the transistor, and the PMOS transistor Mp10 will be turned on accordingly, pulling up the gate voltage V G0, the NMOS transistor Mn11 will be accidentally triggered. In contrast, the present invention can better handle a rapid power-on event of 100 ns, having better ability to handle rapid power-on events and good anti-accidental trigger characteristics.

[0065] As Figure 9 shown, since the circuit of the present invention, compared with the traditional RC-triggered clamping circuit, except for the different RC network structures, the inverter circuit and the clamping transistor sizes are the same, so it has almost the same ESD protection ability. However, as can be seen from Figure 4 the ability of the clamping transistor in to discharge the electrostatic discharge current. Although the traditional scheme selects the resistors and capacitors with the largest resistance and capacitance per unit area in the process, it still occupies more than half of the layout area, resulting in a large area waste. The scheme proposed by the present invention significantly reduces the layout area through an optimized RC structure. The size of the clamping circuit of the present invention (53 µm × 27 µm) realizes an area optimization of about 60% compared with the size of the traditional clamping circuit (100 µm × 39 µm).

[0066] As described above, the above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention.

Claims

1. An electrostatic discharge clamping circuit with anti-mis-triggering, characterized in that, It includes a control transistor, a PMOS current mirror resistor branch, an NMOS current mirror capacitor branch, an inverter, and a clamping transistor; The control transistor is respectively connected to the PMOS current mirror resistor branch, the NMOS current mirror capacitor branch, and the inverter, and is externally connected to the power supply voltage VDD; the PMOS current mirror resistor branch is respectively connected to the NMOS current mirror capacitor branch and the inverter, and is externally connected to the power supply voltage VDD and the ground level VSS; the PMOS current mirror resistor branch and the NMOS current mirror capacitor branch form an RC structure; the NMOS current mirror capacitor branch is connected to the inverter and is externally grounded to the ground level VSS; the inverter is connected to the clamping transistor and is respectively externally connected to the power supply voltage VDD and the ground level VSS; the clamping transistor is respectively externally connected to the power supply voltage VDD and the ground level VSS.

2. The electrostatic discharge clamping circuit for preventing mis-triggering according to claim 1, wherein The control transistor uses a PMOS transistor Mp0 with feedback control, serves as the switching transistor of the PMOS current mirror resistor branch, and at the same time serves as the voltage dividing transistor for normal power-on and fast power-on; The source and substrate of the PMOS transistor Mp0 are both externally connected to the power supply voltage VDD; the gate of the PMOS transistor Mp0 is respectively connected to the PMOS current mirror resistance branch and the NMOS current mirror capacitance branch for receiving the detection signal V of the RC structure RC , forming a feedback structure; the drain of the PMOS transistor Mp0 is connected to the PMOS current mirror resistance branch.

3. The electrostatic discharge clamping circuit for preventing mis-triggering according to claim 2, wherein, The PMOS current mirror resistor branch includes a PMOS transistor Mp1, a PMOS transistor Mp2, and a resistor R; The substrate of the PMOS transistor Mp1 is externally connected to the power supply voltage VDD; the source of the PMOS transistor Mp1 is connected to the drain of the PMOS transistor Mp0; the gate of the PMOS transistor Mp1 is respectively connected to the drain, one end of the resistor R, and the gate of the PMOS transistor Mp2; the other end of the resistor R is externally grounded to the level VSS; the source and substrate of the PMOS transistor Mp2 are both externally connected to the power supply voltage VDD; the drain of the PMOS transistor Mp2 is connected to the NMOS current mirror capacitor branch to be used for generating the detection signal V of the RC structure RC .

4. The electrostatic discharge clamping circuit for preventing mis-triggering according to claim 3, characterized in that, The NMOS current mirror capacitor branch includes a PMOS transistor Mp3, an NMOS transistor Mn0, and an NMOS transistor Mn1 connected in a capacitor manner; The source of the PMOS transistor Mp3 is respectively connected to the drain, the substrate, the drain of the PMOS transistor Mp2, the gate of the PMOS transistor Mp0, the drain of the NMOS transistor Mn1, and an inverter to generate a detection signal V of the RC structure RC ; the gate of the PMOS transistor Mp3 is respectively connected to the gate of the NMOS transistor Mn1, the drain and the gate of the NMOS transistor Mn0; the source and the substrate of the NMOS transistor Mn0 are both externally grounded to the ground level VSS; the source and the substrate of the NMOS transistor Mn1 are both externally grounded to the ground level VSS.

5. The electrostatic discharge clamping circuit for preventing mis-triggering according to claim 4, characterized in that, The inverter includes a PMOS transistor Mp4 and an NMOS transistor Mn2; The gate of the PMOS transistor Mp4 is connected to the gate of the NMOS transistor Mn2 and the drain of the NMOS transistor Mn1 respectively; the source and substrate of the PMOS transistor Mp4 are externally connected to the power supply voltage VDD; the source and substrate of the NMOS transistor Mn2 are externally grounded to the ground level VSS; the drain of the PMOS transistor Mp4 is connected to the drain of the NMOS transistor Mn2 and the clamping transistor respectively, for generating a driving voltage V G and input it to the clamping transistor.

6. The electrostatic discharge clamping circuit for preventing mis-triggering according to claim 5, wherein The clamping transistor uses an NMOS transistor Mn3; The gate of the NMOS transistor Mn3 is connected to the drain of the PMOS transistor Mp4 and the drain of the NMOS transistor Mn2 respectively, for receiving a driving voltage V G ; the drain of the NMOS transistor Mn3 is externally connected to a power supply voltage VDD; the source and the substrate of the NMOS transistor Mn3 are both externally grounded to a ground level VSS.

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