Floating power supply, circuit system and electronic equipment

Abstract

The invention provides a floating power supply, a circuit system and electronic equipment. The floating power supply comprises a voltage drop bias unit, a bias current source, a power supply transistor, a first voltage stabilizing transistor and a second voltage stabilizing transistor, the voltage drop bias unit carries out fixed voltage drop on an external input power supply according to the bias current of the bias current source to obtain a bias voltage and outputs the bias voltage; the power transistor follows the bias voltage to obtain a power supply voltage and outputs the power supply voltage to a load from a first end of the power transistor. The first voltage stabilizing transistor and the second voltage stabilizing transistor form a current mirror structure, and the width-to-length ratio of the first voltage stabilizing transistor and the second voltage stabilizing transistor is greater than 1, so that the load current flowing through the power supply transistor is at least doubled, and the area requirement on the power supply transistor is at least doubled, namely, the influence of power supply voltage jump on the bias of the power supply transistor is reduced; therefore, rapid stabilization of the power supply voltage can be realized through a current source with smaller output, and finally low-cost and low-power-consumption power supply voltage stabilization is realized.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular, to a floating power supply, a circuit system, and an electronic device. Background Art

[0002] In high-voltage applications, for the purposes of protecting low-voltage circuits, ensuring effective driving of power switching elements, or optimizing energy efficiency, etc., a supply voltage with a fixed voltage drop relative to an external input power supply is usually generated by a floating power supply to supply power to a load.

[0003] However, when the load current changes suddenly, the prior art usually sacrifices circuit area and circuit power consumption to maintain the stability of the supply voltage. Summary of the Invention

[0004] The present invention provides a floating power supply, a circuit system, and an electronic device to maintain the stability of the supply voltage on the basis of low cost and low power consumption.

[0005] To solve the above technical problems, the technical solution of the present invention provides a floating power supply, including:

[0006] A bias current source, the cathode of the bias current source is connected to the ground terminal;

[0007] A voltage-drop bias unit, the input end of the voltage-drop bias unit is connected to an external input power supply, the output end of the voltage-drop bias unit is connected to the anode of the bias current source, and the voltage-drop bias unit is used to perform a fixed voltage drop on the external input power supply according to the bias current output by the bias current source to form and output a bias voltage;

[0008] A power transistor, the control end of the power transistor is connected to the output end of the voltage-drop bias unit, and the power transistor is used to perform voltage following on the bias voltage to obtain a supply voltage and output it from its first end to a corresponding load;

[0009] A first voltage-regulating transistor and a second voltage-regulating transistor, the second end of the first voltage-regulating transistor is connected to the second end of the power transistor, the control end of the first voltage-regulating transistor is respectively connected to its own second end and the control end of the second voltage-regulating transistor, the second end of the second voltage-regulating transistor is connected to the first end of the power transistor, the first ends of the first voltage-regulating transistor and the second voltage-regulating transistor are both connected to the ground terminal, and the width-to-length ratio between the second voltage-regulating transistor and the first voltage-regulating transistor is greater than 1.

[0010] Optionally, it further includes a third voltage-regulating transistor, the second end of the third voltage-regulating transistor is connected to the control end of the power transistor, the control end of the third voltage-regulating transistor is connected to the control end of the first voltage-regulating transistor, and the first end of the third voltage-regulating transistor is connected to the ground terminal.

[0011] Optionally, the voltage drop biasing unit includes a biasing transistor and a fixed voltage drop sub-unit. The fixed voltage drop sub-unit is coupled between the external input power supply and the first end of the biasing transistor. The fixed voltage drop sub-unit is configured to perform a fixed voltage drop on the external input power supply according to the biasing current. The control end of the biasing transistor serves as the output end of the voltage drop biasing unit and is connected to the anode of the biasing current source. The second end of the biasing transistor is connected to its own control end.

[0012] Optionally, both the biasing transistor and the power transistor are PMOS transistors. The first ends of the biasing transistor and the power transistor are the sources of the PMOS transistors respectively. The second ends of the biasing transistor and the power transistor are the drains of the PMOS transistors respectively. The control ends of the biasing transistor and the power transistor are the gates of the PMOS transistors respectively.

[0013] Optionally, both the biasing transistor and the power transistor are PNP bipolar transistors. The first ends of the biasing transistor and the power transistor are the collectors of the PNP bipolar transistors respectively. The second ends of the biasing transistor and the power transistor are the emitters of the PNP bipolar transistors respectively. The control ends of the biasing transistor and the power transistor are the bases of the PNP bipolar transistors respectively.

[0014] Optionally, the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor all include NMOS transistors. The first ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the sources of the NMOS transistors respectively. The second ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the drains of the NMOS transistors respectively. The control ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the gates of the NMOS transistors respectively.

[0015] Optionally, the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor all include NPN bipolar transistors. The first ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the collectors of the NPN bipolar transistors respectively. The second ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the emitters of the NPN bipolar transistors respectively. The control ends of the first voltage stabilizing transistor, the second voltage stabilizing transistor, and the third voltage stabilizing transistor are the bases of the NPN bipolar transistors respectively.

[0016] Optionally, the fixed voltage drop sub-unit includes a Zener diode. The negative electrode of the Zener diode is connected to the external input power supply, and the positive electrode of the Zener diode is connected to the first end of the biasing transistor.

[0017] The technical solution of the present invention also provides a circuit system, including the floating power supply.

[0018] The technical solution of the present invention also provides an electronic device, including the circuit system.

[0019] Compared with the prior art, the technical solution provided by the present invention has the following beneficial effects:

[0020] The floating power supply provided by the technical solution of the present invention, by setting the first voltage stabilizing transistor and the second voltage stabilizing transistor of the current mirror structure, and setting the aspect ratio ratio between the second voltage stabilizing transistor and the first voltage stabilizing transistor to be greater than 1, so that the load current flowing through the power transistor is reduced by at least 1 time, and further the area requirement for the power transistor is also reduced by at least 1 time. Since the area requirement for the power transistor is reduced by at least 1 time, the parasitic capacitance between the control terminal and the first terminal of the power transistor itself can also be reduced by a factor of two, thereby reducing the influence of the supply voltage on the control terminal of the power transistor. Further, when the supply voltage jumps, the bias current output by the bias current source can make the control terminal voltage of the power transistor recover to the bias voltage faster, so as to ensure the stability of the supply voltage. Also, because the present invention controls the aspect ratio ratio between the second voltage stabilizing transistor and the first voltage stabilizing transistor without additionally increasing the area of the power transistor and the output current of the bias current source, the stability of the supply voltage is achieved on the basis of low cost and low power consumption.

[0021] Further, the third voltage stabilizing transistor is additionally provided. Since the third voltage stabilizing transistor and the second voltage stabilizing transistor form a current mirror, and the second terminal of the third voltage stabilizing transistor is connected to the control terminal of the voltage stabilizing transistor, the current flowing through the third voltage stabilizing transistor is positively correlated with the mutated load current. When the load current mutates, the current flowing through the third voltage stabilizing transistor cooperates with the bias current to further accelerate the recovery of the control terminal voltage of the power transistor to the bias voltage, thereby further improving the stability of the supply voltage. Description of the Drawings

[0022] Figure 1 It is a schematic circuit structure diagram of an embodiment of a floating power supply;

[0023] Figure 2 It is a schematic circuit structure of the floating power supply provided by the embodiment of the present invention Figure 1 ;

[0024] Figure 3 It is a schematic circuit structure of the floating power supply provided by the embodiment of the present invention Figure 2 ;

[0025] Figure 4 Schematic diagram of the circuit structure of the floating power supply provided by the embodiment of the present invention Figure 3 ;

[0026] Figure 5 Schematic diagram of the circuit structure of the floating power supply provided by the embodiment of the present invention Figure 4 。 Detailed implementation manners

[0027] As described in the background art, when the load current changes suddenly in the prior art, it usually sacrifices circuit area and circuit power consumption to maintain the stability of the supply voltage. The problems existing in the prior art are illustrated by an embodiment of a floating power supply as follows:

[0028] Figure 1 It is a schematic diagram of the circuit structure of an embodiment of a floating power supply.

[0029] Please refer to Figure 1 , this embodiment of the floating power supply includes a Zener diode D0, a first PMOS transistor MP0, a second PMOS transistor MP1, and a current source Ibias.

[0030] The Zener diode D0 is coupled between an external input power supply Vin and the source of the first PMOS transistor MP0. The anode of the current source Ibias is connected to the drain of the first PMOS transistor MP0, and the cathode of the current source Ibias is connected to the ground terminal. The current source Ibias outputs a bias current, and this bias current flows through the Zener diode D0, thereby providing a fixed voltage drop between the external input power supply Vin and the source of the first PMOS transistor MP0.

[0031] The gate of the first PMOS transistor MP0 is respectively connected to its own drain and the gate of the second PMOS transistor MP1. The source of the second PMOS transistor MP1 outputs a supply voltage Vout to the load, and the drain of the second PMOS is connected to the ground terminal.

[0032] The first PMOS transistor MP0 is used to perform voltage stabilization biasing on the gate of the second PMOS transistor MP1, and by setting the first PMOS transistor MP0 and the second PMOS transistor MP1 to be both matched in size and current, the source voltage of the first PMOS transistor MP0 is approximated to the source voltage of the second PMOS transistor MP1. Therefore, the formula for the source voltage of the second PMOS transistor MP1, that is, the supply voltage Vout, is as follows:

[0033] Vout = Vin - Vdrop Formula (1)

[0034] Among them, Vout is used to represent the supply voltage, Vin is used to represent the external input power supply, and Vdrop is used to represent the fixed voltage drop when the Zener diode is broken down.

[0035] However, the problem with this embodiment is that when the high-side power switch transistor is turned on, a large transient current will be generated, resulting in the increase of the supply voltage Vout. And the increase of the supply voltage Vout usually leads to problems such as abnormal function of the load circuit, damage to the stability of the bias circuit, and aggravation of noise and electromagnetic interference. Therefore, in order to maintain the stability of the supply voltage Vout, it is necessary to increase the width-to-length ratio of the second PMOS transistor MP1 to reduce its own on-resistance, thereby improving the current driving ability of the second PMOS transistor MP1 to reduce the jump amplitude of the supply voltage Vout, and further maintaining the stability of the supply voltage Vout. However, increasing the width-to-length ratio of the second PMOS transistor MP1 will also increase the gate-source capacitance of the second PMOS transistor MP1, exacerbating the jump of the supply voltage Vout being transmitted to the gate of the second PMOS transistor MP1, thus forming a positive feedback for the increase of the supply voltage Vout, and exacerbating the increase of the supply voltage Vout. At this time, it is necessary to make the current source Ibias output a sufficient large bias current to pull down the gate voltage of the second PMOS transistor MP1, so as to accelerate the gate voltage of the second PMOS transistor MP1 to recover to the original preset voltage, thereby maintaining the stability of the supply voltage Vout.

[0036] Therefore, when the load current jumps in this embodiment, in order to maintain the stability of the supply voltage Vout, it is necessary to set the second PMOS transistor MP1 to have a sufficient large width-to-length ratio and the current source Ibias to output a sufficient large bias current at the same time, thus greatly increasing the circuit area and circuit power consumption.

[0037] In view of this, the embodiment of the present invention provides a new floating power supply to maintain the stability of the supply voltage on the basis of low cost and low power consumption.

[0038] To make the above objects, features, and beneficial effects of the present invention more obvious and understandable, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units does not necessarily limit to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products, or devices.

[0039] Figure 2 Schematic circuit structure of the floating power supply provided by the embodiment of the present invention Figure 1 。

[0040] Please refer to Figure 2 , the floating power supply provided by the embodiment of the present invention includes:

[0041] A voltage drop bias unit 10 and a bias current source Ibias1; the input end of the voltage drop bias unit 10 is connected to an external input power supply VIN, the output end of the voltage drop bias unit 10 is connected to the anode of the bias current source Ibias1, the cathode of the bias current source Ibias1 is connected to the ground end, and the voltage drop bias unit 10 is used to perform a fixed voltage drop on the external input power supply VIN according to the bias current output by the bias current source Ibias1 to obtain a bias voltage Vbias and output it;

[0042] A power transistor M1, a first voltage stabilizing transistor M2, and a second voltage stabilizing transistor M3; a control end of the power transistor M1 is connected to an output end of the voltage drop biasing unit 10, and the power transistor M1 is configured to perform voltage following on the bias voltage Vbias to obtain a supply voltage and output the supply voltage from its first end to a corresponding load; a second end of the first voltage stabilizing transistor M2 is connected to the second end of the power transistor M1, a control end of the first voltage stabilizing transistor M2 is respectively connected to its second end and a control end of the second voltage stabilizing transistor M3, a second end of the second voltage stabilizing transistor M3 is connected to the first end of the power transistor M1, a first end of the first voltage stabilizing transistor M2 and a first end of the second voltage stabilizing transistor M3 are both connected to a ground end, and a ratio of a channel width to a channel length between the second voltage stabilizing transistor M3 and the first voltage stabilizing transistor M2 is greater than 1.

[0043] Normally, the supply voltage of the floating power supply needs to be stabilized at a fixed voltage drop with respect to the external input power supply VIN. When the external input power supply VIN does not change, the supply voltage should also remain stable, that is, the supply voltage should stably equal the bias voltage Vbias. However, when a transient large current is generated in the load due to the conduction of the driving switch, the supply voltage at the first end of the current transistor will jump up. Therefore, in order to maintain the stability of the supply voltage when a transient large current is generated in the load, it is necessary to quickly pull down the supply voltage to the bias voltage Vbias.

[0044] In the embodiments of the present invention, when the load generates a transient large current, the power transistor M1 and the second voltage stabilizing transistor M3 will also provide corresponding transient large currents to suppress the jump of the supply voltage. Moreover, the larger the transient large currents provided by the power transistor M1 and the second voltage stabilizing transistor M3, the smaller the jump amplitude of the supply voltage. At the same time, in the embodiments of the present invention, the aspect ratio ratio between the second voltage stabilizing transistor M3 and the first voltage stabilizing transistor M2 is also set to be greater than 1, so that the transient current flowing through the power transistor M1 is reduced by 1 times compared with the case where the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are not provided, thereby reducing the area requirement of the power transistor M1 by several times, and further reducing the parasitic capacitance between the control terminal and the first terminal of the power transistor M1 by several times. Since when the supply voltage jumps, this voltage change will be transferred to the control terminal of the power transistor M1 through the parasitic capacitance, which further exacerbates the jump of the supply voltage. Therefore, the several-fold reduction of the parasitic capacitance can greatly reduce the influence of the jump of the supply voltage on the control terminal of the power transistor M1, thereby accelerating the bias current source Ibias1 to pull down the voltage at the control terminal of the power transistor M1 to the bias voltage Vbias. Therefore, setting a bias current source Ibias1 with a smaller output can also meet the stability requirement of the circuit for the supply voltage, thereby reducing the power consumption of the circuit.

[0045] Therefore, compared with the above floating power supply embodiments, the embodiments of the present invention only need to set a bias current source Ibias1 with a smaller output and a power transistor M1 with a smaller area to meet the stability requirement of the supply voltage, thereby realizing the stability of the supply voltage on the basis of low power consumption and low cost.

[0046] It should be noted that since the transient large current generated by the load will vary with different application scenarios, the aspect ratio ratio between the second voltage stabilizing transistor M3 and the first voltage stabilizing transistor M2 can be adaptively set according to specific application scenarios and will not be limited herein.

[0047] Figure 3 Schematic diagram of the circuit structure of the floating power supply provided by the embodiments of the present invention Figure 2 。

[0048] Please refer to Figure 2 and Figure 3As a specific implementation, the voltage drop bias unit 10 includes a bias transistor M4 and a fixed voltage drop sub-unit 11, the fixed voltage drop sub-unit 11 is coupled between the external input power supply VIN and the first end of the bias transistor M4, and the fixed voltage drop sub-unit 11 is used to perform a fixed voltage drop on the external input power supply VIN according to the bias current; the control end of the bias transistor M4 serves as the output end of the voltage drop bias unit 10 and is connected to the anode of the bias current source Ibias1, and the second end of the bias transistor M4 is connected to its own control end.

[0049] Figure 4 A schematic diagram of a circuit structure of a floating power supply provided in an embodiment of the present invention Figure 3 .

[0050] Please refer to Figure 4 Specifically, the fixed voltage drop subunit 11 includes a Zener diode D1, a cathode of the Zener diode D1 is connected to the external input power source VIN, and an anode of the Zener diode D1 is connected to the first end of the bias transistor M4. Of course, in addition to the Zener diode D1, the fixed voltage drop subunit 11 may also include other circuit devices with a fixed voltage difference, such as a resistor, etc., which is not limited here.

[0051] Specifically, Figure 3 and Figure 2 The bias transistor M4 and the power transistor M1 shown are both PMOS tubes, the first ends of the bias transistor M4 and the power transistor M1 are both sources of the PMOS tube, the second ends of the bias transistor M4 and the power transistor M1 are both drains of the PMOS tube, and the control ends of the bias transistor M4 and the power transistor M1 are both gates of the PMOS tube.

[0052] Figure 3 and Figure 2 The first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 shown both include NMOS tubes, the first ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are respectively the sources of the NMOS tubes, the second ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are respectively the drains of the NMOS tubes, and the control ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are respectively the gates of the NMOS tubes.

[0053] Of course, in addition to both being set as PMOS transistors, the bias transistor M4 and the power supply transistor M1 can also both be set as PNP triodes. The first ends of the bias transistor M4 and the power supply transistor M1 are both the collectors of the PNP triodes. The second ends of the bias transistor M4 and the power supply transistor M1 are both the emitters of the PNP triodes. The control ends of the bias transistor M4 and the power supply transistor M1 are both the bases of the PNP triodes.

[0054] In addition to both being set as NMOS transistors, the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 can also both be set as NPN triodes. The first ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are both the collectors of the NPN triodes. The second ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are both the emitters of the NPN triodes. The control ends of the first voltage stabilizing transistor M2 and the second voltage stabilizing transistor M3 are both the bases of the NPN triodes.

[0055] Figure 5 Schematic diagram of the circuit structure of the floating power supply provided by the embodiment of the present invention Figure 4 。

[0056] Please refer to Figure 5 , in another preferred embodiment, the floating power supply further includes a third voltage stabilizing transistor M5. The second end of the third voltage stabilizing transistor M5 is connected to the control end of the power supply transistor M1. The control end of the third voltage stabilizing transistor M5 is connected to the control end of the first voltage stabilizing transistor M2. The first end of the third voltage stabilizing transistor M5 is connected to the ground terminal.

[0057] Since the third voltage stabilizing transistor M5 and the first voltage stabilizing transistor M2 form a current source structure, the current flowing through the first voltage stabilizing transistor M2 will be mirrored to the third voltage stabilizing transistor M5. Also, because the second end of the third voltage stabilizing transistor M5 is connected to the control end of the power supply transistor M1 and the first end of the third voltage stabilizing transistor M5 is connected to the ground terminal. Therefore, the third voltage stabilizing transistor M5 introduces an additional pull-down current to the control end of the power supply transistor M1, so that when the supply voltage jumps up, the voltage at the control end of the power supply transistor M1 can be pulled down to the bias voltage Vbias more quickly, thereby further improving the stability of the supply voltage. In addition, since the current flowing through the third voltage stabilizing transistor M5 is proportional to the transient large current of the load, the larger the transient large current of the load, the larger the jump amplitude of the supply voltage, that is, the worse the stability of the supply voltage, the larger the current flowing through the third voltage stabilizing transistor M5, so that the recovery speed of the control end voltage is faster, that is, the higher the stability of the supply voltage, thereby forming a negative feedback on the stability of the supply voltage.

[0058] It should be noted that the aspect ratio ratio between the third voltage stabilizing transistor M5 and the first voltage stabilizing transistor M2 can also be adaptively set according to specific application scenarios, and is not limited herein.

[0059] Specifically, Figure 5 The shown third voltage stabilizing transistor M5 is an NMOS transistor. The first end of the third voltage stabilizing transistor M5 is the source of the NMOS transistor, the second end of the third voltage stabilizing transistor M5 is the drain of the NMOS transistor, and the control end of the third voltage stabilizing transistor M5 is the gate of the NMOS transistor.

[0060] Of course, in addition to the NMOS transistor, the third voltage stabilizing transistor M5 can also be set as an NPN bipolar transistor. The first end of the third voltage stabilizing transistor M5 is the collector of the NPN bipolar transistor, the second end of the third voltage stabilizing transistor M5 is the emitter of the NPN bipolar transistor, and the control end of the third voltage stabilizing transistor M5 is the base of the NPN bipolar transistor.

[0061] Since the structures and working principles of the voltage drop biasing unit 10, the biasing current source Ibias1, the power transistor M1, the first voltage stabilizing transistor M2, and the second voltage stabilizing transistor M3 in this embodiment are the same as those in the previous embodiment, they will not be elaborated herein.

[0062] In summary, the floating power supply provided by the embodiment of the present invention sets the first voltage stabilizing transistor and the second voltage stabilizing transistor with a current mirror structure, and sets the aspect ratio ratio between the second voltage stabilizing transistor and the first voltage stabilizing transistor to be greater than 1, so that the load current flowing through the power transistor is reduced by at least 1 time, and further the area requirement for the power transistor is also reduced by at least 1 time. Since the area requirement for the power transistor is reduced by at least 1 time, the parasitic capacitance between the control end and the first end of the power transistor itself can also be reduced by a factor of two, thereby reducing the influence of the supply voltage on the control end of the power transistor. Furthermore, when the supply voltage jumps, the bias current output by the bias current source can make the control end voltage of the power transistor recover to the bias voltage faster, so as to ensure the stability of the supply voltage. Also, because the present invention does not need to additionally increase the area of the power transistor and the output current of the bias current source, the stability of the supply voltage is achieved on the basis of low cost and low power consumption.

[0063] Furthermore, the third voltage-stabilizing transistor is additionally provided. Since the third voltage-stabilizing transistor and the second voltage-stabilizing transistor form a current mirror, and the second end of the third voltage-stabilizing transistor is connected to the control end of the voltage-stabilizing transistor, the current flowing through the third voltage-stabilizing transistor is positively correlated with the mutated load current. When the load current mutates, the current flowing through the third voltage-stabilizing transistor cooperates with the bias current to further accelerate the recovery of the control-end voltage of the power transistor to the bias voltage, thereby further improving the stability of the supply voltage.

[0064] An embodiment of the present invention further provides a circuit system, including the floating power supply..

[0065] An embodiment of the present invention further provides an electronic device, including the circuit system.

[0066] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A floating power supply, characterized in that: include: A bias current source, wherein a cathode of the bias current source is connected to a ground terminal; A voltage drop bias unit, wherein the input end of the voltage drop bias unit is connected to an external input power supply, the output end of the voltage drop bias unit is connected to the anode of the bias current source, and the voltage drop bias unit is used to perform a fixed voltage drop on the external input power supply according to the bias current output by the bias current source and output a bias voltage; A power transistor, wherein a control end of the power transistor is connected to an output end of the voltage drop bias unit, and the power transistor is used to perform voltage following on the bias voltage to obtain a power supply voltage and output it from its first end to a corresponding load; A first voltage-stabilizing transistor and a second voltage-stabilizing transistor, wherein the second end of the first voltage-stabilizing transistor is connected to the second end of the power supply transistor, the control end of the first voltage-stabilizing transistor is respectively connected to the second end of the first voltage-stabilizing transistor and the control end of the second voltage-stabilizing transistor, the second end of the second voltage-stabilizing transistor is connected to the first end of the power supply transistor, the first end of the first voltage-stabilizing transistor and the first end of the second voltage-stabilizing transistor are both connected to the ground end, and the width-to-length ratio between the second voltage-stabilizing transistor and the first voltage-stabilizing transistor is greater than 1.

2. The floating power supply according to claim 1, characterized in that: It also includes a third voltage-stabilizing transistor, a second end of the third voltage-stabilizing transistor is connected to the control end of the power transistor, the control end of the third voltage-stabilizing transistor is connected to the control end of the first voltage-stabilizing transistor, and a first end of the third voltage-stabilizing transistor is connected to the ground end.

3. The floating power supply according to claim 2, characterized in that: The voltage drop bias unit includes a bias transistor and a fixed voltage drop sub-unit, wherein the fixed voltage drop sub-unit is coupled between the external input power supply and the first end of the bias transistor, and the fixed voltage drop sub-unit is used to perform a fixed voltage drop on the external input power supply according to the bias current; the control end of the bias transistor serves as the output end of the voltage drop bias unit and is connected to the anode of the bias current source, and the second end of the bias transistor is connected to its own control end.

4. The floating power supply according to claim 3, characterized in that: The bias transistor and the power transistor are both PMOS tubes, the first ends of the bias transistor and the power transistor are both sources of the PMOS tube, the second ends of the bias transistor and the power transistor are both drains of the PMOS tube, and the control ends of the bias transistor and the power transistor are both gates of the PMOS tube.

5. The floating power supply according to claim 3, characterized in that: The bias transistor and the power transistor are both PNP transistors, the first ends of the bias transistor and the power transistor are respectively the collectors of the PNP transistor, the second ends of the bias transistor and the power transistor are respectively the emitters of the PNP transistor, and the control ends of the bias transistor and the power transistor are respectively the bases of the PNP transistor.

6. The floating power supply according to claim 3, characterized in that: The first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor all include NMOS tubes, the first ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are all sources of the NMOS tubes, the second ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are all drains of the NMOS tubes, and the control ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are all gates of the NMOS tubes.

7. The floating power supply according to claim 3, characterized in that: The first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor all include NPN transistors, the first ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are respectively the collectors of the NPN transistors, the second ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are respectively the emitters of the NPN transistors, and the control ends of the first voltage-stabilizing transistor, the second voltage-stabilizing transistor and the third voltage-stabilizing transistor are respectively the bases of the NPN transistors.

8. The floating power supply according to claim 3, characterized in that: The fixed voltage drop subunit includes a Zener diode, a cathode of the Zener diode is connected to the external input power supply, and an anode of the Zener diode is connected to the first end of the bias transistor.

9. A circuit system, characterized in that: The floating power supply comprises the floating power supply as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: A circuit system comprising the circuit system of claim 9.

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