On-time control circuit, control circuit and DC-DC conversion circuit

Abstract

According to the conduction time control circuit, the control circuit and the DC-DC conversion circuit provided by the invention, the frequency compensation circuit is introduced into the conduction time control circuit, and the frequency compensation circuit can generate the corresponding adjusting signal according to the starting signal of the power switch circuit; the adjusting signal can adjust the mirror image proportion of a variable current mirror in the turn-on time control circuit so as to regulate and control the voltage output by a voltage conversion circuit in the turn-on time control circuit. Therefore, the frequency of the turn-on time control signal output by the turn-on time control circuit reaches the required frequency (that is, the turn-on time control signal changes at a specific frequency), and the frequency locking effect of the DC-DC conversion circuit system is achieved. The scheme is not only suitable for a DC-DC conversion circuit in an ACOT mode, but also suitable for a DC-DC conversion circuit in a voltage mode with fixed frequency and a current mode with fixed frequency.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and particularly relates to a conduction time control circuit, a control circuit, and a DC-DC conversion circuit. Background Art

[0002] As a highly efficient switching power supply conversion circuit, a DC-DC (direct current to direct current) conversion circuit has the advantages of fast dynamic response, simple control, and direct control of output current, and is widely used in the power management systems of various products. Currently, control modes such as an Adaptive Constant On Time (ACOT) mode, a constant voltage mode with a fixed frequency, or a constant current mode with a fixed frequency are commonly used in DC-DC conversion circuits to achieve the control of the system frequency. However, the circuit architectures of these control modes are easily limited by PVT (P refers to the process deviation in the chip manufacturing process; V refers to the supply voltage of the chip; T refers to the operating temperature of the chip), resulting in a change in the system frequency of the DC-DC conversion circuit. Summary of the Invention

[0003] The purpose of the present invention is to provide a conduction time control circuit, a control circuit, and a DC-DC conversion circuit, which can reduce the influence of the internal resistance of the power switch transistor on the circuit frequency without increasing the area of the power switch transistor.

[0004] To achieve the above purpose, the present invention provides a conduction time control circuit for controlling the on and off of a power switch circuit in a DC-DC conversion circuit, so that the DC-DC conversion circuit converts a corresponding input voltage into an output voltage. The conduction time control circuit includes:

[0005] A current conversion circuit for converting the input voltage into an input current;

[0006] A variable current mirror coupled to the current conversion circuit and used for mirroring and amplifying the input current and then outputting it;

[0007] A voltage conversion circuit coupled to the variable current mirror and used for converting the current output by the variable current mirror into a corresponding voltage;

[0008] A first comparator, with a first input terminal coupled to the voltage conversion circuit and a second input terminal coupled to the output voltage, and used for comparing the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit to output a corresponding conduction time control signal for controlling the conduction time of the power switch circuit;

[0009] A frequency compensation circuit, coupled to the variable current mirror and used to adjust the mirror ratio of the variable current mirror so as to regulate the voltage converted by the voltage conversion circuit, enabling the frequency of the conduction time control signal output by the first comparator to reach the required frequency.

[0010] Optionally, within each switching cycle of the power switch circuit, the adjustment of the frequency compensation circuit enables the required duration for the voltage converted by the voltage conversion circuit to increase from the minimum value to the output voltage to reach a first specific value, thereby enabling the frequency of the conduction time control signal to reach a second specific value.

[0011] Optionally, the frequency compensation circuit includes:

[0012] An edge sampling circuit, used to sample the rising edge or falling edge of the turn-on signal of the power switch circuit and generate a corresponding sampling signal;

[0013] A frequency reference circuit, coupled to the edge sampling circuit and used to generate a plurality of reference pulse signals with different duty cycles according to the sampling signal;

[0014] A frequency discriminator and phase detector, coupled to the frequency reference circuit and used to generate an adjustment signal for adjusting the mirror ratio of the variable current mirror according to the corresponding reference pulse signal.

[0015] Optionally, the adjustment signal adjusts the mirror ratio of the variable current mirror, enabling the voltage converted by the voltage conversion circuit to first gradually increase non-linearly in a manner of gradually decreasing to a specific slope value with a slope, and then gradually increase linearly to the output voltage in a manner of maintaining the specific slope value with a slope.

[0016] Optionally, the frequency reference circuit includes a plurality of reference pulse circuits, and each reference pulse circuit includes:

[0017] A fluctuating voltage circuit, used to provide a fluctuating voltage with a corresponding fluctuating frequency, and the fluctuating frequencies of the fluctuating voltages output by different reference pulse circuits are different;

[0018] A threshold voltage circuit, used to provide a corresponding threshold voltage, and the magnitudes of the threshold voltages provided by different reference pulse circuits are the same or different;

[0019] A comparison circuit, coupled to the fluctuating voltage circuit, the threshold voltage circuit, and the edge sampling circuit, used to compare the fluctuating voltage with the threshold voltage under the control of the sampling signal so as to output a reference pulse signal with a corresponding duty cycle according to the comparison result.

[0020] Optionally, the fluctuating voltage circuit includes a first current source and a first capacitor. The first current source is coupled to the first capacitor and is configured to charge and discharge the capacitor. A connection node between the first current source and the first capacitor outputs the fluctuating voltage. Among them, capacitance values of the first capacitors in different reference pulse circuits are different;

[0021] and / or,

[0022] The threshold voltage circuit includes a threshold transistor. A gate of the threshold transistor is coupled to the fluctuating voltage. A source of the threshold transistor is grounded. A drain of the threshold transistor is coupled to the comparison circuit.

[0023] Optionally, the comparison circuit includes a pull-up transistor, a pull-down transistor, a control transistor, and a buffer. Gates of the pull-up transistor, the pull-down transistor, and the control transistor are respectively coupled to the edge sampling circuit. A source of the pull-up transistor is coupled to a corresponding power supply voltage. A drain of the pull-up transistor is coupled to a drain of the pull-down transistor. A source of the pull-down transistor is coupled to a drain of the control transistor. A source of the control transistor is grounded.

[0024] Optionally, each reference pulse circuit further includes a reset circuit, which is coupled to the fluctuating voltage circuit and the edge sampling circuit and is configured to reset the fluctuating voltage circuit according to a corresponding sampling signal output by the edge sampling circuit.

[0025] Optionally, the reset circuit includes a reset transistor. A gate of the reset transistor is coupled to the edge sampling circuit. A source of the reset transistor is grounded. A drain of the reset transistor is coupled to the fluctuating voltage.

[0026] Optionally, the frequency reference circuit includes first to third reference pulse circuits. The first reference pulse circuit and the second reference pulse circuit are coupled to the frequency discriminator and phase detector. The frequency discriminator and phase detector performs frequency monitoring and integration processing on reference pulse signals output by the first reference pulse circuit and the second reference pulse circuit to obtain the adjustment signal. The third reference pulse circuit is coupled to the variable current mirror. A corresponding edge of the third reference pulse signal output by the third reference pulse circuit corresponds to a moment when a slope of the voltage converted by the voltage conversion circuit decreases to the specific slope value.

[0027] Optionally, a duty cycle of the reference pulse signal output by the first reference signal pulse circuit is 0.5.

[0028] Optionally, the frequency discriminator and phase detector includes a charge pump phase-locked loop; alternatively, the frequency discriminator and phase detector includes a second current source, an upper integration transistor, a lower integration transistor, a third current source, and a second capacitor; a gate of the upper integration transistor is coupled to an output terminal of the first reference pulse circuit, a source of the upper integration transistor is coupled to one end of the third current source, a drain of the upper integration transistor is coupled to a drain of the lower integration transistor and one end of the second capacitor and outputs the adjustment signal; a gate of the lower integration transistor is coupled to an output terminal of the second reference pulse circuit, and a source of the lower integration transistor is coupled to one end of the second current source.

[0029] Optionally, the variable current mirror circuit includes:

[0030] A first mirror branch, coupled to the current conversion circuit, and configured to mirror-amplify the input current according to a first mirror ratio;

[0031] A second mirror branch, coupled to the first mirror branch, and configured to mirror-amplify the mirror current provided by the first mirror branch according to a variable second mirror ratio, and the second mirror branch has an adjustment transistor and a reference transistor, a gate of the adjustment transistor is coupled to the adjustment signal to adjust the second mirror ratio under the control of the adjustment signal, and a gate of the reference transistor is coupled to the third reference pulse signal.

[0032] Optionally, the current conversion circuit includes a first error amplifier, a conversion switch, and a first resistor, a source of the conversion switch is coupled to one end of the first resistor and a second input terminal of the first error amplifier, the other end of the first resistor is grounded, a first input terminal of the first error amplifier receives the input voltage, an output terminal of the first error amplifier is coupled to a gate of the conversion switch, and a drain of the conversion switch is coupled to the variable current mirror.

[0033] Optionally, the voltage conversion circuit includes a third capacitor and a discharge switch, one end of the third capacitor is coupled to one end of the discharge switch, a first input terminal of the first comparator, and one end of the variable current mirror, the other end of the third capacitor and the other end of the discharge switch are both grounded, and a control terminal of the discharge switch is coupled to an inverted signal of the turn-on signal of the power switch circuit.

[0034] Based on the same inventive concept, the present invention further provides a control circuit for controlling the on / off of the power switch circuit in the DC-DC conversion circuit, and the control circuit includes the on-time control circuit as described in the present invention.

[0035] Optionally, the control circuit further includes:

[0036] A PWM generator, configured to generate a pulse-width modulation signal according to the voltage of the output node of the power switch circuit and the feedback voltage of the output voltage;

[0037] A zero-crossing detection circuit, configured to detect the zero-crossing point of the voltage of the output node of the power switch circuit to generate a zero-crossing signal;

[0038] A logic control circuit, coupled to the PWM generator, the on-time control circuit, the zero-crossing detection circuit, and the power switch circuit, configured to drive the power switch circuit to conduct or turn off according to the pulse-width modulation signal, the on-time control signal, and the zero-crossing signal.

[0039] Optionally, the PWM generator includes:

[0040] A second error amplifier, configured to compare the feedback voltage with a first reference voltage to generate an error amplification signal;

[0041] A ramp generator, configured to compare the voltage of the output node of the power switch circuit with a second reference voltage to generate a ramp signal;

[0042] A second comparator, with its first input terminal coupled to the output terminal of the error amplifier and its second input terminal coupled to the output terminal of the ramp generator, configured to compare the error amplification signal and the ramp signal to generate the pulse-width modulation signal.

[0043] Based on the same inventive concept, the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit and the control circuit as described in the present invention. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

[0044] Compared with the prior art, in the technical solution of the present invention, a frequency compensation circuit is introduced into the on-time control circuit. The frequency compensation circuit can generate a corresponding adjustment signal according to the turn-on signal of the power switch circuit. The adjustment signal can adjust the mirror ratio of the variable current mirror in the on-time control circuit to regulate the voltage output by the voltage conversion circuit in the on-time control circuit, so that the frequency of the on-time control signal output by the on-time control circuit reaches the required frequency (that is, the on-time control signal changes at a specific frequency), achieving the effect of locking the frequency of the DC-DC conversion circuit system. This solution is applicable not only to the DC-DC conversion circuit in the ACOT mode, but also to the DC-DC conversion circuits in the fixed-frequency voltage mode and the fixed-frequency current mode. Description of the Drawings

[0045] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0046] Figure 1 It is a schematic structural diagram of the control circuit of the DC-DC conversion circuit according to an embodiment of the present invention.

[0047] Figure 2 It is a schematic structural diagram of the on-time control circuit according to an embodiment of the present invention.

[0048] Figure 3 is Figure 2 A schematic timing diagram of the operation of the on-time control circuit shown.

[0049] Figure 4 is Figure 2 A structural example diagram of the on-time control circuit excluding the frequency compensation circuit part shown.

[0050] Figure 5 is Figure 2 A schematic structural diagram of the frequency compensation circuit in the on-time control circuit shown.

[0051] Figure 6 is Figure 5 A schematic structural diagram of the i-th reference pulse circuit in the frequency compensation circuit shown.

[0052] Figure 7 is with Figure 6 A schematic structural diagram of the frequency compensation circuit with the reference pulse circuit shown.

[0053] Figure 8 is Figure 7 A schematic timing diagram of the operation of the first reference pulse circuit in

[0054] Figure 9 is Figure 2 A schematic structural diagram of the frequency discriminator and phase detector in the on-time control circuit shown.

[0055] Figure 10 It is a schematic structural diagram of the DC-DC conversion circuit according to another embodiment of the present invention and the DC-DC conversion circuit for which it is used. Detailed implementation manners

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention. It should be understood that the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like reference numerals refer to like elements throughout. It should be understood that when an element is referred to as being "connected to" or "coupled to" another element, it can be directly connected to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "comprises" is used to identify the presence of features, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0057] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be more clearly understood. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0058] Please refer to Figure 1 , an embodiment of the present invention provides a conduction time control circuit 100, which is used to control the on and off of the power switch circuit of the DC-DC conversion circuit, so that the DC-DC conversion circuit converts the corresponding input voltage V IN into an output voltage V OUT . The DC-DC conversion circuit has a control circuit 10 and a power stage circuit 11. The power stage circuit 11 has an inductor L, an output capacitor C OUT and electronic components and circuit structures such as a power switch circuit including at least one power switch tube. By controlling the on and off of the power switch circuit in the power stage circuit 11 through the control circuit 10, the power stage circuit 11 converts the input voltage V IN into an output voltage V OUT . The power stage circuit 11 can be any suitable topology such as a Buck topology, a Boost topology or a Buck-Boost topology.

[0059] As an example, please refer toFigure 1 , the power stage circuit 11 is a buck topology, which includes an inductor L and an output capacitor C OUT and a power switch circuit, which is formed by connecting a power switch tube HS (which can be called the upper power tube) and a power switch tube LS (which can be called the lower power tube). Among them, the power switch tube HS and the power switch tube LS can be any controllable semiconductor switch device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a triode, etc. The control circuit 10 outputs an enable signal HS_ON to the gate of the power switch tube HS to control the power switch tube HS to alternately conduct and turn off, and outputs an enable signal LS_ON to the gate of the power switch tube LS to control the power switch tube LS to alternately conduct and turn off. The source of the power switch tube HS is coupled to the input voltage V IN , the source of the power switch tube LS is grounded, and the drain of the power switch tube HS and the drain of the power switch tube LS are coupled to form the output node of the power switch circuit to generate a voltage V SW . The output node of the power switch circuit is coupled to one end of the inductor L, and the other end of the inductor L is coupled to the output capacitor C OUT to generate an output voltage V OUT . One end of the output capacitor C OUT is grounded at the other end. When the DC-DC conversion circuit is working, the enable signal HS_ON and the enable signal LS_ON are anti-phase signals.

[0060] In this embodiment, the on-time control circuit (ON_TIMER) 100 belongs to the internal circuit of the control circuit 10, which is used to generate an on-time control signal TON for controlling the on-time of the power switch tubes HS and LS according to the input voltage V IN and the output voltage V OUT of the DC-DC conversion circuit and the enable signals HS_ON and LS_ON. And the on-time control signal TON changes at a specific required frequency to achieve the purpose of frequency locking of the DC-DC conversion circuit system.

[0061] Please refer to Figure 2 , the on-time control circuit 100 includes a current conversion circuit 100a, a frequency compensation circuit 100c, a variable current mirror 100b, a voltage conversion circuit 100d and a first comparator CMP0.

[0062] Among them, the current conversion circuit 100a is coupled to the input voltage VIN and is used to convert the input voltage VIN into an input current I1 = V IN / Rton.

[0063] The variable current mirror 100b is coupled to the current conversion circuit 100a, the frequency compensation circuit 100c, and the voltage conversion circuit 100d, and is used to mirror-amplify the input current I1 into Im according to a corresponding mirror ratio (or referred to as "mirror amplification factor") under the control of the frequency compensation circuit 100c.

[0064] The voltage conversion circuit 100d is coupled to the variable current mirror 100b, and is used to convert the current Im output by the variable current mirror 100b into a corresponding voltage RAMP (such as a sawtooth wave signal).

[0065] The first input terminal (such as the non-inverting input terminal "+", for example) of the first comparator CMP0 is coupled to the voltage conversion circuit 100d to receive the voltage RAMP output by the voltage conversion circuit 100d, and the second input terminal (such as the inverting input terminal "-") receives the output voltage V OUT , and the first comparator CMP0 is used to compare the magnitude between the voltage V OUT and the voltage RAMP converted by the voltage conversion circuit, so as to output a corresponding on-time control signal TON.

[0066] The frequency compensation circuit 100c is coupled to the variable current mirror 100b, and is used to adjust the mirror ratio of the variable current mirror 100b according to the turn-on signal HS_ON of the power switch circuit (such as sampling the turn-on signal HS_ON of the power switch circuit), so as to regulate the voltage RAMP (such as a sawtooth wave signal) converted by the voltage conversion circuit 100d, so that the frequency of the on-time control signal TON output by the first comparator CMP0 reaches the required frequency.

[0067] Optionally, please refer to Figure 3 , within each switching cycle of the power switch circuit, the adjustment of the frequency compensation circuit 100c enables the required duration T_RAMP for the voltage RAMP converted by the voltage conversion circuit 100d to increase from the minimum value (such as 0V) to the output voltage V OUT when reaching the first specific value, and further enables the frequency of the on-time control signal TON output by the first comparator CMP0 to reach the second specific value. Among them, the first specific value is regulated by the adjustment signal S1 generated by the frequency compensation circuit 100c.

[0068] Further optionally, the frequency compensation circuit 100c adjusts the mirror ratio of the variable current mirror 100b, so that within each switching cycle T of the power switch circuit, the voltage RAMP output by the voltage conversion circuit 100d first gradually increases non-linearly in a manner of gradually decreasing the slope to a specific slope value, and then the voltage RAMP gradually increases linearly at a slope of this specific slope value to reach the output voltage V OUT , thereby enabling the voltage RAMP to increase from the minimum value to the output voltage V OUTThe required duration T_RAMP at this time reaches a first specific value. This first specific value is, for example, the high-level duration of the turn-on signal HS_ON within a single switching period T of the power switching circuit.

[0069] It should be understood that circuit modules such as the current conversion circuit 100a, variable current mirror 100b, frequency compensation circuit 100c, voltage conversion circuit 100d, and first comparator CMP0 inside the turn-on time control circuit 100 can adopt any suitable circuit design, and the internal circuit modules of the turn-on time control circuit 100 can also be not limited to these modules of the current conversion circuit 100a, variable current mirror 100b, frequency compensation circuit 100c, voltage conversion circuit 100d, and first comparator CMP0 according to functional requirements. The present invention does not make specific limitations on this.

[0070] Optionally, please refer to Figure 4 , the current conversion circuit 100a includes a first error amplifier EA0, a switching switch Q0, and a first resistor Rton. Among them, the switching switch Q0 can be any controllable semiconductor switching device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a triode, etc. The source of the switching switch Q0 is coupled to one end of the first resistor Rton and the second input terminal (such as the inverting input terminal “-”) of the first error amplifier EA0. The other end of the first resistor Rton is grounded. The first input terminal (such as the non-inverting input terminal “+”) of the first error amplifier EA0 serves as the input terminal of the current conversion circuit 100a and is connected to the input voltage V IN , the output terminal of the first error amplifier EA0 is coupled to the gate of the switching switch Q0. The drain of the switching switch Q0 serves as the output terminal of the current conversion circuit 100a and outputs a corresponding input current IRAMP = V IN / Rton.

[0071] Optionally, the variable current mirror 100b includes a first mirror branch (not marked) and a second mirror branch (not marked). The first mirror branch is coupled to the current conversion circuit and is used to mirror-amplify the input current I1 according to a fixed first mirror ratio (such as 1:1:1); the second mirror branch is coupled to the first mirror branch and is used to mirror-amplify the mirror current provided by the first mirror branch according to a variable second mirror ratio (such as 1:m), and the second mirror branch has an adjustment transistor Q5 and a reference transistor Q8. The gate of the adjustment transistor Q8 is coupled to the adjustment signal S1 provided by the frequency compensation circuit 100b to adjust the second mirror ratio 1:m under the control of the adjustment signal S1. The gate of the reference transistor Q8 is coupled to the third reference pulse signal PULSE3_A provided by the frequency compensation circuit 100b.

[0072] As an example, please refer to Figure 4 , the first mirror branch has a first MOS transistor Q1 (which can be a PMOS transistor), a second MOS transistor Q2 (which can be a PMOS transistor), and a seventh MOS transistor Q7 (which can be a PMOS transistor). The gates of the first MOS transistor Q1, the second MOS transistor Q2, and the seventh MOS transistor Q7 are all coupled to the drain of the first MOS transistor Q1 and the drain of the switching transistor Q0 to access the input current IRAMP and mirror-amplify the input current IRAMP according to the first mirror ratio W / L Q1 :W / L Q2 :W / L Q7 (i.e., the aspect ratios of Q1, Q2, and Q7). Among them, when the aspect ratios of Q1, Q2, and Q7 are all 1, the first mirror ratio is 1:1:1.

[0073] As an example, please refer to Figure 4 , the second mirror branch includes a third MOS transistor Q3 (which can be an NMOS transistor), a fourth MOS transistor Q4 (which can be an NMOS transistor), an adjustment transistor (which can be an NMOS transistor) Q5, a sixth MOS transistor Q6 (which can be a PMOS transistor), a reference transistor (which can be a PMOS transistor) Q8, and a ninth MOS transistor (which can be a PMOS transistor). Among them, the gates of the third MOS transistor Q3 and the fourth MOS transistor Q4 and the drain of the third MOS transistor Q3 are coupled to the drain of the second MOS transistor Q2. The sources of the third MOS transistor Q3 and the fourth MOS transistor Q4 are grounded. The drain of the fourth MOS transistor Q4 and the source of the adjustment transistor Q5 are connected in series. The drain of the adjustment transistor Q5 and the drain and gate of the sixth MOS transistor Q6 and the gate of the ninth MOS transistor Q9 are coupled. The source of the ninth MOS transistor Q9 is coupled to the drain of the reference transistor Q8. The sources of the sixth MOS transistor Q6 and the reference transistor Q8 and the sources of the first MOS transistor Q1, the second MOS transistor Q2, and the seventh MOS transistor Q7 are mutually coupled and can all be connected to the corresponding power supply voltage (not shown). Among them, the gate of the reference transistor Q8 is coupled to the third reference pulse signal PULSE3_A output by the frequency compensation circuit 100c, and the gate of the adjustment transistor Q5 is coupled to the adjustment signal S1 output by the frequency compensation circuit 100c. The branch formed by connecting Q4 to Q5 mirrors the mirror current flowing through Q2 according to the second mirror ratio 1:m to generate a mirror current mI RAMP , and the adjustment signal S1 adjusts the current magnitude of this branch, thereby adjusting the magnitude of the mirror ratio m (i.e., adjusting the current multiple) of this branch.

[0074] Please refer to Figure 3, in one example, within each switching cycle T of the power switch circuit, the adjustment signal S1 is a signal similar to a triangular wave. Its starting point is the maximum value of S1 and is aligned with the rising edge of the turn-on signal HS_ON. After starting from the starting point and remaining stable at the maximum value for a period of time, it then linearly decreases from the maximum value to the minimum value to form the falling edge of S1. After that, it linearly increases from the minimum value to the maximum value, and then remains stable at the maximum value for a period of time until the next rising edge of the turn-on signal HS_ON arrives to end, thus forming the rising edge of S1. Optionally, the falling edge of S1 is first used to control the adjustment transistor Q5 to adjust the voltage RAMP output by the voltage conversion circuit 100d to non-linearly increase in a manner that the slope gradually decreases to a specific slope value, and the moment when the slope of the voltage RAMP decreases to this specific slope value is aligned with the rising edge of the third reference pulse signal PULSE3_A. Subsequently, the falling edge of the adjustment signal S1 continues to control the adjustment transistor Q5, such that the voltage RAMP gradually linearly increases at a slope of this specific slope value to the output voltage V OUT , thereby, within each switching cycle of the power switch circuit, the voltage RAMP is made to increase from the minimum value to the output voltage V OUT when the required duration T_RAMP is stable. T_RAMP is the high-level duration of the turn-on signal HS_ON within each switching cycle of the power switch circuit.

[0075] In other examples of this embodiment, the branches or MOS transistors in the first mirror branch and the second mirror branch can also be appropriately increased or decreased as needed.

[0076] Optionally, the voltage conversion circuit 100d includes a capacitor Cton and a discharge switch Q10. One end (i.e., the upper plate) of the capacitor Cton is coupled to the drain of the discharge switch Q10, the first input terminal of the first comparator CMP0, and the drains of Q7 and Q9. The other end (i.e., the lower plate) of the capacitor Cton and the source of the discharge switch Q10 are both grounded. The gate of the discharge switch Q10 receives a corresponding control signal (for example, in phase with the turn-on signal LS_ON of the power switch transistor LS. This LS_ON signal is in reverse phase with the HS_ON signal and is also the cut-off signal of the power switch transistor HS). This control signal is usually in phase with the corresponding turn-on signal or cut-off signal received in the power switch circuit (both the turn-on signal and the cut-off signal are generated based on the conduction time control signal TON), but the gate of the discharge switch Q10 is usually not directly coupled to the gate of the power switch transistor in the power switch circuit. For example, when the discharge switch Q10 is an NMOS transistor, the control signal received by its gate can be in phase with the turn-on signal LS_ON received by the gate of the power switch transistor LS. In this article, in order to indicate that the signals received by the two gates are in phase, Figure 4The control signal of the gate of the discharge switch Q10 is also marked as LS_ON. Thus, when the power switch HS needs to be turned on and LS needs to be turned off, the discharge switch Q10 is also turned off, and the mirror current I RAMP output by Q7 and the current mI RAMP output by Q9 jointly charge the capacitor Cton. The charging time is the conduction time of the power switch HS. Furthermore, the current Im = (m + 1)*I RAMP output by the variable current mirror 100b is converted into the corresponding voltage RAMP:

[0077] RAMP = Q / Cton = (m + 1)*I RAMP *t / Cton = (m + 1)*V IN *t / (Rton*Cton).

[0078] Optionally, please refer to Figure 5 , the frequency compensation circuit 100c includes an edge sampling circuit NOSW, a frequency reference circuit FSWR, and a phase frequency detector PFD. Among them, the edge sampling circuit NOSW is used to sample the rising edge (or the falling edge of LS_ON) or the falling edge (or the rising edge of LS_ON) of the turn-on signal HS_ON of the power switch circuit, and generate a first sampling signal NOSW_A and a second sampling signal NOSW_B. The frequency reference circuit FSWR is coupled to the edge sampling circuit NOSW and is used to generate a plurality of reference pulse signals with different duty cycles (such as PULSE1_B, PULSE2_A, PULSE3_A) according to the first sampling signal NOSW_A and the second sampling signal NOSW_B. One of the reference pulse signals is output to the gate of the reference transistor Q8 of the variable current mirror 100b. The phase frequency detector PFD is coupled to the frequency reference circuit FSWR and is used to generate an adjustment signal S1 for adjusting the mirror ratio of the variable current mirror 100b according to the corresponding reference pulse signals (such as PULSE1_B, PULSE2_A). Adjusting the mirror ratio by the adjustment signal S1 actually means adjusting the mirror current of the corresponding mirror branch in the variable current mirror.

[0079] Optionally, the frequency reference circuit FSWR includes a first to a third reference pulse circuit FSWR1 to FSWR3. The first reference pulse circuit FSWR1 and the second reference pulse circuit FSWR2 are coupled to the phase frequency detector PFD. The phase frequency detector PFD performs frequency monitoring and integration processing on the first reference pulse signal PULSE1_B output by the first reference pulse circuit FSWR1 and the second reference pulse signal PULSE2_A output by the second reference pulse circuit FSWR2 to obtain the adjustment signal S1. The third reference pulse circuit FSWR3 is coupled to the variable current mirror 100b, and the third reference pulse signal PULSE3_A is output by the third reference pulse circuit FSWR3.

[0080] Further optionally, one edge (e.g., the falling edge) of the third reference pulse signal PULSE3_A is aligned with the rising edge of the enable signal HS_ON, and determines the time for the adjustment signal S1 to make an adjustment. The other edge (e.g., the falling edge) of the third reference pulse signal PULSE3_A corresponds to the moment when the slope of the voltage RAMP converted by the voltage conversion circuit 100d decreases to a specific slope value.

[0081] In one example, the duty cycle of the first reference pulse signal PULSE1_B is 0.5. Thus, the adjustment signal S1 generated based on PULSE1_B adjusts the mirror ratio of the variable current mirror 100b, enabling the voltage RAMP output by the voltage conversion circuit 100d to increase from the minimum value to the output voltage V OUT when the required duration reaches a first specific value. At this time, the frequency of the conduction time control signal TON output by the conduction time control circuit reaches a second specific value (e.g., a fixed value).

[0082] It should be understood that the edge sampling circuit NOSW, the frequency reference circuit FSWR, and the phase frequency detector PFD in the frequency compensation circuit 100c can be implemented using any suitable circuit design, and the present invention does not make specific limitations thereto.

[0083] For example, the edge sampling circuit NOSW can be implemented using conventional circuits in the art such as a rising edge detection circuit, a falling edge detection circuit, a double-edge detection circuit, etc., and it can include components such as flip-flops and inverters. Please refer to Figure 8 In one example, the edge sampling circuit NOSW is designed as a rising edge detection circuit (not shown), which can sample the rising edge of HS_ON to obtain a first sampling signal NOSW_A. The rising edge of the first sampling signal NOSW_A is aligned with the rising edge of HS_ON. The edge sampling circuit NOSW further includes an inverter (such as Figure 7 INV shown in

[0084] This inverter performs an inversion process on the first sampling signal NOSW_A to obtain a second sampling signal NOSW_B, that is, the falling edge of the second sampling signal NOSW_B is aligned with the rising edge of the first sampling signal NOSW_A.

[0085] Optionally, please refer to Figure 6, the i-th reference pulse circuit FSWRi of the frequency reference circuit FSWR includes a fluctuating voltage circuit 100a1, a threshold voltage circuit 100a2, a comparison circuit 100a3, and a reset circuit 100a4. Among them, the fluctuating voltage circuit 100a1 is used to provide a fluctuating voltage VC with a corresponding fluctuating frequency i . The threshold voltage circuit 100a2 is used to provide a corresponding threshold voltage V THi . The comparison circuit 100a3 is coupled to the fluctuating voltage circuit 100a1, the threshold voltage circuit 100a2, and the edge sampling circuit NOSW, and is used to compare the fluctuating voltage VC i with the threshold voltage V THi under the control of the first sampling signal NOSW_A and the second sampling signal NOSW_B, so as to output a reference pulse signal PULSEi_A with a corresponding duty cycle according to the comparison result. The reset circuit 100a4 is coupled to the fluctuating voltage circuit 100a1 and the edge sampling circuit NOSW, and is used to reset the fluctuating voltage circuit 100a1 according to the first sampling signal NOSW_A.

[0086] It should be noted that the fluctuating frequencies of the fluctuating voltages output by different reference pulse circuits in the frequency reference circuit FSWR are different; the magnitudes of the threshold voltages provided by different reference pulse circuits can be the same or different. The fluctuating voltage circuit 100a1, the threshold voltage circuit 100a2, the comparison circuit 100a3, and the reset circuit 100a4 can be implemented by any suitable circuit design, and the present invention does not make specific limitations on this.

[0087] In an embodiment of the present invention, the fluctuating voltage circuit 100a1 can be implemented by a conventional circuit such as a ramp voltage generator.

[0088] In another embodiment of the present invention, please refer to Figure 6 , the fluctuating voltage circuit 100a1 may include a first current source I 0_i and a first capacitor C i . One end of the first current source I 0_i is coupled to the power supply voltage VDD, and the other end is coupled to one end of the first capacitor C i . The other end of the first capacitor C i is grounded. The first current source I 0_i is used to charge and discharge the first capacitor C i . The connection node of the first current source I 0_i and the first capacitor C i serves as the output end of the fluctuating voltage circuit 100a1 and is used to output the fluctuating voltage VC i , where the first capacitors C in different reference pulse circuits of the frequency reference circuit FSWR iWith different capacitance values, the first capacitor C is designed i By adjusting the capacitance value of i , the fluctuating voltage VC can be adjusted i Regarding the magnitude of the fluctuation period, for the first capacitor C i The larger the capacitance value of the first capacitor C, the fluctuating voltage VC i The longer the fluctuation period is

[0089] In an embodiment of the present invention, please refer to Figure 6 , the reset circuit 100a4 includes a reset transistor M o_i (such as an NMOS transistor). The gate of the reset transistor M o_i is coupled to the edge sampling circuit 100a to access the first sampling signal NOSW_A. The source of the reset transistor M o_i is grounded. The drain of the reset transistor M o_i is coupled to the connection node of the first current source I 0_i and the first capacitor C i to receive the fluctuating voltage VC i .

[0090] In an embodiment of the present invention, the threshold voltage circuit 100a2 can be implemented by using a dedicated circuit such as a bandgap reference circuit

[0091] In another embodiment of the present invention, please refer to Figure 6 , the threshold voltage circuit 100a2 includes a threshold transistor M 4_i . The gate of the threshold transistor M 4_i is coupled to the output terminal of the fluctuating voltage circuit 100a1. The source of the threshold transistor M 4_i is grounded. The drain of the threshold transistor M 4_i is coupled to the comparison circuit 100a3. The threshold transistor M 4_i provides its threshold voltage V THIi to the comparison circuit 100a3 as a reference value

[0092] In an embodiment of the present invention, the comparison circuit 100a3 can be designed by using a conventional circuit such as a comparator

[0093] In another embodiment of the present invention, please refer to Figure 6 , the comparison circuit 100a3 includes a pull-up transistor M 1_i (such as a PMOS transistor), a pull-down transistor M 2_i (such as an NMOS transistor), a control transistor M 3_i (such as an NMOS transistor) and a buffer BUFF_i. The gates of the pull-up transistor M 1_i and the pull-down transistor M 2_i are both coupled to the second sampling signal NOSW_B. The gate of the control transistor M 3_iThe gate is coupled to the first sampling signal NOSW_A, and the source of the pull-up transistor M 1_i is coupled to the corresponding power supply voltage VDD, and the drain of the pull-up transistor M 1_i is coupled to the drain of the pull-down transistor M 2_i to form a node VXi. The source of the pull-down transistor M 2_i is coupled to the drain of the control transistor M 3_i , and the source of the control transistor M 3_i is grounded. The input terminal of the buffer BUFF_i is coupled to the node VXi and outputs a reference pulse signal PULSEi_A under the control of the clock signal CLK_BUFF.

[0094] It should be understood that Figure 6 the shown reference pulse circuit only shows some key components, and does not indicate that the reference pulse circuit only has these components. In other embodiments of the present invention, one or more MOS transistors can be connected between the node VXi and the input terminal of the buffer BUFF_i to achieve amplification, reduction, or clamping of the voltage or current of the node VXi, etc. The reset circuit 100a4 can also include multiple series-connected MOS transistors, and the threshold voltage circuit 100a2 can also include multiple series-connected MOS transistors.

[0095] As an example, please refer to Figure 5 and Figure 7 , and the frequency reference circuit FSWR includes a first reference pulse circuit FSWR1, a second reference pulse circuit FSWR2, and a third reference pulse circuit FSWR3.

[0096] The fluctuation voltage circuit 100a1 of the first reference pulse circuit FSWR1 has a first current source I 0_1 and a first capacitor C1. The threshold voltage circuit 100a2 of the first reference pulse circuit FSWR1 has a threshold transistor M 4_1 and provides a threshold voltage V TH1 . The comparison circuit 100a3 of the first reference pulse circuit FSWR1 has a pull-up transistor M 1_1 (e.g., a PMOS transistor), a pull-down transistor M 2_1 (e.g., an NMOS transistor), a control transistor M 3_1 (e.g., an NMOS transistor), a buffer BUFF_1, and an inverter INV. The reset circuit 100a4 of the first reference pulse circuit FSWR1 has a reset transistor M0 _1 . The connection node of the first current source I 0_1 and the first capacitor C1 outputs a fluctuation circuit VC1. The pull-up transistor M 1_1 and the pull-down transistor M 2_1The connection node VX1 is coupled to the input end of the buffer BUFF_1. The output end of the buffer BUFF_1 outputs a reference pulse signal PULSE1_A. The input end of the inverter INV is coupled to the output end of the buffer BUFF_1, and the output end of the inverter INV outputs a first reference pulse signal PULSE1_B.

[0097] The fluctuation voltage circuit 100a1 of the second reference pulse circuit FSWR2 has a first current source I 0_2 and a first capacitor C2. The threshold voltage circuit 100a2 of the second reference pulse circuit FSWR2 has a threshold transistor M 4_2 and provides a threshold voltage V TH2 . The comparison circuit 100a3 of the second reference pulse circuit FSWR2 has a pull-up transistor M 1_2 (e.g., a PMOS transistor), a pull-down transistor M 2_2 (e.g., an NMOS transistor), a control transistor M 3_2 (e.g., an NMOS transistor) and a buffer BUFF_2. The reset circuit 100a4 of the second reference pulse circuit FSWR2 has a reset transistor M 0_2 . The connection node of the first current source I 0_2 and the first capacitor C2 outputs a fluctuation circuit VC2. The connection node VX2 of the pull-up transistor M 1_2 and the pull-down transistor M 2_2 is coupled to the input end of the buffer BUFF_2, and the output end of the buffer BUFF_2 outputs a second reference pulse signal PULSE2_A.

[0098] The fluctuation voltage circuit 100a1 of the third reference pulse circuit FSWR3 has a first current source I 0_3 and a first capacitor C3. The threshold voltage circuit 100a2 of the second reference pulse circuit FSWR3 has a threshold transistor M 4_3 and provides a threshold voltage V TH3 . The comparison circuit 100a3 of the second reference pulse circuit FSWR3 has a pull-up transistor M 1_3 (e.g., a PMOS transistor), a pull-down transistor M 2_3 (e.g., an NMOS transistor), a control transistor M 3_3 (e.g., an NMOS transistor) and a buffer BUFF_3. The reset circuit 100a4 of the third reference pulse circuit FSWR1 has a reset transistor M 0_3 . The connection node of the first current source I 0_3 and the first capacitor C3 outputs a fluctuation circuit VC3. The connection node of the pull-up transistor M 1_3 and the pull-down transistor M 2_3The connection node VX3 of is coupled to the input end of the buffer BUFF_3, and the output end of the buffer BUFF_3 outputs the third reference pulse signal PULSE3_A. The threshold voltages V TH3 and V TH2 and V TH3 can be the same or different.

[0099] By separately designing the capacitance values of C1, C2, and C3, the fluctuation frequencies of the fluctuation voltages VC1, VC2, and VC3 can be adjusted respectively. The larger the capacitance value, the longer the fluctuation time of the fluctuation voltage. That is, the larger the capacitance value of C1, Figure 8 the longer the time for VC1 to rise from 0V to its maximum value in , and the smaller the slope of VC1.

[0100] In one example, please refer to Figure 8 , when HS_ON changes from low level to high level, the edge detection circuit NOSW samples the rising edge of the turn-on signal HS_ON, generating the first sampling signal NOSW_A (a very short high-level pulse) and the second sampling signal NOSW_B. In the first reference pulse circuit FSWR1, the high-level NOSW_A turns on M 0_1 , clearing the fluctuation voltage VC1. After NOSW_A becomes low level, VC1 gradually increases. Before the fluctuation voltage VC1 increases to the threshold voltage V TH1 , according to the voltage of the node VX1, the first reference pulse signal PULSE1_A generated in this stage is at low level, and the finally output first reference pulse signal PULSE1_B is at high level. After the fluctuation voltage VC1 increases to the threshold voltage V TH1 and before the next high level of the first sampling signal NOSW_A, the first reference pulse signal PULSE1_A generated is at high level, and the finally output first reference pulse signal PULSE1_B is at low level.

[0101] The principle of the second reference pulse circuit FSWR2 generating the second reference pulse signal PULSE2_A and the third reference pulse circuit FSWR3 generating the third reference pulse signal PULSE3_A is the same as that of generating the first reference pulse signal PULSE1_A, and will not be elaborated here.

[0102] In one example, please refer to Figure 3 , the rising edge of the third reference pulse signal PULSE3_A and the starting point of the adjustment signal S1 (i.e., the moment when the adjustment signal S1 starts to adjust the mirror ratio m of the variable current mirror 100b) are both aligned with the falling edge of the turn-on signal HS_ON. The falling edge of the third reference pulse signal PULSE3_A is aligned with the moment when the slope of the voltage RAMP decreases to a specific slope. The voltage RAMP increases to the output voltage V OUTThe timing is aligned with the rising edge of the start signal HS_ON.

[0103] In an example, combine Figure 8 , the rising edge of the first reference pulse signal PULSE1_B, the falling edge of the second reference pulse signal PULSE2_A and the falling edge of the third reference pulse signal PULSE3_A are all aligned with the rising edge of the turn-on signal HS_ON, the falling edge of the first reference pulse signal PULSE1_B, the rising edge of the second reference pulse signal PULSE2_A, the rising edge of the third reference pulse signal PULSE3_A and the falling edge of the turn-on signal HS_ON are staggered with each other, and the falling edge of the first reference pulse signal PULSE1_B is delayed relative to the falling edge of the turn-on signal HS_ON, the rising edge of the second reference pulse signal PULSE2_A is advanced relative to the rising edge of the third reference pulse signal PULSE3_A, and the rising edge of the third reference pulse signal PULSE3_A is advanced relative to the falling edge of the turn-on signal HS_ON.

[0104] In an embodiment of the present invention, the phase frequency detector (PFD) may adopt a common circuit structure such as a charge pump phase locked loop.

[0105] In another embodiment of the present invention, please refer to Figure 9 The phase frequency detector PFD includes a second current source I1, an upper integrating transistor P1, a lower integrating transistor N1, a third current source I2, and a second capacitor C0. The gate of the upper integrating transistor P1 is coupled to the output end of the first reference pulse circuit FSWR1 to be turned on or off under the control of the first reference pulse signal PULSE1_B, the source of the upper integrating transistor P1 is coupled to one end of the third current source I2, the drain of the upper integrating transistor P1 is coupled to the drain of the lower integrating transistor N1 and one end of the second capacitor C0 and outputs the adjustment signal S1, the gate of the lower integrating transistor N1 is coupled to the output end of the second reference pulse circuit FSWR2 to be turned on or off under the control of the second reference pulse signal PULSE2_A, and the source of the lower integrating transistor N1 is coupled to one end of the second current source I1. The other end of the second current source I1 is grounded. The current provided by the third current source I2 is twice that of the second current source I1, that is, I 2＝ 2I1.

[0106] It should be understood that Figure 1 HS and LS in Figure 4 Q0~Q10 in Figure 6 and Figure 7 The individual transistors and Figure 9 P1 and N1 in the figure are respectively shown by taking NMOS tube or PMOS tube as an example, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, Figure 1 , Figure 4, Figures 6 - 7 and Figure 9 the corresponding NMOS transistors in Figure 1 , Figure 4 , Figures 6 - 7 and Figure 9 can be replaced with any controllable semiconductor switching devices such as PMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc. Similarly, Figure 1 , Figure 4 , Figures 6 - 7 and Figure 9 the corresponding PMOS transistors in and

[0107] can be replaced with any controllable semiconductor switching devices such as NMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc.

[0107] Based on the same inventive concept, please refer to Figure 1 . This embodiment further provides a control circuit 10 for controlling the on / off of the power switch circuit in the DC-DC conversion circuit. The control circuit 10 includes the on-time control circuit 100 as described in the present invention. For example, the control circuit 10 controls the on-time in each switching cycle of the power switch transistors HS and LS to be constant based on the on-time control circuit 100. Figure 1 Optionally, the control circuit 10 further includes a PWM generator 101 and a logic control circuit (LOGIC CONTROL) 102. The PWM generator 101 generates a pulse width modulation signal PWM according to the voltage V SW at the connection node of the power switch transistors HS and LS and the feedback voltage V FB of the output voltage V OUT . The logic control circuit 102 is coupled to the PWM generator 101, the on-time control circuit 100, and the gates of the power switch transistors HS and LS. The logic control circuit 102 performs a logic operation (such as an AND logic operation) on the pulse width modulation signal PWM and the on-time control signal TON to generate an on signal HS_ON and an on signal LS_ON to drive the power switch transistors HS and LS to alternately turn on and off. The pulse width modulation signal PWM is mainly used to determine the switching cycle (or switching frequency) of the power switch transistors HS and LS, and the on-time control signal TON is mainly used to determine the on-time of the power switch transistors HS and LS in each switching cycle.

[0108] It should be understood that the PWM generator 101 and the logic control circuit (LOGIC CONTROL) 102 can be implemented by any suitable circuit design, and the internal structure of the control circuit 10 is only an example, which does not indicate that the internal structure of the control circuit 10 of the present invention is only limited to this. In other embodiments of the present invention, the control circuit 10 may further have other functional circuits inside, and the DC-DC conversion circuit may further include other circuit structures. SW and OUT the feedback voltage V FB of the output voltage V

[0109] For example, please refer to Figure 10 .

[0110] For example, please refer to Figure 10, in an embodiment of the present invention, the PWM generator 101 includes a second error amplifier EA1, a ramp generator VRAMP, and a second comparator CMP1. The second error amplifier EA1 is used to compare the feedback voltage V OUT of the output voltage V FB of the DC-DC conversion circuit with a first reference voltage V REF1 to generate an error amplification signal V EAO . The ramp generator VRAMP is used to compare the voltage V SW at the connection node of the power switching transistors HS and LS with a second reference voltage V REF2 to generate a ramp signal V RAMP . The first input terminal (for example, the non-inverting input terminal “+”) of the second comparator CMP1 is coupled to the output terminal of the second error amplifier EA1, and the second input terminal (for example, the inverting input terminal “-”) is coupled to the output terminal of the ramp generator VRAMP. The second comparator CMP1 is used to compare the magnitudes of the error amplification signal V EAO and the ramp signal V RAMP to generate a pulse width modulation signal PWM required by the logic control circuit 102.

[0111] For example, in another embodiment of the present invention, please refer to Figure 10 , the control circuit 10 further includes a zero-crossing detection circuit (not labeled), and the output terminal of the zero-crossing detection circuit is coupled to the logic control circuit 102; the zero-crossing detection circuit is used to detect the zero-crossing point of the voltage V SW at the output node of the power switching circuit to generate a zero-crossing signal ZCD; the logic control circuit 102 performs corresponding logical operations on the pulse width modulation signal PWM, the zero-crossing signal ZCD, and the conduction time control signal TON to control the on and off of the corresponding power switching transistor (HS or LS) in the power switching circuit.

[0112] As an example, the zero-crossing detection circuit includes a third comparator CMP2. The first input terminal of the third comparator CMP2 receives the voltage V SW at the connection node of the power switching transistors HS and LS. The second input terminal of the third comparator CMP2 is connected to 0V or grounded or connected to a reference voltage. The output terminal of the third comparator CMP2 is coupled to the logic control circuit 102 to provide the zero-crossing signal ZCD.

[0113] Based on the same inventive concept, please refer to Figure 1 and Figure 10, an embodiment of the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit 11 and a control circuit 10 as described in any embodiment of the present invention. The power stage circuit 11 can adopt any suitable topology such as a Buck topology, a Buck-boost topology, or a Boost topology, and it has an inductor L and an output capacitor C OUT and a corresponding power switch circuit, and this power switch circuit has at least one power switch tube, for example Figure 1 and Figure 9 HS and LS therein. The control circuit 10 is coupled to the gate of the corresponding power switch tube of the power switch circuit in the power stage circuit 11 to turn on and off under the control of this control circuit 10, thereby enabling the DC-DC conversion circuit to operate in a corresponding mode (such as the COT mode), and converting the input voltage V IN into an output voltage V OUT .

[0114] Optionally, please refer to Figure 10 , this DC-DC conversion circuit further includes a feedback circuit 12, which can sample the output voltage V OUT to generate a feedback voltage V OUT for feedback on the change and magnitude of the output voltage V FB . As an example, this feedback circuit 12 includes resistors R1 and R2. One end of resistor R1 is coupled to the upper plate of the output capacitor C OUT and one end of the inductor L. The other end of resistor R1 is connected to one end of resistor R2 and outputs the feedback voltage V FB , and the other end of resistor R2 is grounded.

[0115] In summary, for the turn-on time control circuit, control circuit, and DC-DC conversion circuit provided by the present invention, a frequency compensation circuit is introduced into the turn-on time control circuit. This frequency compensation circuit can generate a corresponding adjustment signal according to the turn-on signal of the power switch circuit, and this adjustment signal can adjust the mirror ratio of the variable current mirror in the turn-on time control circuit to regulate the voltage output by the voltage conversion circuit in the turn-on time control circuit, so as to make the frequency of the turn-on time control signal output by the turn-on time control circuit reach the required frequency (for example, reach a first specific value, that is, at this time the turn-on time control signal changes at a frequency of the first specific value), achieving the effect of locking the frequency of the DC-DC conversion circuit system. This solution is applicable not only to the DC-DC conversion circuit in the ACOT mode, but also to the DC-DC conversion circuits in the fixed-frequency voltage mode and fixed-frequency current mode.

[0116] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the protection scope of the technical solution of the present invention.

Claims

1. A conduction time control circuit is used to control the on / off of a power switch circuit in a DC-DC conversion circuit, so that the DC-DC conversion circuit converts a corresponding input voltage into an output voltage, and is characterized in that, The turn-on time control circuit includes: A current conversion circuit for converting the input voltage into an input current; A variable current mirror coupled to the current conversion circuit and used for mirror-amplifying and outputting the input current; A voltage conversion circuit coupled to the variable current mirror and used for converting the current output by the variable current mirror into a corresponding voltage; A first comparator, with its first input terminal coupled to the voltage conversion circuit and its second input terminal coupled to the output voltage, and used for comparing the magnitudes between the output voltage and the voltage converted by the voltage conversion circuit to output a corresponding turn-on time control signal for controlling the turn-on time of the power switch circuit; A frequency compensation circuit coupled to the variable current mirror and used for adjusting the mirror ratio of the variable current mirror to regulate the voltage converted by the voltage conversion circuit, so that the frequency of the turn-on time control signal output by the first comparator reaches the required frequency.

2. The turn-on time control circuit according to claim 1, wherein During each switching cycle of the power switch circuit, the adjustment of the frequency compensation circuit makes the required duration for the voltage converted by the voltage conversion circuit to increase from the minimum value to the output voltage reach a first specific value, thereby making the frequency of the turn-on time control signal reach a second specific value.

3. The turn-on time control circuit according to claim 1 or 2, characterized in that, The frequency compensation circuit includes: An edge sampling circuit for sampling the rising edge or falling edge of the turn-on signal of the power switch circuit and generating a corresponding sampling signal; A frequency reference circuit coupled to the edge sampling circuit and used for generating a plurality of reference pulse signals with different duty cycles according to the sampling signal; A frequency discriminator and phase detector coupled to the frequency reference circuit and used for generating an adjustment signal for adjusting the mirror ratio of the variable current mirror according to the corresponding reference pulse signal.

4. The turn-on time control circuit according to claim 3, wherein The adjustment signal adjusts the mirror ratio of the variable current mirror, so that the voltage converted by the voltage conversion circuit first increases non-linearly in a manner of gradually decreasing to a specific slope value with a slope and then increases linearly in a manner of maintaining the specific slope value to the output voltage.

5. The turn-on time control circuit according to claim 3, characterized in that, The frequency reference circuit includes a plurality of reference pulse circuits, and each reference pulse circuit includes: A fluctuating voltage circuit for providing a fluctuating voltage with a corresponding fluctuating frequency, and the fluctuating frequencies of the fluctuating voltages output by different reference pulse circuits are different; A threshold voltage circuit for providing a corresponding threshold voltage, and the magnitudes of the threshold voltages provided by different reference pulse circuits are the same or different; A comparison circuit coupled to the fluctuating voltage circuit, the threshold voltage circuit and the edge sampling circuit, and used for comparing the fluctuating voltage with the threshold voltage under the control of the sampling signal to output a reference pulse signal with a corresponding duty cycle according to the comparison result.

6. The turn-on time control circuit according to claim 5, wherein The fluctuating voltage circuit includes a first current source and a first capacitor. The first current source is coupled to the first capacitor and used for charging and discharging the first capacitor, and the connection node between the first current source and the first capacitor outputs the fluctuating voltage, wherein the capacitance values of the first capacitors in different reference pulse circuits are different; And / or The threshold voltage circuit includes a threshold transistor, the gate of the threshold transistor is coupled to the fluctuating voltage, the source of the threshold transistor is grounded, and the drain of the threshold transistor is coupled to the comparison circuit.

7. The turn-on time control circuit according to claim 5 or 6, characterized in that The comparison circuit includes a pull-up transistor, a pull-down transistor, a control transistor, and a buffer. The gates of the pull-up transistor, the pull-down transistor, and the control transistor are respectively coupled to the edge sampling circuit. The source of the pull-up transistor is coupled to a corresponding power supply voltage. The drain of the pull-up transistor is coupled to the drain of the pull-down transistor. The source of the pull-down transistor is coupled to the drain of the control transistor, and the source of the control transistor is grounded.

8. The turn-on time control circuit according to claim 5 or 6, characterized in that Each of the reference pulse circuits further includes a reset circuit, which is coupled to the fluctuating voltage circuit and the edge sampling circuit, and is used to reset the fluctuating voltage circuit according to the corresponding sampling signal output by the edge sampling circuit.

9. The turn-on time control circuit according to claim 7, wherein The reset circuit includes a reset transistor. The gate of the reset transistor is coupled to the edge sampling circuit. The source of the reset transistor is grounded, and the drain of the reset transistor is coupled to the fluctuating voltage.

10. The turn-on time control circuit according to claim 4, wherein, The frequency reference circuit includes first to third reference pulse circuits, and the first reference pulse circuit and the second reference pulse circuit are coupled to the frequency discriminator and phase detector. The frequency discriminator and phase detector performs frequency monitoring and integration processing on the reference pulse signals output by the first reference pulse circuit and the second reference pulse circuit to obtain the adjustment signal. The third reference pulse circuit is coupled to the variable current mirror. The corresponding edge of the third reference pulse signal output by the third reference pulse circuit corresponds to the moment when the slope of the voltage converted by the voltage conversion circuit decreases to the specific slope value.

11. The turn-on time control circuit according to claim 10, wherein The duty cycle of the reference pulse signal output by the first reference signal pulse circuit is 0.

5.

12. The turn-on time control circuit according to claim 10, wherein The frequency discriminator and phase detector includes a charge pump phase-locked loop; alternatively, the frequency discriminator and phase detector includes a second current source, an upper integration transistor, a lower integration transistor, a third current source, and a second capacitor. The gate of the upper integration transistor is coupled to the output terminal of the first reference pulse circuit. The source of the upper integration transistor is coupled to one end of the third current source. The drain of the upper integration transistor is coupled to the drain of the lower integration transistor and one end of the second capacitor and outputs the adjustment signal. The gate of the lower integration transistor is coupled to the output terminal of the second reference pulse circuit. The source of the lower integration transistor is coupled to one end of the second current source.

13. The turn-on time control circuit according to claim 10, wherein The variable current mirror circuit includes: A first mirror branch, which is coupled to the current conversion circuit and is used to mirror-amplify the input current according to a first mirror ratio. A second mirror branch, which is coupled to the first mirror branch and is used to mirror-amplify the mirror current provided by the first mirror branch according to a variable second mirror ratio. The second mirror branch has an adjustment transistor and a reference transistor. The gate of the adjustment transistor is coupled to the adjustment signal to adjust the second mirror ratio under the control of the adjustment signal. The gate of the reference transistor is coupled to the third reference pulse signal.

14. The turn-on time control circuit according to claim 1, characterized in that, The current conversion circuit includes a first error amplifier, a conversion switch, and a first resistor. The source of the conversion switch is coupled to one end of the first resistor and the second input terminal of the first error amplifier. The other end of the first resistor is grounded. The first input terminal of the first error amplifier is connected to the input voltage. The output terminal of the first error amplifier is coupled to the gate of the conversion switch. The drain of the conversion switch is coupled to the variable current mirror.

15. The turn-on time control circuit according to claim 1, wherein The voltage conversion circuit includes a third capacitor and a discharge switch. One end of the third capacitor is coupled to one end of the discharge switch, the first input terminal of the first comparator, and one end of the variable current mirror. The other end of the third capacitor and the other end of the discharge switch are both grounded. The control terminal of the discharge switch is coupled to the inverted signal of the turn-on signal of the power switch circuit.

16. A control circuit for controlling the on / off of a power switch circuit in the DC-DC conversion circuit, characterized in that, The control circuit includes the on-time control circuit according to any one of claims 1-15.

17. The control circuit according to claim 16, characterized in that, Further included are: A PWM generator, configured to generate a pulse width modulation signal according to the voltage at the output node of the power switch circuit and the feedback voltage of the output voltage; A zero-crossing detection circuit, configured to detect the zero-crossing point of the voltage at the output node of the power switch circuit to generate a zero-crossing signal; A logic control circuit, coupled to the PWM generator, the on-time control circuit, the zero-crossing detection circuit, and the power switch circuit, configured to drive the power switch circuit to conduct or turn off according to the pulse width modulation signal, the on-time control signal, and the zero-crossing signal.

18. The control circuit according to claim 17, wherein The PWM generator includes: A second error amplifier, configured to compare the feedback voltage with a first reference voltage to generate an error amplification signal; A ramp generator, configured to compare the voltage at the output node of the power switch circuit with a second reference voltage to generate a ramp signal; A second comparator, with its first input terminal coupled to the output terminal of the error amplifier and its second input terminal coupled to the output terminal of the ramp generator, configured to compare the error amplification signal and the ramp signal to generate the pulse width modulation signal.

19. A DC-DC conversion circuit, characterized in that, It includes a power stage circuit and the control circuit according to any one of claims 16-18. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

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