Control circuit for DC-DC conversion circuit and DC-DC conversion circuit

Abstract

The invention provides a control circuit for a DC-DC conversion circuit and the DC-DC conversion circuit, a load indication signal and an error amplification signal reflecting load current change are introduced into a conduction time control circuit, and the conduction time control circuit controls the conduction time according to the input voltage and the output voltage of the DC-DC conversion circuit, the error amplification signal and the load indication signal. The on-time of the power switch circuit in the corresponding switching period is controlled to be adjustable so as to adjust the peak value of the output voltage, so that the energy output in the switching period in different load states is different, the ripple of the output voltage is reduced and is relatively stable in the whole light load range, and the lighter the load state is, the smaller the direct current value of the error amplification signal is. The conduction time is shorter along with reduction of the direct current value of the error amplification signal, the load state is heavier, the direct current value of the error amplification signal is larger, the conduction time is longer along with increase of the direct current value of the error amplification signal, and the problem that redundant energy generates large output voltage ripples on an output capacitor is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and particularly to a control circuit for a DC-DC conversion circuit and a DC-DC conversion circuit. Background Art

[0002] As a highly efficient switching power converter, a DC-DC (direct current to direct current) converter (also known as a DC-DC conversion circuit) has the advantages of fast dynamic response, simple control, and direct control of the output current, and is widely used in the power management systems of various products. Among them, the constant on-time (COT) mode is one of the commonly used control modes for DC-DC conversion circuits. By setting a fixed on-time for the corresponding power switch tube in the power stage circuit, the output voltage of the DC-DC conversion circuit is adjusted.

[0003] In a traditional DC-DC conversion circuit controlled by the COT mode, the on-time of the power switch tube is constant. Therefore, in the low-load (i.e., light-load) application of the DC-DC conversion circuit controlled by the COT mode, the following problems will occur: the energy output in each charging cycle is the same, but the light load consumes less energy, and the excess energy will generate a large output voltage ripple on the output capacitor of the DC-DC conversion circuit. The lighter the load, the smaller the load current, and the more "remaining" energy there is in COUT after one charge, resulting in a larger ripple. This output voltage ripple will cause many harms and affect the reliability and conversion efficiency of the DC-DC conversion circuit. Therefore, it is necessary to reduce this output voltage ripple. Summary of the Invention

[0004] The purpose of the present invention is to provide a control circuit for a DC-DC conversion circuit and a DC-DC conversion circuit, which can reduce the output voltage ripple in the light-load state of the COT mode without the need for larger external components.

[0005] To achieve the above purpose, the present invention provides a control circuit for a DC-DC conversion circuit. The DC-DC conversion circuit converts an input voltage (VIN) into an output voltage by turning on and off a corresponding power switch circuit, and it includes:

[0006] A first error amplifier, configured to compare and amplify the error between a first reference voltage and the feedback voltage of the output voltage to obtain an error amplification signal whose DC value is positively correlated with the magnitude of the load current;

[0007] A conduction time control circuit, coupled to the output terminal of the first error amplifier, and configured to control the conduction time of the power switch circuit within a corresponding switching period to be adjustable according to the input voltage, the output voltage, the error amplification signal, and a load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage.

[0008] Optionally, the lighter the load state of the DC-DC conversion circuit, the smaller the DC value of the corresponding error amplification signal, and the shorter the corresponding conduction time as the DC value of the error amplification signal decreases; the heavier the load state, the larger the DC value of the corresponding error amplification signal, and the longer the corresponding conduction time as the DC value of the error amplification signal increases.

[0009] Optionally, the conduction time control circuit includes:

[0010] An input voltage conversion circuit, configured to convert the input voltage into an input current;

[0011] A load current introduction circuit, coupled to the first error amplifier and the load indication signal, configured to convert the error amplification signal into an error current reflecting the change in the load current, and output it under the control of the load indication signal;

[0012] A voltage conversion circuit, coupled to the input voltage conversion circuit and the load current introduction circuit, and configured to superimpose the input current and the error current output by the load current introduction circuit, and further convert the superimposed current into a corresponding voltage;

[0013] A first comparator, with its first input terminal coupled to the voltage conversion circuit, its second input terminal receiving the output voltage, and configured to compare the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit, so as to output the corresponding conduction time control signal.

[0014] Optionally, the input voltage conversion circuit includes a second error amplifier, a conversion switch, and a first resistor. The source electrode of the conversion switch is coupled to one end of the first resistor and the second input terminal of the first error amplifier. The other end of the first resistor is grounded. The first input terminal of the first error amplifier is connected to the input voltage, and the output terminal of the first error amplifier is coupled to the gate of the conversion switch.

[0015] Optionally, the input voltage conversion circuit further includes a first switching tube and a second switching tube. The gates of the first switching tube and the second switching tube are both coupled to the drain of the first switching tube and the drain of the conversion switch. The drain of the second switching tube is connected to the load current introduction circuit, the voltage conversion circuit, and the first input terminal of the first comparator.

[0016] Optionally, the load current introduction circuit includes a third switching transistor, a fourth switching transistor, n fifth switching transistors and a bias circuit, where n≥1 and is an integer; the input end of the bias circuit is coupled to the first error amplifier and is used to obtain the DC value of the error amplification signal; the gates of the third switching transistor and the fourth switching transistor are both coupled to the output end of the bias circuit and the drain of the fourth switching transistor, the drain of the third switching transistor is coupled to the drains of the fifth switching transistors, the sources of the fifth switching transistors are coupled to the voltage conversion circuit, the gates of the fifth switching transistors receive the load indication signal, and the lighter the load state of the DC-DC conversion circuit, the more the number of the fifth switching transistors that are turned on.

[0017] Optionally, the voltage conversion circuit includes an adder, a capacitor and a sixth switching transistor. One input end of the adder is coupled to the output end of the input voltage conversion circuit, the other input end of the adder is coupled to the output end of the load current introduction circuit, the output end of the adder is coupled to one end of the capacitor and the first input end of the first comparator, the other end of the capacitor and the other end of the sixth switching transistor are both grounded, and the control end of the sixth switching transistor receives a corresponding control signal.

[0018] Optionally, the control circuit further includes:

[0019] A feedback circuit, coupled to the output end of the DC-DC conversion circuit and one input end of the first error amplifier, and used to sample the output voltage to generate a feedback voltage for feeding back the change and magnitude of the output voltage;

[0020] A PWM generator, coupled to the first error amplifier, and used to generate a pulse width modulation signal according to the node voltage of the power switch circuit and the error amplification signal;

[0021] A logic control circuit, coupled to the PWM generator, the on-time control circuit and the power switch circuit, and used to drive the conduction or turn-off of the power switch circuit according to the pulse width modulation signal and the on-time control signal.

[0022] Optionally, the PWM generator includes:

[0023] A ramp generator, used to compare the node voltage of the power switch circuit with a second reference voltage to generate a ramp voltage signal;

[0024] A second comparator, with the first input end coupled to the output end of the first error amplifier and the second input end coupled to the output end of the ramp generator, and used to compare the magnitudes of the error amplification signal and the ramp voltage signal to generate the pulse width modulation signal.

[0025] Optionally, the ramp generator includes:

[0026] A differential current generating circuit, configured to receive the node voltage of the power switch circuit and a second reference voltage, and obtain a differential current between the node voltage and the second reference voltage;

[0027] A ramp voltage signal generating circuit, coupled to the differential current generating circuit, and configured to convert the differential current into the ramp voltage signal.

[0028] Optionally, the differential current generating circuit includes a third error amplifier, a seventh switching transistor, and a second resistor. The first input terminal of the third error amplifier is connected to the second reference voltage. The second input terminal of the third error amplifier is coupled to the source electrode of the seventh switching transistor and one end of the second resistor. The other end of the second resistor is connected to the node voltage. The output terminal of the third error amplifier is coupled to the gate electrode of the seventh switching transistor;

[0029] And / or, the ramp voltage signal generating circuit includes eighth to tenth switching transistors and a third resistor. The source electrodes of the eighth to tenth switching transistors are mutually coupled. The gate electrodes of the eighth and ninth switching transistors are both coupled to the drain electrode of the eighth switching transistor and the differential current generating circuit. The drain electrodes of the ninth and tenth switching transistors are both connected to one end of the third resistor. The other end of the third resistor is grounded. The gate electrode of the tenth switching transistor receives a corresponding control signal.

[0030] Optionally, the control circuit further includes a zero-crossing detection circuit, configured to detect the zero-crossing point of the node voltage of the power switch circuit to generate a zero-crossing signal; the logic control circuit drives the conduction or cutoff of the power switch circuit according to the pulse width modulation signal, the conduction time control signal, and the zero-crossing signal.

[0031] Based on the same inventive concept, the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit and the control circuit as described in the present invention. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

[0032] Compared with the prior art, the technical solution of the present invention does not require larger external devices. Instead, on the basis of the traditional COT mode, a load indication signal reflecting the load state of the DC-DC conversion circuit and an error amplification signal reflecting the change in load current are introduced into the on-time control circuit. The on-time control circuit controls the on-time of the power switch circuit to be adjustable within the corresponding switching period according to the input voltage, output voltage, the error amplification signal, and the load indication signal of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Thus, the energy output within the switching period under different load states is different, the ripple of the output voltage is reduced and relatively stable throughout the light load range. Moreover, the lighter the load state, the smaller the DC value of the corresponding error amplification signal, and the shorter the on-time along with the decrease of the DC value of the error amplification signal. The heavier the load state, the larger the DC value of the corresponding error amplification signal, and the longer the on-time along with the increase of the DC value of the error amplification signal, avoiding the problem of large output voltage ripple caused by excessive energy on the output capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0034] Figure 1 is a schematic structural diagram of the control circuit according to an embodiment of the present invention and the DC-DC conversion circuit where it is located.

[0035] Figure 2 is a schematic diagram of an exemplary structure of the on-time control circuit according to an embodiment of the present invention.

[0036] Figure 3 is a schematic diagram of an exemplary structure of the ramp generator according to an embodiment of the present invention.

[0037] Figure 4 is Figure 1 a signal timing diagram of the DC-DC conversion circuit shown in the heavy load state of the CCM mode.

[0038] Figure 5 is based on Figures 1 to 3 a signal timing comparison diagram of two DC-DC conversion circuits (whether to introduce a load indication signal and an error amplification signal) obtained.

[0039] Figure 6 is a signal timing comparison diagram of the load change of the DC-DC conversion circuit according to an embodiment of the present invention in the light load state.

[0040] Figure 7 is another schematic diagram of an exemplary structure of the on-time control circuit according to an embodiment of the present invention.

[0041] Figure 8 It is a schematic diagram of the control circuit of another embodiment of the present invention and the architecture of the DC-DC conversion circuit where it is located. Detailed implementation manners

[0042] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other instances, in order to avoid confusion with the present invention, some well-known technical features are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, it can be directly connected to the other element, or there may be intervening elements. In contrast, when an element is referred to as "directly connected to" another element, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0043] The technical solutions proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0044] Please refer to Figure 1 , an embodiment of the present invention provides a control circuit 10 for a DC-DC conversion circuit. The DC-DC conversion circuit also has a power stage circuit 11. The power stage circuit 11 has electronic components and circuit structures such as an inductor L, an output capacitor COUT, and a power switch circuit composed of at least one power switch tube. By controlling the conduction and turn-off of the power switch tubes in the power switch circuit through the control circuit 10, the power stage circuit 11 converts the input voltage VIN into the output voltage VOUT. The power stage circuit 11 can be any suitable topology such as a Buck topology, a Boost topology, or a Buck-Boost topology.

[0045] As an example, please refer to Figure 1, the power stage circuit 11 is a buck topology, which includes a high-side power switch HS, a low-side power switch LS, an inductor L, and an output capacitor COUT. Among them, the high-side power switch HS and the low-side power switch LS are connected to form a power switch circuit, and the high-side power switch HS and the low-side power switch LS can be any controllable semiconductor switch device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a triode, etc. The control circuit 10 outputs drive signals VGATEP and VGATEN to control the high-side power switch HS and the low-side power switch LS to alternately conduct and turn off.

[0046] In this embodiment, the control circuit 10 internally integrates a conduction time control circuit (ON_TIMER) 100, a first error amplifier EA1, a PWM generator 101, a zero-crossing detection circuit (not labeled), and a logic control circuit 102.

[0047] The first error amplifier EA1 is used to compare and amplify the error between the first reference voltage VREF1 and the feedback voltage VFB of the output voltage VOUT of the DC-DC conversion circuit, so as to obtain an error amplification signal VEAO that is positively correlated with the magnitude of the load current ILOAD.

[0048] The PWM generator 101 is coupled to the first error amplifier EA1 and is used to generate a pulse width modulation signal PWM according to the node voltage VSW of the high-side power switch HS and the low-side power switch LS (i.e., the node voltage of the power switch circuit) and the error amplification signal VEAO.

[0049] The output end of the zero-crossing detection circuit is coupled to the logic control circuit 102. The zero-crossing detection circuit is used to detect the zero-crossing point of the node voltage VSW of the corresponding power switch circuit of the power stage circuit 11 to generate a zero-crossing signal ZCD.

[0050] The conduction time control circuit (ON_TIMER) 100 is coupled to the first error amplifier EA1 and is used to generate a conduction time control signal TON for controlling the conduction time of the high-side power switch HS and the low-side power switch LS according to the input voltage VIN, the output voltage VOUT, the error amplification signal VEAO of the DC-DC conversion circuit, and the corresponding load indication signal LOAD. Among them, the load indication signal LOAD is used to represent the load state of the DC-DC conversion circuit, and it can be obtained by sensing the output current or output voltage at the output end of the DC-DC conversion circuit through a corresponding load detection circuit and comparing it with a corresponding reference current or reference voltage. As an example, please refer to Figure 2, the load indication signal LOAD can be a high-low level signal to indicate a light load state and a non-light load state; for example, when the load indication signal LOAD is active high, it indicates that the DC-DC conversion circuit is operating in a light load state (also known as a low load state, low load mode), and the control circuit 10, based on the on-time control signal TON generated by the on-time control circuit 100, causes the power switch HS (or LS) to have an on-time (i.e., Figure 5 the t shown in on _1) that decreases as the DC value VEAO_DC of the error amplification signal VEAO decreases (i.e., as the load current ILOAD decreases), and increases as the DC value VEAO_DC of the error amplification signal VEAO increases (i.e., as the load current ILOAD increases); when the load indication signal LOAD is low level (i.e., invalid), it indicates that the DC-DC conversion circuit is operating in a non-light load state (such as a normal load state or a heavy load state), and the control circuit 10, based on the on-time control signal TON generated by the on-time control circuit 100, causes the power switch HS (or LS) to have a fixed on-time in each switching cycle (i.e., Figure 5 the t shown in on ), and the on-time control signal TON causes the on-time of the power switch in each switching cycle in the light load state (i.e., Figure 5 the t shown in on _1) to be shorter than the on-time in each switching cycle in the non-light load state (i.e., Figure 5 the t shown in on ).

[0051] The logic control circuit 102 is coupled to the PWM generator 101, the on-time control circuit 100, the zero-crossing detection circuit, and the gates of the power switches HS and LS. The logic control circuit 102 performs logic operations (such as AND logic operations) on the pulse width modulation signal PWM, the zero-crossing signal ZCD, and the on-time control signal TON to generate drive signals VGATEP and VGATEN to drive the power switches HS and LS to alternately turn on and off. The PWM is mainly used to determine the switching cycle (or switching frequency) of the power switches HS and LS, and the on-time control signal TON is mainly used to determine the on-time of the power switches HS and LS in each switching cycle. The zero-crossing signal ZCD is mainly used to turn off the power switch HS or LS in a timely manner when it needs to be turned off, to prevent problems such as backflow and unnecessary power consumption.

[0052] Therefore, when the DC-DC conversion circuit in COT mode operates at low load, without changing the peripheral circuit of the control circuit 10, by controlling the introduction of the light load indication signal LOAD and the error amplification signal VEAO that is positively correlated with the load current into the conduction time control module 100, the charging time (i.e., the conduction time) of the power switch tube HS (or LS) in each switching cycle is shortened. And since VEAO contains the information of the load current, the conduction time can be automatically adjusted according to the load size in the light load state, so that the output voltage VOUT remains stable and has a small ripple in different light load states. This mode with a shorter conduction time can be used in parallel with the COT mode as a supplementary control in the low load mode.

[0053] It should be understood that circuit modules such as the conduction time control circuit 100, the first error amplifier EA1, the PWM generator 101, the zero-crossing detection circuit (not marked), and the logic control circuit 102 can adopt any suitable circuit design, and the present invention does not make specific limitations on this.

[0054] As an example, please refer to Figure 2 , the conduction time control circuit 100 includes an input voltage conversion circuit 100a, a load current introduction circuit 100b, a voltage conversion circuit 100c, and a first comparator CMP0.

[0055] Among them, the input voltage conversion circuit 100a is used to receive the input voltage VIN and convert the input voltage VIN into an input current I1 = VIN / Rton.

[0056] The load current introduction circuit 100b is coupled to the output terminal of the first error amplifier EA1 and the load indication signal LOAD, and is used to convert the error amplification signal VEAO output by the first error amplifier EA1 into an error current I2 that can reflect the change of the load current ILOAD, and output it to the voltage conversion circuit 100c when the load indication signal LOAD is valid (for example, high level). That is, when the load indication signal LOAD is valid (for example, high level), I2≠0, and when the load indication signal LOAD is invalid (for example, low level), I2 = 0.

[0057] The voltage conversion circuit 100c is coupled to the output terminal of the input voltage conversion circuit 100a and the output terminal of the load current introduction circuit 100b, and is used to superimpose the input current I1 and the current I2 provided by the load current introduction circuit, and further convert the superimposed current I into a corresponding voltage Vton; among them, when the load indication signal LOAD is invalid, the current I2 = 0, and at this time the voltage conversion circuit 100c actually converts the input current I1 into the corresponding voltage Vton.

[0058] The first input terminal (e.g., the non-inverting input terminal “+”) of the first comparator CMP0 is coupled to the voltage conversion circuit 100c to receive the voltage Vton, and the second input terminal (e.g., the inverting input terminal “-”) receives the output voltage VOUT. The first comparator CMP0 is used to compare the magnitudes of the voltage VOUT and the voltage Vton converted by the voltage conversion circuit, so as to output a conduction time control signal TON.

[0059] Among them, when the load indication signal LOAD is valid, it indicates that the DC-DC conversion circuit is operating in a light load state. At this time, the conduction time control signal TON makes the power switch HS (or LS) have a first conduction time t on _1 in each switching cycle, and this first conduction time t ON _1 increases as the error current I2 (which reflects the change in the load current ILOAD) increases, and decreases as the error current I2 decreases. When the load indication signal LOAD is invalid, it indicates that the DC-DC conversion circuit is operating in a non-light load state. The error current I2 cannot be output to the voltage conversion circuit 100c, and it can be regarded that the I2 received by the voltage conversion circuit 100c is 0. At this time, the conduction time control signal TON makes the power switch HS (or LS) have a second conduction time t on in each switching cycle, and this second conduction time t on is constant, and t on = Q / I1 = Vout*Cton / (VIN / Rton) = Vout*Cton*Rton / VIN.

[0060] It should be understood that circuit modules such as the input voltage conversion circuit 100a, the load current introduction circuit 100b, the voltage conversion circuit 100c, and the first comparator CMP0 inside the conduction time control circuit 100 can adopt any suitable circuit design, and the present invention does not make specific limitations on this.

[0061] As an example, the input voltage conversion circuit 100a includes a second error amplifier EA2, a conversion switch M0, and a first resistor Rton. Among them, the conversion switch M0 can be any controllable semiconductor switch device, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a triode, etc. The source of the conversion switch M0 is coupled to one end of the first resistor Rton and the second input terminal (such as the inverting input terminal "-") of the second error amplifier EA2. The other end of the first resistor Rton is grounded. The first input terminal (such as the non-inverting input terminal "+") of the second error amplifier EA2 serves as the input terminal of the input voltage conversion circuit 100a and is connected to the input voltage VIN. The output terminal of the second error amplifier EA2 is coupled to the gate of the conversion switch M0. The drain of the conversion switch M0 serves as the output terminal of the input voltage conversion circuit 100a and outputs a corresponding input current I1 = VIN / Rton.

[0062] As another example, in addition to including the second error amplifier EA2, the conversion switch M0, and the first resistor Rton, the input voltage conversion circuit 100a further includes a first switching transistor M1 and a second switching transistor M2. The gates of the first switching transistor M1 and the second switching transistor M2 are both coupled to the drain of the first switching transistor M1 and the drain of the conversion switch M0 to access the input current I1. The drain of the second switching transistor M2 is coupled to the output terminal of the load current introduction circuit 100b (such as the source of the fifth switching transistor M5), the voltage conversion circuit 100c (such as the upper plate of the capacitor Cton), and the first input terminal (such as the non-inverting input terminal "+") of the first comparator CMP0. The sources of the first switching transistor M1 and the second switching transistor M2 are both coupled to the corresponding power supply voltage (not shown). Among them, the second switching transistor M2 and the first switching transistor M1 form a current mirror. The second switching transistor M2 is used to mirror the current (i.e., the input current) I1 flowing through the first switching transistor M1, and the mirror ratio is equal to the aspect ratio of the second switching transistor M2 to the second switching transistor M2.

[0063] As an example, the load current introduction circuit 100b includes third to fifth switching transistors M3 to M5 and a bias circuit BIAS. The input terminal of the bias circuit BIAS is coupled to the output terminal of the first error amplifier EA1 and is configured to obtain the DC value VEAO_DC of the error amplification signal VEAO output by the first error amplifier EA1; the gates of the third switching transistor M3 and the fourth switching transistor M4 are both coupled to the output terminal of the bias circuit BIAS and the drain of the fourth switching transistor M4, the drain of the third switching transistor M3 is coupled to the drain of the fifth switching transistor M5, the source of the fifth switching transistor M5 is coupled to the input terminal of the voltage conversion circuit (i.e., the upper plate of the capacitor Cton) and the first input terminal of the first comparator CMP0, and the gate of the fifth switching transistor M5 serves as the control terminal of the load current introduction circuit 100b and receives the load indication signal LOAD. Among them, M3 and M4 form a current mirror, and M3 is used to mirror the current flowing through M4, and the mirror ratio is equal to the aspect ratio of M3 and M4. Taking the aspect ratio of M3 and M4 as 1:1 as an example, when the load indication signal LOAD is valid (for example, high level), M5 is turned on, and the current I2 flowing through M5 is equal to the current flowing through M3. At this time, under the biasing action of the DC value VEAO_DC, the current I2 flowing through M5 = (VIN - VEAO_DC - VTH) * gm, where VTH is the threshold voltage of M4 and gm is the transconductance of M4. When the load indication signal LOAD is invalid (for example, low level), M5 is turned off and I2 = 0.

[0064] Obviously, the load current introduction circuit 100b of this embodiment only operates when the LOAD signal is valid, thereby avoiding changing the operating frequency of the DC-DC conversion circuit during heavy load.

[0065] As an example, the voltage conversion circuit 100c includes an adder U0, a capacitor Cton, and a sixth switching transistor M6. One input terminal of the adder U0 is coupled to the drain of M2, the other input terminal is coupled to the source of M5, and the output terminal is coupled to one end (i.e., the upper plate) of the capacitor Cton, the drain of the sixth switching transistor M6, and the first input terminal of the first comparator CMP0. The other end (i.e., the lower plate) of the capacitor Cton and the source of the sixth switching transistor M6 are both grounded, and the gate of the sixth switching transistor M6 receives a corresponding control signal, and this control signal is usually in phase with the corresponding driving signal received in the power switch circuit (this driving signal is generated based on the on-time control signal TON), but the gate of the sixth switching transistor M6 is usually not directly coupled to the gate of the power switching transistor in the power switch circuit. For example, when the sixth switching transistor M6 is an NMOS transistor, the control signal received by its gate can be in phase with the driving signal received by the gate of the power switching transistor LS. In this article, in order to indicate that the signals received by the two gates are in phase, Figure 2The control signal of the sixth switching transistor M6 is also marked as VGATEN. Thus, when the power switching transistor HS needs to be turned on and LS is turned off, the sixth switching transistor M6 is also turned off. Further, when the load indication signal LOAD is valid (for example, at a high level, indicating a light load state), the capacitor Cton is charged with a current I = I1 + I2, and the charging time is the on-time t on _1 of the power switching transistor HS. When the load indication signal LOAD is invalid, I2 = 0, and the capacitor Cton is charged with a current I = I1, and the charging time is the on-time t on of the power switching transistor HS. Then, the current I output by superimposing the input voltage conversion circuit 100a and the load current introduction circuit 100b is converted into a corresponding voltage Vton = Q / Cton = I*t / Cton. When the power switching transistor HS needs to be turned off and LS is turned on, the sixth switching transistor M6 is also turned on, and at this time, the capacitor Cton is discharged to reset Vton.

[0066] Figure 2 The working principle of the conduction control circuit shown is as follows:

[0067] When the DC-DC conversion circuit is working, M0, M1, and M2 are all turned on. M2 mirrors the input current I1 flowing through M1 and outputs it to the upper plate of the capacitor Cton.

[0068] When the load indication signal LOAD is valid (for example, at a high level), it indicates that the DC-DC conversion circuit is working in a light load state. M5 is turned on, and the bias circuit BIAS obtains the DC value VEAO_DC corresponding to the error amplification signal VEAO output by the first error amplifier EA1. The DC value VEAO_DC is converted into an error current through M4, and M3 mirrors the error current flowing through M4 as I2 and outputs it to the upper plate of the capacitor Cton through M5. Thus, the capacitor Cton is charged with a superimposed current I = I1 + I2, and then the converted voltage Vton = Q / Cton = I*t on _1 / Cton is obtained. Thus, it can be obtained that:

[0069] t on _1 = Cton*VOUT / [VIN / Rton+(VIN - VEAO_DC - VTH,P)*gm,p].

[0070] Obviously, the larger VEAO_DC is (i.e., the larger the load current is), the larger t on _1 is. On the contrary, the smaller VEAO_DC is (i.e., the smaller the load current is), the smaller t on _1 is.

[0071] When the load indication signal LOAD is invalid (e.g., at a low level), the DC-DC conversion circuit operates in a non-light load state (e.g., a normal load state or a heavy load state), M5 is turned off, I2 = 0, and at this time, I = I1 = VIN / Rton, t on = Cton*VOUT / (VIN / Rton). Obviously, t on is greater than t on _1.

[0072] It should be understood that in the above example, the aspect ratios of M2 and M1 are 1:1, and the aspect ratios of M3 and M4 are 1:1 for illustration, but the technical solution of the present invention is not limited thereto.

[0073] As an example, please refer to Figure 1 , the PWM generator 101 includes a ramp generator RAMP and a second comparator CMP1. Among them, the ramp generator RAMP is used to compare the node voltage VSW of the connection node of the power switch tubes HS and LS with the second reference voltage VREF2 to generate a ramp voltage signal VRAMP. The first input terminal of the second comparator CMP1 is coupled to the output terminal of the first error amplifier EA1, and the second input terminal is coupled to the output terminal of the ramp generator RAMP. The second comparator CMP1 is used to compare the magnitudes of the error amplification signal VEAO and the ramp voltage signal VRAMP to generate the required pulse width modulation signal PWM. Optionally, the ramp generator RAMP includes a differential current generation circuit 101a and a ramp voltage signal generation circuit 101b. The differential current generation circuit 101a is used to receive the node voltage VSW of the connection node of the power switch tubes HS and LS and the second reference voltage VREF2, and convert the difference between the node voltage VSW and the second reference voltage VREF2 into a differential current I3; the ramp voltage signal generation circuit 101b is coupled to the differential current generation circuit 101a and is used to convert the differential current I3 into a ramp voltage signal VRAMP.

[0074] It should be understood that the differential current generation circuit 101a, the ramp voltage signal generation circuit 101b inside the ramp generator RAMP, and the second comparator CMP1 can adopt any suitable circuit design, and the present invention does not make specific limitations thereto.

[0075] As an example, please refer to Figure 3, the differential current generating circuit 101a includes a third error amplifier EA3, a seventh switching transistor M7, and a second resistor R1. The first input terminal (e.g., the non-inverting input terminal “+”) of the third error amplifier EA3 is connected to a second reference voltage VREF2. The second input terminal (e.g., the inverting input terminal “-”) of the third error amplifier EA3 is coupled to the source of the seventh switching transistor M7 and one end of the second resistor R1. The other end of the second resistor R1 is connected to the node voltage VSW. The output terminal of the third error amplifier EA3 is coupled to the gate of the seventh switching transistor M7. When the seventh switching transistor M7 is turned on, a differential current I3 is output.

[0076] As an example, the ramp voltage signal generating circuit 101b includes eighth to tenth switching transistors M8 to M10 and a third resistor R3. The sources of the eighth to tenth switching transistors M8 to M10 are mutually coupled. The gates of the eighth switching transistor M8 and the ninth switching transistor M9 are both coupled to the drain of the eighth switching transistor M8 and the drain of the seventh switching transistor M7. The drains of the ninth switching transistor M9 and the tenth switching transistor M10 are both connected to one end of the third resistor R3. The other end of the third resistor R3 is grounded. The gate of the tenth switching transistor M10 receives a corresponding control signal, which is usually in phase with the corresponding drive signal received in the power switching circuit (the drive signal is generated based on the on-time control signal TON), but the gate of the tenth switching transistor M10 is usually not directly coupled to the gate of the power switching transistor in the power switching circuit. For example, when the tenth switching transistor M10 is a PMOS transistor, the control signal received by its gate can be in phase with the drive signal VGATEP received by the gate of the power switching transistor HS. In this article, in order to indicate that the signals received by the two gates are in phase, in Figure 2 the control signal of the gate of the tenth switching transistor M10 is also marked as VGATEP. Thus, when the power switching transistor HS is turned on, the tenth switching transistor M10 is also turned on. When the power switching transistor HS is turned off, the tenth switching transistor M10 is also turned off.

[0077] Taking the DC-DC conversion circuit of the control circuit 10 with the structure shown in Figures 1 to 3 as an example, when it operates in the heavy load state in the CCM (Continuous Conduction Mode) mode, the signal timing of the control circuit 10 is as shown in Figure 4 . Combining with the circuit structure of the ramp generator RAMP shown in Figure 3 , the positive correlation between the ramp voltage signal VRAMP and the load current ILOAD can be deduced as follows:

[0078] VSW = 0 - IL * Rdsn,

[0079] I1 = (VREF2 - VSW) / R1,

[0080] VRAMP = I1 * R2 = [VREF2 + IL * Rdsn] * R2 / R1,

[0081] IL = ILOAD + VOUT * T * (1 - VOUT / VIN) / 2 / L - VOUT * t / L.

[0082] Wherein, IL is the inductor current flowing through the inductor L, Rdsn is the on-resistance of the power switch HS or LS, and ILOAD is the load current of the DC-DC conversion circuit. During the operation of the DC-DC conversion circuit, VIN, VOUT, the period T, and L are all fixed constants. Therefore, IL and VRAMP can be respectively equivalent to:

[0083] IL = ILOAD + K1 - K2 * t,

[0084] VRAMP = K3 + K4 * ILOAD - K5 * t.

[0085] Wherein, K1, K2, K3, K4, and K5 are all equivalent coefficients.

[0086] It can be seen from this that the value of ILOAD is positively correlated with VRAMP. According to the loop control analysis of the control circuit 10 as shown in Figures 1 to 3 , the DC value VEAO_DC of VEAO is actually determined by VRAMP in the circuit of the control circuit 10. Therefore, the change in the DC value VEAO_DC of VEAO can reflect the change in the load current ILOAD. Introduce VEAO into the on-time control circuit 100a to control the on-time TON, and based on Figure 3 the ramp generator circuit shown, t on _1 = Cton * VOUT / [VIN / Rton + (VIN - VEAO_DC - VTH) * gm] can be obtained. From this, it can also be proved that the DC value VEAO_DC of VEAO is proportional to TON. That is to say, the DC value VEAO_DC of VEAO is determined by VRAMP and is positively correlated with ILOAD. The DC value VEAO_DC of VEAO decreases as ILOAD decreases, and t on _1 will also gradually shorten as the DC value VEAO_DC of VEAO decreases.

[0087] To better illustrate the technical effects of the technical solution of this embodiment, two DC-DC conversion circuits are constructed under the condition that other circuit structures and conditions are the same. In the first DC-DC conversion circuit, the on-time control circuit is relatively Figure 2 M3, M4, and M5 are omitted. Therefore, the load indication signal LOAD and the error amplification signal VEAO control are not introduced, and the timing of each signal is as shown in Figure 5as shown in (A) of; The second DC-DC conversion circuit adopts the on-time control circuit of this embodiment as shown in Figure 2 to introduce the load indication signal LOAD and the error amplification signal VEAO for control, and the timing of each signal is as shown in Figure 5 in (B) of. Comparing Figure 5 (A) and (B) of, it can be seen that the fluctuation of the output voltage VOUT of the DC-DC conversion circuit adopting the on-time control circuit of this embodiment as shown in Figure 2 becomes significantly smaller. Therefore, this embodiment can effectively reduce the output voltage ripple of the DC-DC conversion circuit.

[0088] Further analyzing the situation of the above-mentioned second DC-DC conversion circuit when the load size changes under the light load state, the signal timing diagram as shown in Figure 6 is obtained. From Figure 6 it can be seen that under the light load state, when the load becomes lighter (i.e., the load decreases), t on _1 decreases accordingly (from t on _1b to t on _1a), and when the load becomes heavier (i.e., the load increases), t on _1 increases accordingly (from t on _1a to t on _1b). Moreover, the VOUT ripple is relatively stable throughout the light load range. The reasons for this phenomenon are as follows:

[0089] Under the light load state, within each switching cycle of the power switch HS or LS, the energy output by the loop of the DC-DC conversion circuit is: [t on _1*(VIN - VOUT) / L]*t on _1 / D / 2, where D is the switching duty ratio of the power switch HS or LS;

[0090] At the moment when the charging of the power switch HS or LS ends, the energy consumed by the load is: ILOAD * t on _1 / D;

[0091] According to the capacitor characteristics, the voltage ripple generated on the output capacitor COUT during this process is: [t on _1*(VIN - VOUT) / 2 / L - ILOAD]*t on _1 / D / COUT.

[0092] When the VEAO control is not introduced, under the COT control, t on_1 is constant. If ILOAD drops, the VOUT ripple will increase. However, after the introduction of VEAO control in the present invention, taking the load increase as an example, the direct impact of the load increase is that VRAMP based on current sampling increases. Also, because as mentioned above, in the loop of the DC-DC conversion circuit, the DC value VEAO_DC of VEAO is strongly correlated with VRAMP. When the load increases, the load current ILOAD increases, and the DC value VEAO_DC of VEAO also increases accordingly. This will cause the error current I2 introduced by VEAO_DC in the conduction time control circuit 100a to decrease, the charging speed of the capacitor Cton inside the conduction time control circuit 100a to decrease, and the flip time of the first comparator CMP0 to be delayed. Thus, the conduction time ton_1 corresponding to the output TON increases relative to when the load is lighter. The intuitive impact of this is that the corresponding power switch HS or LS transfers more energy to the output terminal in each switching cycle. However, because the output power consumption also increases due to the increased load, so when the specific parameters of the circuit are reasonably selected, the energy "remaining" on the output capacitor COUT in each switching cycle can remain unchanged, that is, the VOUT ripple remains at a stable and low value. Similarly, when the load drops, the energy "remaining" on the output capacitor COUT in each switching cycle can also remain unchanged. That is to say, in the entire light load range, after the introduction of VEAO control, regardless of how the load changes, the VOUT ripple remains at a stable and low value, which will not be elaborated here again.

[0093] That is to say, in this embodiment, the load indication signal LOAD reflecting the load state of the DC-DC conversion circuit and the error amplification signal VEAO are jointly introduced into the conduction time control circuit. The conduction time control circuit can control the conduction time of the power switch circuit in the corresponding switching cycle to be adjustable according to the input voltage, output voltage, load indication signal LOAD, and error amplification signal VEAO, so as to adjust the peak value of the output voltage. Thus, the energy output in the switching cycle under different load states is different, and the lighter the load state, the smaller the DC value of the corresponding error amplification signal, and the shorter the conduction time as the DC value of the error amplification signal decreases. The heavier the load state, the larger the DC value of the corresponding error amplification signal, and the longer the conduction time as the DC value of the error amplification signal increases. Therefore, in different load states, the problem of large output voltage ripple caused by excessive energy on the output capacitor is avoided.

[0094] It should be understood that in the above embodiment, the load indication signal LOAD only has two states, high level and low level. Therefore, it can only indicate two load states, the light load state and the non-light load state. Therefore, as Figure 2 shown, there can be only one switching MOS transistor M5, but the technical solution of the present invention is not limited thereto.

[0095] In another embodiment of the present invention, please refer to Figure 7 , a load indication signal LOAD may include n load indication signals LOAD1 to LOADn corresponding one-to-one to n load states. These n load indication signals LOAD1 to LOADn can be obtained by comparing the detected output voltage Vout or output current with n reference voltages or reference currents through corresponding load detection circuits. In the load current introduction circuit 100b in the on-time control circuit 100, n fifth switching transistors M51 to M5n are provided corresponding to the n load indication signals LOAD1 to LOADn. The drains of the fifth switching transistors M51 to M5n are all coupled to the drain of M3. The sources of the fifth switching transistors M51 to M5n are coupled to each other and are connected together to an input terminal of the adder U0. The gates of the fifth switching transistors M51 to M5n serve as the control terminals of the load current introduction circuit 100b and receive the load indication signals LOAD1 to LOADn one-to-one. The fifth switching transistors M51 to M5n play a role in shunting the current output by M3. Among them, the fifth switching transistors M51 to M5n can be transistors with the same aspect ratio or transistors with different aspect ratios. When the aspect ratios of the fifth switching transistors M51 to M5n are the same, the fifth switching transistors M51 to M5n are equivalent to dividing the current (VIN - VEAO_DC - VTH)*gm flowing through M3 into n paths, and the magnitude of each path of current is K*(VIN - VEAO_DC - VTH)*gm / n, where VTH is the threshold voltage of M4 and gm is the transconductance of M4.

[0096] Optionally, 0 < K < 1, thereby avoiding unnecessary power consumption caused by too small on-time in the light load state.

[0097] In this embodiment, the higher the load of the DC-DC conversion circuit, the fewer the number of conducting MOS transistor switches in the fifth switching transistors M51 to M5n (at least zero can be turned on, corresponding to the state of the highest load), and the lower the load, the more the number of conducting MOS transistor switches in the fifth switching transistors M51 to M5n (at most n can be turned on, corresponding to the state of the lowest load). At this time, the current received by the first input terminal of the first comparator CMP0 is I = I1 + I2, I2 = x*(VIN - VEAO_DC - VTH)*gm / n, and the on-time in each switching cycle of the corresponding power switch circuit is:

[0098] t ON = VOUT * Cton / [VIN / Rton + x*(VIN - VEAO_DC - VTH)*gm / n];

[0099] where x is the number of conducting MOS transistor switches in the fifth switching transistors M51 to M5n.

[0100] When x = 0, the conduction time t ON is relatively the longest. When x = n, the conduction time t ON is relatively the shortest. That is to say, the smaller the load (i.e., the smaller), the larger x, and the shorter the conduction time t ON is. The larger the load (i.e., the heavier), the smaller x, and the longer the conduction time t ON is.

[0101] Thus, in this embodiment, when the DC-DC conversion circuit in the COT mode works, without changing the peripheral circuit of the control circuit 10, by introducing the control of n load indication signals LOAD1~LOADn and the error amplification signal VEAO into the conduction time control module 100, the charging time (i.e., the conduction time t ON ) of the power switch tube HS (or LS) in each switching cycle can be adjusted under different load states. And the lighter the load, the shorter the conduction time t ON is. The heavier the load, the longer the conduction time t ON is. Furthermore, the output voltage VOUT can be kept stable and have a small ripple under different load states. The mode of controlling the change of the conduction time can be used in parallel with the COT mode as supplementary control under different load modes.

[0102] Based on the same inventive concept, please refer to Figure 1 , this embodiment also provides a DC-DC conversion circuit, which includes a power stage circuit 11 and the control circuit 10 as described in this embodiment. The power stage circuit 11 can adopt any suitable topology structure such as a Buck type topology structure or a Buck-boost type topology structure or a Boost type topology structure, and its power switch circuit has corresponding power switch tubes, such as Figure 1 HS and LS in

[0103] . The control circuit 10 is coupled to the gates of the corresponding power switch tubes in the power switch circuit of the power stage circuit 11 to turn on and off under the control of this control circuit, so that the DC-DC conversion circuit works in the corresponding mode (such as the COT mode), and converts the input voltage VIN into the output voltage VOUT.

[0104] It should be understood that the internal structure of the control circuit 10 in the above embodiment and other structures of the DC-DC conversion circuit are only for example, and it does not mean that the internal structure of the control circuit 10 of the present invention and the structure of the DC-DC conversion circuit are only limited to this. In other embodiments of the present invention, the control circuit may also have other functional circuits inside, and some functional circuits may also be omitted. The DC-DC conversion circuit may also include other circuit structures.

[0104] For example, in another embodiment of the present invention, please refer to Figure 7, the control circuit of the DC-DC conversion circuit omits the zero-crossing detection circuit. The logic control circuit 102 performs corresponding logical operations on the pulse-width modulation signal PWM and the conduction time control signal TON to control the on and off of the corresponding power switch transistors in the power switch circuit of the power stage circuit 11.

[0105] For another example, please refer to Figure 7 , the DC-DC conversion circuit further includes a feedback circuit (not marked), which can sample the output voltage VOUT to generate a feedback voltage VFB for feedbacking the change and magnitude of the output voltage VOUT. As an example, the feedback circuit includes feedback resistors Rfb1 and Rfb2. One end of the resistor Rfb1 is coupled to the upper plate of the output capacitor COUT and one end of the inductor L. The other end of the resistor Rfb1 is connected to one end of the resistor Rfb2 and outputs the feedback voltage VFB. The other end of the resistor Rfb2 is grounded.

[0106] In addition, Figures 1 to 7 M0 to M10 in are all illustrated by corresponding NMOS transistors or PMOS transistors as examples. However, the technical solution of the present invention is not limited thereto. In other embodiments of the present invention, Figures 1 to 7 the corresponding NMOS transistors in can be replaced by any controllable semiconductor switch devices such as PMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc. Similarly, Figures 1 to 7 the corresponding PMOS transistors in can be replaced by any controllable semiconductor switch devices such as NMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc.

[0107] In summary, the control circuit and the DC-DC conversion circuit provided by the present invention do not require larger peripheral devices. Instead, on the basis of the traditional COT mode, a load indication signal and an error amplification signal reflecting the change of the load current are introduced into the conduction time control circuit. The conduction time control circuit controls the conduction time of the power switch circuit within a corresponding switching period to be adjustable according to the input voltage, output voltage, the error amplification signal, and the load indication signal of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Thereby, the energy output within the switching period under different load states is different, the ripple of the output voltage is reduced and relatively stable within the entire light load range, and the lighter the load state, the smaller the DC value of the corresponding error amplification signal, and the shorter the conduction time as the DC value of the error amplification signal decreases. The heavier the load state, the larger the DC value of the corresponding error amplification signal, and the longer the conduction time as the DC value of the error amplification signal increases, avoiding the problem of large output voltage ripple caused by excessive energy on the output capacitor.

[0108] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the technical solution of the present invention.

Claims

1. A control circuit for a DC-DC conversion circuit, the DC-DC conversion circuit converting an input voltage into an output voltage by turning on and off a corresponding power switch circuit, characterized in that, Comprising: A first error amplifier for comparing and amplifying the error between a first reference voltage and a feedback voltage of the output voltage to obtain an error amplification signal whose DC value is positively correlated with the magnitude of the load current; A conduction time control circuit coupled to the output terminal of the first error amplifier and configured to control the conduction time of the power switch circuit to be adjustable within a corresponding switching period according to the input voltage, the output voltage, the error amplification signal, and a load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage.

2. The control circuit according to claim 1, wherein, The lighter the load state of the DC-DC conversion circuit, the smaller the DC value of the corresponding error amplification signal, and the shorter the corresponding conduction time as the DC value of the error amplification signal decreases; the heavier the load state, the larger the DC value of the corresponding error amplification signal, and the longer the corresponding conduction time as the DC value of the error amplification signal increases.

3. The control circuit according to claim 1, wherein, The conduction time control circuit includes: An input voltage conversion circuit for converting the input voltage into an input current; A load current introduction circuit coupled to the first error amplifier and the load indication signal, configured to convert the error amplification signal into an error current reflecting the change in the load current and output it under the control of the load indication signal; A voltage conversion circuit coupled to the input voltage conversion circuit and the load current introduction circuit, and configured to superimpose the input current and the error current output by the load current introduction circuit, and further convert the superimposed current into a corresponding voltage; A first comparator, with its first input terminal coupled to the voltage conversion circuit, its second input terminal receiving the output voltage, and configured to compare the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit to output a corresponding conduction time control signal.

4. The control circuit according to claim 2, wherein The input voltage conversion circuit includes a second error amplifier, a conversion switch, and a first resistor. The source of the conversion switch is coupled to one end of the first resistor and the second input terminal of the first error amplifier. The other end of the first resistor is grounded. The first input terminal of the first error amplifier is connected to the input voltage, and the output terminal of the first error amplifier is coupled to the gate of the conversion switch.

5. The control circuit according to claim 2, characterized in that The input voltage conversion circuit further includes a first switching transistor and a second switching transistor. The gates of the first switching transistor and the second switching transistor are both coupled to the drain of the first switching transistor and the drain of the conversion switch. The drain of the second switching transistor is connected to the load current introduction circuit, the voltage conversion circuit, and the first input terminal of the first comparator.

6. The control circuit according to claim 2, wherein The load current introduction circuit includes a third switching transistor, a fourth switching transistor, n fifth switching transistors, and a bias circuit, where n≥1 and is an integer. The input terminal of the bias circuit is coupled to the first error amplifier and is configured to obtain the DC value of the error amplification signal; The gates of the third switching transistor and the fourth switching transistor are both coupled to the output terminal of the bias circuit and the drain of the fourth switching transistor. The drain of the third switching transistor is coupled to the drains of the respective fifth switching transistors. The sources of the respective fifth switching transistors are coupled to the voltage conversion circuit. The gates of the fifth switching transistors receive the load indication signal, and the lighter the load state of the DC-DC conversion circuit, the more fifth switching transistors are turned on.

7. The control circuit according to claim 2, wherein The voltage conversion circuit includes an adder, a capacitor, and a sixth switching transistor. One input terminal of the adder is coupled to the output terminal of the input voltage conversion circuit. The other input terminal of the adder is coupled to the output terminal of the load current introduction circuit. The output terminal of the adder is coupled to one end of the capacitor and the first input terminal of the first comparator. The other end of the capacitor and the other end of the sixth switching transistor are both grounded. The control terminal of the sixth switching transistor receives a corresponding control signal.

8. The control circuit according to claim 1, wherein Further included: A feedback circuit, coupled to the output terminal of the DC-DC conversion circuit and one input terminal of the first error amplifier, and configured to sample the output voltage to generate a feedback voltage for feeding back the change and magnitude of the output voltage; A PWM generator, coupled to the first error amplifier, and configured to generate a pulse width modulation signal according to the node voltage of the power switch circuit and the error amplification signal; A logic control circuit, coupled to the PWM generator, the conduction time control circuit, and the power switch circuit, and configured to drive the conduction or turn-off of the power switch circuit according to the pulse width modulation signal and the conduction time control signal.

9. The control circuit according to claim 8, wherein The PWM generator includes: A ramp generator, configured to compare the node voltage of the power switch circuit with a second reference voltage to generate a ramp voltage signal; A second comparator, with its first input terminal coupled to the output terminal of the first error amplifier and its second input terminal coupled to the output terminal of the ramp generator, and configured to compare the magnitudes of the error amplification signal and the ramp voltage signal to generate the pulse width modulation signal.

10. The control circuit according to claim 9, wherein The ramp generator includes: A difference current generation circuit, configured to receive the node voltage of the power switch circuit and the second reference voltage and obtain a difference current between the node voltage and the second reference voltage; A ramp voltage signal generation circuit, coupled to the difference current generation circuit, and configured to convert the difference current into the ramp voltage signal.

11. The control circuit according to claim 10, characterized in that, The difference current generation circuit includes a third error amplifier, a seventh switching transistor, and a second resistor. The first input terminal of the third error amplifier is connected to the second reference voltage. The second input terminal of the third error amplifier is coupled to the source of the seventh switching transistor and one end of the second resistor. The other end of the second resistor is connected to the node voltage. The output terminal of the third error amplifier is coupled to the gate of the seventh switching transistor; And / or, the ramp voltage signal generating circuit includes an eighth to a tenth switching transistor and a third resistor. The sources of the eighth to tenth switching transistors are coupled to each other. The gates of the eighth and ninth switching transistors are both coupled to the drain of the eighth switching transistor and the difference current generating circuit. The drains of the ninth and tenth switching transistors are both coupled to one end of the third resistor. The other end of the third resistor is grounded. The gate of the tenth switching transistor receives a corresponding control signal.

12. The control circuit according to claim 8, characterized in that, It further includes a zero-crossing detection circuit for detecting the zero-crossing point of the node voltage of the power switching circuit to generate a zero-crossing signal. The logic control circuit drives the conduction or cutoff of the power switching circuit according to the pulse width modulation signal, the conduction time control signal, and the zero-crossing signal.

13. A DC-DC conversion circuit, characterized in that, It includes a power stage circuit and the control circuit according to any one of claims 1-12. The power switching circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

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