On-time control circuit, control circuit and DC-DC conversion circuit

Abstract

According to the turn-on time control circuit, the control circuit and the DC-DC conversion circuit provided by the invention, a larger external device is not needed, and a load indication signal is introduced into the turn-on time control circuit on the basis of a traditional COT mode; the turn-on time control circuit can control the turn-on time of the power switch circuit in a corresponding switching period to be adjustable according to an input voltage, an output voltage and a load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Therefore, the energy output in the switching period in different load states is different, the lighter the load state of the DC-DC conversion circuit is, the shorter the corresponding conduction time is, the heavier the load state is, and the longer the corresponding conduction time is, so that the problem that excessive energy generates larger output voltage ripples on an output capacitor in different load states is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of power conversion, and particularly relates to a conduction time control circuit, a control circuit and a DC-DC conversion circuit. Background Art

[0002] As a high-efficiency switching power converter, a DC-DC (direct current to direct current) converter has the advantages of fast dynamic response, simple control, and direct control of output current, and is widely used in the power management systems of various products. Among them, the constant on-time (COT) mode is one of the commonly used control modes of DC-DC conversion circuits. By setting a fixed conduction time for the corresponding power switch tube in the power stage circuit, the output voltage of the DC-DC conversion circuit is adjusted.

[0003] In a traditional DC-DC conversion circuit controlled by the COT mode, the conduction time of the power switch tube is constant. Therefore, in the low-load application of the DC-DC conversion circuit controlled by the COT mode, the following problems will occur: the energy output in each charging cycle is the same, but the energy consumed under light load is less, and the excess energy will generate a large output voltage ripple on the output capacitor of the DC-DC conversion circuit. This output voltage ripple will cause many harms and affect the reliability and conversion efficiency of the DC-DC conversion circuit. Therefore, it is necessary to reduce this output voltage ripple. Summary of the Invention

[0004] The purpose of the present invention is to provide a conduction time control circuit, a control circuit and a DC-DC conversion circuit, which can reduce the output voltage ripple in the COT mode without the need for larger external devices.

[0005] To achieve the above purpose, the present invention provides a conduction time control circuit for a DC-DC conversion circuit. The DC-DC conversion circuit converts an input voltage into an output voltage by turning on and off a corresponding power switch circuit. Among them, the conduction time control circuit is used to control the conduction time of the power switch circuit in a corresponding switching cycle to be adjustable according to the input voltage, the output voltage and a load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage.

[0006] Optionally, the lighter the load state of the DC-DC conversion circuit, the shorter the corresponding conduction time, and the heavier the load state, the longer the corresponding conduction time.

[0007] Optionally, the conduction time control circuit includes:

[0008] a current conversion circuit for converting the input voltage into an input current;

[0009] A current mirror circuit, coupled to the current conversion circuit and controlled by the load indication signal, for mirroring and outputting the input current according to a corresponding magnification factor, and the lighter the load state of the DC-DC conversion circuit, the larger the magnification factor;

[0010] A voltage conversion circuit, coupled to the current mirror circuit, for converting the current output by the current mirror circuit into a corresponding voltage;

[0011] A first comparator, with a first input terminal coupled to the voltage conversion circuit, a second input terminal receiving the output voltage, and for comparing the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit to output a corresponding on-time control signal for controlling the on-time.

[0012] Optionally, the current conversion circuit includes a first error amplifier, a conversion switch, and a first resistor. The source of the conversion switch is coupled to one end of the first resistor and the second input terminal of the first error amplifier. The other end of the first resistor is grounded. The first input terminal of the first error amplifier is connected to the input voltage, and the output terminal of the first error amplifier is coupled to the gate of the conversion switch.

[0013] Optionally, the current mirror circuit has first to third mirror MOS transistors and n parallel switch MOS transistors, where n is an integer not less than 1. The gates of the first to third mirror MOS transistors are all coupled to the drain of the first mirror MOS transistor and the current conversion circuit; the drain of the second mirror MOS transistor is coupled to the sources of the respective switch MOS transistors, the voltage conversion circuit, and the first input terminal of the first comparator; the drains of the respective switch MOS transistors are all coupled to the drain of the third mirror MOS transistor, and the gates of the respective switch MOS transistors are all controlled by the load indication signal, and the lighter the load state of the DC-DC conversion circuit, the more the number of the conducting switch MOS transistors.

[0014] Optionally, the current mirror circuit has a first mirror MOS transistor, a second mirror MOS transistor, n third mirror MOS transistors, and n switch MOS transistors, where n is an integer not less than 1. The gates of the first mirror MOS transistor, the second mirror MOS transistor, and the respective third mirror MOS transistors are all coupled to the drain of the first mirror MOS transistor and the current conversion circuit; the drain of the second mirror MOS transistor is coupled to the sources of the respective switch MOS transistors, the voltage conversion circuit, and the first input terminal of the first comparator; the drains of the n switch MOS transistors are respectively coupled to the drains of the n third mirror MOS transistors, and the gates of the respective switch MOS transistors are all controlled by the load indication signal;

[0015] Among them, the width-to-length ratios of the respective third mirror MOS transistors are the same. The lighter the load state of the DC-DC conversion circuit, the more the number of the switched-on switch MOS transistors; or, the width-to-length ratios of the respective third mirror MOS transistors are different. The lighter the load state of the DC-DC conversion circuit, the more the number of the switched-on switch MOS transistors and the larger the sum of the width-to-length ratios of the third mirror MOS transistors connected to the switched-on switch MOS transistors.

[0016] Optionally, the voltage conversion circuit includes a capacitor and a discharge switch. One end of the capacitor is coupled to one end of the discharge switch, the first input terminal of the first comparator, and the current mirror circuit. The other end of the capacitor and the other end of the discharge switch are both grounded. The control terminal of the discharge switch receives a corresponding control signal, and the control signal is in phase with the corresponding drive signal received by the power switch circuit, and the drive signal is generated based on the on-time control signal.

[0017] Optionally, the amplification factor of the current mirror circuit for the input current is 1 + q, where 0 ≤ q < 1.

[0018] Based on the same inventive concept, the present invention further provides a control circuit for controlling the on / off of a corresponding power switch circuit in a DC-DC conversion circuit. The control circuit includes the on-time control circuit for the DC-DC conversion circuit as described in the present invention.

[0019] Optionally, the control circuit further includes:

[0020] A feedback circuit, coupled to the output terminal of the DC-DC conversion circuit, and configured to sample the output voltage to generate a feedback voltage for feeding back the change and magnitude of the output voltage;

[0021] A PWM generator, configured to generate a pulse width modulation signal according to the node voltage of the power switch circuit and the feedback voltage of the output voltage;

[0022] A zero-crossing detection circuit, configured to detect the zero-crossing point of the node voltage of the power switch circuit to generate a zero-crossing signal;

[0023] A logic control circuit, coupled to the PWM generator, the on-time control circuit, the zero-crossing detection circuit, and the power switch circuit, and configured to drive the power switch circuit to conduct or turn off according to the pulse width modulation signal, the on-time control signal, and the zero-crossing signal.

[0024] Optionally, the PWM generator includes:

[0025] A second error amplifier, configured to compare a feedback voltage of an output voltage of the DC-DC conversion circuit with a first reference voltage to generate an error amplified signal;

[0026] A ramp generator, configured to compare a node voltage of the power switch circuit with a second reference voltage to generate a ramp signal;

[0027] A second comparator, having a first input terminal coupled to an output terminal of the second error amplifier and a second input terminal coupled to an output terminal of the ramp generator, configured to compare the error amplified signal and the ramp signal to generate the pulse width modulation signal.

[0028] Based on the same inventive concept, the present invention further provides a DC-DC conversion circuit, which includes a power stage circuit and a control circuit as described in the present invention. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

[0029] Optionally, the power stage circuit adopts a Buck topology or a Buck-boost topology or a Boost topology.

[0030] Compared with the prior art, the technical solution of the present invention does not require larger external components. Instead, on the basis of the traditional COT mode, a load indication signal is introduced into the conduction time control circuit. The conduction time control circuit can control the conduction time of the power switch circuit adjustable within a corresponding switching period according to the input voltage, the output voltage, and the load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Thus, the energy output within the switching period under different load states is different. The lighter the load state of the DC-DC conversion circuit, the shorter the corresponding conduction time, and the heavier the load state, the longer the corresponding conduction time. Therefore, the problem of large output voltage ripple generated on the output capacitor by redundant energy under different load states is avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Those of ordinary skill in the art will understand that the provided drawings are used to better understand the present invention and do not constitute any limitation to the scope of the present invention. Among them:

[0032] Figure 1 is a schematic structural diagram of a DC-DC conversion circuit and a control circuit for the DC-DC conversion circuit according to an embodiment of the present invention.

[0033] Figure 2 is a schematic structural diagram of an example of a conduction time control circuit according to an embodiment of the present invention.

[0034] Figure 3 is based on Figure 1Schematic diagram of signal timing comparison of two obtained DC-DC conversion circuits (with or without load indication signal control).

[0035] Figure 4 It is a schematic diagram of the architecture of a DC-DC conversion circuit according to another embodiment of the present invention and a control circuit for the DC-DC conversion circuit.

[0036] Figure 5 Based on Figure 4 Schematic diagram of signal timing comparison of two obtained DC-DC conversion circuits (with or without load indication signal control).

[0037] Figure 6 It is a schematic diagram of another example structure of a conduction time control circuit according to an embodiment of the present invention.

[0038] Figure 7 It is a schematic diagram of yet another example structure of a conduction time control circuit according to an embodiment of the present invention. Detailed implementation manners

[0039] In the following description, numerous specific details are given to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other instances, in order to avoid confusion with the present invention, some well-known technical features are not described. It should be understood that the present invention can be implemented in different forms and should not be construed as limited to the embodiments presented herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. The same reference numerals represent the same elements throughout. It should be understood that when an element is referred to as "connected to", "coupled to" other elements, it can be directly connected to other elements, or there may be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to determine the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0040] The following further elaborates in detail on the technical solutions proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the objectives of the embodiments of the present invention.

[0041] Please refer to Figure 1 , an embodiment of the present invention provides a conduction time control circuit 100 for a DC-DC conversion circuit. The DC-DC conversion circuit has a control circuit 10 and a power stage circuit 11. The power stage circuit 11 has an inductor L, an output capacitor COUT, and a power switch circuit including at least one power switch transistor and other electronic components and circuit structures. The control circuit 10 controls the conduction and turn-off of the power switch circuit in the power stage circuit 11, so that the power stage circuit 11 converts the input voltage VIN into the output voltage VOUT. The power stage circuit 11 can be any suitable topology such as a Buck topology, a Boost topology, or a Buck-Boost topology.

[0042] As an example, please refer to Figure 1 , the power stage circuit 11 is a buck-down Buck topology, which includes an inductor L, an output capacitor COUT, and a power switch circuit formed by connecting a power switch transistor HS and a power switch transistor LS. Among them, the power switch transistor HS and the power switch transistor LS can be any controllable semiconductor switch device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a triode, etc. The control circuit 10 outputs drive signals VGATEP and VGATEN to control the alternating conduction and turn-off of the power switch transistor HS and the power switch transistor LS.

[0043] In this embodiment, the conduction time control circuit (ON_TIMER) 100 belongs to the internal circuit of the control circuit 10, and is used to generate a conduction time control signal TON for controlling the conduction time of the power switch transistors HS and LS according to the input voltage VIN, the output voltage VOUT of the DC-DC conversion circuit, and the corresponding load indication signal LOAD. Among them, the load indication signal LOAD is used to represent the load state of the DC-DC conversion circuit, and it can be obtained by sensing the output current or output voltage at the output end of the DC-DC conversion circuit through a corresponding load detection circuit and comparing it with a corresponding reference current or reference voltage. As an example, please refer to Figure 2 , the load indication signal LOAD can be a high-low level signal to indicate a light load state and a non-light load state; for example, when the load indication signal LOAD is high-level effective, it means that the DC-DC conversion circuit is operating in a light load state (also known as a low load state, a low load mode), and the control circuit 10 makes the power switch transistor HS (or LS) have a first conduction time t in each switching cycle based on the conduction time control signal TON generated by the conduction time control circuit ON_1; When the load indication signal LOAD is at a low level (i.e., invalid), it indicates that the DC-DC conversion circuit is operating in a non-light load state (such as a normal load state or a heavy load state). The control circuit 10, based on the on-time control signal TON generated by the on-time control circuit, causes the power switch HS (or LS) to have a second on-time t ON in each switching cycle, and the first on-time t ON _1 is shorter than the second on-time t ON . Thus, when the DC-DC conversion circuit in COT mode operates in a low load state, without changing the peripheral circuit of the control circuit 10, by introducing the control of the load indication signal LOAD into the on-time control module 100, the charging time (i.e., the on-time t ON ) of the power switch HS (or LS) in each switching cycle is shortened, so that the output voltage VOUT remains stable and has a small ripple in the light load state. This mode of shortening the control on-time can be used in parallel with the COT mode as a supplementary control in the low load mode.

[0044] It should be understood that the on-time control circuit 100 can adopt any suitable circuit design, and the present invention does not make specific limitations thereto.

[0045] Only as an example, please refer to Figure 2 , the on-time control circuit 100 includes a current conversion circuit 100a, a current mirror circuit 100b, a voltage conversion circuit 100c, and a first comparator CMP0. Among them, the current conversion circuit 100a is used to receive the input voltage VIN and convert the input voltage VIN into an input current I1 = VIN / Rton; the current mirror circuit 100b is coupled to the current conversion circuit 100a and is controlled by the load indication signal LOAD, and is used to mirror and amplify the input current I1 by 1 + K times when the load indication signal LOAD is valid (such as at a high level), that is, at this time I2 = (1 + K)*VIN / Rton, where K is a value greater than 0 and less than 1. When the load indication signal LOAD is invalid (such as at a low level), the input current I1 is mirrored in a 1:1 ratio, that is, at this time I2 = VIN / Rton; the voltage conversion circuit 100c is coupled to the current mirror circuit 100b and is used to convert the current I2 output by the current mirror circuit 100b into a corresponding voltage Vton; the first input terminal (such as the non-inverting input terminal “+”) of the first comparator CMP0 is coupled to the voltage conversion circuit 100c to receive the voltage Vton, and the second input terminal (such as the inverting input terminal “-”) receives the output voltage VOUT. The first comparator CMP0 is used to compare the magnitudes of the voltage VOUT and the voltage Vton converted by the voltage conversion circuit to output the on-time control signal TON.

[0046] Among them, when the load indication signal LOAD is valid (for example, high level), it indicates that the DC-DC conversion circuit is operating in a light load state. At this time, the conduction time control signal TON makes the power switch HS (or LS) have a first conduction time t ON _1 in each switching cycle, and the first conduction time t ON _1 is:

[0047] t ON _1 = Q / I2 = Vout * Cton / [(1 + K) * VIN / Rton] = Vout * Cton * Rton / [(1 + K) * VIN],

[0048] where K is a value greater than 0.

[0049] When the load indication signal LOAD is invalid (for example, low level), it indicates that the DC-DC conversion circuit is operating in a non-light load state. At this time, the conduction time control signal TON makes the power switch HS (or LS) have a second conduction time t ON , and:

[0050] t ON = Q / I2 = Vout * Cton / (VIN / Rton) = Vout * Cton * Rton / VIN.

[0051] Obviously, t ON> t ON _1, that is to say, in the light load state, the charging time (i.e., the conduction time t ON ) of the power switch HS (or LS) in each switching cycle is shorter than that in the non-light load state.

[0052] Optionally, 0 < K < 1, so as to avoid unnecessary power consumption caused by too small conduction time in the light load state.

[0053] It should be understood that circuit modules such as the current conversion circuit 100a, current mirror circuit 100b, voltage conversion circuit 100c, and first comparator CMP0 inside the conduction time control circuit 100 can adopt any suitable circuit design, and the internal circuit modules of the conduction time control circuit 100 can also be not limited to these modules such as the current conversion circuit 100a, current mirror circuit 100b, voltage conversion circuit 100c, and first comparator CMP0 according to functional requirements. The present invention does not make specific limitations on this.

[0054] As an example, the current conversion circuit 100a includes a first error amplifier EA0, a conversion switch M0, and a first resistor Rton. Among them, the conversion switch M0 can be any controllable semiconductor switch device, such as a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a triode, etc. The source of the conversion switch M0 is coupled to one end of the first resistor Rton and the second input terminal (such as the inverting input terminal "-") of the first error amplifier EA0. The other end of the first resistor Rton is grounded. The first input terminal (such as the non-inverting input terminal "+") of the first error amplifier EA0 serves as the input terminal of the current conversion circuit 100a and is connected to the input voltage VIN. The output terminal of the first error amplifier EA0 is coupled to the gate of the conversion switch M0. The drain of the conversion switch M0 serves as the output terminal of the current conversion circuit 100a and outputs the corresponding input current I1 = VIN / Rton.

[0055] As an example, the current mirror circuit 100b has first to third mirror MOS transistors M1 to M3 and a switching MOS transistor M4. The gates of the first to third mirror MOS transistors M1 to M3 are all coupled to the drain of the first mirror MOS transistor M1 and the drain of the conversion switch M0 to access the input current I1. The drain of the second mirror MOS transistor M2 is coupled to the source of the switching MOS transistor M4, the voltage conversion circuit 100c, and the first input terminal (such as the non-inverting input terminal "+") of the first comparator CMP0. The drain of the switching MOS transistor M4 is coupled to the drain of the third mirror MOS transistor M3. The gate of the switching MOS transistor M4 serves as the control terminal of the current mirror circuit 100b and receives the load indication signal LOAD. The switching MOS transistor M4 can also be replaced by any other suitable controllable semiconductor switch device, such as an insulated gate bipolar transistor (IGBT), a triode, etc. The ratio of the aspect ratios of the first to third mirror MOS transistors M1 to M3 is 1:1:K.

[0056] The working principle of this current mirror circuit 100b is as follows: When the DC-DC conversion circuit operates in a non-light load state (such as a normal load state or a heavy load state), the load indication signal LOAD is invalid (such as a low level), M4 is turned off, and the current mirrored by M3 of M1 cannot be output to the voltage conversion circuit 100c (that is, cannot be output to the upper plate of Cton). At this time, only the current mirrored by M2 of the current flowing through M1 is output to the voltage conversion circuit 100c. Therefore, I2 = I1 = VIN / Rton; when the DC-DC conversion circuit operates in a light load state, the load indication signal LOAD is valid (such as a high level), the switching MOS transistor M4 is turned on, and the current mirrored by M3 of the current flowing through M1 and the current mirrored by M2 of the current flowing through M1 are both output to the voltage conversion circuit 100c. Therefore, I2 = (1 + K)*I1 = (1 + K)*VIN / Rton.

[0057] As an example, the voltage conversion circuit 100c includes a capacitor Cton and a discharge switch M5. One end (i.e., the upper plate) of the capacitor Cton is coupled to the drain of the discharge switch M5, the first input terminal of the first comparator CMP0, the drain of M2, and the source of M4. The other end (i.e., the lower plate) of the capacitor Cton and the source of the discharge switch M5 are both grounded. The gate of the discharge switch M5 is connected to a corresponding control signal, which is usually in phase with the corresponding drive signal received in the power switch circuit (the drive signal is generated based on the on-time control signal TON), but the gate of the discharge switch M5 is usually not directly coupled to the gate of the power switch transistor in the power switch circuit. For example, when the discharge switch M5 is an NMOS transistor, the control signal received by its gate can be in phase with the drive signal received by the gate of the power switch transistor LS. In this article, in order to indicate that the signals received by the two gates are in phase, in Figure 2 the control signal of the gate of the discharge switch M5 is also marked as VGATEN. Thus, when the power switch transistor HS needs to be turned on and LS needs to be turned off, the discharge switch M5 is also turned off, and the current I2 charges the capacitor Cton. The charging time is the on-time of the power switch transistor HS. Furthermore, the current I2 output by the current mirror circuit 100b is converted into a corresponding voltage Vton = Q / Cton = I2*t / Cton. In the light load state, t = t ON _1. Thus, it can be obtained that t ON _1 = Vout*Cton*Rton / [(1 + K)*VIN]; in the non-light load state, t = t ON , and thus it can be obtained that t ON = Vout*Cton*Rton / *VIN, t ON _1 < t ON . Obviously, in the light load state, the charging duration of the capacitor Cton by the current I2 becomes shorter. In addition, when the power switch transistor LS is turned on, the discharge switch M5 is also turned on, and at this time, the capacitor Cton is discharged.

[0058] To better illustrate the technical effects of the technical solution of this embodiment, two DC-DC conversion circuits are constructed under the condition that other circuit structures and conditions are the same. In the first DC-DC conversion circuit, the on-time control circuit Figure 2 omits M3 and M4, so the load indication signal LOAD control is not introduced, and the timing of each signal is as shown in Figure 3 (A); the second DC-DC conversion circuit adopts the on-time control circuit of this embodiment as shown in Figure 2 to introduce the load indication signal LOAD control, and the timing of each signal is as shown in Figure 3 (B). By comparing Figure 3From (A) and (B) therein, it can be seen that the fluctuation of the output voltage VOUT of the DC-DC conversion circuit of the on-time control circuit of the present embodiment shown in Figure 2 is significantly reduced (i.e., the peak value of the output voltage becomes smaller). Therefore, the present embodiment can effectively reduce the output voltage ripple of the DC-DC conversion circuit.

[0059] That is to say, in the present embodiment, a load indication signal is introduced into the on-time control circuit. The on-time control circuit can control the on-time of the power switch circuit adjustable within the corresponding switching period according to the input voltage, the output voltage, and the load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Thus, the energy output within the switching period under different load states is different. The lighter the load state of the DC-DC conversion circuit, the shorter the corresponding on-time; the heavier the load state, the longer the corresponding on-time. Therefore, the problem of large output voltage ripple generated by redundant energy on the output capacitor is avoided under different load states.

[0060] It should be understood that in the above embodiment, the load indication signal LOAD only has two states, high level and low level. Therefore, it can only indicate two load states, light load state and non-light load state. Therefore, as Figure 2 shown, there can be only one switching MOS transistor M4 and only one third mirror MOS transistor M3, but the technical solution of the present invention is not limited thereto.

[0061] In another embodiment of the present invention, please refer to Figure 6 . A load indication signal LOAD may include n load indication signals LOAD1 to LOADn corresponding one-to-one to n load states. These n load indication signals LOAD1 to LOADn can be obtained by comparing the detected output voltage Vout or output current with n reference voltages or reference currents through corresponding load detection circuits. A third mirror MOS transistor M3 is provided in the current mirror circuit 100b in the on-time control circuit 100, and n switching MOS transistors M41 to M4n are provided corresponding to the n load indication signals LOAD1 to LOADn. The drains of the switching MOS transistors M41 to M4n are all coupled to the drain of M3. The sources of the switching MOS transistors M41 to M4n are all coupled to the drain of M2, the voltage conversion circuit 100c, and the first input terminal (such as the in-phase input terminal “+”) of the first comparator CMP0. The gates of the switching MOS transistors M41 to M4n serve as the control terminals of the current mirror circuit 100b and receive the load indication signals LOAD1 to LOADn one-to-one. The switching MOS transistors M41 to M4n play a role in shunting the mirror current output by M3.

[0062] Optionally, the switching MOS transistors M41 to M4n can be transistors with the same size. In this case, the switching MOS transistors M41 to M4n are equivalent to dividing the mirror current output by M3 into n paths, and the magnitude of each path of current is K*I1 / n.

[0063] Optionally, 0 < K < 1, which can avoid unnecessary power consumption caused by too small conduction time in the light load state.

[0064] In this embodiment, the higher the load of the DC-DC conversion circuit, the fewer the number of conducting MOS switches in the switching MOS transistors M41 to M4n (at least zero can be turned on, corresponding to the state of the highest load), and the lower the load, the more the number of conducting MOS switches in the switching MOS transistors M41 to M4n (at most n can be turned on, corresponding to the state of the lowest load). At this time, the current received by the first input terminal of the first comparator CMP0 is I2 = I1 + m*K*I1 / n, and the conduction time in each switching period of the corresponding power switch circuit is:

[0065] t ON = Vout*Cton / [(1 + m*K / n)*VIN / Rton] = Vout*Cton*Rton / [(1 + m*K / n)*VIN].

[0066] When m = 0, the conduction time t ON is relatively the longest. When m = n, the conduction time t ON is relatively the shortest. That is to say, the smaller the load (i.e., the smaller), the larger m, and the shorter the conduction time t ON . The larger the load (i.e., the heavier), the smaller m, and the longer the conduction time t ON .

[0067] Therefore, in this embodiment, when the DC-DC conversion circuit operates in the COT mode, without changing the peripheral circuit of the control circuit 10, by introducing the control of n load indication signals LOAD1 to LOADn into the conduction time control module 100, the charging time (i.e., the conduction time t ON ) of the power switch tube HS (or LS) in each switching period can be adjusted under different load states. And the lighter the load, the shorter the conduction time t ON , and the heavier the load, the longer the conduction time t ON . Furthermore, the output voltage VOUT is kept stable and has a small ripple under different load states. This mode of controlling the change of the conduction time can be used in parallel with the COT mode as supplementary control under different load modes.

[0068] In another embodiment of the present invention, please refer to Figure 7, a load indication signal LOAD may include n load indication signals LOAD1 to LOADn corresponding one-to-one to n load states. These n load indication signals LOAD1 to LOADn can be obtained by comparing the detected output voltage Vout or output current with n reference voltages or reference currents through corresponding load detection circuits. In the current mirror circuit 100b of the conduction time control circuit 100, n third mirror MOS transistors M31 to M3n and n parallel-connected switch MOS transistors M41 to M4n are set corresponding to the n load indication signals LOAD1 to LOADn. The n third mirror MOS transistors M31 to M3n and the n parallel-connected switch MOS transistors M41 to M4n are coupled one-to-one. The gates of the n third mirror MOS transistors M31 to M3n are all coupled to the gate of the second mirror MOS transistor M2, and the sources of the n third mirror MOS transistors M31 to M3n are all coupled to the source of the second mirror MOS transistor M2. The drain of the switch MOS transistor M41 is coupled to the drain of M31, the voltage conversion circuit 100c, and the first input terminal (such as the non-inverting input terminal “+”) of the first comparator CMP0. The source of the switch MOS transistor M42 is coupled to the drain of M32, the voltage conversion circuit 100c, and the first input terminal (such as the non-inverting input terminal “+”) of the first comparator CMP0. And so on. The source of the switch MOS transistor M4n is coupled to the drain of M3n, the voltage conversion circuit 100c, and the first input terminal (such as the non-inverting input terminal “+”) of the first comparator CMP0. The gates of the switch MOS transistors M41 to M4n serve as the control terminals of the current mirror circuit 100b and receive the load indication signals LOAD1 to LOADn one-to-one. The n third mirror MOS transistors M31 to M3n and the n parallel-connected switch MOS transistors M41 to M4n form n mirror branches.

[0069] Among them, the switch MOS transistors M41 to M4n can be transistors with the same size, and the mirror ratios of M1, M2, and the n third mirror MOS transistors M31 to M3n are 1:1:K1:K2: ……:Kn.

[0070] Optionally, K1 to Kn are all values greater than 0 and less than 1.

[0071] As an example of this embodiment, the aspect ratios of the n third mirror MOS transistors M31 to M3n are the same, that is, K1 = K2 =... = Kn = K / n. And the higher the load of the DC-DC conversion circuit, the fewer the number of conducting MOS transistor switches among the switching MOS transistors M41 to M4n (at least zero can be turned on, corresponding to the state of the highest load), and the lower the load, the more the number of conducting MOS transistor switches among the switching MOS transistors M41 to M4n (at most n can be turned on, corresponding to the state of the lowest load). At this time, the current received by the first input terminal of the first comparator CMP0 is I2 = I1 + m*K*I1 / n, and the conduction time within each switching period of the corresponding power switching circuit is:

[0072] t ON = Vout * Cton / [(1 + m*K / n) * VIN / Rton] = Vout * Cton * Rton / [(1 + m*K / n) * VIN].

[0073] When m = 0, the conduction time t ON is relatively the longest. When m = n, the conduction time t ON is relatively the shortest. That is to say, the smaller the load (i.e., the lighter), the larger m is, and the shorter the conduction time t ON is. The larger the load (i.e., the heavier), the smaller m is, and the longer the conduction time t ON is.

[0074] Further optionally, 0 < K < 1, thereby avoiding unnecessary power consumption caused by too small conduction time in the light load state.

[0075] As another example of this embodiment, the aspect ratios of the n third mirror MOS transistors M31 to M3n are different, that is, K1 < K2 <... < Kn. And the higher the load of the DC-DC conversion circuit, the fewer the number of conducting switching MOS transistors among the switching MOS transistors M41 to M4n (at least zero can be turned on, corresponding to the state of the highest load), and the smaller the sum of the aspect ratios of the third mirror MOS transistors connected to the conducting switching MOS transistors. The lower the load, the more the number of conducting MOS transistor switches among the switching MOS transistors M41 to M4n (at most n can be turned on, corresponding to the state of the lowest load), and the larger the sum of the aspect ratios of the third mirror MOS transistors connected to the conducting switching MOS transistors.

[0076] Optionally, under the heaviest load, none of the conducting switching MOS transistors M41 to M4n are conducting. At this time, the conduction time t within each switching period of the corresponding power switching circuit ON= Vout * Cton * Rton / VIN. In various other load states, a corresponding one of the switching MOS transistors M41 to M4n is turned on. Moreover, the lighter the load, the larger the aspect ratio of the third mirror MOS transistor connected to the turned-on switching MOS transistor among M41 to M4n. At this time, the conduction time t within each switching period of the corresponding power switching circuit ON = Vout * Cton * Rton / [(1 + Ki) * VIN], where Ki = K1 to Kn. Among them, when M4n is turned on, it corresponds to the state of the lowest load. At this time, the conduction time t within each switching period of the corresponding power switching circuit ON = Vout * Cton * Rton / [(1 + Kn) * VIN] = Vout * Cton * Rton / [(1 + K) * VIN]. In this case, obviously, the smaller the load (i.e., the smaller), the shorter the conduction time t ON and the larger the load (i.e., the heavier), the longer the conduction time t ON is. Further optionally, 0 < K1 < K2 <... < Kn < 1, whereby unnecessary power consumption caused by too small a conduction time can be avoided in the light load state.

[0077] Optionally, under the heaviest load, none of the switching MOS transistors M41 to M4n that are turned on are conducting. At this time, the conduction time t within each switching period of the corresponding power switching circuit ON = Vout * Cton * Rton / VIN. In the lightest load state, all of the switching MOS transistors M41 to M4n are turned on. At this time, the conduction time t within each switching period of the corresponding power switching circuit ON = Vout * Cton * Rton / [(1 + K1 + K2 +... + Kn) * VIN]. In this case, obviously, the conduction time under the lightest load is shorter than that under the heaviest load. Further optionally, 0 < K1 + K2 +... + Kn < 1, whereby unnecessary power consumption caused by too small a conduction time can be avoided in the light load state.

[0078] As described above, in Figure 7 the illustrated embodiment, when the DC-DC conversion circuit in the COT mode is operating, without the need to change the peripheral circuit of the control circuit 10, by introducing the control of n load indication signals LOAD1 to LOADn into the conduction time control module 100, the charging time (i.e., the conduction time t ON ) of the power switching transistor HS (or LS) in each switching period can be adjusted in different load states. Moreover, the lighter the load, the shorter the conduction time t ON and the heavier the load, the longer the conduction time t ONThe longer it is, the more stable the output voltage VOUT is and the smaller the ripple is under different load conditions. This mode of controlling the change of the conduction time can be used in parallel with the COT mode as supplementary control under different load modes.

[0079] In summary, please refer to Figure 2 、 Figure 6 and Figure 7 , regardless of the specific circuit structure design of the current mirror circuit (100b), its amplification factor of the input current I1 can be equivalent to 1 + q, where 0 ≤ q < 1 under different load conditions.

[0080] Based on the same inventive concept, please refer to Figure 1 , this embodiment also provides a control circuit 10 for controlling the on and off of the power switch transistors HS and LS in the DC-DC conversion circuit. The control circuit 10 includes the conduction time control circuit 100 described in any embodiment of the present invention. For example, the control circuit 10 controls the alternating on and off of the power switch transistors HS and LS in the DC-DC conversion circuit, and the control circuit 10 controls the conduction time of the power switch transistors HS and LS in each switching cycle under different load conditions based on the conduction time control circuit 100.

[0081] Optionally, the control circuit 10 further includes a PWM generator 101 and a logic control circuit (LOGIC CONTROL) 102. The PWM generator 101 generates a pulse width modulation signal PWM according to the node voltage VSW of the power switch transistors HS and LS and the feedback voltage VFB of the output voltage VOUT. The logic control circuit 102 is coupled to the PWM generator 101, the conduction time control circuit 100, and the gates of the power switch transistors HS and LS. The logic control circuit 102 performs a logic operation (such as an AND logic operation) on the pulse width modulation signal PWM and the conduction time control signal TON to drive the power switch transistors HS and LS to alternate on and off. The PWM is mainly used to determine the switching cycle (or switching frequency) of the power switch transistors HS and LS, and the conduction time control signal TON is mainly used to determine the conduction time of the power switch transistors HS and LS in each switching cycle.

[0082] Based on the same inventive concept, please refer to Figure 1 , this embodiment also provides a DC-DC conversion circuit, which includes a power stage circuit 11 and a control circuit 10 described in any embodiment of the present invention. The power stage circuit 11 can adopt any suitable topology such as a Buck type topology, a Buck-boost type topology, or a Boost type topology, and it has a corresponding power switch circuit, and the power switch circuit has at least one power switch transistor, for example Figure 1In the HS and LS, the control circuit 10 is coupled to the gates of the corresponding power switch transistors of the power switch circuit in the power stage circuit 11 to be turned on and off under the control of this control circuit, thereby enabling the DC-DC conversion circuit to operate in a corresponding mode (such as the COT mode), and converting the input voltage VIN into the output voltage VOUT.

[0083] It should be understood that the internal structure of the control circuit in the above embodiment and other structures of the DC-DC conversion circuit are only taken as an example, and it does not mean that the internal structure of the control circuit of the present invention and the structure of the DC-DC conversion circuit are only limited to this. In other embodiments of the present invention, the control circuit may also have other functional circuits inside, and the DC-DC conversion circuit may also include other circuit structures.

[0084] For example, in another embodiment of the present invention, please refer to Figure 4 , the control circuit for the DC-DC conversion circuit further includes a zero-crossing detection circuit (not marked), and the output end of the zero-crossing detection circuit is coupled to the logic control circuit 102; this zero-crossing detection circuit is used to detect the zero-crossing point of the node voltage VSW of the corresponding power switch transistor in the power stage circuit 11 to generate a zero-crossing signal ZCD; the logic control circuit 102 performs corresponding logical operations on the pulse width modulation signal PWM, the zero-crossing signal ZCD, and the conduction time control signal TON to control the on and off of the corresponding power switch transistor in the power stage circuit 11.

[0085] For another example, please refer to Figure 4 , the DC-DC conversion circuit further includes a feedback circuit (not marked), which can sample the output voltage VOUT to generate a feedback voltage VFB for feedbacking the change and magnitude of the output voltage VOUT. As an example, this feedback circuit includes resistors R1 and R2. One end of resistor R1 is coupled to the upper plate of the output capacitor COUT and one end of the inductor L, the other end of resistor R1 is connected to one end of resistor R2 and outputs the feedback voltage VFB, and the other end of resistor R2 is grounded.

[0086] For yet another example, please refer to Figure 4 , the DC-DC conversion circuit further includes a load detection circuit (not shown), which can detect the output voltage VOUT or the output current, and compare the detection result with a reference voltage or a reference current to generate a load indication signal LOAD for indicating the load state.

[0087] In this embodiment, based on Figure 4 and Figure 2 the structures shown, two DC-DC conversion circuits are constructed. In the first DC-DC conversion circuit, the conduction time control circuit relatively Figure 2 omits M3 and M4, so the load indication signal LOAD control is not introduced, and the timing of each signal is asFigure 5 as shown in (A) of Figure 2 the conduction time control circuit of this embodiment shown in Figure 5 to introduce the load indication signal LOAD control, and the timing of each signal is as shown in Figure 5 (B) of Figure 2 Comparing (A) and (B) of

[0088] It should also be understood that the circuit modules such as the PWM generator 101, the logic control circuit 102, and the zero-crossing detection circuit in the above embodiments of the present invention can adopt any suitable circuit design, and the technical solution of the present invention does not make specific limitations on this.

[0089] For example, please refer to Figure 4 , in an embodiment of the present invention, the PWM generator 101 includes a second error amplifier EA1, a ramp generator RAMP, and a second comparator CMP1. The second error amplifier EA1 is used to compare the feedback voltage VFB of the output voltage VOUT of the DC-DC conversion circuit with the first reference voltage VREF1 to generate an error amplification signal VEAO. The ramp generator RAMP is used to compare the node voltage VSW at the connection node of the power switching transistors HS and LS with the second reference voltage VREF2 to generate a ramp signal VRAMP. The first input terminal (for example, the non-inverting input terminal “+”) of the second comparator CMP1 is coupled to the output terminal of the second error amplifier EA1, and the second input terminal (for example, the inverting input terminal “-”) is coupled to the output terminal of the ramp generator RAMP. The second comparator CMP1 is used to compare the error amplification signal VEAO and the ramp signal VRAMP to generate the pulse width modulation signal PWM required by the logic control circuit 102.

[0090] Again, for example, the zero-crossing detection circuit includes a third comparator CMP2. The first input terminal of the third comparator CMP2 receives the node voltage VSW at the connection node of the power switching transistors HS and LS. The second input terminal of the third comparator CMP2 is connected to 0V or grounded or connected to a reference voltage. The output terminal of the third comparator CMP2 is coupled to the logic control circuit 102 to provide a zero-crossing signal ZCD.

[0091] In addition, Figure 2 , Figure 6 and Figure 7 M0 to M5 in are all shown by taking the corresponding NMOS transistors or PMOS transistors as examples, but the technical solution of the present invention is not limited thereto. In other embodiments of the present invention,Figure 2 , Figure 6 and Figure 7 the corresponding NMOS transistors in can be replaced with any controllable semiconductor switching devices such as PMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc. Similarly, Figure 2 , Figure 6 and Figure 7 the corresponding PMOS transistors in can be replaced with any controllable semiconductor switching devices such as NMOS transistors, triodes, insulated gate bipolar transistors (IGBTs), etc.

[0092] In summary, the on-time control circuit, control circuit, and DC-DC conversion circuit provided by the present invention do not require larger peripheral devices. Instead, on the basis of the traditional COT mode, a load indication signal is introduced into the on-time control circuit. This on-time control circuit can control the on-time of the power switch circuit to be adjustable within the corresponding switching period according to the input voltage, output voltage, and the load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage. Thus, the energy output within the switching period under different load states is different. The lighter the load state of the DC-DC conversion circuit, the shorter the corresponding on-time; the heavier the load state, the longer the corresponding on-time. Therefore, the problem of large output voltage ripple caused by excessive energy on the output capacitor is avoided under different load states.

[0093] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure belong to the protection scope of the technical solution of the present invention.

Claims

1. A conduction time control circuit for a DC-DC conversion circuit, the DC-DC conversion circuit converting an input voltage into an output voltage by turning on and off a corresponding power switch circuit, characterized in that, The on-time control circuit is configured to control the on-time of the power switch circuit to be adjustable within a corresponding switching period according to the input voltage, the output voltage, and a load indication signal reflecting the load state of the DC-DC conversion circuit, so as to adjust the peak value of the output voltage.

2. The turn-on time control circuit according to claim 1, wherein The lighter the load state of the DC-DC conversion circuit, the shorter the corresponding on-time; the heavier the load state, the longer the corresponding on-time.

3. The turn-on time control circuit according to claim 1, wherein The on-time control circuit includes: A current conversion circuit, configured to convert the input voltage into an input current; A current mirror circuit, coupled to the current conversion circuit and controlled by the load indication signal, and configured to mirror-output the input current according to a corresponding magnification factor, and the lighter the load state of the DC-DC conversion circuit, the larger the magnification factor; A voltage conversion circuit, coupled to the current mirror circuit, and configured to convert the current output by the current mirror circuit into a corresponding voltage; A first comparator, with a first input terminal coupled to the voltage conversion circuit, a second input terminal receiving the output voltage, and configured to compare the magnitudes of the output voltage and the voltage converted by the voltage conversion circuit, so as to output a corresponding on-time control signal for controlling the on-time.

4. The turn-on time control circuit according to claim 3, wherein The current conversion circuit includes a first error amplifier, a conversion switch, and a first resistor. The source of the conversion switch is coupled to one end of the first resistor and the second input terminal of the first error amplifier. The other end of the first resistor is grounded. The first input terminal of the first error amplifier is connected to the input voltage, and the output terminal of the first error amplifier is coupled to the gate of the conversion switch.

5. The turn-on time control circuit according to claim 3, characterized in that, The current mirror circuit has first to third mirror MOS transistors and n switching MOS transistors, where n is an integer not less than 1. The gates of the first to third mirror MOS transistors are all coupled to the drain of the first mirror MOS transistor and the current conversion circuit; The drain of the second mirror MOS transistor is coupled to the sources of the respective switching MOS transistors, the voltage conversion circuit, and the first input terminal of the first comparator; the drains of the respective switching MOS transistors are all coupled to the drain of the third mirror MOS transistor, and the gates of the respective switching MOS transistors are all controlled by the load indication signal, and the lighter the load state of the DC-DC conversion circuit, the more the number of the conducting switching MOS transistors.

6. The turn-on time control circuit according to claim 3, wherein The current mirror circuit has a first mirror MOS transistor, a second mirror MOS transistor, n third mirror MOS transistors, and n switching MOS transistors, where n is an integer not less than 1. The gates of the first mirror MOS transistor, the second mirror MOS transistor, and the respective third mirror MOS transistors are all coupled to the drain of the first mirror MOS transistor and the current conversion circuit; the drain of the second mirror MOS transistor is coupled to the sources of the respective switching MOS transistors, the voltage conversion circuit, and the first input terminal of the first comparator; the drains of the n switching MOS transistors are respectively coupled to the drains of the n third mirror MOS transistors in a one-to-one correspondence, and the gates of the respective switching MOS transistors are all controlled by the load indication signal; Among them, the width-to-length ratios of the respective third mirror MOS transistors are the same. The lighter the load state of the DC-DC conversion circuit, the more the number of the switched-on switch MOS transistors; or, the width-to-length ratios of the respective third mirror MOS transistors are different. The lighter the load state of the DC-DC conversion circuit, the more the number of the switched-on switch MOS transistors and the greater the sum of the width-to-length ratios of the third mirror MOS transistors connected to the switched-on switch MOS transistors.

7. The turn-on time control circuit according to claim 3, wherein The voltage conversion circuit includes a capacitor and a discharge switch. One end of the capacitor is coupled to one end of the discharge switch, the first input terminal of the first comparator, and the current mirror circuit. The other end of the capacitor and the other end of the discharge switch are both grounded. The control terminal of the discharge switch is connected to a corresponding control signal.

8. The turn-on time control circuit according to any one of claims 3-7, characterized in that, The amplification factor of the current mirror circuit for the input current is 1 + q, where 0 ≤ q < 1.

9. A control circuit for controlling the on / off of a corresponding power switch circuit in a DC-DC conversion circuit, characterized in that, The control circuit includes the on-time control circuit for the DC-DC conversion circuit according to any one of claims 1-8.

10. The control circuit according to claim 9, characterized in that, It further includes: a feedback circuit, coupled to the output terminal of the DC-DC conversion circuit and configured to sample the output voltage to generate a feedback voltage for feeding back the change and magnitude of the output voltage; a PWM generator, configured to generate a pulse width modulation signal according to the node voltage of the power switch circuit and the feedback voltage of the output voltage; a zero-crossing detection circuit, configured to detect the zero-crossing point of the node voltage of the power switch circuit to generate a zero-crossing signal; a logic control circuit, coupled to the PWM generator, the on-time control circuit, the zero-crossing detection circuit, and the power switch circuit, and configured to drive the power switch circuit to turn on or off according to the pulse width modulation signal, the on-time control signal, and the zero-crossing signal.

11. The control circuit according to claim 9, wherein The PWM generator includes: a second error amplifier, configured to compare the feedback voltage of the output voltage of the DC-DC conversion circuit with a first reference voltage to generate an error amplification signal; a ramp generator, configured to compare the node voltage of the power switch circuit with a second reference voltage to generate a ramp signal; a second comparator, with the first input terminal coupled to the output terminal of the second error amplifier and the second input terminal coupled to the output terminal of the ramp generator, and configured to compare the error amplification signal and the ramp signal to generate the pulse width modulation signal.

12. A DC-DC conversion circuit, characterized in that, It includes a power stage circuit and the control circuit according to any one of claims 9-11. The power switch circuit in the power stage circuit is coupled to the control circuit and is turned on and off under the control of the control circuit.

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