Power converter circuit and control circuit thereof

Abstract

The invention provides a power converter circuit and a control circuit thereof. The power converter circuit converts an input voltage signal to output an output voltage signal, and includes a power stage circuit and a control circuit. The power stage circuit outputs a phase voltage signal. The control circuit generates a first ripple signal according to the phase voltage signal, and generates a second ripple signal according to a DC signal generated by processing the first ripple signal, a reference voltage signal and a feedback signal associated with the output voltage signal. The control circuit controls the power level circuit to operate according to a preset turn-off time to increase the inductive current and comprises a direct current deviation correction circuit. The control circuit more quickly stabilizes the output voltage signal when the load changes through the two ripple signals which are crossed quickly, and corrects the reference voltage signal by using the direct-current deviation correction circuit, so that the power converter circuit has the advantages of better load change response capability, better output voltage stability, elimination of direct-current deviation and the like.

Description

Technical Field

[0001] The present invention relates to a control circuit, and more particularly to a control circuit for a power converter circuit. Background Art

[0002] With the development of semiconductor technology, the ability of a power converter circuit to respond to load fluctuations has become increasingly important. Some related technologies add a ramp signal related to current to a reference voltage to improve loop stability. However, the response speed of these related technologies to load fluctuations is still slow, and it is easy to cause offset problems in the reference voltage or feedback voltage. Therefore, it is necessary to propose a new circuit to solve the above problems. Summary of the Invention

[0003] One aspect of the present invention is a control circuit applicable to a power converter circuit. The power converter circuit includes a power stage circuit and is used to output an inductor current via an inductor. The control circuit includes a first ripple generation circuit, a signal processing circuit, a second ripple generation circuit, and a comparison circuit. The first ripple generation circuit is coupled to the phase output terminal of the power stage circuit and is used to output a first ripple signal according to the phase voltage signal output by the power stage circuit. The signal processing circuit is coupled to the first ripple generation circuit and is used to process the first ripple signal to output a DC signal. The second ripple generation circuit is coupled to the signal processing circuit and is used to output a second ripple signal according to the DC signal, a reference voltage signal, and a feedback signal related to the output voltage signal of the power converter circuit. The second ripple generation circuit includes a DC bias correction circuit and a buffer circuit. The DC bias correction circuit is used to correct the reference voltage signal to eliminate the bias between the reference voltage signal and the feedback signal. The buffer circuit is coupled to the signal processing circuit and is used to buffer the DC signal to output a buffered DC signal, where the buffered DC signal is related to the second ripple signal. The comparison circuit is coupled to the first ripple generation circuit and the buffer circuit and is used to compare the first ripple signal and the second ripple signal, and is used to trigger a conduction time generation circuit to control the power stage circuit to operate according to a preset turn-off time when the second ripple signal continuously exceeds the first ripple signal, so that the inductor current increases.

[0004] In some embodiments, the first ripple generation circuit is a filter circuit, and the filter circuit is used to filter the phase voltage signal to output the first ripple signal, where the first ripple signal is related to the inductor current.

[0005] In some embodiments, the first ripple generating circuit includes a resistive element and a capacitive element. The resistive element includes a first end coupled to the phase output terminal and a second end coupled to the negative input terminal of the comparison circuit. The capacitive element includes a first end coupled to the second end of the resistive element and a second end coupled to a ground voltage.

[0006] In some embodiments, the signal processing circuit is a filter circuit, and the filter circuit is configured to filter the first ripple signal to output the DC signal, where the DC signal is associated with the DC component of the output voltage signal.

[0007] In some embodiments, the signal processing circuit includes a resistive element and a capacitive element. The resistive element includes a first end coupled to the first ripple generating circuit and a second end coupled to the second ripple generating circuit. The capacitive element includes a first end coupled to the second end of the resistive element and a second end coupled to a ground voltage.

[0008] In some embodiments, the second ripple generating circuit further includes an error amplifying circuit. The error amplifying circuit includes a positive input terminal for receiving the corrected reference voltage signal output by the DC offset correction circuit and a negative input terminal for receiving the feedback signal, and is configured to convert the difference between the corrected reference voltage signal and the feedback signal to output an error current signal to a compensation node, where the second ripple generating circuit is configured to output the second ripple signal based on the error current signal and the DC signal.

[0009] In some embodiments, the second ripple generating circuit further includes a resistive element. The resistive element includes a first end and a second end, where the first end is coupled to the compensation node, and the second end is coupled to the buffer circuit to receive the buffered DC signal output by the buffer circuit. Wherein the second ripple generating circuit is configured to output the second ripple signal based on the buffered DC signal and the voltage difference generated by the error current signal and the resistive element.

[0010] In some embodiments, the DC offset correction circuit is configured to correct the reference voltage signal based on the error current signal and the gain of the error amplifying circuit to output the corrected reference voltage signal.

[0011] In some embodiments, the DC offset correction circuit includes a resistive element and a current mirror circuit. The resistive element includes a first end and a second end, where the first end is coupled to the reference voltage signal, and the resistance value of the resistive element is associated with the gain of the error amplifier circuit. The current mirror circuit is coupled to the first end of the resistive element and the error amplifier circuit, and is configured to copy the error current signal to output a copied current signal to the first end of the resistive element, where the DC offset correction circuit is configured to output the corrected reference voltage signal at the second end of the resistive element by passing the copied current signal through the resistive element.

[0012] Another aspect of the present disclosure is a power converter circuit. The power converter circuit is configured to convert an input voltage signal to output an output voltage signal at a load terminal, and includes a power stage circuit and a control circuit. The power stage circuit is configured to receive the input voltage signal and output a phase voltage signal at a phase output terminal, where the phase output terminal is coupled to the load terminal via an inductor. The control circuit is coupled to the power stage circuit, the phase output terminal, and the load terminal, and is configured to generate a first ripple signal based on the phase voltage signal, generate a second ripple signal based on a DC signal generated by processing the first ripple signal, a reference voltage signal, and a feedback signal associated with the output voltage signal, and control the power stage circuit to operate according to a preset turn-off time when the second ripple signal continuously exceeds the first ripple signal, so as to increase the inductor current flowing through the inductor, where the control circuit includes a DC offset correction circuit, and the DC offset correction circuit is configured to correct the reference voltage signal to eliminate the offset between the reference voltage signal and the feedback signal.

[0013] In summary, the first ripple signal and the second ripple signal generated by the control circuit can quickly cross when the load changes, so as to stabilize the output voltage signal faster than the related art. Also, the control circuit can use the DC offset correction circuit to correct the reference voltage signal to eliminate the offset between the feedback signal and the reference voltage signal. Therefore, the power converter circuit of the present disclosure has advantages such as better load change response ability, better output voltage stability, and elimination of DC offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 FIG. 1 is a circuit schematic diagram of a power converter circuit according to some embodiments of the present disclosure.

[0015] Figure 2 FIG. 2 is a timing diagram of some signals in the power converter circuit when the output load changes from light load to heavy load according to some embodiments of the present disclosure.

[0016] Figure 3A timing diagram of some signals in a power converter circuit when the output load changes from heavy load to light load, as illustrated in some embodiments according to the present invention.

[0017] Figure 4A A schematic diagram of a DC signal, a first ripple signal, and a second ripple signal, as illustrated in some embodiments according to the present invention.

[0018] Figure 4B A schematic diagram of a feedback signal and a reference voltage signal, as illustrated in some embodiments according to the present invention.

[0019] Figure 5 A circuit schematic diagram of a DC offset correction circuit, as illustrated in some embodiments according to the present invention. Detailed Description of the Invention

[0020] The following is a detailed description with reference to the accompanying drawings by way of examples. However, the specific embodiments described are only for explaining the present case and are not used to limit the present case. The description of the structure and operation is not used to limit the execution order. Any structure formed by re-combining elements and producing an apparatus with equivalent functions is within the scope covered by the present invention.

[0021] The terms used throughout the specification and claims, unless otherwise specifically noted, generally have their ordinary meanings as used in this field, in the content disclosed herein, and in the specific context.

[0022] Regarding the use of "coupled" or "connected" in this article, it can refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other, and can also refer to two or more elements operating or acting on each other.

[0023] Please refer to Figure 1 , Figure 1 A circuit schematic diagram of a power converter circuit 100, as illustrated in some embodiments according to the present invention. Specifically, the power converter circuit 100 can be a DC / DC converter, such as a single-phase or multi-phase buck converter, etc. In some embodiments, the power converter circuit 100 is used to convert an input voltage signal VIN to output an output voltage signal VOUT at a load terminal NL. For example, the power converter circuit 100 can supply power to a load device (not shown in the figure), such as a central processing unit (CPU), through the output voltage signal VOUT. It should be understood that the load device can be electrically coupled to the load terminal NL. In some embodiments, the power converter circuit 100 includes a control circuit 10, a power stage circuit 20, and a feedback circuit 30.

[0024] In some embodiments, the power stage circuit 20 is configured to receive an input voltage signal VIN and a ground voltage GND. As Figure 1 shown, the power stage circuit 20 includes a phase output terminal NP, a drive circuit 21, a high-side switch Q1, and a low-side switch Q2. The high-side switch Q1 is coupled between the input voltage signal VIN and the phase output terminal NP, and the low-side switch Q2 is coupled between the phase output terminal NP and the ground voltage GND. In other words, the high-side switch Q1 and the low-side switch Q2 are connected in series between the input voltage signal VIN and the ground voltage GND. Specifically, the high-side switch Q1 and the low-side switch Q2 can each be implemented by a transistor, but the present disclosure is not limited thereto.

[0025] In some embodiments, the drive circuit 21 can be controlled by a control signal (not shown in the figure), such as a pulse width modulation (PWM) signal, etc., to drive the high-side switch Q1 and the low-side switch Q2 to conduct alternately (turn-on), thereby outputting a phase voltage signal PO at the phase output terminal NP. It should be understood that the phase voltage signal PO on the phase output terminal NP is a square-wave voltage signal, and the voltage level of this square-wave voltage signal can be switched between the voltage level of the input voltage signal VIN and the voltage level of the ground voltage GND.

[0026] As Figure 1 shown, the phase output terminal NP of the power stage circuit 20 is coupled to the load terminal NL via an inductor L. Also, a resistor RC and an output capacitor COUT are connected in series between the load terminal NL and the ground voltage GND, where the resistor RC is the equivalent series resistance (ESR) of the output capacitor COUT. Specifically, the inductor L, the resistor RC, and the output capacitor COUT will form a circuit (e.g., a low-pass filter circuit), and this circuit is used to perform signal processing (e.g., low-pass filtering) on the phase voltage signal PO, so as to generate an output voltage signal VOUT at the load terminal NL.

[0027] From the above description, it can be seen that the phase voltage signal PO and the output voltage signal VOUT will be at both ends of the inductor L respectively. In this configuration, the inductor current IL will flow through the inductor L. It should be understood that the inductor current IL flowing through the inductor L is a ripple signal.

[0028] In some practical applications, the aforementioned load device may be in a light load or heavy load state due to temporary task changes (e.g., running specific applications and / or software). Compared with the light load state, the load device in the heavy load state requires a larger working current in real time. When the load device switches between the light load state and the heavy load state, the output voltage signal VOUT will correspondingly experience overshoot or undershoot phenomena.

[0029] In order to maintain the stability of the output voltage signal VOUT, in some embodiments, the power converter circuit 100 uses the control circuit 10 coupled between the load terminal NL and the power stage circuit 20 to improve the overshoot or undershoot phenomena of the output voltage signal VOUT, which will be further described in the following paragraphs.

[0030] As described above, as Figure 1 shown, the control circuit 10 is coupled to the phase output terminal NP of the power stage circuit 20 and the drive circuit 21, and is coupled to the load terminal NL (or the output voltage signal VOUT) via the feedback circuit 30. In this configuration, the control circuit 10 can receive the phase voltage signal PO of the phase output terminal NP, the reference voltage signal VREF, and the feedback signal VFB output by the feedback circuit 30 according to the output voltage signal VOUT.

[0031] In some further embodiments, the feedback circuit 30 is implemented by a buffer circuit, so the feedback signal VFB can be substantially the same as the output voltage signal VOUT. In some further embodiments, the feedback circuit 30 is implemented by a voltage divider circuit, so the feedback signal VFB can be substantially the output voltage signal VOUT multiplied by a preset value (e.g., any value between 0 and 1). In short, the feedback signal VFB can vary with the output voltage signal VOUT, that is, the feedback signal VFB is associated with the output voltage signal VOUT.

[0032] Next, in conjunction with Figure 1 describe the circuit architecture of the control circuit 10. In some embodiments, the control circuit 10 includes a first ripple generation circuit 11, a signal processing circuit 13, a second ripple generation circuit 15, a comparison circuit 17, and a conduction time generation circuit 19, where the first ripple generation circuit 11 and the signal processing circuit 13 can be regarded as a second-order filter circuit together.

[0033] In some further embodiments, the first ripple generation circuit 11 is a filter circuit (e.g., a low-pass filter circuit). As Figure 1As shown, the first ripple generation circuit 11 includes a resistor element R1 and a capacitor element C1. The resistor element R1 includes a first terminal and a second terminal. The capacitor element C1 includes a first terminal and a second terminal. The first terminal of the resistor element R1 is coupled to the phase output terminal NP of the power stage circuit 20. The second terminal of the resistor element R1 is coupled to the comparison circuit 17 and the first terminal of the capacitor element C1. The second terminal of the capacitor element C1 is coupled to the ground voltage GND. It can be seen therefrom that the first ripple generation circuit 11 is coupled to the phase output terminal NP of the power stage circuit 20 and the comparison circuit 17.

[0034] In some further embodiments, the signal processing circuit 13 is a filter circuit (e.g., a low-pass filter circuit). As Figure 1 shown, the signal processing circuit 13 includes a resistor element R2 and a capacitor element C2. The resistor element R2 includes a first terminal and a second terminal. The capacitor element C2 includes a first terminal and a second terminal. The first terminal of the resistor element R2 is coupled to the first ripple generation circuit 11. The second terminal of the resistor element R2 is coupled to the second ripple generation circuit 15 and the first terminal of the capacitor element C2. The second terminal of the capacitor element C2 is coupled to the ground voltage GND. It can be seen therefrom that the signal processing circuit 13 is coupled to the first ripple generation circuit 11 and the second ripple generation circuit 15.

[0035] In some further embodiments, the second ripple generation circuit 15 includes a buffer circuit 151, an error amplifier circuit 153, a DC offset correction circuit 155, and a resistor element RCOMP.

[0036] The error amplifier circuit 153 includes a positive input terminal, a negative input terminal, and an output terminal. The resistor element RCOMP includes a first terminal and a second terminal. The positive input terminal of the error amplifier circuit 153 is coupled to the DC offset correction circuit 155. The negative input terminal of the error amplifier circuit 153 is coupled to the feedback circuit 30. The output terminal of the error amplifier circuit 153, the first terminal of the resistor element RCOMP, and the comparison circuit 17 are coupled to a compensation node NC. The second terminal of the resistor element RCOMP is coupled to the buffer circuit 151. Specifically, the error amplifier circuit 153 can be implemented by a transconductance amplifier.

[0037] The buffer circuit 151 includes an operational amplifier OP and a capacitive element C3. The operational amplifier OP includes a positive input terminal (labeled as “+” in the figure), a negative input terminal (labeled as “-” in the figure), and an output terminal. The capacitive element C3 includes a first terminal and a second terminal. The positive input terminal of the operational amplifier OP is coupled to the signal processing circuit 13. The output terminal of the operational amplifier OP is coupled to the negative input terminal of the operational amplifier OP, the first terminal of the capacitive element C3, and the second terminal of the resistive element RCOMP. The second terminal of the capacitive element C3 is coupled to the ground voltage GND. It can be seen from this that the second ripple generation circuit 15 is coupled to the signal processing circuit 13, the comparison circuit 17, and the feedback circuit 30. The capacitive element C3 is used to adjust the signal stability. In some further embodiments, the capacitive element C3 in the buffer circuit 151 can be omitted.

[0038] For Figure 1 the configuration in, the buffer circuit 151 can be regarded as a non-inverting voltage follower. In this non-inverting circuit configuration, the output terminal of the operational amplifier OP is directly coupled to the negative input terminal (i.e., the negative feedback loop), so the feedback ratio is close to 100%. The voltage level at the positive input terminal is substantially exactly equal to the voltage level at the output terminal, that is, the gain of the buffer circuit 151 is substantially 1. Since the input impedance of the operational amplifier OP is infinite under ideal conditions, no current flows through the negative feedback loop and no current flows into the positive input terminal. Therefore, the voltage drop between the positive input terminal and the negative input terminal is close to zero, resulting in a power loss close to zero. The buffer circuit 151 can stabilize the voltage level of the buffered DC signal LP2’ output at the voltage level of the received DC signal LP2, and at the same time provide the effect of signal isolation, that is, the DC signal LP2 will not be affected by the components or signal sources coupled to the buffer circuit 151.

[0039] In some further embodiments, the comparison circuit 17 includes a positive input terminal, a negative input terminal, and an output terminal. The positive input terminal of the comparison circuit 17 and the second ripple generation circuit 15 are coupled to the compensation node NC. The negative input terminal of the comparison circuit 17 is coupled to the first ripple generation circuit 11. The output terminal of the comparison circuit 17 is coupled to the conduction time generation circuit 19. It can be seen from this that the comparison circuit 17 is coupled to the first ripple generation circuit 11, the second ripple generation circuit 15, and the conduction time generation circuit 19. In addition, the conduction time generation circuit 19 is coupled to the drive circuit 21 of the power stage circuit 20.

[0040] Based on the circuit architecture of the above control circuit 10, in some embodiments, the first ripple generation circuit 11 is configured to output a first ripple signal LP1 according to the phase voltage signal PO of the phase output terminal NP. For example, the first ripple generation circuit 11 filters the phase voltage signal PO to output the first ripple signal LP1. The signal processing circuit 13 is configured to process the first ripple signal LP1 to output a DC signal LP2. For example, the signal processing circuit 13 filters the first ripple signal LP1 to output the DC signal LP2.

[0041] The second ripple generation circuit 15 is configured to output a second ripple signal COMP according to the DC signal LP2, the reference voltage signal VREF, and the feedback signal VFB. As Figure 1 shown, the DC offset correction circuit 155 is configured to correct the reference voltage signal VREF to a corrected reference voltage signal VREFX, which will be described in detail in the following paragraphs in conjunction with Figures 4A - 4B and Figure 5 further explanation.

[0042] The error amplification circuit 153 is configured to convert the difference between the corrected reference voltage signal VREFX and the feedback signal VFB into an error current signal IERR, and is configured to output the error current signal IERR to the compensation node NC. The buffer circuit 151 is configured to buffer the DC signal LP2 into a buffered DC signal LP2', and is configured to output the buffered DC signal LP2' to the second terminal of the resistor element RCOMP, where the buffered DC signal LP2' is related to the second ripple signal COMP.

[0043] Since the comparison circuit 17 is implemented by an operational amplifier, the comparison circuit 17 generally does not allow current to flow into its positive input terminal. Therefore, as Figure 1 shown, the error current signal IERR output by the error amplification circuit 153 will sequentially pass through the compensation node NC, the first terminal of the resistor element RCOMP, and the second terminal of the resistor element RCOMP, which further generates a voltage difference (not shown in the figure) between the first terminal and the second terminal of the resistor element RCOMP. In this way, the second ripple generation circuit 15 can output the second ripple signal COMP according to the buffered DC signal LP2' and the aforementioned voltage difference generated by the error current signal IERR and the resistor element RCOMP. For example, the second ripple signal COMP is generated by adding the voltage difference between the first terminal and the second terminal of the resistor element RCOMP to the buffered DC signal LP2'.

[0044] In the above embodiments, the buffered DC signal LP2' is substantially the same as the DC signal LP2. Therefore, the second ripple generation circuit 15 is also equivalent to outputting the second ripple signal COMP according to the error current signal IERR and the DC signal LP2.

[0045] Next, the comparison circuit 17 is used to compare the first ripple signal LP1 and the second ripple signal COMP, and is used to control the on-time generation circuit 19 according to the comparison result of the first ripple signal LP1 and the second ripple signal COMP. The relevant operation details will be described in the following paragraphs in conjunction with Figures 2 - 3 further explanation.

[0046] Next, in conjunction with Figure 2 and Figure 3 describe the circuit operation of the control circuit 10 under load variations (e.g., from light load to heavy load, from heavy load to light load, etc.). Figure 2 FIG. is a timing diagram of the inductor current IL, the first ripple signal LP1, the DC signal LP2, the second ripple signal COMP, and the output voltage signal VOUT in the power converter circuit 100 when the output load changes from light load to heavy load according to some embodiments of the present disclosure. Figure 3 FIG. is a timing diagram of the inductor current IL, the first ripple signal LP1, the DC signal LP2, the second ripple signal COMP, and the output voltage signal VOUT in the power converter circuit 100 when the output load changes from heavy load to light load according to some embodiments of the present disclosure.

[0047] In some embodiments, the output load changes from light load to heavy load at the time point T1 shown in Figure 2 , that is, the output load requires a larger operating current. In this case, the power converter circuit 100 needs to increase the magnitude of the inductor current IL to meet the requirements of the load device. However, due to the characteristics of the inductor L, the inductor current IL cannot immediately increase to the magnitude of the operating current required by the load device. Therefore, the output capacitor COUT coupled to the load terminal NL will discharge to make up for the shortage of the inductor current IL.

[0048] Continuing from the above description, the discharge of the output capacitor COUT further causes an undershoot phenomenon of the output voltage signal VOUT. Therefore, as shown in Figure 2 , the output voltage signal VOUT does not maintain its original periodic steady state since the time point T1, but drops sharply, which may sequentially affect the feedback signal VFB associated with the output voltage signal VOUT, the error current signal IERR output by the error amplifier circuit 153, and the second ripple signal COMP output by the second ripple generation circuit 15. For example, the magnitude of the feedback signal VFB may decrease as the output voltage signal VOUT drops, the magnitude of the error current signal IERR may increase due to the increase in the difference between the corrected reference voltage signal VREFX and the feedback signal VFB, and the magnitude of the second ripple signal COMP may increase as the error current signal IERR increases.

[0049] Another example is as shown in Figure 2As shown, as the magnitude of the second ripple signal COMP increases, the second ripple signal COMP exceeds the first ripple signal LP1 after the time point T1, that is, the voltage level of the second ripple signal COMP will exceed or be greater than the voltage level of the first ripple signal LP1 after the time point T1. In this article, the term "exceeds" should be understood as the phenomenon that the signal level changes from "lower than" to "greater than or equal to", and can also be understood as "jumping upward".

[0050] In some embodiments, when the second ripple signal COMP exceeds the first ripple signal LP1, the comparison circuit 17 triggers the corresponding operation of the on-time generation circuit 19. Specifically, whenever the comparison circuit 17 is triggered by the above-mentioned exceeding phenomenon (for example, the control signal S1 output by the comparison circuit 17 is at a high level), the on-time generation circuit 19 will generate a pulse accordingly. In contrast, when the comparison circuit 17 is not triggered by the above-mentioned exceeding phenomenon, the on-time generation circuit 19 does not generate a pulse (that is, the output is zero).

[0051] For example, the on-time generation circuit 19 can be a Constant On-time pulse generator, which is used to determine whether to generate an output pulse according to the level of the output signal (i.e., the control signal S1) of the comparison circuit 17. The frequency of pulse generation can be determined by the output load, but the time length of each pulse is fixed. Before the time point T1, that is, in the light load state of stable output current, the on-time generation circuit 19 outputs pulses at an approximately fixed frequency. Then, in the heavy load state where more current is required (such as from time point T1 to time point T2), the second ripple signal COMP continuously exceeds the first ripple signal LP1 from after the time point T1 to the time point T2. In this way, the comparison circuit 17 continuously outputs a high-level control signal S1, causing the on-time generation circuit 19 to generate a series of pulses, that is, output pulses at a frequency higher than the above fixed frequency, and there will be a preset off time, such as the minimum off time, between the end of each pulse before the next pulse is generated. This can minimize the undershoot of the output voltage signal VOUT. Once the output voltage signal VOUT tends to be stable (such as after the time point T2), the frequency of the pulses will be reduced to the level required to maintain the stable output voltage signal VOUT. Therefore, compared with the prior art, the on-time generation circuit 19 of the present invention can provide a better transient response.

[0052] In addition, the input voltage signal VIN / output voltage signal VOUT corresponding to each output pulse of the on-time generation circuit 19 may vary, thus changing the switching frequencies of the high-side switch Q1 and the low-side switch Q2. To solve this problem, constant on-time control needs to detect the input / output voltage and achieve a constant switching frequency when the input / output voltage changes. Under the premise of the above requirements, asFigure 1 As shown, the conduction time generation circuit 19 can be designed to be coupled to the input voltage signal VIN and the output voltage signal VOUT, so as to adjust the duty cycle of the output signal of the conduction time generation circuit 19 according to the changes of the input voltage signal VIN and the output voltage signal VOUT, and keep the switching frequencies of the high-side switch Q1 and the low-side switch Q2 fixed, but the present invention is not limited thereto. For example, in some embodiments, the conduction time generation circuit 19 may not be coupled to the input voltage signal VIN or the output voltage signal VOUT.

[0053] In some embodiments, as Figure 3 shown, the output load changes from heavy load to light load after time point T2 and before time point T3, that is, enters the load shedding mode, and the output load no longer requires a large operating current. In this case, the power converter circuit 100 needs to reduce the magnitude of the inductor current IL to meet the requirements of the load device. However, due to the characteristics of the inductor L, the inductor current IL also cannot be immediately reduced to the magnitude of the operating current required by the load device. Therefore, the excess inductor current IL will charge the output capacitor COUT coupled to the load terminal NL.

[0054] Continuing from the above description, the charging of the output capacitor COUT further causes an overshoot phenomenon of the output voltage signal VOUT. Therefore, as Figure 3 shown, the output voltage signal VOUT starts to rise significantly at time point T3, which in turn affects the feedback signal VFB associated with the output voltage signal VOUT, the error current signal IERR output by the error amplifier circuit 153, and the second ripple signal COMP output by the second ripple generation circuit 15 in sequence. For example, the magnitude of the feedback signal VFB may increase as the output voltage signal VOUT rises, so that the magnitude of the error current signal IERR may decrease due to the reduction of the difference between the corrected reference voltage signal VREFX and the feedback signal VFB, and the magnitude of the second ripple signal COMP may decrease as the error current signal IERR decreases.

[0055] Another example is Figure 3 shown, as the magnitude of the second ripple signal COMP decreases, the second ripple signal COMP does not exceed the first ripple signal LP1 continuously between time point T3 and time point T4, and the comparison circuit 17 stops triggering the conduction time generation circuit 19 during this period. In other words, in the absence of the above-mentioned exceeding, the comparison circuit 17 continuously outputs a low-level control signal S1, so that the triggering conduction time generation circuit 19 does not generate pulses. As Figure 3 shown, the inductor current IL flowing through the inductor L gradually decreases after time point T3, and the output voltage signal VOUT at the load terminal NL also tends to be stable after time point T3.

[0056] As can be seen from the description of the embodiments, the control circuit 10 is used to generate a first ripple signal LP1 according to the phase voltage signal PO, and is used to generate a second ripple signal COMP according to the DC signal LP2 generated by processing the first ripple signal LP1, the reference voltage signal VREF, and the feedback signal VFB related to the output voltage signal VOUT. When entering the heavy load, when the second ripple signal COMP continuously exceeds the first ripple signal LP1 (for example, between time point T1 and time point T2), the conduction time generation circuit 19 is used to control the power stage circuit 20 to operate according to the minimum off-time (at this time, the conduction frequency of the high-side switch Q1 increases, and there is a minimum off-time interval between each conduction), so that the inductor current IL flowing through the inductor L increases to adapt to the situation of changing from light load to heavy load, and is used to control the power stage circuit 20 to turn off the high-side switch Q1 when entering the light load when the second ripple signal COMP does not continuously exceed the first ripple signal LP1, so that the inductor current IL flowing through the inductor L rapidly decreases to adapt to the situation of changing from heavy load to light load. Figures 2 - 3

[0057]

[0057] For another example Figures 2 - 3 As shown, the first ripple signal LP1 generated by filtering the phase voltage signal PO by the first ripple generation circuit 11 and the inductor current IL flowing through the inductor L have similar waveform changes. That is to say, the first ripple signal LP1 is related to the inductor current IL.

[0058] In addition, the DC signal LP2 is related to the DC component of the output voltage signal VOUT. Further, the DC signal LP2 is equivalent to being generated by filtering the phase voltage signal PO twice by the first ripple generation circuit 11 and the signal processing circuit 13. Therefore, the DC signal LP2 will approximate the DC component of the output voltage signal VOUT. Also, as can be seen from the above description of the second ripple signal COMP, the second ripple signal COMP is a signal that changes between an upper limit and a lower limit based on the DC signal LP2 and changes with the change of the error current signal IERR.

[0059] It should be noted that the first ripple signal LP1 and the second ripple signal COMP generated by the control circuit 10 can quickly cross when the load changes (that is, the second ripple signal COMP exceeds the first ripple signal LP1, or the first ripple signal LP1 exceeds the second ripple signal COMP), so as to stabilize the output voltage signal VOUT faster than the related technology. Therefore, the power converter circuit 100 of the present invention has advantages such as better load change response ability and better output voltage stability.

[0060] Next, combined with Figures 4A - 4B explain the reason for setting the DC bias correction circuit 155 in the power converter circuit 100. Figure 4ASchematic diagram of DC signal LP2, first ripple signal LP1 and second ripple signal COMP illustrated according to some embodiments of the present disclosure. Figure 4B Schematic diagram of feedback signal VFB and reference voltage signal VREF illustrated according to some embodiments of the present disclosure.

[0061] In some embodiments, such as Figure 4A and Figure 4B shown, since the comparison circuit 17 in the control circuit 10 compares the first ripple signal LP1 and the second ripple signal COMP, rather than comparing the first ripple signal LP1 and the DC signal LP2, the deviation OFS1 between the DC signal LP2 and the second ripple signal COMP will cause a deviation OFS2 between the feedback signal VFB and the reference voltage signal VREF after passing through at least the power stage circuit 20 and the feedback circuit 30. It should be noted that the power converter circuit 100 can utilize the DC bias correction circuit 155 to eliminate this deviation OFS2, which will be described in detail in the following paragraphs in conjunction with Figure 5 detailed description.

[0062] Please refer to Figure 5 , Figure 5 Schematic circuit diagram of the DC bias correction circuit 155 illustrated according to some embodiments of the present disclosure. In some embodiments, the deviation OFS2 in Figure 4B can be equivalently designed by dividing the error current signal IERR by the gain gm of the error amplifier circuit 153. Accordingly, the DC bias correction circuit 155 is configured to correct the reference voltage signal VREF based on the error current signal IERR and the gain gm of the error amplifier circuit to output a corrected reference voltage signal VREFX.

[0063] As Figure 5 shown, the DC bias correction circuit 155 includes a current mirror circuit 501 and a resistor element RX. The resistor element RX includes a first terminal and a second terminal. The first terminal of the resistor element RX is coupled to the reference voltage signal VREF. The current mirror circuit 501 is coupled to the first terminal of the resistor element RX and the error amplifier circuit 153. Specifically, the resistance value of the resistor element RX is set to the reciprocal of the gain gm, that is, the resistance value of the resistor element RX is associated with the gain gm of the error amplifier circuit 153.

[0064] In some embodiments, the current mirror circuit 501 is used to copy the error current signal IERR generated by the error amplifier circuit 153, and output a copied current signal IERRM to the first end of the resistor element RX. The copied current signal IERRM will sequentially pass through the first end and the second end of the resistor element RX, which further generates a voltage difference (not shown in the figure) between the first end and the second end of the resistor element RX. It should be understood that the voltage difference between the first end and the second end of the resistor element RX is substantially the reciprocal of the gain gm multiplied by the copied current signal IERRM, which is equivalent to the error current signal IERR divided by the gain gm (i.e., the offset OFS2). Then, the DC offset correction circuit 155 can subtract the voltage difference between the first end and the second end of the resistor element RX from the reference voltage signal VREF, and output a corrected reference voltage signal VREFX at the second end of the resistor element RX.

[0065] It can be seen therefrom that there is substantially no deviation between the corrected reference voltage signal VREFX and the feedback signal VFB. Therefore, using the corrected reference voltage signal VREFX to replace the reference voltage signal VREF is equivalent to the DC offset correction circuit 155 eliminating the offset OFS2 between the feedback signal VFB and the reference voltage signal VREF.

[0066] It should be understood that the control circuit 10 of the present disclosure is not limited to Figure 1 the circuit architecture shown. For example, the on-time generation circuit 19 can be separated from the control circuit 10, such as being externally connected to the control circuit 10.

[0067] It should also be understood that the DC offset correction circuit 155 of the present disclosure is not limited to Figure 5 the circuit architecture shown. For example, in some embodiments, the DC offset correction circuit 155 can obtain the offset OFS1 between the DC signal LP2 and the second ripple signal COMP, calculate a correction value by multiplying the offset OFS1 by a preset proportional parameter, and correct the reference voltage signal VREF to the corrected reference voltage signal VREFX through the correction value, so as to achieve the purpose of correcting the DC offset. In short, any circuit architecture that can eliminate the offset OFS2 between the feedback signal VFB and the reference voltage signal VREF can be used to implement the DC offset correction circuit 155 of the present disclosure.

[0068] Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be defined by the appended claims.

[0069]

Symbol Description

[0070] 10: Control Circuit

[0071] 11: First Ripple Generation Circuit

[0072] 13: Signal Processing Circuit

[0073] 15: Second Ripple Generation Circuit

[0074] 17: Comparison Circuit

[0075] 19: Conduction Time Generation Circuit

[0076] 20: Power Stage Circuit

[0077] 21: Driver Circuit

[0078] 30: Feedback Circuit

[0079] 100: Power Converter Circuit

[0080] 151: Buffer Circuit

[0081] 153: Error Amplification Circuit

[0082] 155: DC Offset Correction Circuit

[0083] 501: Current Mirror Circuit

[0084] C1, C2, C3: Capacitor Components

[0085] COMP: Second Ripple Signal

[0086] COUT: Output Capacitor

[0087] GND: Ground Voltage

[0088] gm: Gain

[0089] IERR: Error Current Signal

[0090] IERRM: Copied Current Signal

[0091] IL: Inductor Current

[0092] L: Inductor

[0093] LP1: First Ripple Signal

[0094] LP2: DC Signal

[0095] LP2’: Buffered DC Signal

[0096] NC: Compensation Node

[0097] NL: Load Terminal

[0098] NP: Phase Output Terminal

[0099] OFS1, OFS2: Deviation

[0100] OP: Operational Amplifier

[0101] PO: Phase Voltage Signal

[0102] Q1: High-Side Switch

[0103] Q2: Low-Side Switch

[0104] R1, R2, RCOMP, RX: Resistive Elements

[0105] RC: Resistor

[0106] S1: Control Signal

[0107] T1, T2, T3, T4: Time Points

[0108] VFB: Feedback Signal

[0109] VIN: Input Voltage Signal

[0110] VOUT: Output Voltage Signal

[0111] VREF: Reference Voltage Signal

[0112] VREFX: Calibrated Reference Voltage Signal.

Claims

1. A control circuit, characterized in that, Applicable to a power converter circuit, where the power converter circuit includes a power stage circuit and is used to output an inductor current via an inductor, and the control circuit includes: A first ripple generation circuit, coupled to the phase output terminal of the power stage circuit, and used to output a first ripple signal according to the phase voltage signal output by the power stage circuit; A signal processing circuit, coupled to the first ripple generation circuit, and used to process the first ripple signal to output a DC signal; A second ripple generation circuit, coupled to the signal processing circuit, and used to output a second ripple signal according to the DC signal, a reference voltage signal, and a feedback signal related to the output voltage signal of the power converter circuit, where the second ripple generation circuit includes: A DC offset correction circuit, used to correct the reference voltage signal to eliminate the offset between the reference voltage signal and the feedback signal; And A buffer circuit, coupled to the signal processing circuit, used to buffer the DC signal to output a buffered DC signal, where the buffered DC signal is related to the second ripple signal; And A comparison circuit, coupled to the first ripple generation circuit and the buffer circuit, used to compare the first ripple signal and the second ripple signal, and used to trigger the conduction time generation circuit to control the power stage circuit to operate according to a preset turn-off time when the second ripple signal continuously exceeds the first ripple signal, so that the inductor current increases.

2. The control circuit according to claim 1, wherein The first ripple generation circuit is a filter circuit, and the filter circuit is used to filter the phase voltage signal to output the first ripple signal, where the first ripple signal is related to the inductor current.

3. The control circuit according to claim 1, characterized in that, The first ripple generation circuit includes: A resistor element, including a first end coupled to the phase output terminal and a second end coupled to the negative input terminal of the comparison circuit; and A capacitor element, including a first end coupled to the second end of the resistor element and a second end coupled to the ground voltage.

4. The control circuit according to claim 1, wherein The signal processing circuit is a filter circuit, and the filter circuit is used to filter the first ripple signal to output the DC signal, where the DC signal is related to the DC component of the output voltage signal.

5. The control circuit according to claim 1, wherein The signal processing circuit includes: A resistor element, including a first end coupled to the first ripple generation circuit and a second end coupled to the second ripple generation circuit; and A capacitor element, including a first end coupled to the second end of the resistor element and a second end coupled to the ground voltage.

6. The control circuit according to claim 1, wherein The second ripple generation circuit further includes: An error amplification circuit, including a positive input terminal for receiving the corrected reference voltage signal output by the DC offset correction circuit and a negative input terminal for receiving the feedback signal, and used to convert the difference between the corrected reference voltage signal and the feedback signal to output an error current signal to a compensation node, where the second ripple generation circuit is used to output the second ripple signal according to the error current signal and the DC signal.

7. The control circuit according to claim 6, wherein The second ripple generation circuit further includes: A resistor element, including a first end and a second end, where the first end is coupled to the compensation node, and the second end is coupled to the buffer circuit to receive the buffered DC signal output by the buffer circuit; The second ripple generating circuit is configured to output the second ripple signal according to the buffered DC signal and the voltage difference generated by the error current signal and the resistor element.

8. The control circuit according to claim 6, characterized in that, The DC offset correction circuit is configured to correct the reference voltage signal according to the error current signal and the gain of the error amplifier circuit to output the corrected reference voltage signal.

9. The control circuit according to claim 6, characterized in that, The DC offset correction circuit includes: A resistor element including a first terminal and a second terminal, wherein the first terminal is coupled to the reference voltage signal, and the resistance value of the resistor element is associated with the gain of the error amplifier circuit; And A current mirror circuit coupled to the first terminal of the resistor element and the error amplifier circuit, and configured to copy the error current signal to output a copied current signal to the first terminal of the resistor element, wherein the DC offset correction circuit is configured to output the corrected reference voltage signal at the second terminal of the resistor element by passing the copied current signal through the resistor element.

10. A power converter circuit, characterized in that, It is configured to convert an input voltage signal to output an output voltage signal at a load terminal, and includes: A power stage circuit configured to receive the input voltage signal and output a phase voltage signal at a phase output terminal, wherein the phase output terminal is coupled to the load terminal via an inductor; And A control circuit coupled to the power stage circuit, the phase output terminal, and the load terminal, configured to generate a first ripple signal according to the phase voltage signal, generate a second ripple signal according to a DC signal generated by processing the first ripple signal, a reference voltage signal, and a feedback signal associated with the output voltage signal, and control the power stage circuit to operate according to a preset turn-off time when the second ripple signal continuously exceeds the first ripple signal, so that the inductor current flowing through the inductor increases, wherein the control circuit includes a DC offset correction circuit, and the DC offset correction circuit is configured to correct the reference voltage signal to eliminate the offset between the reference voltage signal and the feedback signal.

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