Multi-phase voltage stabilizer and current balancing circuit

Abstract

A multi-phase voltage regulator is coupled to a multi-phase DC-DC converter and comprises a plurality of voltage regulator circuits. The voltage stabilizer circuit is coupled between the power output stage circuit and the compensation circuit, and is used for generating a plurality of control signals according to the compensation signal, so that the power output stage circuit generates a plurality of output currents. The voltage regulator circuit includes a current comparison circuit and a delay circuit. The current comparison circuit is used for obtaining an error signal. The error signal is a difference value between the threshold current and the corresponding output current. The delay circuit is coupled to the compensation circuit and the current comparison circuit and is used for generating a corresponding control signal according to the compensation signal. The delay circuit is used for adjusting the bias current in the delay circuit according to the error signal so as to adjust the duty cycle of the corresponding control signal. Therefore, balance control of each phase of current can be realized.

Description

Technical Field

[0001] The present invention relates to current balancing techniques, and particularly to a multi-phase voltage regulator and a current balancing circuit. Background Art

[0002] A DC-to-DC converter is an electromechanical device for power conversion, used to convert the voltage of a DC power supply. DC-to-DC converters are widely used, and can be used to supply power to low-power devices (such as batteries) or high-power devices (such as industrial machines). Among them, a multi-phase DC-to-DC converter includes multiple converters of different phases, which alternately output electrical energy to the output terminal. Whether the output electrical energy between each phase converter is consistent will affect the power supply stability of the DC-to-DC converter. Therefore, there is a real need for a novel DC-to-DC converter to provide better power supply stability. Summary of the Invention

[0003] The present invention relates to a multi-phase voltage regulator, coupled to a multi-phase DC-to-DC converter, and includes a plurality of voltage regulator circuits. The voltage regulator circuits are coupled between the power output stage circuit and the compensation circuit of the multi-phase DC-to-DC converter, and are used to generate a plurality of control signals according to the compensation signal, so that the power output stage circuit generates a plurality of output currents. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used to obtain an error signal. The error signal is the difference between the threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the plurality of control signals according to the compensation signal. The delay circuit is used to adjust the bias current in the delay circuit according to the error signal, so as to adjust the duty cycle of a corresponding one of the plurality of control signals.

[0004] In one embodiment, the delay circuit includes a first current source circuit to provide a first bias current, and the current comparison circuit includes a first current comparator. The first terminal of the first current comparator is used to receive the threshold current, the second terminal of the first current comparator is used to receive a corresponding one of the plurality of output currents, and the first current comparator outputs a first error signal to the first current source circuit to change the first bias current.

[0005] In one embodiment, the delay circuit includes a second current source circuit to provide a second bias current, and the current comparison circuit includes a second current comparator. The first terminal of the second current comparator is used to receive a corresponding one of the plurality of output currents, the second terminal of the second current comparator is used to receive the threshold current, and the second current comparator outputs a second error signal to the second current source circuit to change the second bias current.

[0006] In one embodiment, the threshold current is the average current of the plurality of output currents.

[0007] In one embodiment, the delay circuit further includes an inverter and a delay capacitor. The inverter has an input terminal, an output terminal, a first correction terminal, and a second correction terminal. The input terminal of the inverter is coupled to the output terminal of the compensation circuit to receive a compensation signal. The first correction terminal of the inverter is used to receive a first bias current. The second correction terminal of the inverter is used to receive a second bias current. The output terminal of the inverter is used to output a node signal. The first bias current and the second bias current are used to adjust the phase of the node signal. The delay capacitor is coupled between the output terminal of the inverter and a reference potential. When the error signal is at a high level, the delay capacitor is used to delay the time for the node signal to transition from a high logic level to a low logic level. When the error signal is at a low level, the delay capacitor is used to delay the time for the node signal to transition from a low logic level to a high logic level.

[0008] In one embodiment, the delay circuit further includes a hysteresis comparator. The hysteresis comparator is coupled to the output terminal of the inverter and is used to generate a corresponding one of the plurality of control signals according to the node signal.

[0009] In one embodiment, the delay circuit further includes an inverter. The inverter has an input terminal and an output terminal. The input terminal of the inverter is used to receive a compensation signal, and the output terminal of the inverter is used to output a node signal.

[0010] In one embodiment, the delay circuit further includes a hysteresis comparator. The hysteresis comparator is coupled to the output terminal of the inverter. The hysteresis comparator has an input terminal, an output terminal, a first correction terminal, and a second correction terminal. The input terminal of the hysteresis comparator is coupled to the output terminal of the inverter to receive the node signal from the inverter. The first correction terminal of the hysteresis comparator is used to receive a first bias current. The second correction terminal of the hysteresis comparator is used to receive a second bias current. The hysteresis comparator is used to generate a corresponding one of the plurality of control signals according to the node signal, the first bias current, and the second bias current.

[0011] In one embodiment, the first threshold voltage and the second threshold voltage of the hysteresis comparator change according to the first bias current and the second bias current. When the error signal is at a high level, the second threshold voltage will decrease to delay the time for the node signal to transition from a high logic level to a low logic level. When the error signal is at a low level, the first threshold voltage will increase to delay the time for the node signal to transition from a low logic level to a high logic level.

[0012] The present invention also relates to a multiphase current balancing circuit applied to a multiphase DC-DC converter, which includes a current detection circuit and a plurality of voltage regulator circuits. The current detection circuit is coupled to the power output stage circuit of the multiphase DC-DC converter to obtain a plurality of output currents and a threshold current. The voltage regulator circuits are coupled between the current detection circuit and the compensation circuit of the multiphase DC-DC converter, and are used to generate a plurality of control signals according to the compensation signal, so that the power output stage circuit generates the plurality of output currents. One of the plurality of voltage regulator circuits includes a current comparison circuit and a delay circuit. The current comparison circuit is used to obtain an error signal. The error signal is the difference between the threshold current and a corresponding one of the plurality of output currents. The delay circuit is coupled to the compensation circuit and the current comparison circuit, and is used to generate a corresponding one of the plurality of control signals according to the compensation signal. The delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of a corresponding one of the plurality of control signals.

[0013] The present invention adjusts the duty cycle of the control signal by the difference between the first output current and the average current, so as to achieve the technical effect of balancing the output currents of each phase, without changing the level of the response voltage or the ramp voltage. In contrast, the background art must change the level of the response voltage or the ramp voltage to adjust the duty cycle of the control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1A FIG. is a schematic diagram of a multiphase DC-DC converter according to some embodiments of the present invention.

[0015] Figure 1B FIG. shows a schematic diagram of a current detection circuit according to some embodiments of the present invention.

[0016] Figure 2 FIG. is a schematic diagram of a current detection circuit according to some embodiments of the present invention.

[0017] Figure 3A FIG. is a schematic diagram of a voltage regulator circuit according to some embodiments of the present invention.

[0018] Figure 3B FIG. is a schematic diagram of the voltage characteristic of a hysteresis comparator according to some embodiments of the present invention.

[0019] Figure 4A FIG. is a schematic diagram of a voltage regulator circuit according to some embodiments of the present invention.

[0020] Figure 4B FIG. is a schematic diagram of the voltage characteristic of a hysteresis comparator according to some embodiments of the present invention. DETAILED DESCRIPTION

[0021] The following will disclose multiple embodiments of the present invention with reference to the accompanying drawings. For the sake of clarity, many practical details will be described together in the following narrative. However, it should be understood that these practical details are not used to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements in the prior art will be shown in a simple schematic manner in the drawings.

[0022] In this document, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this document to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless clearly specified in the context, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present invention.

[0023] The present invention relates to a multiphase DC-DC converter for converting an input voltage to output output voltages of different voltages. In one embodiment, the multiphase DC-DC converter is applied to a vehicle power supply. For example, as a power transmission circuit, it can store the power of a charging pile in a battery or provide the stored power of the battery to in-vehicle devices. However, the present invention is not limited thereto. In other embodiments, the multiphase DC-DC converter can also be applied to other devices and loads.

[0024] Figure 1A The schematic diagram of a multiphase DC-DC converter 100 according to some embodiments of the present invention is shown. The multiphase DC-DC converter 100 includes a power output stage circuit 110, a current balancing circuit 120, and a compensation circuit 130. The power output stage circuit 110 includes a plurality of drive circuits DC and a switch circuit 111 formed by a plurality of transistor switches, where each drive circuit DC and the corresponding switch circuit 111 are used to generate corresponding output currents Is1 to Isn according to the input voltage Vin.

[0025] In Figure 1A the embodiment shown, the power output stage circuit 110 includes multiple sets of sub-circuits (for example, two or more sets). Each set of sub-circuits includes a drive circuit DC, and the above-mentioned switch circuit 111 includes an upper bridge switch Ta and a lower bridge switch Tb, and is coupled to the input voltage Vin. The drive circuit DC is used to control the conduction or cutoff of the upper bridge switch Ta and the lower bridge switch Tb according to the received control signal to generate or adjust the corresponding output currents Is1 to Isn. The phases of the output currents Is1 to Isn generated by each set of sub-circuits may be different from each other. For example, when the power output stage circuit 110 includes multiple sets of sub-circuits, there is a predetermined phase difference between the output currents of adjacent sub-circuits.

[0026] In one embodiment, the power output stage circuit 110 generates an output voltage Vout and a feedback voltage Vfb through an energy storage circuit 140 and a voltage dividing circuit 150. The energy storage circuit 140 is coupled to the output terminal of the power output stage circuit 110 and includes a plurality of inductors L1 to Ln and an output capacitor Cout for generating the output voltage Vout according to output currents Is1 to Isn. The voltage dividing circuit 150 is coupled to the power output stage circuit 110 and the energy storage circuit 140 and includes a plurality of voltage dividing resistors R1 and R2 for dividing the output voltage Vout to generate the feedback voltage Vfb. Since those skilled in the art can understand the manner in which the multi-phase DC-DC converter 100 generates the output voltage Vout, more details will not be described herein.

[0027] The current balance circuit 120 is coupled to the power output stage circuit 110 and includes a current detection circuit 121 and a multi-phase voltage regulator 122. The current balance circuit 120 is configured to generate and adjust a plurality of control signals Spwm1 to Spwmn corresponding to different phases, so that the power output stage circuit 110 generates a plurality of output currents Is1 to Isn of different phases accordingly, thereby keeping the currents of each phase balanced. The generation manner of the control signals will be described in detail in the following paragraphs.

[0028] The current balance circuit 120 is coupled to the compensation circuit 130 and the power output stage circuit 110. The compensation circuit 130 is configured to receive a response voltage Vea from the power output stage circuit 110 and generate a compensation signal Vcomp. The response voltage Vea is generated according to the difference between the feedback voltage Vfb provided at the output terminal of the multi-phase DC-DC converter 100 and a reference voltage (such as a reference voltage or a preset fixed voltage). Specifically, in one embodiment, the feedback voltage Vfb generated by the power output stage circuit 110 minus the reference voltage is used as the response voltage Vea. In other embodiments, the power output stage circuit 110 may also directly use the feedback voltage Vfb as the response voltage Vea.

[0029] The compensation circuit 130 is configured to compare the response voltage Vea with a ramp voltage Vramp to generate a compensation signal Vcomp according to the difference between the response voltage Vea and the ramp voltage Vramp. The compensation signal Vcomp is used to reflect the current state of the output voltage Vout (such as a heavy load or a light load state). After the compensation signal Vcomp is provided to the current balance circuit 120, the current balance circuit 120 generates the control signals Spwm1 to Spwmn according to the compensation signal Vcomp.

[0030] Continuing from the above, in one embodiment, the positive terminal of the compensation circuit 130 is used to receive the response voltage Vea, and the negative terminal of the compensation circuit 130 is used to receive the ramp voltage Vramp. Therefore, the magnitude of the compensation signal Vcomp is positively correlated with "the difference between the response voltage Vea and the ramp voltage Vramp". However, the present disclosure is not limited thereto. In other embodiments, the signals received by the positive and negative terminals of the compensation circuit 130 may be swapped according to the actual circuit design.

[0031] In one embodiment, the ramp voltage Vramp is a periodic signal, and its signal magnitude changes periodically within a time period. In some other embodiments, the ramp voltage Vramp may be a sawtooth wave with a fixed slope in the signal period. "Sawtooth wave" means that in each signal period, it starts to change from a fixed level (e.g., rising or falling), and when the current signal period ends and enters the next signal period, it returns to the original fixed level. In some embodiments, the signal slope of the ramp voltage Vramp is positive, meaning that within the signal period, the level of the ramp voltage Vramp gradually increases. However, the present disclosure is not limited thereto. In other embodiments, depending on the slope, the ramp voltage Vramp may also be a triangular wave.

[0032] In one embodiment of the present disclosure, a plurality of voltage regulator circuits 200 are provided in the current balance circuit 120. The voltage regulator circuits 200 can selectively change the level change time of the control signals Spwm1 to Spwmn according to the power supply state of the multi-phase DC-DC converter 100 (e.g., according to the magnitude of the compensation signal Vcomp and / or the output current) to ensure that the currents of each phase output by the multi-phase DC-DC converter 100 can be maintained in balance (i.e., the output currents of each phase can be maintained substantially equal). For ease of explanation, the plurality of voltage regulator circuits 200 corresponding to the multiple phases in the multi-phase DC-DC converter 100 are collectively referred to as "multi-phase voltage regulators" herein.

[0033] As Figure 1A shown, in this embodiment, the current balance circuit 120 includes a current detection circuit 121 and a multi-phase voltage regulator 122. The current detection circuit 121 is coupled to the power output stage circuit 110 to obtain the output currents Is1 to Isn and the current threshold. The current detection circuit 121 is also used to generate a plurality of error signals provided to the plurality of voltage regulator circuits 200 according to the current threshold and the output currents Is1 to Isn.

[0034] In one embodiment, the current threshold is the average or median value of a plurality of drive currents generated by the power output stage circuit 110. In other words, the current threshold is calculated by the current detection circuit 121, but the present disclosure is not limited thereto. In other embodiments, the current threshold may also be a preset fixed current value, for example, the ideal current value output by each phase power output stage circuit 110 when the multi-phase DC-DC converter 100 is operating normally. In still other embodiments, the current threshold can be obtained by looking up a table, for example, according to the level of the input voltage Vin to find the corresponding values of the output currents Is1 to Isn.

[0035] In one embodiment, the error signal is the difference between the threshold current and each output current, such as Figure 1A the error currents Idiff1 to Idiffn shown. In other embodiments, the current detection circuit 121 is used to perform signal processing on the current threshold and the corresponding output current to generate an error signal, which is respectively output to the corresponding voltage regulator circuit 200.

[0036] Specifically, in some embodiments, the current detection circuit 121 can detect the phase nodes N1 to Nn between the upper bridge switch Ta and the lower bridge switch Tb of the power output stage circuit 110 to obtain the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and then calculate the corresponding output currents. At the same time, the current detection circuit 121 can also calculate the average current of the plurality of output currents as the current threshold.

[0037] Figure 1B The figure shows a schematic diagram of the current detection circuit 121 according to some embodiments of the present disclosure. As Figure 1A and Figure 1B shown, the current detection circuit 121 includes a transduction circuit 121a, an adder circuit 121b, a divider circuit 121c, and a subtractor circuit 121d. The transduction circuit 121a is coupled to the power output stage circuit 110 to receive the output currents Is1 to Isn. In one embodiment, the transduction circuit 121a includes a transconductance amplifier to receive the voltages Lx1 to Lxn of the phase nodes N1 to Nn and then calculate the output currents Is1 to Isn.

[0038] The adder circuit 121b is coupled to the transduction circuit 121a for receiving the output currents Is1 to Isn and calculating the average current Iavg of the output currents Is1 to Isn through the divider circuit 121c. The subtractor circuit 121d is coupled to the divider circuit 121c for calculating the difference between the output current of the corresponding phase and the average current Iavg to generate the error currents Idiff1 to Idiffn.

[0039] The multi-phase voltage regulator 122 includes a plurality of voltage regulator circuits 200, coupled between the compensation circuit 130 and the current detection circuit 121, for receiving an error signal and a compensation signal Vcomp. As described above, the error signal provided by the current detection circuit 121 may be the error currents Idiff1~Idiffn calculated by the current detection circuit 121, or may be the operation result of the current threshold and the corresponding output current provided by the current detection circuit 121. The multi-phase voltage regulator 122 is used to generate a plurality of control signals Spwm1~Spwmn corresponding to different phases according to the error signal and the compensation signal Vcomp, so that the power output stage circuit 110 generates output currents Is1~Isn. In addition, the voltage regulator circuit 200 can also selectively change the level change time point of the corresponding control signal (e.g., delay or advance), so that the plurality of output currents Is1~Isn between different phases can be kept balanced.

[0040] In one embodiment, the multi-phase voltage regulator 122 includes a plurality of voltage regulator circuits 200, and each voltage regulator circuit 200 is used to generate control signals Spwm1~Spwmn for the output currents Is1~Isn of the corresponding phases, so as to provide the control signals Spwm1~Spwmn to each driving circuit DC.

[0041] In some embodiments, the control signals Spwm1~Spwmn generated by each voltage regulator circuit 200 are a kind of Pulse-width modulation (PWM) signals. The voltage regulator circuit 200 can also adjust the duty ratio of the control signals Spwm1~Spwmn, thereby changing the magnitudes of the output currents Is1~Isn generated by the power output stage circuit 110. Since those skilled in the art can understand the manner of transmitting control signals between the power output stage circuit 110 and the current balance circuit in digital signals, it will not be described in detail here.

[0042] Figure 2 Some embodiments according to the present invention are shown to illustrate the concept of "ensuring the balance of the phase currents output by the multi-phase DC-DC converter 100 by controlling the level change time points of the control signals Spwm1~Spwmn". Please refer to Figure 1A and Figure 2 As shown, the current balance circuit 120 and the voltage regulator circuit 200 for controlling the output current Is1 are taken as examples for illustration here. In Figure 2Among them, waveforms Spwm-A to Spwm-C respectively represent the waveform changes of control signal Spwm1 under different conditions. Waveform Spwm-A represents the waveform when "output current Is1 is equal to average current Iavg". Waveform Spwm-B represents the waveform that control signal Spwm1 should be adjusted when "output current Is1 is greater than average current Iavg" (i.e., reducing the duty cycle). Waveform Spwm-C represents the waveform that control signal Spwm1 should be adjusted when "output current Is1 is less than average current Iavg" (i.e., increasing the duty cycle).

[0043] As Figure 2 shown, the time point when the levels of response voltage Vea and ramp voltage Vramp are the same will be the time point when the level of control signal Spwm1 changes. In other words, "the time point when the levels of response voltage Vea and ramp voltage Vramp are the same" is related to the duty cycle of control signal Spwm1. As shown in waveform Spwm-A, when response voltage Vea drops from a high level to the level of ramp voltage Vramp (i.e., time point P1), control signal Spwm1 will change from a low level to a high level. When response voltage Vea rises from a low level to the level of ramp voltage Vramp (i.e., time point P3), control signal Spwm1 will change from a high level to a low level. Note that the present disclosure does not adjust the duty cycle of control signal Spwm1 by changing the levels of response voltage Vea or ramp voltage Vramp, but adjusts the duty cycle of control signal Spwm1 through the difference between output current Is1 and average current Iavg to achieve the technical effect of balanced output current for each phase.

[0044] Please refer to Figure 2 shown. For example, during the positive half cycle of the operation of power output stage circuit 110 (for waveform Spwm-A, the positive half cycle is from time point P1 to time point P3), when control signal Spwm1 is at a high level and ramp voltage Vramp is lower than response voltage Vea, upper bridge switch Ta conducts and lower bridge switch Tb disconnects, and input voltage Vin charges output capacitor Cout and inductor L1, forming output current Is1 flowing from phase node N1 to output capacitor Cout. Then, current detection circuit 121 receives voltages Lx1 to Lxn of phase nodes N1 to Nn and calculates output currents Is1 to Isn based on voltages Lx1 to Lxn. As Figure 1B and Figure 2As shown, the current detection circuit 121 compares the output currents Is1 to Isn with the current average value of these currents (i.e., the average current Iavg or the aforementioned current threshold). For example, when the output current Is1 is greater than the average current Iavg, the duty cycle of the control signal Spwm1 should be adjusted downward at this time to reduce the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 can delay the "time point when the control signal Spwm1 rises from the low level to the high level" (e.g., for waveform Spwm-B, when it is delayed from time point P1 to time point P2), so as to adjust the duty cycle of the control signal Spwm1. In this way, by reducing the duty cycle of the control signal Spwm1, that is, the conduction time of the upper bridge switch Ta becomes shorter, the output current Is1 can be reduced.

[0045] Similarly, when the output current Is1 is less than the average current Iavg, the duty cycle of the control signal Spwm1 should be adjusted upward at this time to increase the output current Is1. Therefore, the voltage regulator circuit 200 corresponding to the control signal Spwm1 can delay the "time point when the control signal Spwm1 drops from the high level to the low level" (e.g., for waveform Spwm-C, from time point P3 to time point P4), so as to adjust the duty cycle of the control signal Spwm1 upward. In this way, by increasing the duty cycle of the control signal Spwm1, that is, the conduction time of the upper bridge switch Ta becomes longer, the output current Is1 can be increased.

[0046] The following begins to describe the method and corresponding circuit for the voltage regulator circuit 200 to adjust the time points at which the control signals Spwm1 to Spwmn change levels. As Figure 1A shown, the voltage regulator circuit 200 includes a current comparison circuit 210 and a delay circuit 220, and the current comparison circuit 210 is coupled to the delay circuit 220. The current comparison circuit 210 is coupled to the current detection circuit 121 to obtain an error signal, for example, receiving one of the error currents Idiff1 - Idiffn corresponding thereto from the current detection circuit 121, or receiving the current threshold (e.g., the current average value, refer to Figure 3A the average current Iavg) and the corresponding output current (refer to Figure 3A the output current Is1) from the current detection circuit 121.

[0047] The delay circuit 220 is coupled to the compensation circuit 130 and the current comparison circuit 210, and is used to generate corresponding control signals according to the compensation signal Vcomp. The delay circuit 220 is also used to adjust the bias current in the delay circuit according to the error signal (for example, the corresponding error current Idiff1, or the average current Iavg and the output current Is1 as shown in Figure 1B 、 Figure 3A ), so as to adjust the duty cycle of the corresponding control signal.

[0048] The present invention utilizes an error signal to confirm the state of the output current of each phase at present (such as being too large or too small), and then selectively changes the level change time of the corresponding control signal. For example, it changes the time point when the control signal enters the high level, or changes the time point when the control signal enters the low level. Accordingly, the duty cycle of the control signal can be adjusted to achieve the purpose of keeping the currents of each phase balanced.

[0049] In some embodiments, the multi-phase DC-DC converter 100 can achieve the purpose of "the level change time of the control signal" by controlling the phase of the signal on the control node in the control delay circuit 220. In other embodiments, the multi-phase DC-DC converter 100 can also achieve the purpose of "the level change time of the control signal" by controlling the threshold voltage of the circuit elements in the control delay circuit 220. Each control method of the present invention will be described through Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B embodiments.

[0050] Figure 3A Shown is a schematic diagram of a voltage regulator circuit 300 according to some embodiments of the present invention, which can be applied to Figure 1A the multi-phase DC-DC converter 100 shown in Figure 3A The shown voltage regulator circuit can be Figure 1A a example of the voltage regulator circuit 200 shown. The voltage regulator circuit 300 includes a current comparison circuit 310 and a delay circuit 320, wherein the current comparison circuit 310 is coupled to the delay circuit 320. The current comparison circuit 310 is coupled to the current detection circuit 121 for receiving the average current Iavg and the output current Is1. The delay circuit 320 is coupled to the compensation circuit 130 and the current comparison circuit 310 to adjust the phase of the signal (hereinafter referred to as the node signal S3) on the control node NA in the delay circuit 320 according to the error signal, so as to adjust the duty cycle of the corresponding control signal. Among them, the current comparison circuit 310 and the delay circuit 320 can be examples of the current comparison circuit 210 and the delay circuit 220 respectively.

[0051] As Figure 3A shown, in one embodiment, the current comparison circuit 310 includes a first current comparator 311. The first current comparator 311 is coupled to the current detection circuit 121. Its first terminal (such as the negative terminal) is used to receive the threshold current (the average current Iavg in this embodiment), and its second terminal (such as the positive terminal) is used to receive the corresponding output current Is1. The first current comparator 311 will generate a first error signal S1 according to the difference between the average current Iavg and the output current Is1.

[0052] Continuing from the above, in one embodiment, the delay circuit 320 includes a first current source circuit 321 for providing a first bias current Ib1 according to the power supply Vcc. The first current source circuit 321 is further configured to receive a first error signal S1 generated by the first current comparator 311 and change the magnitude of the output first bias current Ib1 according to the first error signal S1. In some embodiments, the first error signal S1 may be a voltage signal for changing the magnitude of the first bias current Ib1. In some other embodiments, the current comparison circuit 310 may be omitted. In this setting, the first current source circuit 321 and the second current source circuit 322 may be directly coupled to the current detection circuit 121 to receive one of the error currents Idiff1 - Idiffn, such as the error current Idiff1, and directly use the error current Idiff1 as the first error signal S1 and the inverted error current Idiff1 as the second error signal S2; or directly use the error current Idiff1 as the second error signal S2 and the inverted error current Idiff1 as the first error signal S1.

[0053] Similarly, in one embodiment, the current comparison circuit 310 may further include a second current comparator 312. The second current comparator 312 is coupled to the current detection circuit 121 and the inverter 323. The first terminal (e.g., the negative terminal) of the second current comparator 312 is configured to receive the corresponding output current Is1, and the second terminal (e.g., the positive terminal) of the second current comparator 312 is configured to receive a threshold current (which is the average current Iavg in this embodiment). The second current comparator 312 generates a second error signal S2 according to the difference between the average current Iavg and the output current Is1.

[0054] Continuing from the above, the delay circuit 320 further includes a second current source circuit 322 for providing a second bias current Ib2 according to the power supply Vcc. The second current source circuit 322 is coupled to the second current comparator 312 and the inverter 323, configured to receive the second error signal S2 generated by the second current comparator 312 and change the magnitude of the output second bias current Ib2 according to the second error signal S2. Here, it should be particularly noted that both the first current comparator 311 and the second current comparator 312 are configured to receive the corresponding output current Is1 and the average current Iavg, but the receiving positions (i.e., the positive and negative terminals) are opposite. Therefore, the first error signal S1 and the second error signal S2 will have different logic levels.

[0055] Specifically, as Figure 3AAs shown, the delay circuit 320 includes an inverter 323, a delay capacitor C31, and a hysteresis comparator 324. The input terminal of the inverter 323 is coupled to the output terminal of the compensation circuit 130 to receive a compensation signal Vcomp. The output terminal of the inverter 323 is coupled to a control node NA to output a node signal. The first calibration terminal of the inverter 323 is coupled to a first current source circuit 321 to receive a first bias current Ib1, and the second calibration terminal of the inverter 323 is coupled to a second current source circuit 322 to receive a second bias current Ib2. The inverter 323 is configured to control the charging or discharging of the delay capacitor C31 according to the first bias current and / or the second bias current to adjust the phase of the node signal of the control node NA.

[0056] The delay capacitor C31 is coupled between the output terminal of the inverter 323 (such as the control node NA) and a reference potential (such as a ground potential). The hysteresis comparator 324 is also coupled to the output terminal of the inverter 323 (the control node NA) to generate a corresponding control signal Spwm1 according to the node signal S3. In one embodiment, the hysteresis comparator 324 can be implemented by a Schmitt trigger.

[0057] Figure 3B The following shows the voltage characteristic diagram of the hysteresis comparator 324 in some embodiments, where the horizontal axis is the input voltage received by the hysteresis comparator 324 (i.e., the node signal S3), and the vertical axis is the output voltage output by the hysteresis comparator 324 (i.e., Spwm1). The voltage characteristic of the hysteresis comparator 324 presents a hysteresis curve. When the input voltage of the hysteresis comparator 324 rises to a first threshold voltage VTH, the output voltage will flip to a low level (as shown by the curve L31); when the input voltage of the hysteresis comparator 324 drops to a second threshold voltage VTL, the output voltage will flip to a high level (as shown by the changing curve L32); and when the input voltage of the hysteresis comparator 324 is between the first threshold voltage VTH and the second threshold voltage VTL, the output voltage will not flip. Since those skilled in the art can understand the characteristics and implementation manners of the hysteresis comparator 324, more details will not be elaborated here.

[0058] Please refer to Figure 1A 、 Figure 2 and Figures 3A - 3B , the following describes the operation process in which the delay circuit 320 adjusts the bias current in the delay circuit according to an error signal, and then changes the duty cycle of the corresponding control signal. As Figure 2As shown, during the positive half-cycle of the operation of the power output stage circuit, that is, when the response voltage Vea is greater than the ramp voltage Vramp, the compensation signal Vcomp is at a high level at this time. The node signal S3 output by the inverter 323 should change to a low level. If the output current Is1 is greater than the average current Iavg at this time, the first error signal S1 is at a high level and the second error signal S2 is at a low level. In this way, the first current source circuit 321 is controlled to increase the first bias current Ib1 and the second current source circuit 322 is controlled to decrease the second bias current Ib2 respectively. When the first bias current Ib1 increases and the second bias current Ib2 decreases, the delay capacitor C31 will be additionally charged. Therefore, the time point when the node signal S3 drops to a low level (as low as at least the second threshold voltage VTL) will become slower, that is, the time point when the hysteresis comparator 324 converts the received node signal S3 with a low level into a control signal Spwm1 with a high level will be delayed, as Figure 2 shown in the waveform Spwm-B. At this time, the time point when the control signal Spwm1 rises to a high level will be delayed from the original time point P1 to the time point P2. In this way, it is equivalent to reducing the duty cycle of Spwm1. When the duty cycle of Spwm1 decreases, the conduction time of the upper bridge switch Ta becomes shorter. Therefore, the output current Is1 is reduced, achieving the effect of balancing the phase currents.

[0059] Regarding the positive half-cycle of the operation of the power output stage circuit 110, please refer to the waveform Spwm-C. If the output current Is1 is less than the average current Iavg, it will cause the first bias current Ib1 to decrease and the second bias current Ib2 to increase. In this way, the delay capacitor C31 discharges smoothly. Therefore, the time when the node signal S3 enters a low level (as low as at least the second threshold voltage VTL) is not affected, that is, the time when the control signal Spwm1 enters a high level is not affected. Therefore, the time when the waveform Spwm-C enters a high level in the positive half-cycle is the same as the time when the waveform Spwm-A enters a high level.

[0060] Next, as Figure 2As shown, during the negative half-cycle when the power output stage circuit 110 operates, that is, when the response voltage Vea is less than the ramp voltage Vramp, the compensation signal Vcomp is at a low level at this time. The node signal S3 output by the inverter 323 should change to a high level. If the output current Is1 is less than the average current Iavg at this time, the first error signal S1 is at a low level and the second error signal S2 is at a high level, respectively controlling the first current source circuit 321 to decrease the first bias current Ib1 and controlling the second current source circuit 322 to increase the second bias current Ib2. When the first bias current Ib1 becomes smaller and the second bias current Ib2 becomes larger, the delay capacitor C31 will be additionally discharged. Therefore, the level of the node signal S3 rises to a high level (it must be at least as high as the first threshold voltage VTH to meet the voltage inversion condition, and the principle can be referred to Figure 3B ). The time point will become slower, that is, the time point when the hysteresis comparator 324 converts the received node signal S3 with a high level into a control signal Spwm1 with a low level will be delayed, as shown in the waveform Spwm-C in Figure 2 . At this time, the time point when the control signal Spwm1 drops to a low level will be delayed from the original time point P3 to the time point P4. In this way, it is equivalent to increasing the duty cycle of Spwm1. When the duty cycle of Spwm1 increases, the conduction time of the upper bridge switch Ta becomes longer, so the output current Is1 is increased, achieving the effect of balancing the phase currents.

[0061] As for the negative half-cycle when the power output stage circuit 110 operates, if the output current Is1 is greater than the average current Iavg, it will cause the first bias current Ib1 to rise and the second bias current Ib2 to drop. In this way, the delay capacitor C31 is successfully charged. Therefore, the time when the node signal S3 enters the high level (at least as high as the first threshold voltage VTH) is not affected. So, during the negative half-cycle, the time when the waveform Spwm-B enters the low level is the same as the time when the waveform Spwm-A enters the low level.

[0062] In the foregoing embodiments, the voltage regulator circuit 300 includes a first current comparator 311, a second current comparator 312, a first current source circuit 321, and a second current source circuit 322. The first current comparator 311 and the corresponding first current source circuit 321 are used to generate a first bias current Ib1 to change the phase change time of the node signal on the control node NA. Similarly, the second current comparator 312 and the corresponding second current source circuit 322 are also used to generate a second bias current Ib2 to change the phase change time of the node signal on the control node NA. However, in other embodiments, the voltage regulator circuit 300 may also have only the first bias current Ib1 or the second bias current Ib2 to change the phase change time of the node signal on the control node NA. In other words, in other embodiments, the voltage regulator circuit 300 may include only the first current comparator 311 and the corresponding first current source circuit 321, or only the second current comparator 312 and the corresponding second current source circuit 322.

[0063] Figure 4A The figure shows a schematic diagram of a voltage regulator circuit 400 according to some embodiments of the present disclosure, which can be applied to Figure 1A the multi-phase DC-DC converter 100 shown. Figure 4A The voltage regulator circuit shown can be Figure 1A a example of the voltage regulator circuit 200 shown. The voltage regulator circuit 400 includes a current comparison circuit 410 and a delay circuit 420. The current comparison circuit 410 is coupled to the current detection circuit 121 to receive an error signal. The delay circuit 420 is coupled to the compensation circuit 130 and the current comparison circuit 410 to adjust the phase of the node signal on the control node NA in the delay circuit 420 according to the error signal, so as to adjust the duty cycle of the corresponding control signal Spwm1. Among them, the current comparison circuit 410 and the delay circuit 420 can be examples of the current comparison circuit 210 and the delay circuit 220 respectively.

[0064] As Figure 4A shown, in one embodiment, the current comparison circuit 410 includes a first current comparator 411 and a second current comparator 412, and the delay circuit 420 includes a first current source circuit 421 and a first current source circuit 421.

[0065] The first current comparator 411 and the first current source circuit 421 are configured to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate a first bias current Ib1. The second current comparator 412 and the second current source circuit 422 are configured to receive the average current Iavg and the corresponding output current Is1 from the current detection circuit 121 to generate a second bias current Ib2. In an embodiment, the circuits of the first current comparator 411, the first current source circuit 421, the second current comparator 412, and the second current source circuit 422 are respectively Figure 3A similar to the first current comparator 311, the first current source circuit 321, the second current comparator 312, and the second current source circuit 322 shown, so the details are not described herein again.

[0066] Specifically, as Figure 4A shown, the delay circuit 420 includes an inverter 423, a delay capacitor C41, and a hysteresis comparator 424. The input terminal of the inverter 423 is coupled to the output terminal of the compensation circuit 130 to receive the compensation signal Vcomp. The output terminal of the inverter 423 is coupled to the control node NA and the delay capacitor C41 to output a node signal S4.

[0067] The input terminal of the hysteresis comparator 424 is coupled to the output terminal of the inverter 423 to use the node signal S4 of the control node NA as the input voltage. The first correction terminal (e.g., the positive correction terminal) of the hysteresis comparator 424 is coupled to the first current source circuit 421 to receive the first bias current Ib1. The second correction terminal (e.g., the negative correction terminal) of the hysteresis comparator 424 is coupled to the second current source circuit 422 to receive the second bias current Ib2. The output terminal of the hysteresis comparator 424 is used to output a control signal Spwm1. The hysteresis comparator 424 is configured to generate the control signal Spwm1 according to the node signal S4, the first bias current Ib1, and / or the second bias current Ib2, and can control the charging or discharging of the delay capacitor C41 according to the magnitudes of the first bias current Ib1 and / or the second bias current Ib to adjust the phase of the node signal S4.

[0068] In an embodiment, the hysteresis comparator 424 can also be implemented by a Schmitt trigger, and its voltage characteristics are as described above Figure 4B shown. The first threshold voltage VTH of the hysteresis comparator 424 is controlled by the second bias current Ib2 and changes. For example, when the second bias current Ib2 increases, the first threshold voltage VTH also increases; similarly, the second threshold voltage VTL is controlled by the first bias current Ib1 and changes. For example, when the first bias current Ib1 increases, the second threshold voltage VTL decreases accordingly.

[0069] When the first error signal S1 is at a high level, the first bias current Ib1 will increase, thereby reducing the second threshold voltage VTL (refer to Figure 4B , changing from the change curve L41 to the change curve L42), so that the time when the node signal "enters the low logic level from the high logic level" can be delayed. On the other hand, when the second error signal S2 is at a high level, the second bias current Ib2 will increase, thereby increasing the first threshold voltage VTH (refer to Figure 4B , changing from the change curve L43 to the change curve L44), so that the time when the node signal "enters the high logic level from the low logic level" can be delayed.

[0070] Please refer to Figure 1A , Figure 2 and Figures 4A - 4B for the following description of the operation process in which the delay circuit 420 adjusts the bias current in the delay circuit according to the error signals (i.e., the first error signal S1 and the second error signal S2), thereby changing the duty cycle of the corresponding control signal Spwm1. In the positive half-cycle of the operation of the power output stage circuit, that is, when the response voltage Vea is greater than the ramp voltage Vramp, the compensation signal Vcomp is at a high level at this time, and the node signal S4 output by the inverter 423 should change to a low level. If the output current Is1 is greater than the average current Iavg at this time, the error signal S1 is at a high level and the error signal S2 is at a low level, respectively controlling the first current source circuit 421 to increase the bias current Ib1 and controlling the second current source circuit 422 to decrease the bias current Ib2. When the first bias current Ib1 increases and the second bias current Ib2 decreases, the second threshold voltage VTL will decrease and the first threshold voltage VTH will increase. Therefore, as the second threshold voltage VTL decreases, the level on the control node NA (i.e., the node signal S4) needs to drop to a lower level before it will be converted into a control signal Spwm1 with a high level by the hysteresis comparator 324, that is, the time point when the control signal Spwm1 enters the high level is delayed, as shown by the waveform Spwm-B in Figure 2 , and the time point when the control signal Spwm1 rises to the high level will be delayed from the original time point P1 to the time point P2. In this way, it is equivalent to reducing the duty cycle of the control signal Spwm1. When the duty cycle of the control signal Spwm1 decreases, the conduction time of the upper bridge switch Ta becomes shorter, so the output current Is1 is reduced, achieving the effect of balancing the phase currents.

[0071] Regarding the positive half-cycle of the operation of the power output stage circuit 110, if the output current Is1 is less than the average current Iavg, the first bias current Ib1 will decrease and the second bias current Ib2 will increase. This does not affect the second threshold voltage VTL (only the first threshold voltage VTH will increase). Therefore, the time when the node signal S4 is converted into the control signal Spwm1 with a high level is not affected, that is, the control signal Spwm1 still enters the high level at the time point P1. So, in the positive half-cycle, the time point when the waveform Spwm-C enters the high level is the same as the time point when the waveform Spwm-A enters the high level.

[0072] Next, as Figure 2 shown, in the negative half-cycle of the operation of the power output stage circuit 110, that is, when the response voltage Vea is less than the ramp voltage Vramp, at this time the compensation signal Vcomp is at a low level, and the node signal S4 output by the inverter 423 should change to a high level. If the output current Is1 is less than the average current Iavg at this time, the first error signal S1 is at a low level and the second error signal S2 is at a high level, respectively controlling the first current source circuit 421 to decrease the first bias current Ib1 and controlling the second current source circuit 322 to increase the second bias current Ib2. In the case where the first bias current Ib1 becomes smaller and the second bias current Ib2 becomes larger, the first threshold voltage VTH will increase. Therefore, the node signal S4 must rise to a higher level before it will be converted into the control signal Spwm1 with a low level, that is, the time point when the control signal Spwm1 enters the low level will be delayed. As Figure 2 shown in the waveform Spwm-C shown, at this time the time point when the control signal Spwm1 drops to the low level will be delayed from the original time point P3 to the time point P4. In this way, it is equivalent to increasing the duty cycle of Spwm1. When the duty cycle of Spwm1 increases, the conduction time of the upper bridge switch Ta becomes longer, so Is1 is increased, achieving the effect of balancing the phase currents.

[0073] Regarding the negative half-cycle of the operation of the power output stage circuit 110, if the output current Is1 is greater than the average current Iavg, the first bias current Ib1 will increase and the second bias current Ib2 will decrease. In this way, the first threshold voltage VTH is not affected (only the second threshold voltage VTL is pulled down), that is, the time point when the node signal is converted into the control signal Spwm1 with a low level is not affected (still the time point P3). Therefore, in the negative half-cycle, the time when the waveform Spwm-B enters the low level is the same as the time when the waveform Spwm-A enters the low level.

[0074] In the foregoing embodiment, the voltage regulator circuit 400 includes a first current comparator 411, a second current comparator 412, a first current source circuit 421, and a second current source circuit 422.

[0075] The first current comparator 411 and the corresponding first current source circuit 421 are used to generate a first bias current Ib1 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. Similarly, the second current comparator 412 and the corresponding second current source circuit 422 are also used to generate a second bias current Ib2 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. However, in other embodiments, the voltage regulator circuit 400 may also have only the first bias current Ib1 or the second bias current Ib2 to change the first threshold voltage VTH and the second threshold voltage VTL of the hysteresis comparator 424. In other words, in other embodiments, the voltage regulator circuit 400 may include only the first current comparator 411 and the corresponding first current source circuit 421, or only the second current comparator 412 and the corresponding second current source circuit 422.

[0076] In summary, the present invention adjusts the duty cycle of the control signal Spwm1 by the difference between the first output current Is1 and the average current Iavg to achieve the technical effect of balancing the output currents of each phase, without changing the level of the response voltage Vea or the ramp voltage Vramp. In contrast, the background art must change the level of the response voltage Vea or the ramp voltage Vramp to adjust the duty cycle of the control signal Spwm1.

[0077] The various elements, method steps, or technical features in the foregoing embodiments may be combined with each other, without being limited by the order of the text description or the order of the drawings in the present invention.

[0078] Although the present invention has been disclosed above in the form of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope defined by the appended claims.

[0079]

Symbol Description

[0080] 100: Multi-phase DC-DC converter

[0081] 110: Power output stage circuit

[0082] 111: Switching circuit

[0083] 120: Current balance circuit

[0084] 121: Current detection circuit

[0085] 121a: Transduction circuit

[0086] 121b: Adder circuit

[0087] 121c: Divider circuit

[0088] 121d: Subtractor circuit

[0089] 122: Polyphase voltage regulator

[0090] 130: Compensation circuit

[0091] 140: Energy storage circuit

[0092] 150: Voltage divider circuit

[0093] 200: Voltage regulator circuit

[0094] 210: Current comparison circuit

[0095] 220: Delay circuit

[0096] 300: Voltage regulator circuit

[0097] 310: Current comparison circuit

[0098] 311: First current comparator

[0099] 312: Second current comparator

[0100] 320: Delay circuit

[0101] 321: First current source circuit

[0102] 322: Second current source circuit

[0103] 323: Inverter

[0104] 324: Hysteresis comparator

[0105] 400: Voltage regulator circuit

[0106] 410: Current comparison circuit

[0107] 411: First current comparator

[0108] 412: Second current comparator

[0109] 420: Delay circuit

[0110] 421: First current source circuit

[0111] 422: Second current source circuit

[0112] 423: Inverter

[0113] 424: Hysteresis comparator

[0114] C31: Delay capacitor

[0115] C41: Delay capacitor

[0116] Cout: Output capacitor

[0117] DC: Drive circuit

[0118] Iavg: Average current

[0119] Idiff1-Idiffn: Error current

[0120] Is1-Isn: Output current

[0121] Ib1-Ib2: Bias current

[0122] L1-Ln: Inductor

[0123] L31-L32: Variation curve

[0124] L41-L44: Variation curve

[0125] Lx1-Lxn: Voltage

[0126] N1-Nn: Phase node

[0127] NA: Control node

[0128] P1-P4: Time point

[0129] R1-R2: Voltage-dividing resistor

[0130] S1-S2: Error signal

[0131] S3-S4: Node signal

[0132] Spwm1-Spwmn: Control signal

[0133] Spwm-A: Waveform

[0134] Spwm-B: Waveform

[0135] Spwm-C: Waveform

[0136] Ta: Upper bridge switch

[0137] Tb: Lower bridge switch

[0138] Vramp: Ramp voltage

[0139] Vcomp: Compensation signal

[0140] Vfb: Feedback voltage

[0141] Vin: Input voltage

[0142] Vout: Output voltage

[0143] Vcc: Power supply

[0144] See: Response Voltage

[0145] VTH: Threshold Voltage

[0146] VTL: Threshold Voltage.

Claims

1. A multiphase voltage regulator, coupled to a multiphase DC-DC converter, characterized in that Comprising: A plurality of voltage regulator circuits, coupled between a power output stage circuit and a compensation circuit of the multi-phase DC-DC converter, for generating a plurality of control signals according to a compensation signal, so that the power output stage circuit generates a plurality of output currents; Wherein one of the plurality of voltage regulator circuits comprises: A current comparison circuit for obtaining an error signal, wherein the error signal is the difference between a threshold current and a corresponding one of the plurality of output currents; And A delay circuit, coupled to the compensation circuit and the current comparison circuit, for generating a corresponding one of the plurality of control signals according to the compensation signal, wherein the delay circuit is used to adjust a bias current in the delay circuit according to the error signal to adjust a duty cycle of a corresponding one of the plurality of control signals.

2. The polyphase voltage regulator according to claim 1, characterized in that, The delay circuit includes a first current source circuit to provide a first bias current, and the current comparison circuit includes: A first current comparator, a first terminal of the first current comparator is used to receive the threshold current, a second terminal of the first current comparator is used to receive the corresponding one of the plurality of output currents, and the first current comparator outputs a first error signal to the first current source circuit to change the first bias current.

3. The polyphase voltage regulator according to claim 2, wherein The delay circuit includes a second current source circuit to provide a second bias current, and the current comparison circuit includes: A second current comparator, a first terminal of the second current comparator is used to receive the corresponding one of the plurality of output currents, a second terminal of the second current comparator is used to receive the threshold current, and the second current comparator outputs a second error signal to the second current source circuit to change the second bias current.

4. The polyphase voltage regulator according to claim 3, characterized in that, The threshold current is an average current of the plurality of output currents.

5. The polyphase voltage regulator according to claim 4, characterized in that, The delay circuit further includes: An inverter, having an input terminal, an output terminal, a first correction terminal, and a second correction terminal, the input terminal of the inverter is coupled to an output terminal of the compensation circuit to receive the compensation signal, the first correction terminal of the inverter is used to receive the first bias current, the second correction terminal of the inverter is used to receive the second bias current, and the output terminal of the inverter is used to output a node signal, wherein the first bias current and the second bias current are used to adjust a phase of the node signal; And A delay capacitor, coupled between the output terminal of the inverter and a reference potential, wherein when the error signal is at a high level, the delay capacitor is used to delay a time when the node signal changes from a high logic level to a low logic level; When the error signal is at a low level, the delay capacitor is used to delay a time when the node signal changes from a low logic level to a high logic level.

6. The polyphase voltage regulator according to claim 5, wherein The delay circuit further includes: A hysteresis comparator, coupled to the output terminal of the inverter, for generating a corresponding one of the plurality of control signals according to the node signal.

7. The polyphase voltage regulator according to claim 4, characterized in that, The delay circuit further includes: An inverter, having an input terminal and an output terminal, the input terminal of the inverter is used to receive the compensation signal, and the output terminal of the inverter is used to output a node signal.

8. The polyphase voltage regulator according to claim 7, characterized in that, The delay circuit further includes: A hysteresis comparator coupled to the output terminal of the inverter. The hysteresis comparator has an input terminal, an output terminal, a first calibration terminal, and a second calibration terminal. The input terminal of the hysteresis comparator is coupled to the output terminal of the inverter to receive the node signal from the inverter; The first calibration terminal of the hysteresis comparator is used to receive the first bias current; The second calibration terminal of the hysteresis comparator is used to receive the second bias current, wherein the hysteresis comparator is used to generate a corresponding one of the plurality of control signals according to the node signal, the first bias current, and the second bias current.

9. The polyphase voltage regulator according to claim 8, wherein The first threshold voltage and the second threshold voltage of the hysteresis comparator change according to the first bias current and the second bias current. When the error signal is at a high level, the second threshold voltage will decrease to delay the time for the node signal to enter the low logic level from the high logic level; when the error signal is at a low level, the first threshold voltage will increase to delay the time for the node signal to enter the high logic level from the low logic level.

10. A polyphase current balancing circuit, applied to a polyphase DC-DC converter, characterized in that including: A current detection circuit coupled to the power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents and threshold currents; and A plurality of voltage regulator circuits coupled between the current detection circuit and the compensation circuit of the multi-phase DC-DC converter, and used to generate a plurality of control signals according to the compensation signal, so that the power output stage circuit generates the plurality of output currents; wherein one of the plurality of voltage regulator circuits includes: A current comparison circuit used to obtain an error signal, where the error signal is the difference between the threshold current and a corresponding one of the plurality of output currents; and A delay circuit coupled to the compensation circuit and the current comparison circuit, and used to generate a corresponding one of the plurality of control signals according to the compensation signal. The delay circuit is used to adjust the bias current in the delay circuit according to the error signal to adjust the duty cycle of a corresponding one of the plurality of control signals.

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