DC voltage converter and DC voltage controller

Abstract

A DC voltage controller includes a compensation circuit and a control circuit. The compensation circuit is coupled to the power output circuit of the DC voltage converter and is used for receiving the ramp signal, the voltage feedback signal and the driving feedback signal so as to generate a control compensation signal. The voltage feedback signal is generated according to the output voltage, and the drive feedback signal is associated with a phase node voltage in the power output circuit. The control circuit is used for comparing the voltage feedback signal and the control compensation signal to generate a comparison signal. The control circuit is also used for outputting a pulse width modulation signal to the power output circuit according to the comparison signal and the clock pulse signal. The pulse width modulation signal has a duty cycle, and the control circuit is also used for setting the duty cycle according to the comparison signal and resetting the duty cycle according to the clock signal. Therefore, the DC voltage converter can adjust the work period of the pulse width modulation signal according to the load condition so as to improve the power supply stability.

Description

Technical Field

[0001] The present disclosure relates to power control, and particularly to a DC voltage converter and a DC voltage controller. Background Art

[0002] A DC-to-DC converter is an electromechanical device for power conversion, which is used to convert the voltage of a DC power supply. The DC-to-DC converter has a wide range of applications and can be used to supply power to small-power devices (such as batteries) or large-power devices (such as industrial machines). Since the power required by the load to which the DC-to-DC converter is applied may vary at any time according to different operating states, the power supply stability of the DC-to-DC converter is very important. Summary of the Invention

[0003] The present disclosure relates to a DC voltage controller applied to a DC voltage converter. The DC voltage converter includes a DC voltage controller, a power output circuit, and an energy storage circuit. The power output circuit is coupled between the DC voltage controller and the energy storage circuit and is used to convert the input voltage into an output voltage. The DC voltage controller includes a compensation circuit and a control circuit. The compensation circuit is coupled to the power output circuit and is used to receive a ramp signal, a voltage feedback signal, and a drive feedback signal of the power output circuit to generate a compensation signal. The voltage feedback signal is generated according to the output voltage, and the drive feedback signal is related to the phase node voltage of the phase node in the power output circuit. The control circuit is coupled between the compensation circuit and the power output circuit and is used to compare the voltage feedback signal and control the compensation signal to generate a comparison signal. The control circuit is further used to output a pulse width modulation signal to a drive circuit according to the comparison signal and a clock signal. The pulse width modulation signal has a duty cycle. The control circuit is further used to set the duty cycle according to the comparison signal and reset the duty cycle according to the clock signal.

[0004] In an embodiment, the compensation circuit further generates a control compensation signal according to an error signal, and the error signal is generated according to the voltage feedback signal.

[0005] In an embodiment, the compensation circuit includes an error detection circuit and an arithmetic circuit. The error detection circuit is used to generate an error signal according to the voltage feedback signal and a voltage reference signal. The arithmetic circuit is coupled to the error detection circuit and is used to generate a control compensation signal according to the error signal, the ramp signal, and the drive feedback signal.

[0006] In an embodiment, the power output circuit includes a drive circuit, an upper bridge switch, and a lower bridge switch. The energy storage circuit includes an inductor. The upper bridge switch and the lower bridge switch are coupled to the control circuit, the phase node is coupled between the upper bridge switch and the lower bridge switch, and one end of the inductor is coupled to the phase node. The power output circuit is used to alternately turn on the upper bridge switch and the lower bridge switch to output an output voltage at the other end of the inductor.

[0007] In one embodiment, the DC voltage controller further includes a feedback circuit. The feedback circuit is coupled between the phase node of the power output circuit and the compensation circuit, and is used to generate a drive current signal according to the phase node voltage as a drive feedback signal.

[0008] In one embodiment, the feedback circuit includes a comparison circuit and a transduction amplification circuit. The comparison circuit generates a drive voltage signal according to the phase node voltage and the ground voltage. The transduction amplification circuit is coupled to the comparison circuit and is used to generate a drive current signal according to the drive voltage signal.

[0009] In one embodiment, the feedback circuit includes a filter circuit and a comparison circuit. The filter circuit is used to generate a plurality of filtered signals according to the phase node voltage. The comparison circuit is coupled to the filter circuit and is used to generate a drive voltage signal according to the plurality of filtered signals. The drive voltage signal is used to generate a drive feedback signal.

[0010] In one embodiment, the filter circuit is a second-order filter, which is used to generate a first-order filtered signal and a second-order filtered signal according to the phase node voltage. The comparison circuit is used to compare the first-order filtered signal and the second-order filtered signal to generate a drive voltage signal.

[0011] In one embodiment, the control circuit includes a signal comparator and a signal register. The signal comparator has a first input terminal and a second input terminal. The first input terminal is used to receive a control compensation signal, and the second input terminal is used to receive a voltage feedback signal to generate a comparison signal. The signal register is coupled to the signal comparator and the power output circuit, and is used to receive the comparison signal to output a pulse width modulation signal.

[0012] The present disclosure also relates to a DC voltage converter, which includes a power output circuit, an energy storage circuit, a compensation circuit, and a control circuit. The power output circuit includes an upper bridge switch, a lower bridge switch, and a drive circuit, and is used to convert an input voltage into an output voltage. The energy storage circuit is coupled to the power output circuit and is used to receive the output voltage. The compensation circuit is coupled to the power output circuit and is used to receive a ramp signal, a voltage feedback signal, and a drive feedback signal of the power output circuit to generate a control compensation signal. The voltage feedback signal is generated according to the output voltage, and the drive feedback signal is related to the phase node voltage of the phase node in the power output circuit. The control circuit is coupled between the compensation circuit and the power output circuit, and is used to compare the voltage feedback signal and the control compensation signal to generate a comparison signal. The control circuit is also used to output a pulse width modulation signal to the drive circuit according to the comparison signal and a clock signal. The pulse width modulation signal has a duty cycle, and the control circuit is also used to set the duty cycle according to the comparison signal and reset the duty cycle according to the clock signal.

[0013] Accordingly, by using the "driving feedback signal associated with the phase node voltage" as the control compensation signal and generating the control compensation signal in a negative feedback manner, the DC voltage converter can adjust the duty cycle of the pulse width modulation signal according to the load condition to improve the power supply stability. At the same time, the application bandwidth and transient response of the DC voltage converter can also be improved accordingly. Description of the Drawings

[0014] Figure 1A FIG. is a schematic diagram of a DC voltage converter according to an embodiment of the present disclosure.

[0015] Figure 1B FIG. is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure.

[0016] Figure 1C FIG. is a schematic diagram of a feedback circuit and a compensation circuit according to an embodiment of the present disclosure.

[0017] Figure 2A FIG. is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure.

[0018] Figure 2B FIG. is a schematic diagram of a DC voltage converter according to another embodiment of the present disclosure.

[0019] Figure 2C FIG. is a schematic diagram of a feedback circuit and a compensation circuit according to another embodiment of the present disclosure.

[0020] Figures 3A to 3C FIG. is a signal change diagram of the DC voltage converter in different states according to some embodiments of the present disclosure. Detailed Embodiments

[0021] Hereinafter, multiple embodiments of the present invention will be disclosed with reference to the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0022] In this document, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this document to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless the context clearly indicates, these terms do not specifically refer to or imply an order or sequence, nor are they used to limit the present invention.

[0023] Figure 1A Schematic diagram of a DC voltage converter 100 according to an embodiment of the present disclosure. The DC voltage converter 100 includes a power output circuit 110, a DC voltage controller 200, and an energy storage circuit LC. Among them, the power output circuit 110 further includes a drive circuit 111 and a switching circuit 112, and the DC voltage controller 200 further includes a compensation circuit 120 and a control circuit 130. The switching circuit 112 is used to receive the input voltage Vin and receive a control signal through the drive circuit 111. In addition, the energy storage circuit LC includes an inductor L1 and a capacitor C1.

[0024] The power output circuit 110 is coupled between the DC voltage controller 200 and the energy storage circuit LC, and is used to selectively (e.g., alternately) turn on or off the upper bridge switch T1 and the lower bridge switch T2 according to the control signal, so as to convert the input voltage Vin into the output voltage Vout and output the output voltage Vout to the energy storage circuit LC. At the same time, the power output circuit 110 also generates a voltage feedback signal Vfb through a plurality of resistors R1 and R2. In one embodiment, the voltage feedback signal Vfb can be a voltage division of the output voltage Vout.

[0025] In one embodiment, there is a phase voltage node between the upper bridge switch T1 and the lower bridge switch T2 (such as Figure 1A the phase node N shown). One end of the inductor L1 is coupled to the phase node N, and the other end is used to generate the output voltage Vout through the output capacitor C1. Since those skilled in the art can understand the operation mode of the power output circuit 110, it will not be described in detail here. In addition, in one embodiment, the DC voltage converter 100 can be applied as one of the conversion circuits in a multi-phase DC voltage converter to output single-phase current.

[0026] Referring to Figure 1A , the compensation circuit 120 generates a drive feedback signal Isen according to the lower bridge current IML (i.e., the current flowing through the lower bridge switch T2). The drive feedback signal Isen is related to the phase node voltage Vx of the phase node N. In this embodiment, the drive feedback signal Isen is a drive current signal generated according to the lower bridge current IML (for example, the current flowing through the lower bridge switch T2) to provide lower bridge current information.

[0027] The compensation circuit 120 is coupled to the power output circuit 110, and is used to receive the ramp signal Vramp, the voltage feedback signal Vfb, and the drive feedback signal Isen, and generate a control compensation signal Vcomps according to the ramp signal Vramp and the drive feedback signal Isen.

[0028] In one embodiment, the compensation circuit 120 includes an error detection circuit 121 and an arithmetic circuit 122. The error detection circuit 121 is coupled to the power output circuit 110, and its input terminal is used to receive a voltage reference signal Vref (such as a fixed bias signal) and a voltage feedback signal Vfb to generate an error signal Vcomp. The error signal Vcomp is generated based on the voltage feedback signal Vfb and the voltage reference signal Vref, so that the compensation circuit 120 generates a control compensation signal Vcomps. In one embodiment, the error detection circuit 121 includes a comparator for generating an error signal Vcomp according to the difference between the voltage reference signal Vref and the voltage feedback signal Vfb.

[0029] The arithmetic circuit 122 is coupled between the error detection circuit 121 and the control circuit 130 to receive the error signal Vcomp, the ramp signal Vramp, and the drive feedback signal Isen respectively. The arithmetic circuit 122 is used to generate a control compensation signal Vcomps according to the error signal Vcomp, the ramp signal Vramp, and the drive feedback signal Isen. The ramp signal Vramp can be a sawtooth wave with a fixed slope. A "sawtooth wave" means that in each signal cycle, it will start to change from a fixed level (such as rising or falling), and when the current signal cycle ends and enters the next signal cycle, it will return to the initial fixed level. In some embodiments, the signal slope of the ramp signal Vramp is positive, that is, in the signal cycle, the level of the ramp signal Vramp gradually rises. However, the present disclosure is not limited thereto. In other embodiments, depending on the slope, the ramp signal Vramp can also be a triangular wave.

[0030] In one embodiment, the drive feedback signal Isen is fed back to the arithmetic circuit 122, and the control compensation signal Vcomps is the error signal Vcomp plus the ramp signal Vramp minus the drive feedback signal Isen.

[0031] The control circuit 130 is coupled between the compensation circuit 120 (arithmetic circuit 122) and the power output circuit 110, and is used to compare the voltage feedback signal Vfb and the control compensation signal Vcomps to generate a comparison signal Va. The control circuit 130 is also used to generate a pulse width modulation signal Vdt according to the comparison signal Va and the clock signal CLK, and output the pulse width modulation signal Vdt to the drive circuit 111. The drive circuit 111 will generate a corresponding control signal according to the duty ratio of the pulse width modulation signal Vdt to selectively turn on or off the upper bridge switch T1 and the lower bridge switch T2. The drive feedback signal Isen can be regarded as a half-cycle current signal, and its waveform is as Figure 1AThe half-cycle signal shown, for example, in the positive half-cycle of the pulse-width modulation signal Vdt, the upper-bridge switch T1 is turned on and the lower-bridge switch T2 is turned off. At this time, the input voltage Vin charges the capacitor C1, and the current flows from the phase node N to the capacitor C1. At this time, the drive feedback signal Isen is zero; in the negative half-cycle of the pulse-width modulation signal Vdt, the upper-bridge switch T1 is turned off and the lower-bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower-bridge switch T2. According to the characteristic of inductor volt-second balance, when the input voltage Vin no longer charges the inductor L1 and the capacitor C1 through the upper-bridge switch T1, the inductor L1 tends to maintain the original current direction for output to continue providing the inductor current. At this time, the direction of the current of the lower-bridge switch T2 (i.e., the lower-bridge current IML) will be from the ground terminal to the phase node N. When the current flowing through the lower-bridge switch T2 is larger, the drive feedback signal Isen will be larger.

[0032] The control circuit 130 is used to set the working cycle of the pulse-width modulation signal Vdt (i.e., switch to the enabling level) according to the comparison signal Va, and reset the working cycle of the pulse-width modulation signal Vdt (i.e., switch to the disabling level) according to the clock signal CLK. In an embodiment, the control circuit 130 uses the "leading-edge" of each pulse of the clock signal CLK as a judgment condition to generate the pulse-width modulation signal Vdt. When the comparison signal Va changes (i.e., the voltage feedback signal Vfb and the control compensation signal Vcomps cross each other), the control circuit 130 sets the pulse-width modulation signal Vdt to the enabling level; when the clock cycle of the clock signal CLK is generated, the pulse-width modulation signal Vdt is reset to the disabling level.

[0033] In an embodiment, the control circuit 130 includes a signal comparator 131 and a signal register 132. The signal comparator 131 has a first input terminal (e.g., the positive terminal) and a second input terminal (e.g., the negative terminal). The first input terminal is used to receive the control compensation signal Vcomps, and the second input terminal is used to receive the voltage feedback signal Vfb. The comparison signal Va is generated according to the difference between the control compensation signal Vcomps and the voltage feedback signal Vfb. The signal register 132 is coupled between the signal comparator 131 and the power output circuit 110. Its input terminal is used to receive the comparison signal Va, and it can output the pulse-width modulation signal Vdt according to the clock signal CLK. In an embodiment, the signal register 132 can be a type of SR flip-flop, and the S terminal is used to receive the comparison signal Va.

[0034] The present disclosure uses the drive feedback signal Isen associated with the phase node N in the power output circuit 110 as a control compensation signal to generate the control compensation signal Vcomps in a negative feedback manner (i.e., subtraction). Accordingly, the DC voltage converter 100 / DC voltage controller 200 can adjust the duty cycle of the pulse width modulation signal Vdt in advance according to the load condition to instantaneously provide electric energy corresponding to the load condition, improving the power supply stability of the DC voltage converter 100. In addition, using the drive feedback signal Isen for control compensation can increase the application bandwidth of the DC voltage converter 100 and improve the transient response of the signal.

[0035] For example, when the DC voltage converter 100 is in heavy load (i.e., the load at the output end requires more power), the duty cycle of the pulse width modulation signal Vdt should be increased accordingly to increase the output current of the DC voltage converter 100. In this regard, the present disclosure can instantaneously reflect the current load condition of the DC voltage converter 100 by using the drive feedback signal Isen associated with the phase node N and providing the drive feedback signal Isen to the input terminal of the signal comparator 131 to adjust the pulse width modulation signal Vdt, so as to provide better transient response and accuracy of the output.

[0036] Please refer to Figure 1B , Figure 1B To correspond to Figure 1A a schematic diagram of a variant of the DC voltage converter 100. As Figure 1B shown, the DC voltage converter 100' further includes a feedback circuit 140, and the power output circuit 110 generates the drive feedback signal Isen through the feedback circuit 140. The feedback circuit 140 is coupled between the phase node N of the power output circuit 110 and the compensation circuit 120, and is used to generate a drive current signal according to the phase node voltage Vx of the phase node N as the drive feedback signal Isen. The input and output of the feedback circuit 140 can be in the form of voltage-to-current conversion, current-to-current conversion, or current-to-voltage conversion, and are used to generate the control compensation signal Vcomps in cooperation with other signals in Figure 1B and, similar elements related to the embodiment in Figure 1A are denoted by the same reference numerals for easy understanding, and the specific principles of the similar elements have been described in detail in the previous paragraphs. Unless it is necessary to introduce due to the cooperative operation relationship between the elements in Figure 1B , they will not be elaborated here.

[0037] Figure 1C A schematic diagram of the feedback circuit 300 and the compensation circuit 120A according to an embodiment of the present disclosure, where the feedback circuit 300 can be Figure 1B a example of the feedback circuit 140 inFigure 1B An example of the middle compensation circuit 120. As Figure 1C shown, the compensation circuit 120A includes an error detection circuit 121 and an arithmetic circuit 122, and the error detection circuit 121 provides an error signal Vcomp to the arithmetic circuit 122 through a buffer 121a. The buffer 121a includes an operational amplifier connected in negative feedback to generate an essentially identical error signal Vcomp based on the error signal Vcomp1 output by the error detection circuit 121, such that the error signal Vcomp1 is not affected by the drive feedback signal Isen, achieving the effect of signal isolation. In addition, the error signal Vcomp generates a current I31 through a resistor 122b, a current I32 generated by the ramp signal Vramp passing through a transduction amplifier 122c, and the drive feedback signal Isen are added in an accumulator 122a to generate a control compensation signal Vcomps, where the transduction amplifier 122c is coupled to the voltage VCC.

[0038] In addition, the compensation circuit 120A also obtains a ramp signal Vramp through a signal generation circuit 150. The signal generation circuit 150 includes a current source 151, a capacitor 152, and a switch 153 for generating a ramp signal Vramp according to a clock signal CLK, where the current source 151 is coupled to the voltage VCC. Specifically, the signal generation circuit 150 controls the on and off of the switch 153 according to the clock signal CLK to control the charging time of the capacitor 152 by the current source 151.

[0039] Specifically, in the positive half cycle, the clock signal CLK turns off the switch 153. At this time, the current source 151 charges the capacitor 152, and the voltage of the node 154 to which the capacitor 152 is coupled rises, and the slope of the ramp signal Vramp is positive; in the negative half cycle, the clock signal CLK turns on the switch, and at this time, the capacitor 152 discharges to the ground terminal, and the voltage of the node 154 to which the capacitor 152 is coupled drops, and the slope of the ramp signal Vramp is negative. Since those skilled in the art can understand various ways or methods of generating the ramp signal Vramp, it will not be elaborated here, and the signal generation circuit 150 of the present disclosure is not limited to Figure 1C what is shown.

[0040] In this embodiment, the feedback circuit 300 is a transduction amplification circuit and includes a comparison circuit 310 and a current source 320, where the current source is coupled to the voltage VCC. The comparison circuit 310 generates a drive voltage signal according to the difference between the phase node voltage Vx and the ground voltage Vg, and this drive voltage signal equivalently provides information about the lower bridge current. The current source 320 is coupled to the comparison circuit 310 to generate a drive current signal according to the received drive voltage signal, and the generated drive current signal will be used as the drive feedback signal Isen.

[0041] Please refer toFigure 1B and Figure 1C As shown, in one embodiment, the feedback circuit 140 / 300 is coupled to the phase node N, and processes (e.g., subtracts) the phase node voltage Vx and the ground voltage Vg to simulate the lower bridge current information. Therefore, the generated drive feedback signal Isen has the lower bridge current information. Thus, the drive feedback signal Isen generated by the feedback circuit 140 corresponds to the current of the lower bridge switch T2 (i.e., a half-cycle signal of the output current of the DC voltage converter 100'). Similarly, the drive feedback signal Isen can be regarded as a kind of half-cycle current signal, and its waveform is as shown in Figure 1B or Figure 1C shown.

[0042] For example, in the positive half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned on and the lower bridge switch T2 is turned off. At this time, the input voltage Vin charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, and the phase node voltage Vx is not zero. The pulse output by the comparison circuit 310 is serrated.

[0043] On the other hand, in the negative half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned off and the lower bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower bridge switch T2. According to the characteristic of inductor volt-second balance, when the input voltage Vin no longer charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, the current direction of the inductor L1 tends to maintain the original current direction to continue to provide the inductor current. At this time, the current direction of the lower bridge switch T2 will be from the ground terminal to the phase node N. Therefore, the phase node voltage Vx will be negative. As shown in Figure 1C shown, the change in the voltage level of the phase node voltage Vx will affect the output of the comparison circuit 310, and further adjust the current magnitude of the current source 320. For example: when the current flowing through the lower bridge switch T2 is large, at this time the phase node voltage Vx is lower than the ground voltage Vg and becomes more negative, making the voltage level change between the phase node voltage Vx and the ground voltage Vg larger. Therefore, the drive feedback signal Isen generated by the current source 320 is larger. That is, the difference between the "phase node voltage Vx and the ground voltage Vg" detected by the comparison circuit 310 can be used to adjust the magnitude of the drive feedback signal Isen generated by the current source 320.

[0044] Figure 2A Schematic diagram of a DC voltage converter 400 according to another embodiment of the present disclosure. In Figure 2A , similar elements related to the embodiment of Figure 1A are denoted by the same reference numerals for easy understanding, and the specific principles of the similar elements have been described in detail in the previous paragraphs and will not be repeated here. Figure 2A The DC voltage converter 400 of Figure 1AThe difference between the DC voltage converter 100 is that the compensation circuit 120 generates the drive feedback signal Isen based on the inductor current information (i.e., the current flowing through the inductor L1), rather than based on the lower bridge current information. Accordingly, the DC voltage converter 400 will be able to adjust the duty cycle of the pulse width modulation signal Vdt in advance according to the load condition, so as to improve the power supply stability of the DC voltage converter 100 and improve the transient response of the signal.

[0045] Please refer to Figure 2B , Figure 2B For corresponding Figure 2A A schematic diagram of a variation of the DC voltage converter 400. In Figure 2B , the similar elements related to the Figure 2A embodiment are denoted by the same reference numerals for easy understanding, and the specific principles of the similar elements have been described in detail in the previous paragraphs. If there is no need to introduce the elements that do not have a cooperative operation relationship with the Figure 2B elements, they will not be elaborated here. As Figure 2B shown, the DC voltage converter 400' further includes a feedback circuit 440, and the power output circuit 110 generates the drive feedback signal Isen through the feedback circuit 440. The feedback circuit 440 is coupled between the power output circuit 110 and the compensation circuit 120, and is used to generate a drive current signal according to the phase node voltage Vx of the phase node N as the drive feedback signal Isen.

[0046] As Figure 1A , Figure 1B , Figure 2A and Figure 2B shown, in the circuit architecture of the present disclosure, the positive terminal of the signal comparator 131 is used to receive the control compensation signal Vcomps, and the control compensation signal Vcomps is based on the "error signal Vcomp and the ramp signal Vramp", and at the same time further introduces the "current information of the power output circuit 110 (such as: lower bridge current, inductor current)" as control compensation. The negative terminal of the signal comparator 131 receives the voltage feedback signal Vfb. The signal comparator 131 adjusts the duty cycle of the pulse width modulation signal in real time by comparing the signals received at the positive and negative terminals. Accordingly, the DC voltage converter will be able to have a faster transient response and at the same time improve the control stability. The present disclosure provides a novel circuit architecture for the DC voltage converter, which is faster in control compared with the fixed frequency control technology or the constant on time technology. When the control compensation signal Vcomps rapidly pulls up and the voltage feedback signal Vfb drops, due to the fast transient response, the signal intersection of the control compensation signal Vcomps and the voltage feedback signal Vfb will be significantly advanced to achieve the effect of generating the duty cycle earlier.

[0047] In addition, when the output current of the DC voltage converter is too large, the control compensation signal Vcomps will decrease accordingly, and the present disclosure can also immediately shorten the duty cycle. By appropriately adjusting the transconductance amplification factor of the lower bridge circuit, it can be ensured that the capacitor C1 in the energy storage circuit LC will not be overcharged, thereby improving system stability.

[0048] Figure 2C FIG. 440 is a schematic diagram of the feedback circuit 440 and the compensation circuit 120B according to another embodiment of the present disclosure. The compensation circuit 120B can be the same as Figure 1C the compensation circuit 120A. As Figure 2C shown, in this embodiment, the feedback circuit 440 includes a scaling circuit 401, a filtering circuit 402, a comparison circuit 403, and a current source 404. The comparison circuit 403 and the current source 404 can be regarded as a transconductance amplification circuit together, and the current source 404 is coupled to the voltage VCC. The scaling circuit 401 is coupled to the phase node N of the power output circuit 110 to receive the phase node voltage Vx. In one embodiment, the scaling circuit 401 (scale circuit) is used to step down the phase node voltage Vx and input the adjusted phase node voltage Vx to the filtering circuit 402. In some embodiments, the scaling circuit 401 can be omitted.

[0049] The filtering circuit 402 is coupled to the scaling circuit 401 and is used to generate a plurality of filtered signals according to the adjusted phase node voltage Vx. As Figure 2C shown, in one embodiment, the filtering circuit 402 is a second-order filter and is used to generate a first-order filtered signal V01 and a second-order filtered signal V02 according to the phase node voltage Vx. After filtering, the first-order filtered signal V01 includes the DC signal component and the AC signal component in the phase node voltage Vx, and the second-order filtered signal V02 only includes the DC signal component of the phase node voltage Vx.

[0050] The comparison circuit 403 is coupled to the filtering circuit 402 and is used to generate a driving voltage signal according to the filtered signal, and the driving voltage signal is used to generate a driving feedback signal Isen. For example, the positive input terminal of the comparison circuit 403 is used to receive the first-order filtered signal V01, and the negative input terminal of the comparison circuit 403 is used to receive the second-order filtered signal V02. By comparing the first-order filtered signal V01 and the second-order filtered signal V02, a driving voltage signal is generated. The comparison circuit 403 subtracts the second-order filtered signal V02 from the first-order filtered signal V01 to output the full-cycle current information of the inductor current. The full-cycle current information includes the current information of the upper bridge switch T1 in the positive half cycle and the current information of the lower bridge switch T2 in the negative half cycle.

[0051] The current source 404 is coupled to the comparison circuit 403 and 120B to generate a drive current signal according to the received drive voltage signal, and the generated drive current signal will be used as the drive feedback signal Isen. The drive feedback signal Isen will approximate the AC signal of the current of the inductor L1 (e.g., the slope of the signal is approximate or the same).

[0052] For example, in the positive half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned on and the lower bridge switch T2 is turned off. At this time, the input voltage Vin charges the inductor L1 and the capacitor C1 through the upper bridge switch T1, and the phase node voltage Vx is not zero. The pulse output by the comparison circuit 403 is serrated.

[0053] On the other hand, in the negative half-cycle of the pulse width modulation signal Vdt, the upper bridge switch T1 is turned off and the lower bridge switch T2 is turned on. At this time, the energy stored in the inductor L1 is released through the lower bridge switch T2. According to the characteristic of the inductor volt-second balance described above, the current direction of the lower bridge switch T2 will be from the ground terminal to the phase node N at this time. Therefore, the phase node voltage Vx will be negative. Figure 2C As shown, the change in the voltage level of the phase node voltage Vx will change the output of the comparison circuit 403, thereby adjusting the drive current signal output by the current source 404.

[0054] As in the foregoing embodiment, the DC voltage converters 100 / 100' / 400 / 400' and the DC voltage controller 200 are based on the error signal Vcomp between the voltage reference signal Vref and the voltage feedback signal Vfb, combined with a ramp signal Vramp (e.g., a full-cycle sawtooth wave), and then combined with the negative feedback drive feedback signal Isen to generate a control compensation signal Vcomps (e.g., a full-cycle signal or a half-cycle signal of the output current of the DC voltage converter). Accordingly, the bandwidth and transient response of the DC voltage converter 100 can be improved, and the output capacitor C1 will not be overcharged, realizing advantages such as stable power supply, fixed-frequency control, and fast response.

[0055] Please refer to Figure 1A and Figure 3A , Figure 3A Shown is a schematic diagram of the transient response of the signals of the DC voltage converter 100 in some embodiments of the present disclosure when the load increases gradually. From top to bottom are the waveform diagrams of the current IL (the current flowing through the inductor L1), the waveform diagrams of the control compensation signal Vcomps / error signal Vcomp / voltage feedback signal Vfb, the waveform diagram of the pulse width modulation signal Vdt, and the waveform diagram of the lower bridge current IML (i.e., the detected current flowing through the lower bridge switch T2).

[0056] During the process that the load condition of the DC voltage converter 100 gradually changes from light load to heavy load, as the current IL (inductor current) rises, the error signal Vcomp and the control compensation signal Vcomps will gradually increase. Whenever the control compensation signal Vcomps is greater than the voltage feedback signal Vfb (indicating insufficient load and the upper bridge switch T1 needs to be turned on for a longer time), the pulse width modulation signal Vdt will immediately respond and output a high level, providing an immediate transient response. If only relying on the comparison between the error signal Vcomp and the voltage feedback signal Vfb to achieve the transient response, as can be seen from Figure 3A the error signal Vcomp exceeds the voltage feedback signal Vfb only at the time point P1, that is, the pulse width modulation signal Vdt will output a high level only at the time point P1, so it has a relatively poor transient response.

[0057] Please also refer to Figure 1A and Figure 3B , Figure 3B FIG. shows a schematic diagram of the transient response of the signals of the DC voltage converter 100 in some embodiments of the present disclosure when the load rapidly increases to heavy load. From top to bottom, they are the waveform diagram of the current IL (the current flowing through the inductor L1), the waveform diagrams of the control compensation signal Vcomps / error signal Vcomp / voltage feedback signal Vfb, the waveform diagram of the pulse width modulation signal Vdt, and the waveform diagram of the lower bridge current IML (that is, the detected current flowing through the lower bridge switch T2).

[0058] During the process that the load condition of the DC voltage converter 100 rapidly changes from light load to heavy load, as the current IL (inductor current) rises, the error signal Vcomp and the control compensation signal Vcomps will gradually increase. Whenever the control compensation signal Vcomps is greater than the voltage feedback signal Vfb (indicating insufficient load and the upper bridge switch T1 needs to be turned on for a longer time), the pulse width modulation signal Vdt will immediately respond and output a high level, providing an immediate transient response. In addition, by quickly pulling down the control compensation signal Vcomps in each cycle, the minimum off time of the upper bridge switch T1 can be achieved when the circuit is in heavy load (such as from time point P2 to time point P3). In addition, when the circuit changes to light load at time point P3, the control compensation signal Vcomps will quickly pull down to be less than the voltage feedback signal Vfb, making the pulse width modulation signal Vdt immediately present a low level. According to the above comparison, compared with the method of only relying on the error signal Vcomp and the voltage feedback signal Vfb for control compensation, the solution of the present disclosure obviously has a better transient response.

[0059] Please also refer to Figure 1A and Figure 3C , Figure 3CThe figure shows a schematic diagram of the transient response of signal fast unloading of the DC voltage converter 100 in some embodiments of the present disclosure. From top to bottom, they are the waveform diagram of the current IL (the current flowing through the inductor L1), the waveform diagram of the control compensation signal Vcomps / error signal Vcomp / voltage feedback signal Vfb, the waveform diagram of the pulse width modulation signal Vdt, and the waveform diagram of the lower bridge current IML (that is, the detected current flowing through the lower bridge switch T2). During the rapid unloading of the load condition of the DC voltage converter 100, the solution of the present disclosure can pull down the control compensation signal Vcomps below the voltage feedback signal Vfb at time point P4, and the pulse width modulation signal Vdt will immediately respond and output a low level, providing an immediate transient response. Now, if only relying on the comparison of the error signal Vcomp and the voltage feedback signal Vfb, the pulse width modulation signal Vdt must wait until time point P5 to output a low level. From the above, it can be seen that the technical solution of the present disclosure obviously has a better transient response.

[0060] For the various elements, method steps or technical features in the foregoing embodiments, they can be combined with each other, and are not limited by the order of text description or the order of presentation in the drawings in the present disclosure.

[0061] Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to that defined by the appended claims.

[0062]

Symbol Description

[0063] 100: DC voltage converter

[0064] 100’: DC voltage converter

[0065] 110: Power output circuit

[0066] 111: Driver circuit

[0067] 112: Switching circuit

[0068] 120: Compensation circuit

[0069] 120A: Compensation circuit

[0070] 120B: Compensation circuit

[0071] 121: Error detection circuit

[0072] 121a: Buffer

[0073] 122: Operational circuit

[0074] 122a: Accumulator

[0075] 122b: Resistance

[0076] 122c: Transduction amplifier

[0077] 130: Control circuit

[0078] 131: Signal comparator

[0079] 132: Signal register

[0080] 140: Feedback circuit

[0081] 150: Signal generation circuit

[0082] 151: Current source

[0083] 152: Capacitor

[0084] 153: Switch

[0085] 154: Node

[0086] 200: DC voltage controller

[0087] 300: Feedback circuit

[0088] 310: Comparison circuit

[0089] 320: Current source

[0090] 400: DC voltage converter

[0091] 400’: DC voltage converter

[0092] 440: Feedback circuit

[0093] 401: Multiplication circuit

[0094] 402: Filter circuit

[0095] 403: Comparison circuit

[0096] 404: Current source

[0097] C1: Capacitor

[0098] CLK: Clock signal

[0099] I31: Current

[0100] I32: Current

[0101] Isen: Drive feedback signal

[0102] IL: Current

[0103] IML: Lower bridge current

[0104] LC: Energy storage circuit

[0105] L1: Inductor

[0106] N: Phase node

[0107] P1 - P5: Time points

[0108] R1: Resistor

[0109] R2: Resistor

[0110] T1: Upper - bridge switch

[0111] T2: Lower - bridge switch

[0112] V01: First - order filtered signal

[0113] V02: Second - order filtered signal

[0114] Va: Comparison signal

[0115] VCC: Voltage

[0116] Vcomp: Error signal

[0117] Vcomp1: Error signal

[0118] Vcomps: Control compensation signal

[0119] Vdt: Pulse - width modulation signal

[0120] Vfb: Voltage feedback signal

[0121] Vg: Ground voltage

[0122] Vin: Input voltage

[0123] Vn: Reference voltage

[0124] Vout: Output voltage

[0125] Vramp: Ramp signal

[0126] Vref: Voltage reference signal

[0127] Vx: Phase - node voltage.

Claims

1. A DC voltage controller is applied to a DC voltage converter. The DC voltage converter includes the DC voltage controller, a power output circuit, and an energy storage circuit. The power output circuit is coupled between the DC voltage controller and the energy storage circuit and is used to convert an input voltage into an output voltage. It is characterized in that, The DC voltage controller includes: A compensation circuit, coupled to the power output circuit, and configured to receive a ramp signal, a voltage feedback signal, and a drive feedback signal of the power output circuit to generate a control compensation signal, wherein the voltage feedback signal is generated according to the output voltage, and the drive feedback signal is related to the phase node voltage of the phase node in the power output circuit; And A control circuit, coupled between the compensation circuit and the power output circuit, configured to compare the voltage feedback signal and the control compensation signal to generate a comparison signal, wherein the control circuit is further configured to output a pulse width modulation signal to the power output circuit according to the comparison signal and a clock signal; Wherein the pulse width modulation signal has a duty cycle, the control circuit is further configured to set the duty cycle according to the comparison signal, and reset the duty cycle according to the clock signal.

2. The DC voltage controller according to claim 1, characterized in that The compensation circuit further generates the control compensation signal according to an error signal, and the error signal is generated according to the voltage feedback signal.

3. The DC voltage controller according to claim 2, characterized in that, The compensation circuit includes: An error detection circuit, configured to generate the error signal according to the voltage feedback signal and a voltage reference signal; And An arithmetic circuit, coupled to the error detection circuit, configured to generate the control compensation signal according to the error signal, the ramp signal, and the drive feedback signal.

4. The DC voltage controller according to claim 1, characterized in that, The power output circuit includes a drive circuit, an upper bridge switch, and a lower bridge switch, the energy storage circuit includes an inductor, the upper bridge switch and the lower bridge switch are coupled to the control circuit, the phase node is coupled between the upper bridge switch and the lower bridge switch, one end of the inductor is coupled to the phase node, and the power output circuit is configured to alternately turn on the upper bridge switch and the lower bridge switch to output the output voltage at the other end of the inductor.

5. The DC voltage controller according to claim 4, characterized in that, Further includes: A feedback circuit, coupled between the phase node of the power output circuit and the compensation circuit, configured to generate a drive current signal according to the phase node voltage as the drive feedback signal.

6. The DC voltage controller according to claim 5, wherein The feedback circuit includes: A comparison circuit, generating a drive voltage signal according to the phase node voltage and a ground voltage; And A transduction amplification circuit, coupled to the comparison circuit, configured to generate the drive current signal according to the drive voltage signal.

7. The DC voltage controller according to claim 5, characterized in that, The feedback circuit includes: A filtering circuit, configured to generate a plurality of filtered signals according to the phase node voltage; and A comparison circuit, coupled to the filtering circuit, configured to generate a drive voltage signal according to the plurality of filtered signals, wherein the drive voltage signal is used to generate the drive feedback signal.

8. The DC voltage controller according to claim 7, characterized in that, The filtering circuit is a second-order filter, configured to generate a first-order filtered signal and a second-order filtered signal according to the phase node voltage, and the comparison circuit is configured to compare the first-order filtered signal and the second-order filtered signal to generate the drive voltage signal.

9. The DC voltage controller according to claim 1, characterized in that, The control circuit includes: A signal comparator, having a first input terminal and a second input terminal, wherein the first input terminal is configured to receive the control compensation signal, and the second input terminal is configured to receive the voltage feedback signal to generate the comparison signal; And A signal register, coupled to the signal comparator and the power output circuit, configured to receive the comparison signal to output the pulse width modulation signal.

10. A DC voltage converter, characterized in that, Includes: A power output circuit, including an upper bridge switch, a lower bridge switch, and a driving circuit, for converting an input voltage into an output voltage; An energy storage circuit, coupled to the power output circuit, for receiving the output voltage; A compensation circuit, coupled to the power output circuit, for receiving a ramp signal, a voltage feedback signal, and a driving feedback signal of the power output circuit to generate a control compensation signal, wherein the voltage feedback signal is generated according to the output voltage, and the driving feedback signal is related to the phase node voltage of the phase node in the power output circuit; And A control circuit, coupled between the compensation circuit and the power output circuit, for comparing the voltage feedback signal and the control compensation signal to generate a comparison signal, wherein the control circuit is further configured to output a pulse width modulation signal to the power output circuit according to the comparison signal and a clock signal; Wherein the pulse width modulation signal has a duty cycle, and the control circuit is further configured to set the duty cycle according to the comparison signal and reset the duty cycle according to the clock signal.

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