Hybrid switching converter circuit with circulating current

Abstract

The invention discloses a hybrid switching type conversion circuit with circulating current. The switching type conversion circuit comprises a power level circuit which comprises a plurality of power switches, the power switches comprise circulation switches, the circulation switches are coupled to an inductor in parallel, and the inductor and the circulation switches form a circulation loop when the circulation switches are switched on; the current sensing circuit is used for generating a current sensing signal; the power switch is used for switching a switching node voltage on a switching node so as to convert an input power supply to generate an output power supply; in a circulation period in each switching period, the circulation switch is controlled to be conducted according to the current sensing signal, so that the node voltage is switched to be conducted to the output voltage, in a steady state, the inductive current circulates in the circulation loop at a direct current level, and the direct current level is lower than a peak value of the inductive current.

Description

Technical Field

[0001] The present invention relates to a switching conversion circuit, and more particularly to a hybrid switching conversion circuit having a circulating current. Background Art

[0002] Figure 1 A circuit schematic diagram of a known switching conversion circuit is shown. As Figure 1 shown, the known switching conversion circuit 101 includes a plurality of power switches S1 to S3, S6 to S7. The plurality of power switches S1 to S3, S6 to S7 are used to switch the inductor L1 according to the operation signals VS1 to VS3, VS6 to VS7, thereby converting the input voltage VIN to generate the output voltage VOUT. The inductor L1 is coupled between the switching node LX and the output voltage VOUT. The plurality of power switches S1 to S3, S6 to S7 include an upper bridge switch S3, S6, a ground switch S2, a lower bridge switch S7, and a boost switch S1. The upper bridge switch S6 is coupled between one end Nc1 of the capacitor C1 and the switching node LX, the upper bridge switch S3 is coupled between one end Nc1 of the capacitor C1 and the input voltage VIN, and the ground switch S2 is coupled between the other end Nc2 of the capacitor C1 and the ground potential. The lower bridge switch S7 is coupled between the switching node LX and the ground potential, and the boost switch S1 is coupled between the other end Nc2 of the capacitor C1 and the input voltage VIN. The plurality of power switches S1 to S3, S6 to S7 are also used to switch the capacitor C1, wherein one end Nc1 of the capacitor C1 is coupled to the switching node LX. The above-known switching conversion circuit 101 has difficulties in compensator design, and has a large output ripple and low efficiency.

[0003] In view of this, the present invention provides a hybrid switching conversion circuit having a circulating current. Summary of the Invention

[0004] In one aspect, the present invention provides a switching conversion circuit for converting an input power supply to generate an output power supply. The input power supply includes an input voltage, and the output power supply includes an output voltage. The switching conversion circuit includes: a feedback compensation circuit for generating a feedback compensation signal based on a difference between a feedback signal related to the output power supply and a reference signal; a modulation circuit for generating a modulation signal based on the feedback compensation signal and a ramp signal having a switching period; a power stage circuit including a plurality of power switches for switching an inductor according to the modulation signal, thereby converting the input power supply to generate the output power supply, wherein the inductor is coupled between a switching node and the output power supply, wherein the plurality of power switches includes a circulating switch, wherein the circulating switch is coupled in parallel with the inductor, and wherein the inductor and the circulating switch form a circulating loop when the circulating switch is turned on; a current sensing circuit for generating a current sensing signal, wherein the current sensing signal is related to an inductor current flowing through the inductor; and a control and drive circuit for generating a drive signal based on the modulation signal and the current sensing signal to control the switching of the plurality of power switches; wherein in a step-down mode, the plurality of power switches are used to switch the switching node such that a switching node voltage on the switching node switches between the input voltage and a ground potential, thereby converting the input power supply to generate the output power supply, and the input voltage is higher than or equal to the output voltage; wherein in the step-down mode, during a circulating period in each switching period, the circulating switch is controlled to be turned on, thereby causing the switching node voltage to conduct to the output voltage, and wherein in a steady state, the inductor current circulates in the circulating loop at a DC current level, and the DC current level is lower than a peak value of the inductor current.

[0005] In one embodiment, the plurality of power switches are further used to switch a capacitor, wherein one end of the capacitor is coupled to the switching node; wherein in a step-up mode, the plurality of power switches are used to switch the capacitor and the inductor such that the switching node voltage switches between a pumped voltage and the input voltage, thereby converting the input power supply to generate the output power supply, wherein the pumped voltage is higher than the input voltage, and the pumped voltage is related to the input voltage and a capacitance voltage across the capacitor, and the output voltage is between the pumped voltage and the input voltage; wherein in the step-up mode, during the circulating period in each switching period, the circulating switch is controlled to be turned on, thereby causing the switching node voltage to conduct to the output voltage, and the inductor current circulates in the circulating loop at the DC current level, and wherein in a steady state, the DC current level is lower than a peak value of the inductor current.

[0006] In one embodiment, in a buck-boost mode, the plurality of power switches are further configured to switch the capacitor and the inductor, such that the switching node voltage is switched between the boost voltage, the input voltage, and the ground potential, thereby converting the input power supply to generate the output power supply, wherein the output voltage is higher than, lower than, or equal to the input voltage.

[0007] In one embodiment, the ramp signal is generated according to a clock signal having the switching period, wherein the switching period is a fixed period, thereby causing the modulation signal to have the fixed period.

[0008] In one embodiment, the modulation circuit is configured to compare the feedback compensation signal with the ramp signal having the fixed period to determine a duty cycle of the modulation signal, thereby adjusting an electrical characteristic of the output power supply to a target value.

[0009] In one embodiment, the switching converter circuit further includes a sample-and-hold circuit; wherein in the buck mode, the sample-and-hold circuit is configured to sample and hold the current sensing signal at a time point after a preset delay time after the inductor starts to demagnetize, so as to obtain a buck current sampling level, wherein in each switching period, when the current sensing signal drops to the buck current sampling level, a corresponding circulating current period in each switching period is started and the circulating current switch is turned on; and / or wherein in the boost mode, the sample-and-hold circuit is configured to sample and hold the current sensing signal at a time point after a preset delay time after the inductor starts to demagnetize, so as to obtain a boost current sampling level, wherein in each switching period, when the current sensing signal drops to the boost current sampling level, a corresponding circulating current period in each switching period is started and the circulating current switch is turned on.

[0010] In one embodiment, in the buck mode or the boost mode, during the corresponding circulating current period, the inductor and the circulating current switch form a circulating current loop when the circulating current switch is turned on, such that a double pole formed by the inductor and an output capacitor is at least partially degenerated into a single pole characteristic, thereby improving the stability and bandwidth of the switching converter circuit.

[0011] In one embodiment, the plurality of power switches further include: an upper bridge switch coupled between the input power supply and the switching node; a ground switch coupled between the other end of the capacitor and the ground potential; a lower bridge switch coupled between the switching node and the other end of the capacitor, or coupled between the switching node and the ground potential; and a charge pump switch coupled between the other end of the capacitor and the input power supply.

[0012] In one embodiment, in a bypass mode, the upper bridge switch is constantly turned on to bypass the input power supply to the output power supply through the inductor.

[0013] In one embodiment, the duration of the circulating current period is related to the stability of the switching conversion circuit and / or related to the power conversion efficiency of the switching conversion circuit.

[0014] In one embodiment, when the lower bridge switch is coupled between the switching node and the other end of the capacitor, the lower bridge switch and the ground switch are respectively transistors with the same withstand voltage.

[0015] The following is described in detail through specific embodiments to more easily understand the purpose, technical content, features and achieved effects of the present invention. Brief Description of the Drawings

[0016] Figure 1 A circuit schematic diagram showing a known switching conversion circuit is shown.

[0017] Figure 2A A circuit schematic diagram showing a switching conversion circuit according to an embodiment of the present invention is shown.

[0018] Figure 2B A circuit schematic diagram showing a switching conversion circuit according to another embodiment of the present invention is shown.

[0019] Figure 3A A circuit schematic diagram showing a conversion control circuit of a switching conversion circuit according to an embodiment of the present invention is shown.

[0020] Figure 3B A circuit schematic diagram showing a conversion control circuit of a switching conversion circuit according to another embodiment of the present invention is shown.

[0021] Figure 3C A circuit schematic diagram showing a conversion control circuit of a switching conversion circuit according to still another embodiment of the present invention is shown.

[0022] Figure 4 A circuit schematic diagram showing a partial control and drive circuit for a circulating current switch of a switching conversion circuit according to an embodiment of the present invention is shown.

[0023] Figure 5 A circuit schematic diagram showing a partial control and drive circuit for a circulating current switch of a switching conversion circuit according to another embodiment of the present invention is shown.

[0024] Figures 6A - 6C , Figures 7A - 7C , Figures 8A - 8C , Figure 9 A circuit schematic diagram and an operation schematic diagram showing a multiphase conversion circuit according to an embodiment of the present invention are shown.

[0025] Figures 10A - 10C 、 Figures 11A - 11C 、 Figures 12A - 12C 、 Figure 13 are circuit schematic diagrams and operation schematic diagrams showing a multiphase conversion circuit according to an embodiment of the present invention.

[0026] Figure 14A 、 Figure 14B and Figure 14C are signal waveform schematic diagrams showing related signals of a switching conversion circuit according to an embodiment of the present invention.

[0027] Figure 15 is a comparison diagram showing the comparison between the present invention and the prior art in terms of unity gain bandwidth and phase margin according to an embodiment of the present invention.

[0028] Symbol Explanation in the Figures

[0029] 10, 10B, 101, 102A, 102B: Switching conversion circuit

[0030] 109, 110: Partial control and drive circuit

[0031] 20: Feedback compensation circuit

[0032] 30, 30’: Conversion control circuit

[0033] 31, 310: Modulation circuit

[0034] 31’: Comparator

[0035] 32: Current sensing circuit

[0036] 33: Control and drive circuit

[0037] 33’: Logic drive circuit

[0038] 35: Circulating current comparator

[0039] 36: Sampling and holding circuit

[0040] 37: Fixed time generation circuit

[0041] 38: Ramp signal generation circuit

[0042] 39: State control circuit

[0043] C1: Capacitor

[0044] CLK: Clock signal

[0045] Co: Output capacitor

[0046] CPC: Circulating current comparison result

[0047] CPO: Comparison result

[0048] Csh: Sampling hold capacitor

[0049] DT: Delay time

[0050] EAO: Feedback compensation signal

[0051] GND: Ground potential

[0052] IL: Inductor current

[0053] IOUT: Output current

[0054] L1: Inductor

[0055] LX: Switching node

[0056] Nc, Nc2: The other end

[0057] Nc1: One end

[0058] S1: Pump pressure switch / Power switch

[0059] S2: Ground switch / Power switch

[0060] S3, S6: Upper bridge switch / Power switch

[0061] S4, S4’, S7: Lower bridge switch / Power switch

[0062] S5: Circulating current switch / Power switch

[0063] SCOT: Fixed time signal

[0064] Sdrv: Modulation signal

[0065] SIL: Current sensing signal

[0066] SIL_dcd: Buck current sampling level

[0067] SIL_dcu: Boost current sampling level

[0068] Spw: Modulation signal

[0069] Ssh: Sampling hold switch

[0070] ST1~ST10: Status

[0071] T: Switching period

[0072] t0~t6: Time point

[0073] Tpw: Pulse width

[0074] Trig: Trigger signal

[0075] VC1: Capacitor cross voltage

[0076] Vfb: Feedback signal

[0077] VIN: Input voltage

[0078] VLX: Switching node voltage

[0079] VOUT: Output voltage

[0080] VRAMP, VRAMP’, VRAMP”: Ramp signal

[0081] Vref: Reference signal

[0082] VS1~VS7, VS4’: Operation signal

[0083] Vsh: Sampling hold control signal Detailed implementation manners

[0084] The drawings in the present invention are all schematic, mainly intended to show the coupling relationships between circuits and the relationships between signal waveforms. As for circuits, signal waveforms and frequencies, they are not drawn to scale.

[0085] Figure 2A is a circuit schematic diagram showing a switching conversion circuit according to an embodiment of the present invention. As Figure 2A shown, the switching conversion circuit 102A of the present invention is used to convert an input power supply to generate an output power supply. The input power supply includes an input voltage VIN, and the output power supply includes an output voltage VOUT. The switching conversion circuit 102A includes a power stage circuit 10. In one embodiment, the power stage circuit 10 includes a plurality of power switches S1~S5. Please also refer to Figure 2A and Figure 3A , the plurality of power switches S1~S5 are controlled by a driving signal Sdrv generated according to a modulation signal Spw to switch the inductor L1, thereby converting the input power supply to generate the output power supply. Details of the foregoing modulation signal Spw and driving signal Sdrv will be described in detail later. Please refer to Figure 2A again. The inductor L1 is coupled between the switching node LX and the output power supply. The plurality of power switches S1~S5 include a circulating switch S5. The circulating switch S5 is connected in parallel to the inductor L1, and a circulating loop is formed between the inductor L1 and the circulating switch S5 when the circulating switch S5 is turned on. The plurality of power switches S1~S5 further include an upper bridge switch S3, a ground switch S2, a lower bridge switch S4, and a pumping switch S1. As Figure 2AAs shown, a plurality of power switches S1 to S5 are also used to switch the capacitor C1, and one end of the capacitor C1 is coupled to the switching node LX. The upper bridge switch S3 is coupled between the input power supply and the switching node LX, and the grounding switch S2 is coupled between the other end Nc of the capacitor C1 and the ground potential. The lower bridge switch S4 is coupled between the switching node LX and the other end Nc of the capacitor C1, and the pumping switch S1 is coupled between the other end Nc of the capacitor C1 and the input power supply.

[0086] Figure 2B is a circuit schematic diagram showing a switching conversion circuit according to another embodiment of the present invention. The difference between this embodiment and Figure 2A the embodiment is that the lower bridge switch S4' of the power stage circuit 10B in this embodiment is coupled between the switching node LX and the ground potential.

[0087] It should be noted that according to the present invention, the foregoing power stage circuit 10 or 10B having a circulating current period can be paired with various modes of conversion control circuits. The following are several non-limiting embodiments.

[0088] Figure 3A is a circuit schematic diagram showing a conversion control circuit of a switching conversion circuit according to an embodiment of the present invention. The power stage circuit 10 of this embodiment adopts Figure 2A the power stage circuit. The conversion control circuit of this embodiment controls the power stage circuit 10 to operate in a voltage mode. As Figure 3A shown, the switching conversion circuit 108 of the present invention further includes a conversion control circuit 30. The conversion control circuit 30 includes a feedback compensation circuit 20, a modulation circuit 31, a current sensing circuit 32, and a control and drive circuit 33. The feedback compensation circuit 20 is used to generate a feedback compensation signal EAO according to the difference between the feedback signal Vfb related to the output power supply and the reference signal Vref. The modulation circuit 31 is used to generate a modulation signal Spw according to, for example, comparing the feedback compensation signal EAO with a ramp signal VRAMP having a switching period. The current sensing circuit 32 is used to generate a current sensing signal SIL, where the current sensing signal SIL is related to the inductor current IL flowing through the inductor L1. In the following embodiments, the current sensing signal SIL is positively related to the inductor current IL flowing through the inductor L1, but this does not limit the maximum scope of the present invention. The control and drive circuit 33 is used to generate a drive signal Sdrv according to the modulation signal Spw, the clock signal CLK, and the current sensing signal SIL to control the switching of the plurality of power switches S1 to S5. As Figure 3A shown, the drive signal Sdrv includes operation signals VS1 to VS5.

[0089] Figure 3BFIG. 0 is a circuit schematic diagram of a conversion control circuit for a switching conversion circuit according to another embodiment of the present invention. The conversion control circuit of this embodiment controls the power stage circuit 10 to operate in current mode. This embodiment is similar to Figure 3A FIG. 1, the difference being that the ramp signal VRAMP' in this embodiment is the superposition of the ramp signal VRAMP and the current sensing signal SIL.

[0090] Figure 3C FIG. 6 is a circuit schematic diagram of a conversion control circuit for a switching conversion circuit according to yet another embodiment of the present invention. The conversion control circuit of this embodiment controls the power stage circuit 10 to operate in constant ON-time mode. This embodiment is similar to the embodiment of Figure 3A FIG. 8, the difference being that the conversion control circuit 30' of this embodiment further includes a fixed time generation circuit 37, a ramp signal generation circuit 38, and a state control circuit 39. In this embodiment, the modulation circuit 310 includes a comparator 31', a fixed time generation circuit 37, and a state control circuit 39. The ramp signal generation circuit 38 is used to generate a ramp signal VRAMP" according to the input voltage VIN and the output voltage VOUT. The comparator 31' is used to compare the feedback compensation signal EAO with the ramp signal VRAMP" to generate a comparison result CPO. The fixed time generation circuit 37 is used to generate a fixed time signal SCOT according to the comparison result CPO. The state control circuit 39 is used to generate a modulation signal Spw with a fixed ON-time according to the comparison result CPO and the fixed time signal SCOT.

[0091] Figure 4 FIG. 12 is a circuit schematic diagram of a partial control and drive circuit for a circulating current switch of a switching conversion circuit according to an embodiment of the present invention. As shown in Figure 4 FIG. 14, the partial control and drive circuit 109 for the circulating current switch S5 of the present invention includes a logic drive circuit 33', a circulating current comparator 35, and a sample and hold circuit (S / H) 36. The sample and hold circuit (S / H) 36 generates a buck current sampling level SIL_dcd (hereinafter, in the buck mode) or a boost current sampling level SIL_dcu (hereinafter, in the boost mode) according to the current sensing signal SIL and the sample and hold control signal Vsh. The circulating current comparator 35 compares the current sensing signal SIL with the buck current sampling level SIL_dcd or the boost current sampling level SIL_dcu to generate a circulating current comparison result CPC. The logic drive circuit 33' generates an operation signal VS5 according to the circulating current comparison result CPC.

[0092] Figure 5It is a circuit schematic diagram showing a partial control and drive circuit for a circulating current switch of a switching conversion circuit according to a specific embodiment of the present invention. In this embodiment, the sampling and holding circuit 36 includes a sampling and holding switch Ssh and a sampling and holding capacitor Csh. The sampling and holding switch Ssh is switched according to the sampling and holding control signal Vsh to sample a signal related to the current sensing signal SIL at the moment when the sampling and holding control signal Vsh turns to disabled, and maintain the step-down current sampling level SIL_dcd or the step-up current sampling level SIL_dcu as described above on the sampling and holding capacitor Csh.

[0093] Figures 6A - 6C 、 Figures 7A - 7C 、 Figures 8A - 8C 、 Figure 9 is a circuit schematic diagram and an operation schematic diagram showing a multi-phase conversion circuit according to an embodiment of the present invention, where Figures 6A - 6C corresponds to the step-up mode, Figures 7A - 7C corresponds to the step-down mode, Figures 8A - 8C corresponds to the buck-boost mode, Figure 9 corresponds to the bypass mode. Please refer to Figure 6A and Figure 14A shown. In state ST1, the ground switch S2, the upper bridge switch S3, the lower bridge switch S4, and the circulating current switch S5 are switched to non-conductive, and the pumping switch S1 is switched to conductive according to the operation signal VS1, so that the capacitor C1 and the inductor L1 are connected in series between the input voltage VIN and the output voltage VOUT. It should be noted that in the embodiment corresponding to Figure 2A , the lower bridge switch S4, for example, in Figure 6A state ST1, withstands a voltage stress of 2*VIN in series with the ground switch S2. Specifically, the lower bridge switch S4 and the ground switch S2 respectively only withstand the voltage stress of the input voltage VIN, and do not need to withstand the voltage stress of 2*VIN alone. Therefore, a lower voltage process can be adopted. For example, the lower bridge switch S4 and the ground switch S2 can be transistors with the same withstand voltage respectively, thus saving circuit cost and size.

[0094] Please refer to Figure 6B and Figure 14A shown. In state ST2, the pumping switch S1, the lower bridge switch S4, and the circulating current switch S5 are switched to non-conductive, and the ground switch S2 and the upper bridge switch S3 are switched to conductive according to the operation signals VS2 and VS3, so that the capacitor C1 is electrically connected between the input voltage VIN and the ground potential, and the switching node LX is coupled to the input voltage VIN.

[0095] Specifically, as Figure 6A 、 6B and Figure 14AAs shown, in the step-up mode, multiple power switches S1 to S5 are used to switch the capacitor C1 and the inductor L1. In state ST2, the capacitor C1 is charged with the input voltage VIN, and at the same time, the node voltage VLX is switched to be electrically connected to the input voltage VIN. And in state ST1, the other end Nc of the capacitor C1 is electrically connected to the input voltage VIN, thereby superimposing the capacitance voltage VC1 on the capacitor C1 on the input voltage VIN, and further making the switching node voltage VLX a boosted voltage. In other words, the multiple power switches S1 to S5 make the switching node voltage VLX switch between the pumped voltage and the input voltage VIN through the above operations, thereby converting the input power supply to generate the output power supply. Wherein the pumped voltage is higher than the input voltage VIN. Since in the steady state, the capacitance voltage VC1 on the capacitor C1 is at the level of the input voltage VIN, the pumped voltage is equal to twice the input voltage VIN. From one perspective, in the step-up mode, the switching capacitor part achieves the step-up effect through a charge pump, and although the switching inductor conversion part is a buck operation, the output voltage VOUT can be higher than the input voltage VIN. Therefore, for the voltage conversion from the input voltage VIN to the output voltage VOUT, the step-up effect can still be achieved.

[0096] Please also refer to Figure 6C and Figure 14A , in state ST3, the charge pump switch S1, the ground switch S2, the high-side switch S3, and the low-side switch S4 are switched to non-conductive, and the circulating switch S5 is switched to conductive according to the operation signal VS5, so that the inductor current IL circulates in the circulating loop formed by the circulating switch S5 and the inductor L1. As Figure 6C shown in state ST3 of, in the step-up mode, during the circulating period of each switching cycle, the circulating switch S5 is controlled to be conductive, thereby making the switching node voltage VLX conductive to the output voltage VOUT, and the inductor current IL circulates in the circulating loop at a DC current level. The details of the circulating period and the DC current level will be described in detail later.

[0097] From one perspective, according to the present invention, in the step-up mode, the multiple power switches S1 to S5 also control the power stage circuit to switch between states ST1, ST2, and ST3, so that the switching node voltage VLX switches between the pumped voltage, the input voltage VIN, and the output voltage VOUT, thereby converting the input power supply to generate the output power supply.

[0098] Please also refer to Figure 7A and Figure 14BAs shown, in state ST4, the pump voltage switch S1, the ground switch S2, the lower bridge switch S4, and the circulating current switch S5 are switched to non-conductive, while the upper bridge switch S3 is switched to conductive according to the operation signal VS3, so that the switching node LX is electrically connected to the input voltage VIN. Please also refer to Figure 7B and Figure 14B As shown, in state ST5, the pump voltage switch S1, the upper bridge switch S3, and the circulating current switch S5 are switched to non-conductive, while the ground switch S2 and the lower bridge switch S4 are switched to conductive according to the operation signals VS2 and VS4, so that the switching node LX is electrically connected to the ground potential. In other words, as shown in Figure 7A and 7B In states ST4 and ST5, in the step-down mode, the plurality of power switches S1 to S5 are used to switch the switching node LX, so that the switching node voltage VLX on the switching node LX is switched between the input voltage VIN and the ground potential, thereby converting the input power supply to generate the output power supply. In this embodiment, the input voltage VIN is higher than or equal to the output voltage VOUT.

[0099] Please also refer to Figure 7C and Figure 14B As shown, in state ST3, the pump voltage switch S1, the ground switch S2, the upper bridge switch S3, and the lower bridge switch S4 are switched to non-conductive, while the circulating current switch S5 is switched to conductive according to the operation signal VS5, so that the inductor current IL circulates in the circulating current loop formed by the circulating current switch S5 and the inductor L1. As shown in Figure 7C In state ST3, in the step-down mode, during the circulating current period in each switching cycle, the circulating current switch S5 is controlled to be conductive, so that the switching node voltage VLX is conductive to the output voltage VOUT. As shown in Figure 14B As shown, in the steady state, the inductor current IL circulates in the circulating current loop at a DC current level. Details of the circulating current period and the DC current level will be described later.

[0100] In one aspect, according to the present invention, in the step-down mode, the plurality of power switches S1 to S5 also control the power stage circuit to switch between states ST4, ST5, and ST3, so that the switching node voltage VLX is switched between the input voltage VIN, the ground potential, and the output voltage VOUT, thereby converting the input power supply to generate the output power supply.

[0101] It should be noted that according to the present invention, in the buck mode or the boost mode, during the corresponding circulating current period, the inductor L1 and the circulating current switch S5 form a circulating current loop when the circulating current switch S5 is turned on, so that the double poles generated by the inductor L1 and the output capacitor Co can be at least partially degenerated into single pole characteristics, thereby improving the stability and bandwidth of the switching conversion circuit 108.

[0102] Please refer to Figure 8A 、 Figure 8B and Figure 8C , as shown in states ST1, ST2 and ST5, in the buck-boost mode, the plurality of power switches S1 to S5 are also used to switch the capacitor C1 and the inductor L1, so that the switching node voltage VLX is switched between the boosted voltage, the input voltage VIN and the ground potential, thereby converting the input power supply to generate an output power supply. In this embodiment, the output voltage VOUT can be higher than, lower than or equal to the input voltage VIN. In the buck-boost mode, it can also be operated in state ST3 as Figure 7C shown, that is, during the circulating current period in each switching cycle, the circulating current switch S5 is controlled to be turned on, so that the switching node voltage VLX is turned on to the output voltage VOUT.

[0103] As Figure 9 shown, in the bypass mode, the upper bridge switch S3 is constantly turned on to bypass the input power supply and the output power supply through the inductor L1.

[0104] Figures 10A - 10C 、 Figures 11A - 11C 、 Figures 12A - 12C 、 Figure 13 are schematic circuit diagrams and operation schematic diagrams showing a multiphase conversion circuit according to an embodiment of the present invention. This embodiment is similar to Figures 6A - 6C 、 Figures 7A - 7C 、 Figures 8A - 8C 、 Figure 9 corresponding, the main difference is that the lower bridge switch S4' of these several embodiments is coupled between the switching node LX and the ground potential. Among them, states ST6, ST7 and ST8 respectively correspond to the aforementioned states ST1, ST2 and ST3, and states ST9 and ST10 respectively correspond to the aforementioned states ST4 and ST5. Since the lower bridge switch S4' of these several embodiments is coupled between the switching node LX and the ground potential, therefore, when the switching node LX needs to be electrically connected to the ground potential (such as in state ST10), the lower bridge switch S4 is controlled to be turned on, and the ground switch S2 is controlled to be turned off. The rest of the states can be deduced by analogy and will not be elaborated here.

[0105] Figure 14A 、 Figure 14B and Figure 14CIt is a schematic diagram of signal waveforms showing relevant signals of a switching conversion circuit according to an embodiment of the present invention. The operation signals VS1 to VS5, the switching node voltage VLX, the current sense signal SIL, the trigger signal Trig, and the sample hold control signal Vsh are shown in Figure 14A and Figure 14B . The clock signal CLK, the ramp signal VRAMP, the feedback compensation signal EAO, the drive signal Sdrv, or the modulation signal Spw are shown in Figure 14C .

[0106] Figure 14A Corresponding to the boost mode, in this embodiment, the output voltage VOUT is between the boosted voltage (2*VIN) and the input voltage VIN, and the exact level of the output voltage is determined according to the duty cycle of each state. Please also refer to Figure 14A and Figure 5 , Figures 6A to 6C . In the boost mode, in each switching cycle (such as the first switching cycle T1), the sample hold circuit 36 is used to sample and hold the current sense signal SIL at a time point (such as time point t2) after a preset delay time DT from the time point (such as time point t1) when the inductor L1 starts to demagnetize, so as to obtain the boost current sampling level SIL_dcu corresponding to the first switching cycle T1. In the next switching cycle (such as the second switching cycle T2), when the current sense signal SIL drops to reach the boost current sampling level SIL_dcu (time point t5) sampled and held in the previous switching cycle (the first switching cycle T1), the operation signal VS5 is enabled to start the corresponding circulating current period (from time point t5 to time point t6) in the second switching cycle T2 and turn on the circulating current switch S5. Similarly, in the second switching cycle T2, the sample hold circuit 36 is triggered to sample and hold the current sense signal SIL again at a time point (such as time point t5) after a preset delay time DT from the time point (such as time point t4) when the inductor L1 starts to demagnetize, so as to obtain the boost current sampling level SIL_dcu corresponding to the second switching cycle T2, which is used to determine the timing of entering the circulating current period in the next switching cycle. It should be noted that in the steady state, the sample hold time point will overlap with the starting time point of the circulating current period (such as time point t2 or t5 in this embodiment), and in the transient state caused by, for example, load changes, the sample hold time point and the starting time point of the circulating current period may not overlap. From one perspective, the time length of the preset delay time DT determines the time length of the circulating current period in the steady state.

[0107] Figure 14B Corresponding to the buck mode, in this embodiment, the output voltage VOUT is between the input voltage VIN and the ground potential, and the exact level of the output voltage is determined according to the duty cycle of each state. Please also refer to Figure 14B and Figure 5 , Figures 7A to 7C, in the buck mode, in each switching period (such as the first switching period T1), the sample hold circuit 36 is used to sample the hold current sense signal SIL at time point t2 after a preset delay time DT after the inductor L1 starts to demagnetize (time point t1), so as to obtain the buck current sampling level SIL_dcd corresponding to the first switching period T1. In the next switching period (such as the second switching period T2), when the current sense signal SIL drops to reach the buck current sampling level SIL_dcd sampled and held in the previous switching period (the first switching period T1) (time point t5), the enable operation signal VS5 is used to start the corresponding circulating current period (from time point t5 to time point t6) in the second switching period T2 and turn on the circulating current switch S5. Similarly, in the second switching period T2, the sample hold circuit 36 is triggered to sample the hold current sense signal SIL again at a time point (such as time point t5) after a preset delay time DT after the inductor L1 starts to demagnetize (such as time point t4), so as to obtain the buck current sampling level SIL_dcd corresponding to the second switching period T2, which is used to judge the timing of entering the circulating current period in the next switching period.

[0108] Such as Figure 14A And Figure 14B As shown, in the aforementioned boost mode or buck mode, the trigger signal Trig is triggered corresponding to the time point t1 when the current sense signal SIL changes from rising to falling, which can be synchronized with the rising edge of the operation signal VS2 determined by the circuit for example, and the trigger signal Trig is used to enable the sample hold control signal Vsh. In an embodiment, the time length of the enable period (i.e., the delay time DT) of the sample hold control signal Vsh can be set by the user according to the requirements such as loop stability and power consumption.

[0109] It should be noted that in the above Figure 14A And Figure 14B In the embodiment, the current sense signal SIL is positively correlated with the inductor current IL. The time point when the current sense signal SIL changes from rising to falling corresponds to the time point when the peak value of the inductor current IL occurs for example, and the boost current sampling level SIL_dcu and the buck current sampling level SIL_dcd respectively correspond to the DC current levels of the inductor current IL during the circulating current period in the boost mode and the buck mode. Therefore, in the above Figure 14A And Figure 14B In the embodiment, at steady state, the DC current level is lower than the peak value of the inductor current IL.

[0110] Figure 14C Is a schematic diagram of the signal waveform corresponding to the voltage mode. Such as Figure 14CAs shown, the ramp signal VRAMP is generated according to a clock signal CLK having a switching period T, where the switching period T is a fixed period, thereby causing the modulation signal Sdrv to have a fixed period. Please also refer to Figure 3A and Figure 14C , in the voltage mode, the modulation circuit 31 is used to compare the feedback compensation signal EAO with the ramp signal VRAMP having a fixed period to determine the duty cycle of the modulation signal Sdrv, thereby adjusting electrical characteristics of the output power supply such as the output voltage VOUT or the output current IOUT to a target value. In one embodiment, the duty cycle is equal to the value obtained by dividing the pulse width Tpw of the modulation signal Spw by the switching period T. In one embodiment, the pulse width Tpw is used to determine, for example, the period corresponding to Figure 14A from time point t0 to time point t1.

[0111] Figure 15 is a comparison graph showing the present invention and the prior art in terms of unity gain bandwidth and phase margin according to an embodiment of the present invention. From Figure 15 it can be seen that the voltage mode with circulating current of the present invention has better performance in terms of unity gain bandwidth and phase margin compared to the voltage mode without circulating current or the current mode without circulating current.

[0112] In summary, the switching conversion circuit of the present invention can achieve easier design of element compensators compared to the traditional architecture, can reduce the die size, can reduce the overall integrated circuit cost, and is faster than traditional converters in terms of DVS and transient response, has smaller output ripple, higher efficiency, reduces the safe operating area (SOA) problem caused by equivalent series inductance (ESL), and has greater SOA tolerance compared to the traditional four-switch buck-boost (FSBB) converter architecture.

[0113] The present invention has been described above with reference to the preferred embodiments. However, the above description is only for making it easy for those skilled in the art to understand the content of the present invention, and is not used to limit the scope of the rights of the present invention. Each of the described embodiments is not limited to being applied alone, and can also be applied in combination. For example, two or more embodiments can be combined and used, and some components in one embodiment can also be used to replace the corresponding components in another embodiment. In addition, under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations. For example, the so-called "processing or operating or generating a certain output result according to a certain signal" in the present invention is not limited to the signal itself, but also includes, when necessary, performing voltage-current conversion, current-voltage conversion, and / or ratio conversion on the signal, and then processing or operating according to the converted signal to generate a certain output result. It can be seen from this that under the same spirit of the present invention, those skilled in the art can think of various equivalent changes and various combinations, and there are many combination methods, which are not listed one by one here. Therefore, the scope of the present invention should cover the above and all other equivalent changes.

Claims

1. A switching conversion circuit for converting an input power supply to generate an output power supply. The input power supply includes an input voltage, and the output power supply includes an output voltage. The switching conversion circuit comprises: A feedback compensation circuit for generating a feedback compensation signal according to the difference between a feedback signal related to the output power supply and a reference signal; A modulation circuit for generating a modulation signal according to the feedback compensation signal and a ramp signal having a switching period; A power stage circuit including a plurality of power switches for switching an inductor according to the modulation signal, thereby converting the input power supply to generate the output power supply. The inductor is coupled between a switching node and the output power supply. The plurality of power switches includes a circulating switch which is coupled in parallel to the inductor. When the circulating switch is turned on, the inductor and the circulating switch form a circulating loop; A current sensing circuit for generating a current sensing signal, wherein the current sensing signal is related to an inductance current flowing through the inductor; And A control and drive circuit for generating a drive signal according to the modulation signal and the current sensing signal to control the switching of the plurality of power switches; In a buck mode, the plurality of power switches are used to switch the switching node so that a switching node voltage on the switching node switches between the input voltage and a ground potential, thereby converting the input power supply to generate the output power supply, where the input voltage is higher than or equal to the output voltage; In the buck mode, during a circulating period in each switching cycle, the circulating switch is controlled to be turned on, so that the switching node voltage is turned on to the output voltage. In a steady state, the inductor current circulates in the circulating loop at a DC current level, and the DC current level is lower than a peak value of the inductor current.

2. The switching conversion circuit according to claim 1, wherein, The plurality of power switches are further used to switch a capacitor, and one end of the capacitor is coupled to the switching node; In a boost mode, the plurality of power switches are used to switch the capacitor and the inductor so that the switching node voltage switches between a boosted voltage and the input voltage, thereby converting the input power supply to generate the output power supply. The boosted voltage is higher than the input voltage, and the boosted voltage is related to the input voltage and a capacitance voltage across the capacitor. The output voltage is between the boosted voltage and the input voltage; In the boost mode, during the circulating period in each switching cycle, the circulating switch is controlled to be turned on, so that the switching node voltage is turned on to the output voltage, and the inductor current circulates in the circulating loop at the DC current level. In a steady state, the DC current level is lower than a peak value of the inductor current.

3. The switching conversion circuit according to claim 2, wherein, In a buck-boost mode, the plurality of power switches are further used to switch the capacitor and the inductor so that the switching node voltage switches between the boosted voltage, the input voltage and the ground potential, thereby converting the input power supply to generate the output power supply, where the output voltage is higher than, lower than or equal to the input voltage.

4. The switching conversion circuit according to claim 1, wherein, The ramp signal is generated according to a clock signal having the switching period. The switching period is a fixed period, so that the modulation signal has the fixed period.

5. The switching conversion circuit according to claim 4, wherein, The modulation circuit is used to compare the feedback compensation signal with the ramp signal having the fixed period to determine a duty cycle of the modulation signal, thereby adjusting an electrical characteristic of the output power supply to a target value.

6. The switching conversion circuit according to claim 1, wherein It further includes a sample-and-hold circuit; In the buck mode, the sample-and-hold circuit is used to sample and hold the current sensing signal at a time point after a preset delay time when the inductor starts to demagnetize, so as to obtain a buck current sampling level. In a single switching cycle, when the current sensing signal drops to reach the buck current sampling level, the corresponding circulating current period in the single switching cycle is started and the circulating current switch is turned on; and / or In the boost mode, the sample-and-hold circuit is used to sample and hold the current sensing signal at a time point after a preset delay time when the inductor starts to demagnetize, so as to obtain a boost current sampling level. In a single switching cycle, when the current sensing signal drops to reach the boost current sampling level, the corresponding circulating current period in the single switching cycle is started and the circulating current switch is turned on.

7. The switching conversion circuit according to claim 2, wherein In the buck mode or the boost mode, during the corresponding circulating current period, when the circulating current switch is turned on, the inductor and the circulating current switch form a circulating current loop, so that the double poles generated by the inductor and an output capacitor can degenerate at least partially into single-pole characteristics, thereby improving the stability and bandwidth of the switching conversion circuit.

8. The switching conversion circuit according to claim 2, wherein, The plurality of power switches further include: An upper bridge switch, coupled between the input power supply and the switching node; A ground switch, coupled between the other end of the capacitor and the ground potential; A lower bridge switch, coupled between the switching node and the other end of the capacitor, or coupled between the switching node and the ground potential; and A pump voltage switch, coupled between the other end of the capacitor and the input power supply.

9. The switching conversion circuit according to claim 8, wherein, In a bypass mode, the upper bridge switch is constantly turned on to bypass the input power supply and the output power supply through the inductor.

10. The switching conversion circuit according to claim 1, wherein, The time length of the circulating current period is related to the stability of the switching conversion circuit, and / or related to the power conversion efficiency of the switching conversion circuit.

11. The switching conversion circuit according to claim 8, wherein, When the lower bridge switch is coupled between the switching node and the other end of the capacitor, the lower bridge switch and the ground switch are respectively transistors having the same breakdown voltage.

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