Current balancing circuit and multiphase voltage stabilizer circuit

Abstract

A multi-phase voltage stabilizer circuit is applied to a multi-phase DC-DC converter and comprises a plurality of comparison circuits. The comparison circuit is coupled to a power output stage circuit of the multi-phase DC-DC converter and is used for generating a plurality of control signals, so that the power output stage circuit generates a plurality of output currents. One of the comparison circuits includes a comparator for receiving a compensation signal and a reference signal. The comparator also receives the correction signal through the correction end so as to adjust the duty cycle of the corresponding one of the control signals according to the correction signal. The correction signal of each phase is generated according to an error current of the phase, wherein the error current of the phase is a difference between a current threshold and an output current of the phase. Therefore, the duty cycle of the control signal can be adjusted in real time so as to realize balance control of each phase of current.

Description

Technical Field

[0001] The present disclosure relates to current balancing techniques, and particularly to a current balancing circuit and a multi-phase voltage regulator circuit. Background Art

[0002] A DC-to-DC converter is an electromechanical device for power conversion, used to convert the voltage of a DC power supply. DC-to-DC converters are widely used, and can be used to supply power to low-power devices (such as batteries) or high-power devices (such as industrial machines). Among them, a multi-phase DC-to-DC converter includes multiple converters of different phases, which alternately output electrical energy to the output terminal. Whether the output electrical energy between each phase converter is consistent will affect the power supply stability of the DC-to-DC converter. Therefore, there is a real need for a novel DC-to-DC converter to provide better power supply stability. Summary of the Invention

[0003] The present disclosure relates to a multi-phase voltage regulator circuit applied to a multi-phase DC-to-DC converter, which includes a plurality of comparison circuits. The comparison circuits are coupled to the power output stage circuit of the multi-phase DC-to-DC converter and are used to generate a plurality of control signals so that the power output stage circuit generates a plurality of output currents. One of the comparison circuits includes a comparator, and the comparator is used to receive a compensation signal and a reference signal. The comparator also receives a correction signal through a correction terminal to adjust the duty cycle of one of the corresponding control signals according to the correction signal. The correction signal is generated according to an error current, and the error current is the difference between a current threshold and an output current.

[0004] In one embodiment, the compensation signal is the difference between the feedback voltage provided at the output terminal of the multi-phase DC-to-DC converter and the reference voltage.

[0005] In one embodiment, the correction signal is used to form a correction voltage at the correction terminal, and the comparator adjusts the duty cycle of one of the corresponding control signals according to the correction voltage.

[0006] In one embodiment, one of the comparison circuits further includes a current detection circuit. The current detection circuit is coupled to the power output stage circuit and is used to receive the output currents to calculate the current threshold.

[0007] In one embodiment, the current threshold is the average value of the output currents.

[0008] In one embodiment, one of the comparison circuits further includes a first calibration circuit and a second calibration circuit. The first calibration circuit is coupled to the calibration terminal of the comparator, and is configured to input a corresponding one of the output currents as a first calibration signal to the calibration terminal. The second calibration circuit is coupled to another calibration terminal of the comparator, and is configured to input a current threshold as a second calibration signal to the other calibration terminal. The comparator compares the compensation signal and the reference signal based on a plurality of calibration voltages formed by the first calibration signal and the second calibration signal.

[0009] In one embodiment, one of the comparison circuits further includes a calibration conversion circuit. The calibration conversion circuit is coupled between the current detection circuit and the comparator of the multi-phase DC-DC converter to receive a current threshold and a corresponding one of the output currents, or to receive an error current. The calibration conversion circuit is configured to convert the current threshold and the corresponding one of the output currents into a voltage signal or a current signal, or to convert the error current into a voltage signal or a current signal.

[0010] In one embodiment, the calibration conversion circuit includes a transconductance amplifier, a transresistance amplifier, or a current amplifier.

[0011] In one embodiment, the reference signal is a periodic signal.

[0012] The present disclosure also relates to a current balance circuit applied to a multi-phase DC-DC converter, including a current detection circuit and a comparison circuit. The current detection circuit is coupled to the power output stage circuit of the multi-phase DC-DC converter to obtain a plurality of output currents, and is configured to calculate an average current of the output currents. The comparison circuit is coupled to the current detection circuit, and is configured to compare a compensation signal and a reference signal to output a control signal, such that the power output stage circuit is configured to adjust a first output current among the output currents. The comparison circuit is further configured to use a difference between the average current and the first output current as a calibration signal to adjust a duty cycle of the control signal according to the calibration signal.

[0013] Accordingly, by generating a calibration signal based on the error current and inputting the calibration signal to the calibration terminal of the comparator, the duty cycle of the control signal can be adjusted in real time to achieve balanced control of the currents of each phase. In addition, since the present disclosure does not require a compensation signal, there is no need for a complex circuit, nor to change the operation mode of the multi-phase DC-DC converter, and it can be easily applied and implemented. Description of the Drawings

[0014] Figure 1 A schematic diagram of a multi-phase DC-DC converter according to some embodiments of the present disclosure.

[0015] Figure 2 A schematic diagram of a current detection circuit according to some embodiments of the present disclosure.

[0016] Figure 3A Schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

[0017] Figure 3B Schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

[0018] Figure 3C Waveform diagram of a control signal according to some embodiments of the present disclosure.

[0019] Figure 4A Schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

[0020] Figure 4B Schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

[0021] Figure 5A Schematic diagram of a comparison circuit according to some embodiments of the present disclosure.

[0022] Figure 5B Schematic diagram of a comparison circuit according to some embodiments of the present disclosure. Detailed implementation

[0023] Multiple embodiments of the present invention will be disclosed below with reference to the accompanying drawings. For the sake of clarity, many practical details will be described together in the following description. However, it should be understood that these practical details are not intended to limit the present invention. That is to say, in some embodiments of the present invention, these practical details are not necessary. In addition, for the purpose of simplifying the drawings, some conventional structures and elements will be shown in a simple schematic manner in the drawings.

[0024] In this document, when an element is referred to as "connected" or "coupled", it may mean "electrically connected" or "electrically coupled". "Connected" or "coupled" can also be used to indicate the mutual cooperation or interaction between two or more elements. In addition, although terms such as "first", "second",... are used in this document to describe different elements, these terms are only used to distinguish elements or operations described with the same technical terms. Unless clearly specified in the context, these terms do not particularly refer to or imply an order or sequence, nor are they used to limit the present invention.

[0025] The present disclosure relates to a multiphase DC-DC converter for converting an input voltage to output output voltages of different voltages. In one embodiment, the multiphase DC-DC converter is applied to a vehicle power supply. For example, as a power transmission circuit, it can store the power of a charging pile in a battery or provide the stored power of the battery to in-vehicle devices. However, the present disclosure is not limited thereto. In other embodiments, the multiphase DC-DC converter can also be applied to other devices and loads.

[0026] Figure 1 Shown is a schematic diagram of a multiphase DC-DC converter 100 according to some embodiments of the present disclosure. The multiphase DC-DC converter 100 includes a power output stage circuit 110, a current balancing circuit 120, and a compensation circuit 130. The power output stage circuit 110 includes a plurality of driving circuits DC and a switching circuit 111 formed by a plurality of transistor switches, wherein each driving circuit DC and the corresponding switching circuit 111 are used to generate corresponding output currents Is1 to Isn according to the input voltage Vin.

[0027] In Figure 1 In the illustrated embodiment, the power output stage circuit 110 includes multiple sets of sub-circuits (e.g., two or more sets), each set of sub-circuits includes a driving circuit DC, and the switching circuit 111 includes an upper bridge switch Ta and a lower bridge switch Tb, and is coupled to the input voltage Vin. The driving circuit DC is used to control the conduction or cutoff of the upper bridge switch Ta and the lower bridge switch Tb according to the received control signal to generate or adjust the corresponding output currents Is1 to Isn. The phases of the output currents Is1 to Isn generated by each set of sub-circuits are different from each other. For example, when the power output stage circuit 110 includes multiple sets of sub-circuits, there is a corresponding phase difference between the output currents Is1 to Isn of each set of sub-circuits.

[0028] In one embodiment, the power output stage circuit 110 generates an output voltage Vout and a feedback voltage Vfb through an energy storage circuit 140 and a voltage dividing circuit 150. The energy storage circuit 140 is coupled to the power output stage circuit 110 and includes a plurality of inductors L1 to Ln and an output capacitor Cout. The voltage dividing circuit 150 includes a plurality of voltage dividing resistors R1, R2. Since those skilled in the art can understand the manner in which the power output stage circuit 110 generates the output voltage Vout, more details are not described herein.

[0029] The current balancing circuit 120 is coupled to the power output stage circuit 110 and includes a plurality of comparison circuits 200. Each comparison circuit 200 is used to generate control signals Spwm1 to Spwmn for the corresponding phase of the output currents Is1 to Isn to provide the control signals Spwm1 to Spwmn to each driving circuit DC. The generation manner of the control signals will be described in detail in the following paragraphs.

[0030] The compensation circuit 130 is respectively coupled to the power output stage circuit 110 and the current balance circuit 120 to receive the feedback voltage Vfb from the power output stage circuit 110. In one embodiment, the feedback voltage Vfb is the voltage value after the output voltage Vout at the output end is divided by the voltage dividing resistors R1 and R2. The compensation circuit 130 is further configured to compare the feedback voltage Vfb with the reference voltage Vref to generate a compensation signal Vcomp according to the difference between the feedback voltage Vfb and the reference voltage Vref. The reference voltage Vref can be a fixed voltage value. Therefore, the compensation signal Vcomp is used to reflect the current state of the output voltage Vout (e.g., heavy load or light load state). The compensation signal Vcomp will be provided to the current balance circuit 120, and the current balance circuit 120 will generate control signals Spwm1~Spwmn to the drive circuit DC according to the compensation signal Vcomp.

[0031] Continuing from the above, in one embodiment, the positive terminal of the compensation circuit 130 is used to receive the reference voltage Vref, and the negative terminal of the compensation circuit 130 is used to receive the feedback voltage Vfb. Therefore, the magnitude of the compensation signal Vcomp is positively correlated with "the difference between the reference voltage Vref and the feedback voltage Vfb". However, the present disclosure is not limited thereto. In other embodiments, the signals received by the positive and negative terminals of the compensation circuit 130 can be swapped according to the actual circuit design.

[0032] In one embodiment of the present disclosure, a plurality of comparison circuits 200 are provided in the current balance circuit 120 to adjust the control signals Spwm1~Spwmn provided to the power output stage circuit 110 in real time according to the power supply state of the multi-phase DC-DC converter 100 (e.g., according to the compensation signal Vcomp and / or the output current) to ensure that the output currents of each phase of the multi-phase DC-DC converter 100 can be maintained in balance (i.e., the output currents of each phase can be maintained substantially equal).

[0033] For ease of explanation, the plurality of comparison circuits 200 in the multi-phase DC-DC converter 100 are collectively referred to as the multi-phase voltage regulator circuit 122 herein. The multi-phase voltage regulator circuit 122 is configured to generate and adjust a plurality of control signals Spwm1~Spwmn corresponding to different phases, so that the power output stage circuit 110 generates a plurality of output currents Is1~Isn of different phases accordingly, thereby keeping the currents of each phase in balance.

[0034] In some embodiments, the control signals Spwm1 to Spwmn generated by each comparison circuit 200 are a kind of Pulse-width modulation (PWM) signals, and the control signals Spwm1 to Spwmn are provided to the drive circuit DC through the logic circuit CL. In addition, the comparison circuit 200 can also adjust the duty ratio (also known as the duty cycle) of the control signals Spwm1 to Spwmn, thereby changing the magnitudes of the output currents Is1 to Isn generated by the power output stage circuit 110. Since those skilled in the art can understand the manner in which the logic circuit CL and the drive circuit DC transmit control signals in digital signals, it will not be elaborated herein.

[0035] In some embodiments, the reference signals VR1 to VRn can be a kind of periodic signals, and their signal magnitudes change periodically within a time period. In other embodiments, the reference signals VR1 to VRn can be sawtooth waves with a fixed slope in a signal cycle. A "sawtooth wave" means that in each signal cycle, it starts to change from a fixed level (e.g., rising or falling), and when the current signal cycle ends and enters the next signal cycle, it returns to the original fixed level. In some embodiments, the signal slope of the ramp signal Vramp is positive, that is, in the signal cycle, the level of the ramp signal Vramp gradually rises. However, the present disclosure is not limited thereto. In other embodiments, depending on the slope, the ramp signal Vramp can also be a triangular wave. In addition, the phases between the reference signals VR1 to VRn are also different from each other to generate control signals Spwm1 to Spwmn with different phases.

[0036] Here, the manner in which the comparison circuit 200 generates the control signals Spwm1 to Spwmn is described. As Figure 1 shown, in one embodiment, each comparison circuit 200 is coupled between the compensation circuit 130 and the power output stage circuit 110, and includes a comparator 210. Multiple input terminals of the comparator 210 are respectively used to receive the compensation signal Vcomp and the reference signals VR1 to VRn, so as to generate the control signals Spwm1 to Spwmn according to the relative relationship between the compensation signal Vcomp and the corresponding reference signal. The output of the comparator 210 is converted into the control signals Spwm1 to Spwmn through the logic circuit CL and transmitted to the power output stage circuit 110. However, in some embodiments of the present disclosure, the logic circuit CL can be omitted. In one embodiment, the positive input terminal of the comparator 210 is used to receive the compensation signal Vcomp, and the negative input terminal of the comparator 210 is used to receive the corresponding reference signal (one of the reference signals VR1 to VRn, such as the reference signal VR1 in the figure), but the present disclosure is not limited thereto.

[0037] Specifically, when the compensation signal Vcomp is greater than the corresponding reference signal, the comparison circuit 200 can adjust the corresponding control signal to a high level, and when the compensation signal Vcomp is less than the corresponding reference signal, the comparison circuit 200 can adjust the corresponding control signal to a low level. Since the compensation signal Vcomp reflects the state of the output voltage Vout, when the compensation signal Vcomp changes, the comparison circuit 200 can adjust the duty cycle of the corresponding control signal in real time, change the output current, and thus change the output voltage Vout.

[0038] For example, when the output voltage Vout is too large, the feedback voltage Vfb also increases, resulting in a smaller difference between the reference voltage Vref and the feedback voltage Vfb, causing the compensation signal Vcomp to decrease.

[0039] Continuing from the above, the comparison circuit 200 is used to compare the compensation signal Vcomp with the corresponding reference signal (i.e., one of the reference signals VR1 to VRn) to generate one of the control signals Spwm1 to Spwmn, and then adjust the corresponding output current. However, since the compensation signal Vcomp only reflects the overall load level of the multi-phase DC-DC converter 100 and does not reflect the "difference between the output currents of different phases", the comparator 210 of the comparison circuit 200 in this embodiment also receives the corresponding correction signals Sc1 to Scn through the correction terminal, and adjusts / corrects the duty cycle of the generated control signal according to the corresponding correction signals Sc1 to Scn.

[0040] The correction signals Sc1 to Scn are generated according to the error currents Idiff1 to Idiffn, and the error currents Idiff1 to Idiffn are the differences between the output currents Is1 to Isn and the current threshold. For example, the control signal Spwm1 generated by the comparison circuit 200 is used to cause the power output stage circuit 110 to generate the output current Is1 of the first phase. The difference between the output current Is1 of the first phase and a specific current threshold is the error current Idiff1. The error currents Idiff1 to Idiffn can be directly used as the correction signals Sc1 to Scn, or can be used as the correction signals Sc1 to Scn after conversion.

[0041] In one embodiment, the current threshold can be a preset fixed current value, such as the ideal value of the output current when the multi-phase DC-DC converter 100 operates normally. In another embodiment, the current threshold can be the average or median value of the multiple drive currents generated by the power output stage circuit 110, but the disclosure is not limited thereto. In some variations of the disclosure, the current threshold can be a preset value or can be obtained by looking up a table.

[0042] The present disclosure does not directly change the signals received by the comparison circuit 200 (i.e., the compensation signal Vcomp and the corresponding reference signals VR1-VRn), but receives the calibration signals Sc1-Scn through a calibration terminal outside the input terminals (the positive input terminal and the negative input terminal) of the comparison circuit 200, thereby affecting the comparison result of the comparison circuit 200 to change the duty cycle of the control signal.

[0043] In one embodiment, the comparator 210 uses the calibration signals Sc1-Scn as its own calibration voltages to compare the compensation signal Vcomp and the corresponding reference signals according to these calibration voltages. The calibration voltage can be regarded as the reference basis for the comparator 210 to perform signal comparison. Therefore, when the calibration signals Sc1-Scn form a calibration voltage on the calibration terminal, it will indirectly affect the comparison result of the comparator 210 (i.e., change the duty cycle of the control signal). In other words, the comparator 210 adjusts the duty cycle of the corresponding control signal according to the corresponding calibration voltage. The generation method of the calibration signals Sc1-Scn will be described in detail in the following paragraphs.

[0044] In one embodiment, the current balance circuit 120 further includes a current detection circuit 121. The current detection circuit 121 is coupled to the power output stage circuit 110 to obtain a plurality of output currents Is1-Isn generated by the power output stage circuit 110, and is used to calculate a current threshold according to the output currents Is1-Isn. In another embodiment, the current detection circuit 121 can detect the phase nodes N1-Nn between the upper bridge switch Ta and the lower bridge switch Tb in the power output stage circuit 110 to obtain the voltages Lx1-Lxn of the phase nodes N1-Nn, and then calculate the corresponding output currents. At the same time, the current detection circuit 121 can also calculate the average current of the plurality of output currents as the current threshold. The current detection circuit 121 can directly output the current threshold and the output current of the corresponding phase to the corresponding comparison circuit 200, or output the error currents Idiff1-Idiffn of the corresponding phase to the corresponding comparison circuit 200 after calculating the error currents Idiff1-Idiffn.

[0045] Figure 2 Shown is a schematic diagram of the current detection circuit 121 according to some embodiments of the present disclosure. As Figure 1 and Figure 2As shown, the current detection circuit 121 includes a transduction circuit 121a, an adder circuit 121b, a divider circuit 121c, and a subtractor circuit 121d. The transduction circuit 121a is coupled to the power output stage circuit 110 to receive the output currents Is1 to Isn. In one embodiment, the transduction circuit 121a includes a transconductance amplifier to receive the voltages Lx1 to Lxn of the phase nodes N1 to Nn and then calculate the output currents Is1 to Isn.

[0046] The adder circuit 121b is coupled to the transduction circuit 121a to receive the output currents Is1 to Isn and calculate the average current Iavg of the output currents Is1 to Isn through the divider circuit 121c. The subtractor circuit 121d is coupled to the divider circuit 121c to calculate the difference between the output current of the corresponding phase and the average current Iavg to generate the error currents Idiff1 to Idiffn.

[0047] In one embodiment, the comparison circuit 200 further includes a calibration conversion circuit 220 coupled between the current detection circuit 121 and the comparator 210. The calibration conversion circuit 220 is configured to receive the corresponding one of the error currents Idiff1 to Idiffn from the current detection circuit 121 and directly use the corresponding error current as a calibration signal, or convert the corresponding error current into a voltage signal or a current signal to provide the calibration signal to the calibration terminal of the comparator 210.

[0048] In another embodiment, the calibration conversion circuit 220 can separately receive the current threshold and the corresponding output current from the current detection circuit 121 and then calculate / generate the corresponding calibration signal. For example, the calibration conversion circuit 220 converts the current threshold and the corresponding output current into voltage signals or current signals respectively and provides them as calibration signals to the calibration terminal of the comparator 210.

[0049] The calibration conversion circuit 220 inputs the error current / calibration signal to the calibration terminal of the comparator 210 to form a calibration voltage, so that the comparator 210 can compare the compensation signal Vcomp and the reference signals VR1 to VRn according to the calibration voltage. Specifically, the calibration conversion circuit 220 may include a current mirror to transfer the corresponding one of the error currents Idiff1 to Idiffn to the corresponding comparator 210. In other embodiments, the calibration conversion circuit 220 may further include a transconductance amplifier for voltage-current conversion, or a transimpedance amplifier or a current amplifier for current-voltage conversion. Specific embodiments of the calibration conversion circuit 220 will be introduced in Figure 3A 、 Figure 3B, Figure 4A , Figure 4B , Figure 5A , Figure 5B .

[0050] For ease of understanding, the operation of the comparison circuit will be described herein according to Figure 3A the disclosed embodiments. Figure 3A The figure shows a schematic diagram of a comparison circuit according to some embodiments of the present disclosure, which can be applied to Figure 1 the multi-phase DC-DC converter 100 shown. Figure 3A The comparison circuit shown can be Figure 1 an example of the comparison circuit 200 shown, and the included comparator 310A and calibration circuit 320A can be Figure 1 examples of the comparator 210 and calibration conversion circuit 220 shown, respectively. Two input terminals of the comparator 310A are respectively used to receive a compensation signal Vcomp and a reference signal (here, VR1 is taken as an example), and the compensation signal Vcomp and the reference signal VR1 are compared according to a calibration voltage formed by an error current. In addition, the comparator 310A also has a plurality of nodes N31A to N34A, and the voltage level of the node N31A can be an example of the aforementioned calibration voltage.

[0051] In this embodiment, the comparator 310A is a second-order / two-stage comparator, including a first-stage comparator 311A and a second-stage comparator 312A. The first-stage comparator 311A and the second-stage comparator 312A are respectively coupled to a power supply Vcc and have current sources M31 / M32 and a plurality of transistors T31A to T38A. Taking the first-stage comparator 311A as an example, the control terminal of the transistor T31A is the node N31A, which serves as a calibration terminal. The transistors T33A and T34A are coupled to the current source M31. However, the comparator 310A is not limited to a two-stage comparator. In other embodiments, the comparator 310A can also be implemented as a single-stage comparator.

[0052] The calibration circuit 320A includes a first calibration circuit 321A and a second calibration circuit 322A. The first calibration circuit 321A and the second calibration circuit 322A can include current mirrors (but the present disclosure is not limited thereto), which are used to receive a first output current Is1 and an average current Iavg (e.g., through Figure 1 the current detection circuit 121 and the calibration conversion circuit 220 shown) and generate currents of the same magnitude at the node N31A, where the average current Iavg can also be replaced by a fixed current threshold instead of real-time calculation. The first calibration circuit 321A and the second calibration circuit 322A are coupled to the same calibration terminal of the comparator 310A. Therefore, the current value of the node N31A will depend on "the relative relationship between the first output current Is1 and the average current Iavg (i.e., the aforementioned error current or calibration signal)".

[0053] The correction circuit 320A is used to adjust the duty cycle of the control signal (such as the control signals Spwm1 to Spwmn shown), so that the output current of the corresponding phase can be consistent with the output currents of other phases. Please also refer to Figure 1 , Figure 1 , Figure 3A and Figure 3C , where Figure 3C the waveforms of the compensation signal Vcomp and the reference signal VR1, the waveform Spwm-A of the control signal Spwm1 when "the first output current Is1 is equal to the average current Iavg", the waveform Spwm-B of the control signal Spwm1 when "the first output current Is1 is greater than the average current Iavg", and the waveform Spwm-C of the control signal Spwm1 when "the first output current Is1 is less than the average current Iavg" are respectively shown from top to bottom.

[0054] Please refer to Figure 3A shown. For example, in the positive half-cycle of the control signal Spwm1, when the control signal Spwm1 is at a high level and the reference signal VR1 is lower than the compensation signal Vcomp, the upper bridge switch Ta is turned on and the lower bridge switch Tb is turned off, and the input voltage Vin charges the output capacitor Cout and the inductor L1, forming an output current Is1 flowing from the phase node N1 to the output capacitor Cout. Then, the current detection circuit 121 receives the voltages Lx1 to Lxn of the phase nodes N1 to Nn, and calculates the output currents Is1 to Isn according to the voltages Lx1 to Lxn. As Figure 1 and Figure 2 shown, the current detection circuit 121 compares the output currents Is1 to Isn with the current average value of these currents (i.e., the average current Iavg or the aforementioned current threshold). If the first output current Is1 is equal to the average current Iavg, then at the time point P2 shown in Figure 3C , the time point when the control signal Spwm1 changes to a high level will be the same as the time point when "the compensation signal Vcomp is equal to the reference signal VR1".

[0055] When the detected first output current Is1 is greater than the average current Iavg, the correction circuit 320A will reduce the duty cycle of the control signal Spwm1 to reduce the first output current Is1 so that it is equal to the output currents of other phases, as shown in the waveform Spwm-B in Figure 3C . Conversely, when the detected first output current Is1 is lower than the average current Iavg, the correction circuit 320A will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 so that the first output current Is1 is equal to the output currents of other phases, as shown in the waveform Spwm-C in Figure 3C .

[0056] As Figure 3A shown, when the first output current Is1 is greater than the average current Iavg, the current will flow from node N31A to transistor T35A. Therefore, the voltage of node N31A will gradually rise, causing the control terminal of transistor T35A to have a high level and turn on, forming a current path from node N33A via current source M32 to the ground terminal, causing the level of node N33A to quickly drop to a low level. Therefore, the pull-down control signal Spwm1 is equivalent to delaying the time for the control signal Spwm1 to enter the high level, that is, reducing the duty cycle of the control signal Spwm1. As Figure 3C shown at time point P3, at this time the control signal Spwm1 will be delayed from entering the high level at time point P3, rather than entering the high level at time point P2. In addition, because the currents flowing through nodes N31A and N32A compete for the current from current source M31, when node N31A has a high level, node N32A will have a low level, causing transistor T32 to turn off. At this time, node N34A has a high level, causing transistors T37A and T38A to turn off.

[0057] Note that the buffer circuit 330A is Figure 1 an example of the logic circuit CL in [[ ]], and may include but is not limited to two inverters connected in series for providing a digital signal with a logic level identical to that of node N33 as the control signal Spwm1. In some embodiments of the present disclosure, if the buffer circuit 330A is coupled to node N34A instead of node N33A, the buffer circuit 330A must be designed to include only a single inverter to maintain the same output phase. Also, for example, if the first correction circuit 321A and the second correction circuit 322A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 330A must also be designed to include only a single inverter to maintain the same output phase.

[0058] In addition, the control signal Spwm1 generated by the buffer circuit 330A also has better signal driving force. However, in some embodiments of the present disclosure, the setting of the buffer circuit 330A can be omitted. Through the setting of the correction circuit 320A in the present disclosure, when the first output current Is1 is greater than the average current Iavg, node N33 will quickly enter the low level, delaying the time for the control signal Spwm1 to enter the high level (refer to Figure 3C , the control signal Spwm1 is delayed from entering the high level at time point P3, rather than at time point P2), so as to reduce the duty cycle of the control signal Spwm1, and further reduce the magnitude of the output current (such as: the first output current Is1) output by the switching circuit 111, achieving the purpose of equalizing each phase current.

[0059] On the other hand, when the first output current Is1 is less than the average current Iavg, current will flow from node N31A to the correction circuit 320A, causing node N31A to be at a low level, making the control terminal of transistor T35A at a low level and turning off transistor T35A. In addition, since the currents flowing from the current source to nodes N31A and N32A are in a competitive relationship (i.e., when the current flowing to one increases, the current flowing to the other decreases), when node N31A is at a low level, node N32A will be at a high level, turning on transistors T32A and T36A. At this time, the potential of node N34A is pulled down to the ground terminal via current source M32 and is at a low level, turning on transistors T37A and T38A. Therefore, node N33A is pulled to a high level in advance, which is equivalent to making the control signal Spwm1 enter the high level in advance (as Figure 3C shown, at this time the control signal Spwm1 enters the high level in advance at time point P1 instead of at time point P2), increasing the duty cycle of the control signal Spwm1.

[0060] In other words, through the setting of the correction circuit 320A, when the first output current Is1 is less than the average current Iavg, node N33 will quickly enter the high level to increase the duty cycle of the control signal Spwm1 provided to the drive circuit DC, thereby increasing the magnitude of the output current (such as the first output current Is1) generated by the switching circuit 111, achieving the purpose of equalizing each phase current.

[0061] According to the above content, the present disclosure does not adjust the received signals at the two input terminals of the comparator 310A (or comparator 210), that is, the compensation signal or reference signal received by the comparator is not adjusted. Instead, the duty cycle of the control signal is adjusted through the correction terminal (such as node N31) according to the difference between the output current of the corresponding phase (such as the first output current Is1) and the average current Iavg, thereby increasing or decreasing the magnitude of the output current of the phase power output stage circuit 110, and finally achieving the effect of equalizing the output current of each phase power output stage circuit 110. Note that Figure 3A 、 Figure 3B 、 Figure 4A 、 Figure 4B 、 Figure 5A and Figure 5B The working principles of are all illustrated with the positive half-cycle of the control signal Spwm1 in Figure 3C .

[0062] Figure 3B The schematic diagram of the comparison circuit according to some embodiments of the present disclosure is shown. Figure 3B And Figure 3AThe difference is that the comparator 310B is a first-order comparator. The comparison circuit includes the comparator 310B, the calibration circuit 320B, and the buffer circuit 330B. The calibration circuit 320B includes a first calibration circuit 321B and a second calibration circuit 322B. Different from Figure 3A Similarly, the comparator 310B is coupled to the power supply Vcc and has a current source M33 and a plurality of transistors T31B to T34B.

[0063] The calibration circuit 320B is used to adjust the duty cycle of the control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output currents of other phases. Therefore, when the detected first output current Is1 is greater than the average current Iavg, the calibration circuit 320B will decrease the duty cycle of the control signal Spwm1 to reduce the first output current Is1 and make it equal to the output currents of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the calibration circuit 320B will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 and make it equal to the output currents of other phases.

[0064] As Figure 3B shown, when the first output current Is1 is greater than the average current Iavg, the current will flow from the node N31B to the transistor T32B. At this time, the voltage of the node N31B rises, causing the control terminal of the transistor T32B to have a high level and turn on. The voltage level of the node N31B can be an example of the aforementioned calibration voltage.

[0065] Since the transistor T32B is turned on, the node N32B is quickly pulled down, thus delaying the time for the control signal Spwm1 to enter the high level (refer to Figure 3C , the control signal Spwm1 enters the high level at the time point P3 instead of the time point P2). Therefore, the duty cycle of the control signal Spwm1 is decreased, so that the first output current Is1 output by the drive circuit DL also decreases accordingly, achieving the purpose of controlling the equality of each phase current.

[0066] Figure 3B The calibration circuit 320B of can be the same as Figure 3A the calibration circuit 320A of, and the buffer circuit 330B can be the same as Figure 3Ais the same as the buffer circuit 330A. Note that the buffer circuit 330B may include two inverters in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 330B is changed to be coupled to the node N31B instead of the node N32B, the buffer circuit 330B must be designed to include only a single inverter to maintain the same output phase. Another example is that if the first correction circuit 321B and the second correction circuit 322B are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 330B must also be designed to include only a single inverter to maintain the same output phase.

[0067] On the other hand, when the first output current Is1 is less than the average current Iavg, the current will flow from the node N31B to the correction circuit 320B, thereby making the node N31B at a low level, so that the control terminal of the transistor T32B has a low level and the transistor T32B is not turned on. At this time, the node N32B will be pulled to a high level in advance, advancing the time when the control signal Spwm1 enters the high level (refer to Figure 3C , the control signal Spwm1 enters the high level in advance at the time point P1 instead of the time point P2), so that the duty cycle of the control signal Spwm1 is increased. In other words, by means of the error current / correction signal / correction voltage, the node N32B enters the high level faster, and the time when the control signal Spwm1 is at the high level becomes longer, so that the duty cycle of the control signal Spwm1 becomes larger, thereby also increasing the first output current Is1, and the purpose of making each phase current equal can also be achieved.

[0068] Figure 4A The figure shows a schematic diagram of a comparison circuit according to some embodiments of the present disclosure, which can be applied to Figure 1 The shown multi-phase DC-DC converter 100. The comparison circuit includes a comparator 410A, a correction circuit 420A, and a buffer circuit 430A. Two input terminals of the comparator 410A are respectively used to receive a compensation signal Vcomp and a reference signal VR1, and also have a plurality of nodes N41A to N44A, wherein the voltage level of the node N41A can be an example of the aforementioned correction voltage. Figure 4A The shown comparison circuit can be Figure 1 A example of the comparison circuit 200 shown, and the included comparator 410A and correction circuit 420A can be respectively Figure 1 Examples of the correction conversion circuit 220 shown.

[0069] In this embodiment, the comparator 410A is a second-order / second-stage comparator, including a first-stage comparator 411A and a second-stage comparator 412A. The comparator 410A can be associated with Figure 3ASimilar to the comparator 310A shown, it includes a plurality of transistors T41A to T48A and current sources M41, M42. However, the present disclosure is not limited thereto. In other embodiments, the comparator 410A can also be implemented as a single-stage comparator.

[0070] The calibration circuit 420A includes a first calibration circuit 421A and a second calibration circuit 422A. The first calibration circuit 421A and the second calibration circuit 422A include current mirrors and are respectively coupled to different calibration terminals (such as nodes N41A, N42A) of the comparator 310A. The calibration circuit 420A receives the first output current Is1 and the average current Iavg through the first calibration circuit 421A and the second calibration circuit 422A, that is, it is like obtaining the error current between the first output current Is1 and the average current Iavg.

[0071] Specifically, the first calibration circuit 421A is coupled to a calibration terminal (i.e., node N41A) of the comparator 410A to input the first output current Is1 as a first calibration signal to node N41. The second calibration circuit 422A is coupled to another calibration terminal (i.e., node N42A) of the comparator 410A to input the current threshold (such as the average current Iavg) as a second calibration signal to node N42. Accordingly, the comparator 410A compares the compensation signal Vcomp and the reference signal VR1 according to the plurality of calibration voltages formed by the first calibration signal and the second calibration signal.

[0072] The calibration circuit 420A is used to adjust the duty cycle of the control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output currents of other phases. When the detected first output current Is1 is greater than the average current Iavg, the calibration circuit 320A will lower the duty cycle of the control signal Spwm1 to reduce the first output current Is1 and make it equal to the output currents of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, the calibration circuit 320A will increase the duty cycle of the control signal Spwm1 to increase the first output current Is1 and make it equal to the output currents of other phases.

[0073] As Figure 4A shown, when the first output current Is1 and the average current Iavg are input to nodes N41A, N42A, and the first output current Is1 is greater than the average current Iavg, node N41A has a high level, so the transistor T45A is turned on, forming a current path from node N43A through the current source M42 to the ground terminal, causing the level of node N43A to be pulled down, which is equivalent to delaying the time for the control signal Spwm1 to enter the high level (refer to Figure 3C, the control signal Spwm1 enters the high level after the time point P3, rather than at the time point P2). In addition, since the currents flowing through nodes N41A and N42A compete for the current from the current source M41, when node N41A has a high level, node N42A will have a low level, causing the transistor T46A to turn off. At this time, node N44A has a high level, causing the transistors T47A and T48A to turn off. In other words, the error current / correction signal / correction voltage pulls down the level of node N43A, thereby reducing the duty cycle of the control signal Spwm1, and further reducing the magnitude of the output current (such as the first output current Is1) output by the switching circuit 111, achieving the purpose of equalizing each phase current.

[0074] On the other hand, when the first output current Is1 and the average current Iavg are input to nodes N41A and N42A, and the first output current Is1 is less than the average current Iavg, the voltage of node N41A will be at a low level, causing the control terminal of the transistor T45A to have a low level and not turn on the transistor T45A. In addition, since the currents flowing from the current source M41 to nodes N41A and N42A are in a competitive relationship, when node N41A is at a low level, node N42A will have a high level, causing the transistors T42A and T46A to turn on. At this time, the potential of node N44A is pulled down to the ground terminal by the current source M41 and has a low level, causing the transistors T47A and T48A to turn on. Therefore, node N43A is pulled to the high level in advance, which is equivalent to making the control signal Spwm1 enter the high level in advance (refer to Figure 3C , the control signal Spwm1 enters the high level before the time point P1, rather than at the time point P2), causing the duty cycle of the control signal Spwm1 to be increased.

[0075] Please note that the buffer circuit 430A may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 430A is changed to be coupled to node N44A instead of node N43A, the buffer circuit 430A must be designed to include only a single inverter to maintain the same output phase. Another example is that if the first correction circuit 421A and the second correction circuit 422A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 430A must also be designed to include only a single inverter to maintain the same output phase.

[0076] Figure 4B The figure shows a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. Figure 4B and Figure 4A The difference is that the comparator 410B is a first-order / single-stage comparator. The correction circuit 420B includes a first correction circuit 421B and a second correction circuit 422B. And Figure 4ASimilarly, comparator 410B is coupled to power supply Vcc and includes current source M43 and transistors T41B to T44B.

[0077] Calibration circuit 420B is used to adjust the duty cycle of control signal Spwm1 so that the output current of the corresponding phase can be consistent with the output currents of other phases. Therefore, when the detected first output current Is1 is greater than the average current Iavg, calibration circuit 420B will decrease the duty cycle of control signal Spwm1 to reduce the first output current Is1 and make it equal to the output currents of other phases. Conversely, when the detected first output current Is1 is lower than the average current Iavg, calibration circuit 420B will increase the duty cycle of control signal Spwm1 to increase the first output current Is1 and make it equal to the output currents of other phases.

[0078] As Figure 4B shown, when the first output current Is1 and the average current Iavg are input to nodes N41B and N42B and the first output current Is1 is greater than the average current Iavg, node N41B has a high level to turn on transistor T42B (where the voltage level of node N41B can be an example of the aforementioned calibration voltage), causing the level of node N42 to be pulled down, which is equivalent to delaying the time for control signal Spwm1 to enter the high level (refer to Figure 3C , control signal Spwm1 enters the high level at a later time point P3 instead of time point P2), that is, the duty cycle of control signal Spwm1 is decreased, so that the first output current Is1 also decreases accordingly, achieving the purpose of controlling the equality of each phase current.

[0079] Similarly, when the first output current Is1 and the average current Iavg are input to nodes N41B and N42B and the first output current Is1 is less than the average current Iavg, the voltage of node N42B will enter the high level faster, that is, advance the time for control signal Spwm1 to enter the high level, increasing the duty cycle of control signal Spwm1, so that the first output current Is1 also increases accordingly, achieving the purpose of controlling the equality of each phase current.

[0080] Please note that buffer circuit 430B may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments, if buffer circuit 430B is changed to be coupled to node N41B instead of node N42B, buffer circuit 430B must be designed to include only a single inverter to maintain the same output phase. Another example is that if first calibration circuit 421B and second calibration circuit 422B are changed to receive the average current Iavg and the first output current Is1 respectively, buffer circuit 430B must also be designed to include only a single inverter to maintain the same output phase.

[0081] Figure 5A Shown is a schematic diagram of a comparison circuit according to some embodiments of the present disclosure, which can be applied to Figure 1 the multi-phase DC-DC converter 100 shown. The comparison circuit includes a comparator 510A, a calibration circuit 520A, and a buffer circuit 530A. Figure 5A The comparison circuit shown can be Figure 1 an example of the comparison circuit 200 shown, and the comparator 510A and the calibration circuit 520A included are respectively Figure 1 examples of the comparator 210 and the calibration conversion circuit 220 shown. Two input terminals of the comparator 510A are respectively used to receive a compensation signal Vcomp and a reference signal VR1, and further include a plurality of nodes N51-N53.

[0082] In this embodiment, the comparator 510A is a second-order / second-stage comparator, including a first-stage comparator 511A and a second-stage comparator 512A. The comparator 510A can be Figure 3A the same as the comparator 310A shown, including a plurality of transistors T51A-T58A and current sources M51, M52. However, the present disclosure is not limited thereto. In other embodiments, the comparator 510A can also be implemented as a single-stage comparator.

[0083] The calibration circuit 520A includes a first calibration circuit 521A and a second calibration circuit 522A. The first calibration circuit 521A and the second calibration circuit 522A may include a current mirror (but the present disclosure is not limited thereto), and are used to receive a first output current Is1 and an average current Iavg, where the average current Iavg can also be changed to a fixed current threshold. The first calibration circuit 521A and the second calibration circuit 522A are coupled to the same calibration terminal (e.g., node N51A) of the comparator 510A. Therefore, the current value of node N51A will depend on "the relative relationship between the average current Iavg and the first output current Is1 (i.e., the aforementioned error current or calibration signal)".

[0084] As Figure 5A shown, when the first output current Is1 is greater than the average current Iavg, the current will flow from node N51A to the calibration circuit 520A. Therefore, the voltage of node N51A will gradually decrease, and the voltage of node N52A will gradually increase (where the voltage level of node N52A can be an example of the aforementioned calibration voltage), making the control terminal of the transistor T55A have a high level and turn on. Node N53A is pulled down via the current source M52, which is equivalent to delaying the time for the control signal Spwm1 to enter the high level (refer to Figure 3C, the control signal Spwm1 enters the high level after the time point P3 instead of the time point P2), that is, the duty cycle of the control signal Spwm1 = 1 is reduced, so that the first output current Is1 also decreases accordingly, achieving the purpose of controlling the equality of each phase current. In addition, when the node N51A has a low level, the transistor T56A will turn off. At this time, the node N54A is at a high level, causing the transistors T57A and T58A to turn off.

[0085] On the other hand, when the first output current Is1 is less than the average current Iavg, the current will flow from the correction circuit 520A to the node N51. Since the currents flowing from the current source M51 to the nodes N51A and N52A are in a competitive relationship, the voltage of the node N51A will gradually rise, and the voltage of the node N52A will gradually decrease, causing the control terminal of the transistor T51A to have a low level and be turned off. In addition, when the node N51A has a high level, the transistor T56A will conduct. At this time, the node N54A is pulled down to a low level by the current source M52, causing the transistors T57A and T58A to conduct. Therefore, the node N53A is at a high level, advancing the time when the control signal Spwm1 enters the high level (refer to Figure 3C , the control signal Spwm1 enters the high level before the time point P1 instead of the time point P2), that is, the duty cycle of the control signal Spwm1 is increased, so that the first output current Is1 also increases accordingly, and the purpose of making each phase current equal can also be achieved.

[0086] Please note that the buffer circuit 530A may include two inverters connected in series, but the disclosure is not limited thereto. For example, in some embodiments of the present disclosure, if the buffer circuit 530A is changed to be coupled to the node N54A instead of the node N53A, the buffer circuit 530A must be designed to include only a single inverter to maintain the same output phase. Another example is that if the first correction circuit 521A and the second correction circuit 522A are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 530A must also be designed to include only a single inverter to maintain the same output phase.

[0087] Figure 5B The figure shows a schematic diagram of a comparison circuit according to some embodiments of the present disclosure. Figure 5B and Figure 5A The difference is that the comparator 510B is a first-order / first-level comparator. The comparison circuit includes a comparator 510B, a correction circuit 520B, and a buffer circuit 530B. The correction circuit 520B includes a first correction circuit 521B and a second correction circuit 522B. Similar to Figure 5A , the comparator 510B is coupled to the power supply Vcc and has a current source M53 and a plurality of transistors T51B to T54B.

[0088] AsFigure 5B As shown, when the first output current Is1 is greater than the average current Iavg, the current will flow from node N51B to the correction circuit 520B, where the voltage level of node N51B can be an example of the aforementioned correction voltage. At this time, since the currents flowing from the current source to nodes N51B and N52B are in a competitive relationship, the voltage of node N51B will gradually decrease, and the voltage of node N52B will gradually increase. The control signal Spwm1 is pulled down to the low level in advance, which is equivalent to delaying the time for the control signal Spwm1 to enter the high level (refer to Figure 3C , the control signal Spwm1 enters the high level after time point P3 instead of time point P2), that is, the duty cycle of the control signal Spwm1 is reduced, so that the first output current Is1 also decreases accordingly, achieving the purpose of controlling the equality of each phase current.

[0089] On the other hand, when the first output current Is1 is less than the average current Iavg, the current will flow from the correction circuit 520B to node N51B. Therefore, the voltage of node N51B will gradually increase, and the voltage of node N52B will gradually decrease. Therefore, the time for the control signal Spwm1 to enter the high level is advanced (refer to Figure 3C , the control signal Spwm1 enters the high level before time point P1 instead of time point P2), that is, the duty cycle of the control signal Spwm1 is increased, so that the first output current Is1 also increases accordingly, achieving the purpose of controlling the equality of each phase current.

[0090] Please note that the buffer circuit 530B may include two inverters connected in series, but the present disclosure is not limited thereto. For example, in some embodiments of the present invention, if the buffer circuit 530B is connected to node N52B instead of node N51B, the buffer circuit 530B must be designed to include only a single inverter to maintain the same output phase. Another example is that if the first correction circuit 521B and the second correction circuit 522B are changed to receive the average current Iavg and the first output current Is1 respectively, the buffer circuit 530B must also be designed to include only a single inverter to maintain the same output phase.

[0091] The various elements, method steps or technical features in the foregoing embodiments can be combined with each other, and are not limited by the order of text description or the order of presentation in the drawings in the present disclosure.

[0092] Although the present disclosure has been disclosed as above in embodiments, it is not intended to limit the present disclosure. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be determined by the appended claims.

[0093]

Symbol Description

[0094] 100: Polyphase DC-DC Converter

[0095] 110: Power Output Stage Circuit

[0096] 111: Switching Circuit

[0097] 120: Current Balancing Circuit

[0098] 121: Current Detection Circuit

[0099] 121a: Transduction Circuit

[0100] 121b: Adder Circuit

[0101] 121c: Divider Circuit

[0102] 121d: Subtractor Circuit

[0103] 122: Polyphase Voltage Regulator Circuit

[0104] 130: Compensation Circuit

[0105] 140: Energy Storage Circuit

[0106] 150: Voltage Divider Circuit

[0107] 200: Comparison Circuit

[0108] 210: Comparator

[0109] 220: Calibration Conversion Circuit

[0110] 310A: Comparator

[0111] 311A: First-Order Comparator

[0112] 312A: Second-Order Comparator

[0113] 320A: Calibration Circuit

[0114] 321A: First Calibration Circuit

[0115] 322A: Second Calibration Circuit

[0116] 310B: Comparator

[0117] 320B: Calibration Circuit

[0118] 321B: First Calibration Circuit

[0119] 322B: Second Calibration Circuit

[0120] 330A: Buffer Circuit

[0121] 330B: Buffer Circuit

[0122] 410A: Comparator

[0123] 411A: First - order Comparator

[0124] 412A: Second - order Comparator

[0125] 420A: Calibration Circuit

[0126] 421A: First Calibration Circuit

[0127] 422A: Second Calibration Circuit

[0128] 410B: Comparator

[0129] 420B: Calibration Circuit

[0130] 421B: First Calibration Circuit

[0131] 422B: Second Calibration Circuit

[0132] 430A: Buffer Circuit

[0133] 430B: Buffer Circuit

[0134] 510A: Comparator

[0135] 511A: First - order Comparator

[0136] 512A: Second - order Comparator

[0137] 520A: Calibration Circuit

[0138] 521A: First Calibration Circuit

[0139] 522A: Second Calibration Circuit

[0140] 510B: Comparator

[0141] 520B: Calibration Circuit

[0142] 521B: First Calibration Circuit

[0143] 522B: Second Calibration Circuit

[0144] 530A: Buffer Circuit

[0145] 530B: Buffer Circuit

[0146] CL: Logic Circuit

[0147] Cout: Output Capacitance

[0148] DC: Driver Circuit

[0149] Iavg: Average Current

[0150] Idiff1 - Idiffn: Error current

[0151] Is1 - Isn: Output current

[0152] L1 - Ln: Inductor

[0153] Lx1 - Lxn: Voltage

[0154] M31 - M33: Current source

[0155] M41 - M43: Current source

[0156] M51 - M53: Current source

[0157] N1 - Nn: Phase node

[0158] N31A - N34A: Node

[0159] N31B - N32B: Node

[0160] N41A - N44A: Node

[0161] N41B - N42B: Node

[0162] N51A - N54A: Node

[0163] N51B - N52B: Node

[0164] P1 - P3: Time point

[0165] R1 - R2: Voltage - dividing resistor

[0166] Sc1 - Scn: Correction signal

[0167] Spwm1 - Spwmn: Control signal

[0168] Spwm - A: Waveform

[0169] Spwm - B: Waveform

[0170] Spwm - C: Waveform

[0171] Ta: Upper - bridge switch

[0172] Tb: Lower - bridge switch

[0173] T31A - T38A: Transistor

[0174] T31B - T34B: Transistor

[0175] T41A - T48A: Transistor

[0176] T41B - T44B: Transistor

[0177] T51A - T58A: Transistor

[0178] T51B - T54B: Transistor

[0179] Vcomp: Compensation signal

[0180] VR1 - VRn: Reference signal

[0181] Vfb: Feedback voltage

[0182] Vref: Reference voltage

[0183] Vin: Input voltage

[0184] Vout: Output voltage

[0185] Vcc: Power supply.

Claims

1. A multiphase voltage regulator circuit, applied to a multiphase DC-DC converter, characterized in that, Comprising: A plurality of comparison circuits, coupled to the power output stage circuit of the multi-phase DC-DC converter, and configured to generate a plurality of control signals to cause the power output stage circuit to generate a plurality of output currents; Wherein one of the comparison circuits includes a comparator for receiving a compensation signal and a reference signal; and Wherein the comparator further receives a correction signal through a correction terminal to adjust a duty cycle of a corresponding one of the control signals according to the correction signal, wherein the correction signal is generated according to an error current, and the error current is a difference between a current threshold and a corresponding one of the output currents.

2. The polyphase voltage regulator circuit according to claim 1, wherein The compensation signal is a difference between a feedback voltage provided at an output terminal of the multi-phase DC-DC converter and a reference voltage.

3. The polyphase voltage regulator circuit according to claim 1, wherein The correction signal is used to form a correction voltage at the correction terminal, and the comparator adjusts the duty cycle of the corresponding one of the control signals according to the correction voltage.

4. The polyphase voltage regulator circuit according to claim 3, wherein, One of the comparison circuits further includes: A current detection circuit, coupled to the power output stage circuit, configured to receive the output currents to calculate the current threshold.

5. The polyphase voltage regulator circuit according to claim 4, characterized in that The current threshold is an average value of the output currents.

6. The polyphase voltage regulator circuit according to claim 3, wherein One of the comparison circuits further includes: A first correction circuit, coupled to the correction terminal of the comparator, and configured to input the corresponding one of the output currents as a first correction signal to the correction terminal; And A second correction circuit, coupled to another correction terminal of the comparator, and configured to input the current threshold as a second correction signal to the another correction terminal; Wherein the comparator compares the compensation signal and the reference signal according to a plurality of correction voltages formed by the first correction signal and the second correction signal.

7. The polyphase voltage regulator circuit according to claim 1, wherein One of the comparison circuits further includes: A correction conversion circuit, coupled between the current detection circuit of the multi-phase DC-DC converter and the comparator, to receive the current threshold and the corresponding one of the output currents, or to receive the error current; Wherein the correction conversion circuit is configured to convert the current threshold and the corresponding one of the output currents into a voltage signal or a current signal, or to convert the error current into a voltage signal or a current signal.

8. The polyphase voltage regulator circuit according to claim 7, wherein, The correction conversion circuit includes a transconductance amplifier, a transresistance amplifier or a current amplifier.

9. The polyphase voltage regulator circuit according to claim 1, wherein The reference signal is a periodic signal.

10. A current balancing circuit, applied to a multi-phase DC-DC converter, characterized in that Comprising: A current detection circuit, coupled to the power output stage circuit of the multi-phase DC-DC converter, to obtain a plurality of output currents, and configured to calculate an average current of the output currents; And A comparison circuit, coupled to the current detection circuit, and configured to compare a compensation signal and a reference signal to output a control signal to cause the power output stage circuit to adjust a first output current among the output currents; Wherein the comparison circuit is further configured to use a difference between the average current and the first output current as a correction signal to adjust a duty cycle of the control signal according to the correction signal.

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