Neutral-point balance control method and device for three-level converter, three-level converter and power supply equipment

Abstract

The invention provides a neutral-point balance control method and device for a three-level converter, the three-level converter and power supply equipment, and relates to the technical field of power supplies. The method comprises the following steps: acquiring a neutral-point voltage state and a target voltage vector of the three-level converter; if the neutral-point voltage state is a first unbalanced state, when the three-level converter is a three-level inverter, synthesizing a target voltage vector by adopting the basic voltage vector with the common-mode voltage being a positive value, and when the three-level converter is a three-level rectifier, synthesizing the target voltage vector by adopting the basic voltage vector with the common-mode voltage being a negative value; and if the neutral-point voltage state is a second unbalanced state, when the three-level converter is a three-level inverter, synthesizing a target voltage vector by adopting the basic voltage vector with the common-mode voltage being a negative value, and when the three-level converter is a three-level rectifier, synthesizing the target voltage vector by adopting the basic voltage vector with the common-mode voltage being a positive value. The problem that the neutral-point potential of the three-level converter is unbalanced can be solved.

Description

Technical Field

[0001] The present application relates to the technical field of power supplies, and particularly to a neutral point balance control method and device for a three-level converter, a three-level converter, and a power supply device. Background Art

[0002] The three-level converter has the advantages of high output voltage waveform quality, low voltage borne by switching devices, and low electromagnetic interference, and is widely used in fields such as uninterruptible power supplies, data center power supplies, new energy power generation, and electric vehicles.

[0003] However, the three-level converter has the problem of unbalanced neutral point potential. If the neutral point potential is unbalanced, it will affect the voltage waveform quality, switching device stress, stability, and whether the load can operate normally in the three phases of the three-level converter. Therefore, how to achieve neutral point potential balance of the three-level converter is an urgent problem to be solved at present. Summary of the Invention

[0004] Embodiments of the present application provide a neutral point balance control method and device for a three-level converter, a three-level converter, and a power supply device to solve the problem of unbalanced neutral point potential of the three-level converter.

[0005] In a first aspect, embodiments of the present application provide a neutral point balance control method for a three-level converter, including:

[0006] Obtaining the neutral point voltage state and the target voltage vector of the three-level converter;

[0007] If the neutral point voltage state is the first unbalanced state, when the three-level converter is a three-level inverter, a basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, a basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector;

[0008] If the neutral point voltage state is the second unbalanced state, when the three-level converter is a three-level inverter, a basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, a basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector;

[0009] Wherein, the first unbalanced state is a state where the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is a state where the positive half-bus voltage is less than the negative half-bus voltage.

[0010] In a possible implementation manner, after obtaining the neutral point voltage state and the target voltage vector of the three-level converter, it further includes:

[0011] If the midpoint voltage state is in an equilibrium state, a basic voltage vector with a common-mode voltage of zero is used to synthesize the target voltage vector.

[0012] In a possible implementation manner, the using of the basic voltage vector with a common-mode voltage of zero to synthesize the target voltage vector includes:

[0013] Obtain a first target region where the target voltage vector is located;

[0014] Use three basic voltage vectors with a common-mode voltage of zero corresponding to the first target region to synthesize the target voltage vector;

[0015] Among them, six non-zero basic voltage vectors with a common-mode voltage of zero are used as vertices to form a first space vector hexagon; the first space vector hexagon is divided into six first triangles; the first target region is the region where one of the first triangles is located.

[0016] In a possible implementation manner, the using of the basic voltage vector with a negative common-mode voltage to synthesize the target voltage vector includes:

[0017] Use basic voltage vectors with a common-mode voltage all being a first voltage to synthesize the target voltage vector; the first voltage is less than 0;

[0018] The using of the basic voltage vector with a positive common-mode voltage to synthesize the target voltage vector includes:

[0019] Use basic voltage vectors with a common-mode voltage all being a second voltage to synthesize the target voltage vector; the second voltage is greater than 0.

[0020] In a possible implementation manner, the using of the basic voltage vectors with a common-mode voltage all being the first voltage to synthesize the target voltage vector includes:

[0021] Obtain a second target region where the target voltage vector is located;

[0022] Use three basic voltage vectors with a common-mode voltage being the first voltage corresponding to the second target region to synthesize the target voltage vector;

[0023] Among them, three basic voltage vectors with a common-mode voltage being the first voltage, which are the vertices of a second space vector hexagon, form a second triangle; the second triangle is divided into four third triangles; the second target region is the region where one of the third triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0024] In a possible implementation, synthesizing the target voltage vector by using the basic voltage vectors with the common-mode voltage all being the second voltage includes:

[0025] Obtaining a third target region where the target voltage vector is located;

[0026] Synthesizing the target voltage vector by using the three basic voltage vectors corresponding to the third target region and having the common-mode voltage being the second voltage;

[0027] Among them, the three basic voltage vectors with the common-mode voltages being the vertices of the second space vector hexagon are the second voltage, forming a fourth triangle; dividing the fourth triangle into four fifth triangles; the third target region is the region where one of the fifth triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0028] In a possible implementation, during the process of synthesizing the target voltage vector, the phase with the minimum current or the maximum current among the three phases of the three-level converter is selected as the phase with the most switching times within one cycle.

[0029] In a second aspect, an embodiment of the present application provides a midpoint balance control device for a three-level converter, including:

[0030] An acquisition module, configured to acquire the midpoint voltage state and the target voltage vector of the three-level converter;

[0031] A first control module, configured to, if the midpoint voltage state is a first unbalanced state, when the three-level converter is a three-level inverter, synthesize the target voltage vector by using the basic voltage vectors with the common-mode voltage being positive, and when the three-level converter is a three-level rectifier, synthesize the target voltage vector by using the basic voltage vectors with the common-mode voltage being negative;

[0032] A second control module, configured to, if the midpoint voltage state is a second unbalanced state, when the three-level converter is a three-level inverter, synthesize the target voltage vector by using the basic voltage vectors with the common-mode voltage being negative, and when the three-level converter is a three-level rectifier, synthesize the target voltage vector by using the basic voltage vectors with the common-mode voltage being positive; where the first unbalanced state is a state where the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is a state where the positive half-bus voltage is less than the negative half-bus voltage.

[0033] In a third aspect, an embodiment of the present application provides a control device, including a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the neutral point balance control method of the three-level converter in the first aspect or any possible implementation manner of the first aspect as described above.

[0034] In a fourth aspect, an embodiment of the present application provides a three-level converter, including conversion units corresponding to three phases respectively and the control device as described in the third aspect; the conversion units are controlled by the control device.

[0035] In a fifth aspect, an embodiment of the present application provides a power supply device, including the three-level converter as described in the fourth aspect.

[0036] In a sixth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program, and when the computer program is executed by a processor, it implements the neutral point balance control method of the three-level converter in the first aspect or any possible implementation manner of the first aspect as described above.

[0037] In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, and when the computer program is executed by a processor, it implements the neutral point balance control method of the three-level converter in the first aspect or any possible implementation manner of the first aspect as described above.

[0038] In the embodiment of the present application, when the neutral point voltage state of the three-level converter is in the first unbalanced state, that is, the positive half-bus voltage is greater than the negative half-bus voltage, if the three-level converter is a three-level inverter, the basic voltage vectors with positive common-mode voltage are used to synthesize the target voltage vector; if the three-level converter is a three-level rectifier, the basic voltage vectors with negative common-mode voltage are used to synthesize the target voltage vector, so that the neutral point voltage can rise and gradually reach the balanced state; when the neutral point voltage state of the three-level converter is in the second unbalanced state, that is, the positive half-bus voltage is less than the negative half-bus voltage, if the three-level converter is a three-level inverter, the basic voltage vectors with negative common-mode voltage are used to synthesize the target voltage vector; if the three-level converter is a three-level rectifier, the basic voltage vectors with positive common-mode voltage are used to synthesize the target voltage vector, so that the neutral point voltage can drop and gradually reach the balanced state; thus, the problem of unbalanced neutral point potential of the three-level converter can be solved. Description of the Drawings

[0039] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0040] Figure 1 is the implementation flowchart of the neutral point balance control method for the three-level converter provided by the embodiment of the present application;

[0041] Figure 2 is the space vector diagram of the three-level converter provided by the embodiment of the present application;

[0042] Figure 3 is the schematic diagram of the first space vector hexagon and the first triangle provided by the embodiment of the present application;

[0043] Figure 4 is the schematic diagram of the control signals of the three phases when synthesizing the target voltage vector by using the three basic voltage vectors with zero common-mode voltage corresponding to the first target area provided by the embodiment of the present application;

[0044] Figure 5 is the schematic diagram of the second space vector hexagon, the second triangle and the third triangle provided by the embodiment of the present application;

[0045] Figure 6 is the schematic diagram of the control signals of the three phases when synthesizing the target voltage vector by using the three basic voltage vectors with the first voltage as the common-mode voltage corresponding to the second target area provided by the embodiment of the present application;

[0046] Figure 7 is the schematic diagram of the second space vector hexagon, the fourth triangle and the fifth triangle provided by the embodiment of the present application;

[0047] Figure 8 is the schematic diagram of the control signals of the three phases when synthesizing the target voltage vector by using the three basic voltage vectors with the second voltage as the common-mode voltage corresponding to the third target area provided by the embodiment of the present application;

[0048] Figure 9 is the schematic diagram of the control signals of the three phases corresponding to the three basic voltage vectors with zero common-mode voltage under different sorting methods provided by the embodiment of the present application;

[0049] Figure 10 is the structural schematic diagram of the neutral point balance control device for the three-level converter provided by the embodiment of the present application;

[0050] Figure 11 is the schematic diagram of the control device provided by the embodiment of the present application. Detailed implementation manners

[0051] In the following description, specific details such as specific system architectures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. However, those skilled in the art should clearly understand that the present application can also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to avoid unnecessary details from interfering with the description of the present application.

[0052] To make the objectives, technical solutions, and advantages of the present application clearer, the following will be described through specific embodiments in conjunction with the accompanying drawings.

[0053] Refer to Figure 1 , which shows the implementation flowchart of the neutral point balance control method for a three-level converter provided by the embodiments of the present application, and is described in detail as follows:

[0054] In S101, obtain the neutral point voltage state and the target voltage vector of the three-level converter.

[0055] The neutral point voltage state of the three-level converter is used to indicate whether the potential of the neutral point on the DC side of the three-level converter is in a balanced state, and may include a first unbalanced state, a second unbalanced state, or a balanced state.

[0056] Among them, the balanced state means that the potential of the neutral point on the DC side of the three-level converter is in a balanced state, that is, the positive half-bus voltage of the three-level converter is equal to the negative half-bus voltage of the three-level converter. The positive half-bus voltage is the voltage between the positive DC bus of the three-level converter and its DC side neutral point, that is, the voltage across the first capacitor between the positive DC bus and the DC side neutral point. The negative half-bus voltage is the voltage between the DC side neutral point of the three-level converter and its negative DC bus, that is, the voltage across the second capacitor between the DC side neutral point and the negative DC bus.

[0057] Both the first unbalanced state and the second unbalanced state are unbalanced states, that is, the positive half-bus voltage of the three-level converter is not equal to the negative half-bus voltage of the three-level converter. The first unbalanced state means that the positive half-bus voltage of the three-level converter is greater than the negative half-bus voltage of the three-level converter. The second unbalanced state means that the positive half-bus voltage of the three-level converter is less than the negative half-bus voltage of the three-level converter.

[0058] The target voltage vector of the three-level converter can be understood as the desired voltage vector of the three-level converter, and can be determined according to the desired three-phase voltages of the three-level converter.

[0059] In some possible implementation manners, the three-level converter may be a three-level inverter or a three-level rectifier. The specific type of the three-level inverter or the three-level rectifier is not specifically limited, and any type is acceptable.

[0060] The embodiments of the present application do not specifically limit the specific implementation means for obtaining the neutral point voltage state of the three-level converter, and any implementable means is acceptable.

[0061] Exemplarily, the voltages across the first capacitor and the second capacitor may be collected, and by comparing the magnitude relationship between the voltages across the first capacitor and the second capacitor, the neutral point voltage state of the three-level converter is determined.

[0062] In S102, if the neutral point voltage state is the first unbalanced state, when the three-level converter is a three-level inverter, a basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector; when the three-level converter is a three-level rectifier, a basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector.

[0063] Figure 2 The space vector diagram of the three-level converter is shown. Refer to Figure 2 , there are 27 basic voltage vectors of the three-level converter, which are PPP, OOO, NNN, POO, PPO, OPO, OPP, OOP, POP, ONN, OON, NON, NOO, NNO, ONO, PON, OPN, NPO, NOP, ONP, PNO, PNN, PPN, NPN, NPP, NNP, and PNP respectively. Among the 27 basic voltage vectors, there are 3 zero vectors, 12 small vectors, 6 medium vectors, and 6 large vectors. The 3 zero vectors are PPP, OOO, and NNN respectively; the 12 small vectors are POO, PPO, OPO, OPP, OOP, POP, ONN, OON, NON, NOO, NNO, and ONO respectively; the 6 medium vectors are PON, OPN, NPO, NOP, ONP, and PNO respectively; the 6 large vectors are PNN, PPN, NPN, NPP, NNP, and PNP respectively.

[0064] Among them, the small vectors can also be called short vectors, and the large vectors can also be called long vectors.

[0065] The space vector diagram is divided into six regions by 60°, which are Figure 2 I, II, III, IV, V, and VI shown, and the angle of each sector is 60°.

[0066] The common-mode voltages of the above 27 basic voltage vectors are positive, negative, or zero.

[0067] In the embodiments of the present application, when synthesizing the target voltage vector using the basic voltage vector with a positive common-mode voltage, the phase voltage of the three-level converter will be in the positive level state for a longer time within one cycle. If the three-level converter is a three-level inverter, that is, converting direct current into alternating current and outputting energy from the positive and negative busbars, which is equivalent to drawing energy from the positive and negative DC busbars. At this time, if the midpoint voltage state is the first unbalanced state, that is, the positive half-bus voltage is greater than the negative half-bus voltage, in order to achieve the balance of the DC side midpoint, compared with the negative half-bus, more energy needs to be drawn from the positive half-bus. As mentioned above, when synthesizing the target voltage vector using the basic voltage vector with a positive common-mode voltage, the phase voltage of the three-level converter can be in the positive level state for a longer time within one cycle, which is equivalent to drawing energy from the positive half-bus for a longer time and from the negative half-bus for a shorter time within one cycle. Thus, the positive half-bus voltage and the negative half-bus voltage can gradually become equal, and the DC side midpoint of the three-level inverter reaches the balanced state.

[0068] When synthesizing the target voltage vector using the basic voltage vector with a negative common-mode voltage, the phase voltage of the three-level converter will be in the negative level state for a longer time within one cycle. If the three-level converter is a three-level rectifier, that is, converting alternating current into direct current and inputting energy from the outside to the positive and negative busbars, which is equivalent to delivering energy to the positive and negative DC busbars. At this time, if the midpoint voltage state is the first unbalanced state, that is, the positive half-bus voltage is greater than the negative half-bus voltage, in order to achieve the balance of the DC side midpoint, compared with the positive half-bus, more energy needs to be delivered to the negative half-bus. As mentioned above, when synthesizing the target voltage vector using the basic voltage vector with a negative common-mode voltage, the phase voltage of the three-level converter can be in the negative level state for a longer time within one cycle, which is equivalent to delivering energy to the negative half-bus for a longer time and to the positive half-bus for a shorter time within one cycle. Thus, the positive half-bus voltage and the negative half-bus voltage can gradually become equal, and the DC side midpoint of the three-level rectifier reaches the balanced state.

[0069] In S103, if the midpoint voltage state is the second unbalanced state, when the three-level converter is a three-level inverter, use the basic voltage vector with a negative common-mode voltage to synthesize the target voltage vector; when the three-level converter is a three-level rectifier, use the basic voltage vector with a positive common-mode voltage to synthesize the target voltage vector.

[0070] Among them, the first unbalanced state is the state where the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is the state where the positive half-bus voltage is less than the negative half-bus voltage.

[0071] In an embodiment of the present application, when the three-level converter is a three-level inverter, it converts direct current into alternating current, and the positive and negative busbars output energy, which is equivalent to extracting energy from the positive and negative DC busbars. At this time, if the midpoint voltage state is the second unbalanced state, that is, the positive half-bus voltage is less than the negative half-bus voltage, in order to achieve the balance of the DC side midpoint, compared with the positive half-bus, more energy needs to be extracted from the negative half-bus. As described above, using the basic voltage vector with a negative common-mode voltage for target voltage vector synthesis can make the phase voltage of the three-level converter be in the negative level state for more time in a cycle, which is equivalent to extracting energy from the negative half-bus for more time and from the positive half-bus for less time in a cycle. Thus, the positive half-bus voltage and the negative half-bus voltage can be gradually made equal, and the DC side midpoint of the three-level inverter reaches the balanced state.

[0072] When the three-level converter is a three-level rectifier, it converts alternating current into direct current, and external energy is input to the positive and negative busbars, which is equivalent to delivering energy to the positive and negative DC busbars. At this time, if the midpoint voltage state is the second unbalanced state, that is, the positive half-bus voltage is less than the negative half-bus voltage, in order to achieve the balance of the DC side midpoint, compared with the negative half-bus, more energy needs to be delivered to the positive half-bus. As described above, using the basic voltage vector with a positive common-mode voltage for target voltage vector synthesis can make the phase voltage of the three-level converter be in the positive level state for more time in a cycle, which is equivalent to delivering energy to the positive half-bus for more time and to the negative half-bus for less time in a cycle. Thus, the positive half-bus voltage and the negative half-bus voltage can be gradually made equal, and the DC side midpoint of the three-level rectifier reaches the balanced state.

[0073] In an embodiment of the present application, when the midpoint voltage state of the three-level converter is the first unbalanced state, that is, the positive half-bus voltage is greater than the negative half-bus voltage, if the three-level converter is a three-level inverter, the basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector; if the three-level converter is a three-level rectifier, the basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector, so that the midpoint voltage can rise and gradually reach the balanced state. When the midpoint voltage state of the three-level converter is the second unbalanced state, that is, the positive half-bus voltage is less than the negative half-bus voltage, if the three-level converter is a three-level inverter, the basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector; if the three-level converter is a three-level rectifier, the basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector, so that the midpoint voltage can drop and gradually reach the balanced state. Thus, the problem of the midpoint potential imbalance of the three-level converter can be solved, and further, the equipment life and the waveform quality of the three phases of the equipment can be improved.

[0074] The above embodiments introduce the implementation process of the neutral point balance control method for a three-level converter. However, the neutral point voltage state of the three-level converter includes not only the above-mentioned first unbalanced state and second unbalanced state, but also a balanced state. Next, how to synthesize the target voltage vector in the balanced state will be continued to be introduced so that the three-level converter can maintain the balanced state.

[0075] In some embodiments, after the above S101, the neutral point balance control method for the three-level converter may further include:

[0076] If the neutral point voltage state is a balanced state, a basic voltage vector with a zero common-mode voltage is used to synthesize the target voltage vector.

[0077] When the neutral point voltage state of the three-level converter is in a balanced state, whether it is a three-level inverter or a three-level rectifier, only need to keep this state. At this time, a basic voltage vector with a zero common-mode voltage can be used to synthesize the target voltage vector. Because when using a basic voltage vector with a zero common-mode voltage to synthesize the target voltage vector, within one cycle, the energy drawn from the positive half-bus by the three-level inverter is equal to the energy drawn from the negative half-bus, and the energy input to the positive half-bus by the three-level rectifier is equal to the energy input to the negative half-bus. Therefore, whether it is a three-level inverter or a three-level converter, when the neutral point voltage is in a balanced state, using a basic voltage vector with a zero common-mode voltage to synthesize the target voltage vector can keep the voltage at the DC side neutral point unchanged.

[0078] In the embodiments of the present application, when the neutral point voltage state of the three-level converter is in a balanced state, a basic voltage vector with a zero common-mode voltage is used to synthesize the target voltage vector, which can keep the DC side neutral point of the three-level converter in a balanced state all the time, and thus can improve the lifespan of the three-level converter and the waveform quality of the three phases. In addition, using basic voltage vectors with zero common-mode voltages to synthesize the target voltage vector can keep the common-mode voltage of the three-level converter unchanged within a single switching cycle, which can alleviate or eliminate the leakage current caused by the common-mode voltage, and thus can weaken the electromagnetic interference and reduce the possibility of the electromagnetic interference affecting the normal operation of the three-level converter, as well as reduce the cost of electromagnetic compatibility (EMC).

[0079] Next, the specific implementation process of using a basic voltage vector with a zero common-mode voltage to synthesize the target voltage vector will be introduced in detail.

[0080] In some embodiments, using a basic voltage vector with a zero common-mode voltage to synthesize the target voltage vector may include:

[0081] Obtain the first target area where the target voltage vector is located;

[0082] Synthesize the target voltage vector by using three basic voltage vectors with zero common-mode voltage corresponding to the first target region;

[0083] Among them, the six non-zero basic voltage vectors with zero common-mode voltage are used as vertices to form the first space vector hexagon; the first space vector hexagon is divided into six first triangles; the first target region is the region where one of the first triangles is located.

[0084] In a three-level converter, there are 7 basic voltage vectors with zero common-mode voltage, namely PON, OPN, NPO, NOP, ONP, PNO, and OOO, that is, it includes six medium vectors and one zero vector. These six medium vectors are the six non-zero basic voltage vectors with zero common-mode voltage mentioned above.

[0085] See Figure 3 , Figure 3 The difference between the space vector diagram shown in Figure 2 and the space vector diagram shown in Figure 3 is that the space vector diagram in Figure 3 shows 25 basic voltage vectors, and in Figure 3 the zero vector only includes OOO, and the zero vectors PPP and NNN are removed, that is, only the zero vector with zero common-mode voltage among the 3 zero vectors is retained.

[0086] See Figure 3 , the six non-zero basic voltage vectors with zero common-mode voltage, that is, the six medium vectors, are used as six vertices to form the first space vector hexagon. That is, the first space vector hexagon is the hexagon with the above six medium vectors as vertices. The first space vector hexagon is a regular hexagon, and its center point is the zero vector OOO with zero common-mode voltage mentioned above.

[0087] The first space vector hexagon can be divided into six first triangles by dividing it by 60 degrees. The three vertices of each first triangle are two adjacent vertices of the first space vector hexagon and the center point of the first space vector hexagon. The six first triangles are the triangles with PON, OPN, and OOO as three vertices, the triangles with NPO, OPN, and OOO as three vertices, the triangles with NPO, NOP, and OOO as three vertices, the triangles with NOP, ONP, and OOO as three vertices, the triangles with ONP, PNO, and OOO as three vertices, and the triangles with PNO, PON, and OOO as three vertices.

[0088] In the embodiments of the present application, the region where the target voltage vector is located in the above-mentioned first space vector hexagon is referred to as the first target region. The first target region can be any region where a first triangle is located and is determined according to the position of the target voltage vector. The three basic voltage vectors corresponding to the first target region with zero common-mode voltage are the basic voltage vectors corresponding to the three vertices of the first triangle corresponding to the first target region.

[0089] Exemplarily, assuming that the first target region is a triangle with PON, OPN, and OOO as the three vertices, then the three basic voltage vectors corresponding to the first target region with zero common-mode voltage are PON, OPN, and OOO; assuming that the first target region is a triangle with NPO, OPN, and OOO as the three vertices, then the three basic voltage vectors corresponding to the first target region with zero common-mode voltage are NPO, OPN, and OOO; assuming that the first target region is a triangle with PNO, PON, and OOO as the three vertices, then the three basic voltage vectors corresponding to the first target region with zero common-mode voltage are PNO, PON, and OOO; and so on.

[0090] In some possible implementation manners, synthesizing the target voltage vector by using the three basic voltage vectors corresponding to the first target region with zero common-mode voltage may include:

[0091] Obtain the modulation waves and carrier fundamental waves of the three phases of the three-level converter;

[0092] Shift the carrier fundamental wave of one of the phases by half a cycle and keep the carrier fundamental waves of the remaining two phases unchanged to obtain the carriers of the three phases;

[0093] Compare the modulation wave of each phase with the corresponding carrier to generate a control signal to control the three-level converter.

[0094] Among them, the modulation wave of the first phase includes the first modulation wave, the modulation wave of the second phase includes the second modulation wave, and the modulation wave of the third phase includes the first modulation wave and the second modulation wave;

[0095] Comparing the modulation wave of each phase with the corresponding carrier to generate a control signal includes:

[0096] Compare the first modulation wave with the carrier of the first phase to generate the control signal of the first phase;

[0097] Compare the second modulation wave with the carrier of the second phase to generate the control signal of the second phase;

[0098] Compare the first modulation wave and the second modulation wave with the carrier of the third phase at the same time to generate the control signal of the third phase;

[0099] Among them, the first phase, the second phase, and the third phase are different phases and are randomly the A phase, the B phase, and the C phase.

[0100] The carrier wave of each phase of the three-level converter is two carrier waves, one of which is used to switch between O and P, and the other is used to switch between O and N.

[0101] Exemplarily, it is assumed that the target voltage vector is synthesized by using PNO, PON, and OOO. Refer to Figure 4 , Ma is the modulation wave of the first phase, that is, the above-mentioned first modulation wave, Ma = Msinwt, M is the modulation ratio, w is the angular frequency, and t is the time; Mb is the modulation wave of the second phase, that is, the above-mentioned second modulation wave, Mb = Msin(wt - 2*π / 3); Mc1 and Mc2 are the modulation waves of the third phase, Mc1 = Mb, Mc2 = Ma. The fundamental wave of the carrier wave of the first phase is phase-shifted by half a cycle, and the fundamental waves of the carrier waves of the other two phases remain unchanged.

[0102] After the first modulation wave is compared with the carrier wave of the first phase, the control signal of the first phase generated is OPPPO. After the second modulation wave is compared with the carrier wave of the second phase, the control signal of the second phase generated is OONOO. After the first modulation wave and the second modulation wave are simultaneously compared with the carrier wave of the third phase, the control signal of the third phase generated is ONONO.

[0103] It should be noted that in Figure 4 , only one carrier wave of each phase is drawn, that is, only the carrier wave that intersects with the corresponding modulation wave of each phase is drawn, and the other carrier wave is not drawn. However, in actual applications, there are two carrier waves corresponding to each phase.

[0104] In addition, the embodiments of the present application give the specific implementation manners of synthesizing the target voltage vector by using the basic voltage vectors with zero common-mode voltage. However, in the related art, any achievable manner can be used to implement the above-mentioned synthesis of the target voltage vector by using the basic voltage vectors with zero common-mode voltage, and no specific limitation is made here.

[0105] Next, the specific implementation means of synthesizing the target voltage vector by using the basic voltage vectors with negative common-mode voltage will be continued to be introduced.

[0106] In some embodiments, the above-mentioned synthesis of the target voltage vector by using the basic voltage vectors with negative common-mode voltage includes:

[0107] Using the basic voltage vectors with the common-mode voltage being the first voltage to synthesize the target voltage vector; the first voltage is less than 0.

[0108] Among them, the first voltage can be -V DC / 6, and V DC is the DC bus voltage of the three-level converter.

[0109] When the midpoint voltage state of the three-level rectifier is in the first unbalanced state, or when the midpoint voltage state of the three-level inverter is in the second unbalanced state, the basic voltage vectors with the same negative common-mode voltage and the same first voltage are used to synthesize the target voltage vector. This can not only make the midpoint gradually reach the balanced state, but also keep the common-mode voltage of the three-level converter unchanged within a single switching cycle, which can alleviate or eliminate the leakage current caused by the common-mode voltage, thereby weakening the electromagnetic interference and reducing the possibility of the electromagnetic interference affecting the normal operation of the three-level converter, as well as reducing the electromagnetic compatibility cost.

[0110] In some embodiments, the above-mentioned method of using the basic voltage vectors with the same common-mode voltage as the first voltage to synthesize the target voltage vector includes:

[0111] Obtain the second target region where the target voltage vector is located;

[0112] Use the three basic voltage vectors with the same common-mode voltage as the first voltage corresponding to the second target region to synthesize the target voltage vector;

[0113] Among them, the three basic voltage vectors with the same common-mode voltage as the first voltage, which are the vertices of the second space vector hexagon, form the second triangle; the second triangle is divided into four third triangles; the second target region is the region where one of the third triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0114] See Figure 5 , Figure 5 The difference between the space vector diagram shown in Figure 2 and the space vector diagram shown in Figure 5 is that the space vector diagram in Figure 5 shows 19 basic voltage vectors; Figure 5 In DC / 6 and V DC / 6 of the small vectors.

[0115] See Figure 5, the second space vector hexagon is a hexagon with 6 large vectors as its 6 vertices, that is, a hexagon with PNN, PPN, NPN, NPP, NNP, and PNP as its vertices. Among the six vertices of the second space vector hexagon, the common-mode voltages of the basic voltage vectors corresponding to three vertices are the first voltage, which are PNN, NPN, and NNP respectively, and these three vertices serve as the three vertices of the second triangle. The second triangle can be divided into four equilateral triangles with equal sizes and non-overlapping regions. Both the second triangle and the third triangles are equilateral triangles.

[0116] See Figure 5 , the four third triangles are respectively triangles with NPN, NOO, and OON as three vertices, triangles with NOO, OON, and ONO as three vertices, triangles with NOO, ONO, and NNP as three vertices, and triangles with OON, ONO, and PNN as three vertices.

[0117] Among them, the common-mode voltages of the basic voltage vectors corresponding to the three vertices of the second triangle and each third triangle are all the first voltage, that is, -V DC / 6.

[0118] In the embodiments of this application, the region where the target voltage vector is located in the above-mentioned second triangle is called the second target region. The second target region can be the region where any one of the third triangles is located and is determined according to the position of the target voltage vector. The three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage are the basic voltage vectors corresponding to the three vertices of the third triangle corresponding to the second target region.

[0119] Exemplarily, assume that the second target region is the third triangle with NPN, NOO, and OON as three vertices. Then the three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage are NPN, NOO, and OON; assume that the second target region is the third triangle with NOO, OON, and ONO as three vertices. Then the three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage are NOO, OON, and ONO; assume that the second target region is the third triangle with NOO, ONO, and NNP as three vertices. Then the three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage are NOO, ONO, and NNP; assume that the second target region is the third triangle with OON, ONO, and PNN as three vertices. Then the three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage are OON, ONO, and PNN; and so on.

[0120] In some possible implementation manners, synthesizing the target voltage vector by using the three basic voltage vectors corresponding to the second target region with the common-mode voltage being the first voltage may include:

[0121] Obtain the fundamental modulation wave and fundamental carrier wave of the three phases of the three-level converter;

[0122] Add the first zero-sequence component to the fundamental modulation waves of the three phases to obtain the modulation waves of the three phases;

[0123] Shift the fundamental carrier wave of one of the phases by half a cycle, and keep the fundamental carrier waves of the remaining two phases unchanged to obtain the carriers of the three phases;

[0124] Compare the modulation wave of each phase with the corresponding carrier to generate a control signal to control the three-level converter.

[0125] Among them, the modulation wave of the first phase includes the third modulation wave, the modulation wave of the second phase includes the fourth modulation wave, and the modulation wave of the third phase includes the third modulation wave and the fourth modulation wave;

[0126] Comparing the modulation wave of each phase with the corresponding carrier to generate a control signal includes:

[0127] Compare the third modulation wave with the carrier of the first phase to generate the control signal of the first phase;

[0128] Compare the fourth modulation wave with the carrier of the second phase to generate the control signal of the second phase;

[0129] Compare the third modulation wave and the fourth modulation wave with the carrier of the third phase at the same time to generate the control signal of the third phase;

[0130] Among them, the first phase, the second phase, and the third phase are different phases, and are randomly the A phase, the B phase, and the C phase.

[0131] The first zero-sequence component can be -1 / 3.

[0132] Exemplarily, assume that NOO, OON, and ONO are used to synthesize the target voltage vector. Refer to Figure 6 , Ma1 is the modulation wave of the first phase, that is, the above-mentioned third modulation wave, Ma1 = Msinwt - 1 / 3; Mb1 is the modulation wave of the second phase, that is, the above-mentioned fourth modulation wave, Mb1 = Msin(wt - 2*π / 3) - 1 / 3; Mc3 and Mc4 are the modulation waves of the third phase, Mc3 = Ma1, Mc4 = Mb1. Shift the fundamental carrier wave of the first phase by half a cycle, and keep the fundamental carrier waves of the other two phases unchanged.

[0133] After comparing the third modulation wave with the carrier of the first phase, the control signal of the first phase generated is NOOON. After comparing the fourth modulation wave with the carrier of the second phase, the control signal of the second phase generated is OONOO. After comparing the third modulation wave and the fourth modulation wave with the carrier of the third phase at the same time, the control signal of the third phase generated is ONONO.

[0134] It should be noted that in Figure 6 only one carrier wave of each phase is drawn, that is, only the carrier wave of each phase that intersects with the corresponding modulation wave is drawn, and the other carrier wave is not drawn. However, in actual applications, there are two carrier waves corresponding to each phase.

[0135] It should be noted that the embodiments of the present application give specific implementation manners of synthesizing a target voltage vector by using a basic voltage vector with a negative common-mode voltage. However, in related technologies, any achievable manner can be used to implement the above-mentioned synthesis of a target voltage vector by using a basic voltage vector with a negative common-mode voltage, and specific limitations are not made here.

[0136] Next, the specific implementation means of synthesizing a target voltage vector by using a basic voltage vector with a positive common-mode voltage will be continued to be introduced.

[0137] In some embodiments, the above-mentioned synthesis of a target voltage vector by using a basic voltage vector with a positive common-mode voltage includes:

[0138] Using basic voltage vectors with common-mode voltages all being a second voltage to synthesize a target voltage vector; the second voltage is greater than 0.

[0139] Among them, the second voltage can be V DC / 6.

[0140] When the midpoint voltage state of the three-level inverter in the embodiments of the present application is the first unbalanced state, or the midpoint voltage state of the three-level rectifier is the second unbalanced state, using basic voltage vectors with common-mode voltages all being positive and all being the second voltage to synthesize a target voltage vector can not only make the midpoint gradually reach the balanced state, but also keep the common-mode voltage of the three-level converter unchanged within a single switching period, which can alleviate or eliminate the leakage current caused by the common-mode voltage, and further weaken the electromagnetic interference and reduce the possibility of the three-level converter being affected by electromagnetic interference and the electromagnetic compatibility cost.

[0141] In some embodiments, the above-mentioned synthesis of a target voltage vector by using basic voltage vectors with common-mode voltages all being the second voltage includes:

[0142] Obtain the third target area where the target voltage vector is located;

[0143] Use three basic voltage vectors with common-mode voltages corresponding to the third target area and all being the second voltage to synthesize a target voltage vector;

[0144] Among them, the three common-mode voltages that are the vertices of the second space vector hexagon are the basic voltage vectors of the second voltage, forming a fourth triangle; the fourth triangle is divided into four fifth triangles; the third target region is the region where one of the fifth triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0145] See Figure 7 , Figure 7 The basic voltage vectors shown in the space vector diagram shown are the same as Figure 5 the basic voltage vectors shown in the space vector diagram shown.

[0146] See Figure 7 The second space vector hexagon is a hexagon with 6 large vectors as 6 vertices, that is, a hexagon with PNN, PPN, NPN, NPP, NNP, and PNP as vertices. Among the six vertices of the second space vector hexagon, the common-mode voltages of the basic voltage vectors corresponding to three vertices are the second voltage, which are PPN, NPP, and PNP respectively. These three vertices are the three vertices of the fourth triangle. The fourth triangle can be divided into four equilateral triangles with equal size and non-overlapping regions. Both the fourth triangle and the fifth triangle are equilateral triangles.

[0147] See Figure 7 The four fifth triangles are respectively the triangle with PPN, POO, and OPO as three vertices, the triangle with POO, OPO, and OOP as three vertices, the triangle with NPP, OPO, and OOP as three vertices, and the triangle with PNP, POO, and OOP as three vertices.

[0148] Among them, the common-mode voltages of the basic voltage vectors corresponding to the three vertices of the fourth triangle and each fifth triangle are all the second voltage, that is, V DC / 6.

[0149] In the embodiment of the present application, the region where the target voltage vector is located in the above-mentioned fourth triangle is called the third target region. The third target region can be the region where any one of the fifth triangles is located, and is determined according to the position of the target voltage vector. The three basic voltage vectors with the common-mode voltage of the second voltage corresponding to the third target region are the basic voltage vectors corresponding to the three vertices of the fifth triangle corresponding to the third target region.

[0150] Exemplarily, assuming that the third target region is the third triangle with PPN, POO, and OPO as three vertices, then the three common-mode voltages corresponding to the third target region and the basic voltage vectors of the second voltage are PPN, POO, and OPO; assuming that the third target region is the third triangle with POO, OPO, and OOP as three vertices, then the three common-mode voltages corresponding to the third target region and the basic voltage vectors of the second voltage are POO, OPO, and OOP; assuming that the third target region is the third triangle with NPP, OPO, and OOP as three vertices, then the three common-mode voltages corresponding to the third target region and the basic voltage vectors of the second voltage are NPP, OPO, and OOP; assuming that the third target region is the third triangle with PNP, POO, and OOP as three vertices, then the three common-mode voltages corresponding to the third target region and the basic voltage vectors of the second voltage are PNP, POO, and OOP; and so on.

[0151] In some possible implementation manners, the above-mentioned method of synthesizing the target voltage vector by using the three common-mode voltages corresponding to the third target region as the basic voltage vectors of the second voltage may include:

[0152] Obtain the fundamental modulation wave and the fundamental carrier wave of the three phases of the three-level converter;

[0153] Add the second zero-sequence component to the fundamental modulation waves of the three phases to obtain the modulation waves of the three phases;

[0154] Shift the fundamental carrier wave of one phase by half a cycle and keep the fundamental carrier waves of the remaining two phases unchanged to obtain the carriers of the three phases;

[0155] Compare the modulation waves of each phase with the corresponding carriers to generate control signals for controlling the three-level converter.

[0156] Among them, the modulation wave of the first phase includes the fifth modulation wave, the modulation wave of the second phase includes the sixth modulation wave, and the modulation wave of the third phase includes the fifth modulation wave and the sixth modulation wave;

[0157] Comparing the modulation waves of each phase with the corresponding carriers to generate control signals includes:

[0158] Compare the fifth modulation wave with the carrier of the first phase to generate the control signal of the first phase;

[0159] Compare the sixth modulation wave with the carrier of the second phase to generate the control signal of the second phase;

[0160] Compare the fifth modulation wave and the sixth modulation wave with the carrier of the third phase at the same time to generate the control signal of the third phase;

[0161] Among them, the first phase, the second phase, and the third phase are different phases and are randomly the A phase, the B phase, and the C phase.

[0162] The second zero-sequence component can be 1 / 3.

[0163] Exemplarily, it is assumed that the OPO, PPN, and POO are used to synthesize the target voltage vector. Refer to Figure 8 , Ma2 is the modulation wave of the first phase, that is, the above-mentioned fifth modulation wave, Ma2 = Msinwt + 1 / 3; Mb2 is the modulation wave of the second phase, that is, the above-mentioned sixth modulation wave, Mb2 = Msin(wt - 2*π / 3) + 1 / 3; Mc5 and Mc6 are the modulation waves of the third phase, Mc5 = Mb2, Mc6 = Ma2. The fundamental wave of the carrier of the first phase is phase-shifted by half a cycle, and the fundamental waves of the carriers of the other two phases remain unchanged.

[0164] After the fifth modulation wave is compared with the carrier of the first phase, the control signal of the first phase generated is OPPP0. After the sixth modulation wave is compared with the carrier of the second phase, the control signal of the second phase generated is PPOPP. After the fifth modulation wave and the sixth modulation wave are simultaneously compared with the carrier of the third phase, the control signal of the third phase generated is ONONO.

[0165] It should be noted that in Figure 8 , only one carrier of each phase is drawn, that is, only the carrier of each phase that intersects with the corresponding modulation wave is drawn, and the other carrier is not drawn. However, in actual applications, there are two carriers corresponding to each phase.

[0166] It should be noted that the embodiments of the present application give the specific implementation manners of synthesizing the target voltage vector by using the basic voltage vectors with positive common-mode voltages. However, in the related art, any achievable manner can be used to implement the above-mentioned synthesis of the target voltage vector by using the basic voltage vectors with positive common-mode voltages, and no specific limitation is made here.

[0167] In some embodiments, during the process of synthesizing the target voltage vector, the phase with the minimum current or the maximum current among the three phases of the three-level converter is selected as the phase with the most switching times within one cycle.

[0168] The number of switching times within one cycle can be understood as the number of times of switching between O and P within one cycle or the number of times of switching between O and N within one cycle. Among them, the cycle can be the switching cycle.

[0169] Refer to Figure 9 , there is a phenomenon that the number of switching times of one phase among the control signals of the three phases is more than the number of switching times of the other two phases within one cycle. It is assumed that the three control signals from top to bottom are the control signal of phase A, the control signal of phase B, and the control signal of phase C, respectively. Figure 9 Among the control signals of the three phases on the left, the number of switching times of the control signal of phase A is 4, and the number of switching times of the control signals of phase B and phase C is 2. Figure 9Among the control signals of the three phases in the middle, the switching times of the control signal of phase C are 4, and the switching times of the control signals of phases A and B are 2. Figure 9 Among the control signals of the three phases on the right, the switching times of the control signal of phase B are 4, and the switching times of the control signals of phases A and C are 2.

[0170] By the sorting method of each basic voltage vector for synthesizing the target voltage vector, the switching times of different phases within one cycle can be changed.

[0171] Exemplarily, refer to Figure 9 , taking the synthesis of the target voltage vector with three basic voltage vectors PON, OOO, and PNO respectively as an example. If the sorting of the three basic voltage vectors is PON, OOO, PNO, OOO, and PON, then the control signals of the three phases are Figure 9 The control signal on the left, and the phase with the most switching times within one cycle is phase A. If the sorting of the three basic voltage vectors is OOO, PON, PNO, PON, and OOO, then the control signals of the three phases are Figure 9 The control signal in the middle, and the phase with the most switching times within one cycle is phase C. If the sorting of the three first basic voltage vectors is PON, PNO, OOO, PNO, and PON, then the control signals of the three phases are Figure 9 The control signal on the right, and the phase with the most switching times within one cycle is phase B.

[0172] In the embodiment of the present application, the phase with the smallest current among the three phases can be selected as the phase with the most switching times within one cycle. Since the larger the current, the greater the switching loss, therefore, selecting the phase with the smallest current as the phase with the most switching times within one cycle can reduce the switching loss and achieve the optimal efficiency. Among them, the above-mentioned phase with the smallest current can be the phase with the smallest instantaneous current value among the three phases.

[0173] If there are two phases with the most switching times of the control signals within one cycle, the phase with the smallest current and the phase with the second smallest current can be selected as these two phases to reduce the switching loss.

[0174] In another implementation manner, the phase with the largest current among the three phases can be selected as the phase with the most switching times within one cycle, so that the current ripple of this phase can be minimized, and further optimize the quality of the output current. Specifically, the point with the largest current ripple amplitude is usually at the current peak, and the phase with the largest current has a larger ripple due to the large saturation degree of the magnetic powder core inductor. Therefore, selecting the phase with the largest current as the phase with the most switching times within one cycle can optimize the current ripple of this phase, and further optimize the quality of the output current. Among them, the above-mentioned phase with the largest current can be the phase with the largest instantaneous current value among the three phases.

[0175] If the number of switching times of the control signals of two phases is the largest within one period, the phase with the largest current and the phase with the second largest current can be selected as these two phases to optimize the quality of the output current.

[0176] Specifically, whether to select the phase with the largest current or the phase with the smallest current as the phase with the largest number of switching times within one period can be determined according to actual requirements.

[0177] It should be understood that the magnitudes of the sequence numbers of the steps in the above embodiments do not imply the order of execution. The order of execution of each process should be determined according to its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0178] The following is the device embodiment of the present application. For the details not described in detail, reference can be made to the corresponding method embodiments above.

[0179] Figure 10 The structural schematic diagram of the neutral point balance control device of the three-level converter provided by the embodiment of the present application is shown. For the convenience of description, only the parts related to the embodiment of the present application are shown and are described in detail as follows:

[0180] As Figure 10 shown, the three-level converter neutral point balance control device 4 includes: an acquisition module 41, a first control module 42, and a second control module 43.

[0181] The acquisition module 41 is configured to acquire the neutral point voltage state and the target voltage vector of the three-level converter;

[0182] The first control module 42 is configured to, if the neutral point voltage state is the first unbalanced state, when the three-level converter is a three-level inverter, use the basic voltage vector with a positive common-mode voltage to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, use the basic voltage vector with a negative common-mode voltage to synthesize the target voltage vector;

[0183] The second control module 43 is configured to, if the neutral point voltage state is the second unbalanced state, when the three-level converter is a three-level inverter, use the basic voltage vector with a negative common-mode voltage to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, use the basic voltage vector with a positive common-mode voltage to synthesize the target voltage vector;

[0184] Wherein, the first unbalanced state is the state where the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is the state where the positive half-bus voltage is less than the negative half-bus voltage.

[0185] In a possible implementation manner, the three-level converter neutral point balance control device 4 further includes: a third control module.

[0186] The third control module is configured to, if the midpoint voltage state is in a balanced state, synthesize a target voltage vector by using a basic voltage vector with a zero common-mode voltage.

[0187] In a possible implementation manner, in the third control module, synthesizing a target voltage vector by using a basic voltage vector with a zero common-mode voltage includes:

[0188] Obtain a first target region where the target voltage vector is located;

[0189] Synthesize the target voltage vector by using three basic voltage vectors with a zero common-mode voltage corresponding to the first target region;

[0190] Among them, the points where the six non-zero basic voltage vectors with a zero common-mode voltage are located are used as vertices to form a first space vector hexagon; the first space vector hexagon is divided into six first triangles; the first target region is the region where one of the first triangles is located.

[0191] In a possible implementation manner, in the first control module 42 and the second control module 43, synthesizing a target voltage vector by using a basic voltage vector with a negative common-mode voltage includes:

[0192] Synthesize the target voltage vector by using basic voltage vectors with a first voltage for the common-mode voltage; the first voltage is less than 0;

[0193] In the first control module 42 and the second control module 43, synthesizing a target voltage vector by using a basic voltage vector with a positive common-mode voltage includes:

[0194] Synthesize the target voltage vector by using basic voltage vectors with a second voltage for the common-mode voltage; the second voltage is greater than 0.

[0195] In a possible implementation manner, in the first control module 42 and the second control module 43, synthesizing a target voltage vector by using basic voltage vectors with a first voltage for the common-mode voltage includes:

[0196] Obtain a second target region where the target voltage vector is located;

[0197] Synthesize the target voltage vector by using three basic voltage vectors with a first voltage for the common-mode voltage corresponding to the second target region;

[0198] Among them, three basic voltage vectors with a first voltage for the common-mode voltage that are vertices of a second space vector hexagon form a second triangle; the second triangle is divided into four third triangles; the second target region is the region where one of the third triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0199] In a possible implementation manner, in the first control module 42 and the second control module 43, basic voltage vectors with a common-mode voltage of the second voltage are used to synthesize a target voltage vector, including:

[0200] Obtain a third target area where the target voltage vector is located;

[0201] Use three basic voltage vectors corresponding to the third target area and having a common-mode voltage of the second voltage to synthesize the target voltage vector;

[0202] Among them, three basic voltage vectors with a common-mode voltage of the second voltage and serving as the vertices of the second space vector hexagon form a fourth triangle; the fourth triangle is divided into four fifth triangles; the third target area is the area where one of the fifth triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

[0203] In a possible implementation manner, during the process of synthesizing the target voltage vector, select the phase with the minimum current or the maximum current among the three phases of the three-level converter as the phase with the most switching times within one cycle.

[0204] Figure 11 It is a schematic diagram of the control device provided by the embodiments of the present application. As Figure 11 shown, the control device 5 of this embodiment includes: a processor 50 and a memory 51. The memory 51 stores a computer program 52. When the processor 50 executes the computer program 52, the steps in the above-mentioned various method embodiments are implemented. Alternatively, when the processor 50 executes the computer program 52, the functions of each module / unit in the above-mentioned various device embodiments are implemented.

[0205] Exemplarily, the computer program 52 can be divided into one or more modules / units. The one or more modules / units are stored in the memory 51 and executed by the processor 50 to complete the present application. The one or more modules / units can be a series of computer program instruction segments capable of performing specific functions, and the instruction segments are used to describe the execution process of the computer program 52 in the control device 5.

[0206] The control device 5 may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art can understand that Figure 11 merely examples of the control device 5 do not constitute a limitation on the control device 5, and it may include more or fewer components than shown in the figure, or combine certain components, or different components. For example, the control device 5 may further include input / output devices, network access devices, buses, etc.

[0207] The processor 50 may be a Central Processing Unit (CPU), or may also be other general-purpose processors, Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor, or the processor may also be any conventional processor, etc.

[0208] The memory 51 may be an internal storage unit of the control device 5, such as the hard disk or memory of the control device 5. The memory 51 may also be an external storage device of the control device 5, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. equipped on the control device 5. Further, the memory 51 may also include both the internal storage unit and the external storage device of the control device 5. The memory 51 is used to store the computer program 52 and other programs and data required by the control device 5. The memory 51 may also be used to temporarily store the data that has been output or will be output.

[0209] For the convenience and simplicity of description, only the above-mentioned division of each functional module / unit is used as an example. In actual applications, the above functions can be assigned to different functional modules / units according to needs. The above modules / units can be implemented in the form of hardware, can also be implemented in the form of software, or can be implemented in the form of a combination of hardware and software.

[0210] The embodiment of the present application further provides a three-level converter, including conversion units corresponding to three phases respectively and the control device as described above; the conversion units are controlled by the control device. Among them, the control device can be used to execute any one of the above-mentioned neutral point balance control methods of the three-level converter.

[0211] Among them, the three-level converter may be a three-level inverter or a three-level rectifier.

[0212] Exemplarily, if the three-level converter is a three-level inverter, the method executed by the control device included therein may be the aforementioned three-level converter neutral point balance control method, or a method associated with the three-level inverter. For example, if the neutral point voltage state is the first unbalanced state, a basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector; if the neutral point voltage state is the second unbalanced state, a basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector.

[0213] If the three-level converter is a three-level rectifier, the method executed by the control device included therein may be the aforementioned three-level converter neutral point balance control method, or a method associated with the three-level rectifier. For example, if the neutral point voltage state is the first unbalanced state, a basic voltage vector with a negative common-mode voltage is used to synthesize the target voltage vector; if the neutral point voltage state is the second unbalanced state, a basic voltage vector with a positive common-mode voltage is used to synthesize the target voltage vector.

[0214] An embodiment of the present application further provides a power supply device, including the above three-level converter.

[0215] An embodiment of the present application further provides a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the methods in the above method embodiments are implemented.

[0216] An embodiment of the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the methods in the above method embodiments are implemented.

[0217] Among them, the computer program includes computer program code, and the computer program code may be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, USB flash drive, mobile hard disk, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signal, telecommunication signal, and software distribution medium, etc.

[0218] In the above embodiments, the descriptions of the respective embodiments have their own emphases. For parts not detailed or recorded in a certain embodiment, reference may be made to the relevant descriptions of other embodiments. Without special instructions and logical conflicts, the terms and / or descriptions between different embodiments are consistent and can be mutually referred to, and the technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0219] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A three-level converter midpoint balance control method, characterized in that: include: Obtaining a midpoint voltage state and a target voltage vector of a three-level converter; If the midpoint voltage state is a first unbalanced state, when the three-level converter is a three-level inverter, a basic voltage vector with a positive common mode voltage is used to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, a basic voltage vector with a negative common mode voltage is used to synthesize the target voltage vector; If the midpoint voltage state is a second unbalanced state, when the three-level converter is a three-level inverter, a basic voltage vector with a negative common mode voltage is used to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, a basic voltage vector with a positive common mode voltage is used to synthesize the target voltage vector; The first unbalanced state is a state where the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is a state where the positive half-bus voltage is less than the negative half-bus voltage.

2. The three-level converter midpoint balance control method according to claim 1, characterized in that: After acquiring the midpoint voltage state and the target voltage vector of the three-level converter, the method further includes: If the midpoint voltage state is a balanced state, a basic voltage vector with a common mode voltage of zero is used to synthesize the target voltage vector.

3. The three-level converter midpoint balance control method according to claim 2, characterized in that: The step of using a basic voltage vector with a common mode voltage of zero to synthesize the target voltage vector includes: Acquire a first target area where the target voltage vector is located; Using three basic voltage vectors with a common mode voltage of zero corresponding to the first target area to synthesize the target voltage vector; Among them, the points where the six non-zero basic voltage vectors with zero common mode voltage are located are used as vertices to form a first space vector hexagon; the first space vector hexagon is divided into six first triangles; and the first target area is the area where one of the first triangles is located.

4. The three-level converter neutral point balance control method according to any one of claims 1 to 3, characterized in that: The step of using a basic voltage vector with a negative common mode voltage to synthesize the target voltage vector includes: The target voltage vector is synthesized by using basic voltage vectors whose common mode voltages are all a first voltage; the first voltage is less than 0; The step of using a basic voltage vector with a positive common mode voltage to synthesize the target voltage vector includes: The target voltage vector is synthesized by using basic voltage vectors whose common mode voltages are all a second voltage; the second voltage is greater than zero.

5. The three-level converter midpoint balance control method according to claim 4, characterized in that: The step of synthesizing the target voltage vector by using a basic voltage vector whose common mode voltages are all the first voltage comprises: Acquire a second target area where the target voltage vector is located; Using three common mode voltages corresponding to the second target area as basic voltage vectors of the first voltage to synthesize the target voltage vector; Among them, the three common-mode voltages that are the vertices of the second space vector hexagon are the basic voltage vectors of the first voltage, forming a second triangle; the second triangle is divided into four third triangles; the second target area is the area where one of the third triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

6. The three-level converter midpoint balance control method according to claim 4, characterized in that: The basic voltage vectors whose common mode voltages are all the second voltage are used to synthesize the target voltage vector, including: Acquire a third target area where the target voltage vector is located; Using three common mode voltages corresponding to the third target area as basic voltage vectors of the second voltage to synthesize the target voltage vector; Among them, the three common-mode voltages that are the vertices of the second space vector hexagon are the basic voltage vectors of the second voltage, forming a fourth triangle; the fourth triangle is divided into four fifth triangles; the third target area is the area where one of the fifth triangles is located; the second space vector hexagon is the outer hexagon in the space vector diagram of the three-level converter.

7. The three-level converter midpoint balance control method according to claim 2, characterized in that: In the process of synthesizing the target voltage vector, the phase with the smallest current or the phase with the largest current among the three phases of the three-level converter is selected as the phase with the largest number of switching times in one cycle.

8. A three-level converter midpoint balance control device, characterized in that: include: An acquisition module, used for acquiring a midpoint voltage state and a target voltage vector of a three-level converter; a first control module, configured to, if the midpoint voltage state is a first unbalanced state, synthesize the target voltage vector by using a basic voltage vector having a positive common mode voltage when the three-level converter is a three-level inverter, and synthesize the target voltage vector by using a basic voltage vector having a negative common mode voltage when the three-level converter is a three-level rectifier; A second control module is used for, if the midpoint voltage state is a second unbalanced state, then when the three-level converter is a three-level inverter, using a basic voltage vector with a negative common-mode voltage to synthesize the target voltage vector, and when the three-level converter is a three-level rectifier, using a basic voltage vector with a positive common-mode voltage to synthesize the target voltage vector; wherein the first unbalanced state is a state in which the positive half-bus voltage is greater than the negative half-bus voltage, and the second unbalanced state is a state in which the positive half-bus voltage is less than the negative half-bus voltage.

9. A three-level converter, characterized in that: It comprises conversion units and control devices corresponding to the three phases respectively; the control device is used to execute the three-level converter midpoint balance control method as described in any one of claims 1 to 7; the conversion unit is controlled by the control device.

10. A power supply device, characterized in that: Comprising the three-level converter as claimed in claim 9.

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