Inverter and voltage control method thereof

Abstract

The invention provides an inverter and a voltage control method thereof, and belongs to the technical field of power electronics. The inverter comprises a balance bridge arm, a switch bridge arm, two capacitors, a first inductor and a control circuit. The two capacitors are connected in series between the positive bus and the negative bus, and each pair of output ports is connected with a series connection node (namely the middle point of the bus) of the two capacitors. The control circuit can obtain the DCV component of a target output port in the multiple pairs of output ports and the bus voltage difference between the positive bus and the negative bus, and can output a balance modulation signal to the balance bridge arm when the bus voltage difference is larger than or equal to a first voltage threshold value and smaller than or equal to a second voltage threshold value. The balance bridge arm is controlled to reduce the DCV component of the target output port to be within a target range by adjusting the current flowing through the first inductor, so that the bus voltage difference is reduced to be smaller than a first voltage threshold value. That is, the bus voltage difference can be reduced, so that the voltages on the positive and negative buses can be balanced.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and particularly relates to an inverter and its voltage control method. Background Art

[0002] An inverter is a converter used to convert direct current (DC) into alternating current (AC).

[0003] An inverter is usually connected to a photovoltaic panel and a load respectively, and is used to convert the DC power from the photovoltaic panel into AC power and then transmit it to the load to supply power to the load. An inverter generally includes: two capacitors and a switching bridge arm. Among them, the two capacitors are connected in series between the positive bus and the negative bus (i.e., the positive and negative buses), and the series connection node of the two capacitors is also called the bus midpoint. The switching bridge arm is connected to the positive bus and the negative bus respectively, and the switching bridge arm has multiple output terminals, and each output terminal and the bus midpoint form a pair of output ports. The inverter is connected to the load through multiple pairs of output ports.

[0004] Ideally, the voltage difference between the positive and negative buses is small, that is, the voltages on the positive and negative buses are relatively balanced. However, in practical applications, due to the unbalanced loads carried by multiple pairs of output ports, the generated unbalanced current will flow into the bus midpoint, resulting in voltage imbalance on the positive and negative buses. Summary of the Invention

[0005] This application provides an inverter and its voltage control method, which can solve the technical problem of voltage imbalance on the positive and negative buses in the related art.

[0006] In a first aspect, an inverter is provided. The inverter has multiple pairs of output ports, and the inverter includes: a balanced bridge arm, a switching bridge arm, two capacitors, a first inductor, and a control circuit; the two capacitors are connected in series between a positive bus and a negative bus, and a series node between the two capacitors is the midpoint of the bus; the positive bus and the negative bus are used to connect a DC power supply device; the balanced bridge arm is respectively connected to the positive bus and the negative bus, and is connected to the midpoint of the bus through the first inductor; the switching bridge arm is respectively connected to the positive bus and the negative bus, and the switching bridge arm has multiple output terminals, and each output terminal among the multiple output terminals forms a pair of the output ports with the midpoint of the bus; the control circuit is configured to: obtain a DC voltage (DCV) component of a target output port among multiple pairs of the output ports, and a bus voltage difference between the positive bus and the negative bus; when the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, output a first balanced modulation signal to the balanced bridge arm, and the first balanced modulation signal is used to control the balanced bridge arm to adjust the current flowing through the first inductor to reduce the DCV component of the target output port to within a target range.

[0007] That is, the control circuit can control the balanced bridge arm to adjust the DCV component of the target output port. Since the target output port is connected to the midpoint of the bus, by controlling the balanced bridge arm through the control circuit to adjust the DCV component of the target output port, the purpose of adjusting the voltage at the midpoint of the bus can be achieved. Moreover, by reducing the DCV component of the target output port to within a target range, the bus voltage difference can be made less than the first voltage threshold, that is, the bus voltage difference can be reduced, so that the voltages on the positive and negative buses are more balanced.

[0008] Optionally, the control circuit can also be configured to: when the bus voltage difference is greater than or equal to a third voltage threshold, output a second balanced modulation signal to the balanced bridge arm, and the second balanced modulation signal is used to control the balanced bridge arm to adjust the current flowing through the first inductor to reduce the bus voltage difference; wherein, the third voltage threshold is greater than the second voltage threshold.

[0009] That is to say, when the bus voltage difference is even larger, the control circuit can still output a second balanced modulation signal to the balanced bridge arm to directly reduce the bus voltage difference, making the voltages on the positive and negative buses balanced. After that, if the bus voltage difference is still greater than or equal to the first voltage threshold and less than or equal to the second voltage threshold, the control circuit can further control the balanced bridge arm to adjust the DCV component of the target output port to further reduce the bus voltage difference, making the voltages on the positive and negative buses more balanced. In this way, it can ensure better accuracy in adjusting the bus voltage difference and higher adjustment efficiency.

[0010] Optionally, the control circuit can also be used to: when the bus voltage difference increases from being less than or equal to the second voltage threshold to being greater than the second voltage threshold and less than the third voltage threshold, output the first balance modulation signal to the balance bridge arm; when the bus voltage difference decreases from being greater than or equal to the third voltage threshold to being less than the third voltage threshold and greater than the second voltage threshold, output the second balance modulation signal to the balance bridge arm.

[0011] That is to say, after the control circuit outputs the first balance modulation signal to the balance bridge arm, if the bus voltage difference changes again to be greater than the second voltage threshold and less than the third voltage threshold, the control circuit can continue to output the first balance modulation signal to the balance bridge arm to balance the voltages on the positive and negative buses. After the control circuit outputs the second balance modulation signal to the balance bridge arm, if the bus voltage difference changes again to be greater than the second voltage threshold and less than the third voltage threshold, the control circuit can continue to output the second balance modulation signal to the balance bridge arm to balance the voltages on the positive and negative buses.

[0012] Optionally, the balance bridge arm can include: two first switching tubes; the two first switching tubes can be connected in series between the positive bus and the negative bus, and the series connection node of the two first switching tubes can be connected to the first inductor.

[0013] It can be seen therefrom that the first balance modulation signal can be used to control the conduction and cutoff of the two first switching tubes to adjust the current output to the first inductor, so as to achieve the purpose of adjusting the DCV component of the target output port or the bus voltage difference to balance the voltages on the positive and negative buses.

[0014] Optionally, the switching bridge arm can have two such output terminals; correspondingly, the inverter can have two pairs of output ports, that is, the inverter can be a single-phase inverter. The switching bridge arm can include: two second switching tubes, two third switching tubes and two fourth switching tubes; the two second switching tubes can be connected in series between the positive bus and the negative bus, and the series connection node of the two second switching tubes can correspond to one of the two output terminals; the two third switching tubes can be connected in series between the positive bus and the negative bus, and the series connection node of the two third switching tubes can correspond to the other of the two output terminals; the two fourth switching tubes can be connected in series between the two output terminals.

[0015] Optionally, the control circuit may include: a first sampling circuit and a second sampling circuit; the first sampling circuit may be respectively connected to the positive bus, the negative bus, and the control circuit; the second sampling circuit may be respectively connected to the target output port and the control circuit; the first sampling circuit may be configured to: collect the bus voltage difference; the second sampling circuit may be configured to: collect the DCV component of the target output port; the control circuit may be configured to: obtain the bus voltage difference through the first sampling circuit and obtain the DCV component of the target output port through the second sampling circuit.

[0016] Optionally, both the first sampling sub-circuit and the second sampling sub-circuit may include: at least one sampling resistor.

[0017] Optionally, the inverter may further include: a plurality of second inductors corresponding one-to-one to the plurality of output terminals of the switching bridge arm; each second inductor of the plurality of second inductors may be connected to a corresponding one of the output terminals; and, the second inductor and the first inductor may both be coupled inductors.

[0018] Since the bus voltage difference and the DCV component of the target output port can be adjusted by outputting a balance modulation signal to the balance bridge arm through the control circuit, the selection of inductors in the inverter can be made more flexible. For example, a coupled inductor can be used in the hardware structure instead of a discrete inductor with a higher cost, which can reduce the hardware cost.

[0019] In a second aspect, a voltage control method for an inverter is provided. The inverter has multiple pairs of output ports, and the inverter includes: a balance bridge arm, a switching bridge arm, two capacitors, and a first inductor; the two capacitors are connected in series between the positive bus and the negative bus, and the series connection node between the two capacitors is the bus midpoint; the positive bus and the negative bus are used to connect a DC power supply device; the balance bridge arm is respectively connected to the positive bus and the negative bus, and is connected to the bus midpoint through the first inductor; the switching bridge arm is respectively connected to the positive bus and the negative bus, and the switching bridge arm has multiple output terminals, and each output terminal of the multiple output terminals forms a pair of the output ports with the bus midpoint; the method includes: obtaining the DC voltage DCV component of a target output port among the multiple pairs of output ports of the inverter, and the bus voltage difference between the positive bus and the negative bus; when the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, outputting a first balance modulation signal to the balance bridge arm, where the first balance modulation signal is used to control the balance bridge arm to adjust the current flowing through the first inductor to reduce the DCV component of the target output port to a target range.

[0020] Optionally, the method may further include: when the bus voltage difference is greater than or equal to a third voltage threshold, outputting a second balance modulation signal to the balance bridge arm, where the second balance modulation signal is used to control the balance bridge arm to adjust the current flowing through the first inductor so as to reduce the bus voltage difference; wherein, the third voltage threshold is greater than the second voltage threshold.

[0021] Optionally, the method may further include: when the bus voltage difference increases from being less than or equal to the second voltage threshold to being greater than the second voltage threshold and less than the third voltage threshold, outputting the first balance modulation signal to the balance bridge arm; when the bus voltage difference decreases from being greater than or equal to the third voltage threshold to being less than the third voltage threshold and greater than the second voltage threshold, outputting the second balance modulation signal to the balance bridge arm.

[0022] In summary, the present application provides an inverter and its voltage control method. The inverter has multiple pairs of output ports, and the inverter includes: a balance bridge arm, a switching bridge arm, two capacitors, a first inductor, and a control circuit. The two capacitors are connected in series between the positive and negative buses, and each pair of output ports is connected to the series node of the two capacitors (i.e., the bus midpoint). The control circuit can obtain the DCV component of the target output port among the multiple pairs of output ports and the bus voltage difference between the positive and negative buses, and can output a balance modulation signal to the balance bridge arm when the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, so as to control the balance bridge arm to reduce the DCV component of the target output port to the target range by adjusting the current flowing through the first inductor, so that the bus voltage difference is reduced to less than the first voltage threshold. That is, the bus voltage difference can be reduced, so that the voltages on the positive and negative buses can be balanced. Description of the Drawings

[0023] Figure 1 is a schematic structural diagram of a power supply system provided by an embodiment of the present application;

[0024] Figure 2 is a schematic structural diagram of an inverter provided by an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of the working process of a control circuit in an inverter provided by an embodiment of the present application;

[0026] Figure 4 is a schematic structural diagram of another inverter provided by an embodiment of the present application;

[0027] Figure 5 is a schematic flowchart of a voltage control method of an inverter provided by an embodiment of the present application;

[0028] Figure 6 is a schematic flowchart of another voltage control method of an inverter provided by an embodiment of the present application. Detailed implementation manners

[0029] The following describes in detail the inverter and its voltage control method provided by the embodiments of the present application with reference to the accompanying drawings. First, key terms related to the embodiments of the present application are introduced.

[0030] Inverter: Also known as a power converter, it is used to convert direct current (DC) provided by a photovoltaic panel (also known as a solar panel) or other DC power sources (such as a battery) into alternating current (AC) to supply power to the connected load. The inverter can be, for example, a single-phase hybrid inverter.

[0031] Power grid: The overall combination of substations and power transmission and distribution lines with various voltages in a power system, also known as the public power grid.

[0032] Off-grid operation of the inverter: When there is no voltage provided by the power grid, the inverter directly supplies the converted alternating current (AC) to the load to supply power to the load.

[0033] The inverter and its voltage control method provided by the embodiments of the present application are applied to a power supply system. As Figure 1 shown, the power supply system includes: a power supply device 10 and an inverter 00. Optionally, the inverter 00 can be a single-phase hybrid inverter.

[0034] Among them, the power supply device 10 is connected to the inverter 00, and the inverter 00 is also used to connect to the load 20.

[0035] Moreover, the power supply device 10 is used to provide a power supply voltage to the inverter 00, and the inverter 00 is used to supply power to the load 20 based on the power supply voltage.

[0036] Exemplarily, the power supply device 10 can include a plurality of photovoltaic panels or batteries connected in series and parallel to each other. The power supply voltage provided by the power supply device 10 can be a direct current (DC) voltage, and the inverter 00 can convert the DC voltage into an alternating current (AC) voltage and then transmit it to the load 20 to supply power to the load 20. That is, the power supply device 10 can be a DC power supply device.

[0037] It can be understood that the inverter 00 described in the embodiments of the present application operates off-grid. That is, as Figure 1 can be seen, the inverter 00 can operate independently of the power grid without performing power interaction with the power grid (indicated by a dashed line in the figure). Correspondingly, it can also be known that the establishment of a connection between the inverter 00 and the power grid for power interaction can also be referred to as grid-connected operation of the inverter.

[0038] Affected by the unbalanced load carried by the inverter 00, the voltages on the positive and negative buses in the inverter 00 are unbalanced. The embodiments of the present application provide an inverter that can ensure a small voltage difference between the buses, thereby better balancing the voltages on the positive and negative buses.

[0039] As Figure 2 shown, the inverter 00 provided by the embodiment of the present application has multiple pairs of output ports, and the inverter 00 includes: a balance bridge arm 01, a switching bridge arm 02, two capacitors C1 and C2, a first inductor L1, and a control circuit 03.

[0040] Among them, the two capacitors C1 and C2 are connected in series between the positive bus BUS+ and the negative bus BUS- (i.e., the positive and negative buses described above), and the series connection node N between the two capacitors C1 and C2 is the midpoint of the bus; the positive bus BUS+ and the negative bus BUS- are used to connect to a DC power supply device.

[0041] The balance bridge arm 01 is respectively connected to the positive bus BUS+ and the negative bus BUS-, and is connected to the bus midpoint N through the first inductor L1.

[0042] The switching bridge arm 02 is respectively connected to the positive bus BUS+ and the negative bus BUS-, and the switching bridge arm 02 has multiple output terminals, and each output terminal among the multiple output terminals can form a pair of output ports with the bus midpoint N. Thus, multiple output terminals can form multiple pairs of output ports with the bus midpoint N.

[0043] The control circuit 03 is configured to:

[0044] Obtain the DCV component of the target output port among multiple pairs of output ports, and the bus voltage difference between the positive bus BUS+ and the negative bus BUS-.

[0045] When the bus voltage difference is greater than or equal to the first voltage threshold Z and less than or equal to the second voltage threshold Y, output a first balance modulation signal to the balance bridge arm 01.

[0046] Among them, the first balance modulation signal is used to control the balance bridge arm 01 to adjust the current flowing through the first inductor L1, so as to reduce the DCV component of the target output port to the target range. That is, the first balance modulation signal can be used to control the balance bridge arm 01 to adjust the DCV component of the target output port. Since the target output port is connected to the bus midpoint N, the bus voltage difference can be adjusted by adjusting the DCV component of the target output port. And, in the embodiment of the present application, after reducing the DCV component of the target output port to the target range, the bus voltage difference can be made less than the first voltage threshold Z, thereby making the voltages on the positive and negative buses balanced.

[0047] Optionally, the first voltage threshold Z, the second voltage threshold Y, and the target range can all be pre-stored in the control circuit 03. And the units of the first voltage threshold Z and the second voltage threshold Y can both be volts (V), and the unit of the DCV component in the target range can be millivolts (mV).

[0048] It can be understood that, with reference to Figure 2 , the control circuit 03 is respectively connected to the positive bus bar BUS+, the negative bus bar BUS-, the balancing bridge arm 01, and the target output port among multiple pairs of output ports, so as to obtain the DCV component of the target output port and the bus voltage difference, and output a first balancing modulation signal to the balancing bridge arm 01 based on the bus voltage difference.

[0049] Moreover, by way of example, as Figure 2 shown, the switching bridge arm 02 in the inverter 00 shown therein has two output terminals U and W. Among them, one output terminal U and the bus midpoint N can form a pair of output ports UO; the other output terminal W and the bus midpoint N can form another pair of output ports WO. That is, the two output terminals U and W can form two pairs of output ports UO and WO with the bus midpoint N. The terminal O connected to the bus midpoint N in the two pairs of output ports UO and WO can be obtained by splitting the output terminals U and W. Correspondingly, when the DCV component between the output terminals U and W is fixed, adjusting the DCV component of one output port in the two pairs of output ports UO and WO can achieve the adjustment of the DCV component of the other output port. Therefore, in the embodiment of the present application, the control circuit 03 is connected to a pair of target output ports (such as the output port UO or the output port WO) in the two pairs of output ports UO and WO, and is used to adjust the DCV component of the pair of target output ports. The inverter with this structure is the single-phase hybrid inverter described above.

[0050] Optionally, continuing to refer to Figure 1 it can be seen that both the balancing bridge arm 01 and the switching bridge arm 02 can include multiple switching tubes. The switching tube can be, for example, an insulated gate bipolar transistor (IGBT) or a metal-oxide-semiconductor field-effect transistor (MOSFET), etc. The embodiment of the present application does not limit the type of the switching tube.

[0051] It can be understood that, in the embodiment of the present application, the first balancing modulation signal output by the control circuit 03 can be used to control the conduction and cut-off of multiple switching tubes in the balancing bridge arm 01, so as to achieve the purpose of adjusting the DCV component of the target output port.

[0052] In summary, the embodiments of the present disclosure provide an inverter. The inverter has multiple pairs of output ports and includes: a balancing bridge arm, a switching bridge arm, two capacitors, a first inductor, and a control circuit. The two capacitors are connected in series between the positive and negative buses, and each pair of output ports is connected to the series node of the two capacitors (i.e., the midpoint of the buses). The control circuit can obtain the DCV component of the target output port among the multiple pairs of output ports and the bus voltage difference between the positive and negative buses, and can output a balancing modulation signal to the balancing bridge arm when the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, so as to control the balancing bridge arm to reduce the DCV component of the target output port to a target range by adjusting the current flowing through the first inductor, so that the bus voltage difference is reduced to less than the first voltage threshold. That is, the bus voltage difference can be reduced, so that the voltages on the positive and negative buses can be balanced. This adjustment method can adjust the bus voltage difference more precisely.

[0053] Optionally, the control circuit 03 can also be used for:

[0054] When the bus voltage difference is greater than or equal to a third voltage threshold X, output a second balancing modulation signal to the balancing bridge arm 01. The second balancing modulation signal can be used to control the balancing bridge arm 01 to adjust the current flowing through the first inductor L1 to reduce the bus voltage difference. For example, the bus voltage difference is reduced to less than the third voltage threshold X. That is, the second balancing modulation signal can be used to control the balancing bridge arm 01 to directly adjust the bus voltage difference. Wherein, the third voltage threshold X can be greater than the second voltage threshold Y.

[0055] It can be understood that, similar to the first balancing modulation signal, the second balancing modulation signal output by the control circuit 03 can also be used to control the conduction and cutoff of multiple switching tubes in the balancing bridge arm 01, so as to achieve the purpose of controlling the voltage of the bus midpoint N. Since the bus midpoint N is actually the series node of two capacitors C1 and C2 connected in series between the positive and negative buses, the purpose of adjusting the bus voltage difference can be achieved.

[0056] It can be understood that when the first balancing modulation signal or the second balancing modulation signal controls the switching tubes in the balancing bridge arm 01 to conduct, it can output current to the first inductor L1 to charge the first inductor L1. When the first balancing modulation signal or the second balancing modulation signal controls the switching tubes in the balancing bridge arm 01 to cutoff, it can stop outputting current to the first inductor L1. At this time, the first inductor L1 can discharge. When the first inductor L1 discharges, it can adjust the voltage of the bus midpoint N, so as to achieve the purpose of adjusting the DCV component of the target output port or the bus voltage difference.

[0057] Optionally, the third voltage threshold X can also be pre-stored in the control circuit 03. And the unit of the third voltage threshold X can be V.

[0058] It can be understood that since the third voltage threshold X is greater than the second voltage threshold Y, and the second voltage threshold Y is greater than the first voltage threshold Z, the third voltage threshold X can also be greater than the first voltage threshold Z. That is, X > Y > Z. For example, the first voltage threshold Z can be 1V; the second voltage threshold Y can be 10V, and the third voltage threshold X can be 30V.

[0059] Based on the above analysis, it can be seen that in the above optional embodiment, after the control circuit 03 controls the balance bridge arm 01 through the second balance modulation signal to reduce the bus voltage difference to less than the third voltage threshold X, if the bus voltage difference is less than or equal to the second voltage threshold Y and greater than or equal to the first voltage threshold Z, the control circuit 03 can further output the first balance modulation signal to the balance bridge arm 01 to control the balance bridge arm 01 to further reduce the bus voltage difference to less than the first voltage threshold Z. Since the first voltage threshold Z is less than the third voltage threshold X, the voltages on the positive and negative buses can be better balanced.

[0060] It can be understood that the control circuit 03 outputs the second balance modulation signal to the balance bridge arm 01 to control the balance bridge arm 01 to directly reduce the bus voltage difference, which can be considered a rough adjustment method for balancing the voltages on the positive and negative buses. The control circuit 03 outputs the first balance modulation signal to the balance bridge arm 01 to control the balance bridge arm 01 to indirectly reduce the bus voltage difference by reducing the DCV component of the target output port, which belongs to a further fine adjustment method for balancing the voltages on the positive and negative buses.

[0061] That is to say, in the embodiment of the present application, the control circuit 03 can not only select to directly control the balance bridge arm 01 to reduce the DCV component of the target output port for fine adjustment to balance the voltages on the positive and negative buses, but also select to first control the balance bridge arm 01 to directly reduce the bus voltage difference for rough adjustment to make the voltages on the positive and negative buses relatively balanced, and then control the balance bridge arm 01 to reduce the DCV component of the target output port for fine adjustment to make the voltages on the positive and negative buses more balanced. That is, the control circuit 03 in the embodiment of the present application can select to only fine-tune, or first rough-tune and then fine-tune to reduce the bus voltage difference to balance the voltages on the positive and negative buses.

[0062] As can be seen from the foregoing description, compared with some embodiments where the voltage balance between the positive and negative buses is roughly adjusted only by directly reducing the bus voltage difference, on the one hand, in the embodiments of the present application, the voltage balance between the positive and negative buses is finely adjusted by directly reducing the DCV component of the target output port, with better adjustment fineness and enabling better voltage balance between the positive and negative buses. On the other hand, in the embodiments where the voltage balance between the positive and negative buses is roughly adjusted only by reducing the bus voltage difference, it generally takes multiple adjustments to achieve voltage balance between the positive and negative buses, with a slow adjustment process and poor dynamic response. Therefore, in the embodiments of the present application, the control circuit 03 cooperates with the balance bridge arm 01 to first roughly reduce the bus voltage difference to balance the voltage between the positive and negative buses, and then further reduce the DCV component of the target output port to finely adjust and balance the voltage between the positive and negative buses, which can make the voltage between the positive and negative buses reach balance faster and more reliably, that is, not only with better adjustment accuracy, but also with higher adjustment efficiency and better dynamic response.

[0063] Further optionally, the control circuit 03 can also be used for:

[0064] When the bus voltage difference increases from less than or equal to the second voltage threshold Y to greater than the second voltage threshold Y and less than the third voltage threshold X, output a first balance modulation signal to the balance bridge arm 01.

[0065] When the bus voltage difference decreases from greater than or equal to the third voltage threshold X to less than the third voltage threshold X and greater than the second voltage threshold Y, output a second balance modulation signal to the balance bridge arm 01.

[0066] It can be understood that since the control circuit 03 outputs a first balance modulation signal to the balance bridge arm 01 to balance the voltage between the positive and negative buses when the bus voltage difference is greater than or equal to the first voltage threshold Z and less than or equal to the second voltage threshold Y. Therefore, when the bus voltage difference increases from less than or equal to the second voltage threshold Y to greater than the second voltage threshold Y and less than the third voltage threshold X, it can refer to the situation where after the control circuit 03 outputs a first balance modulation signal to the balance bridge arm 01, the bus voltage difference becomes greater than the second voltage threshold Y and less than the third voltage threshold X, and the reason for this situation is mostly due to an additional load. In this case, the control circuit 03 can be used to continue to output a first balance modulation signal to the balance bridge arm 01 to balance the voltage between the positive and negative buses.

[0067] Similarly, since the control circuit 03 outputs a second balance modulation signal to the balance bridge arm 01 when it is greater than or equal to the third voltage threshold X to balance the voltages on the positive and negative buses. Therefore, when the bus voltage difference decreases from being greater than or equal to the third voltage threshold X to being less than the third voltage threshold X and greater than the second voltage threshold Y, it may mean: after the control circuit 03 outputs the second balance modulation signal to the balance bridge arm 01, the bus voltage difference becomes greater than the second voltage threshold Y and less than the third voltage threshold X. In this case, the control circuit 03 can be used to continue to output the second balance modulation signal to the balance bridge arm 01 to balance the voltages on the positive and negative buses.

[0068] That is, in the embodiment of the present application, when the bus voltage difference is greater than the second voltage threshold Y and less than the third voltage threshold X, the control circuit 03 can output to the balance bridge arm 01 the balance modulation signal output to the balance circuit 01 before the bus voltage difference changes to be greater than the second voltage threshold Y and less than the third voltage threshold X. It may be the first balance modulation signal or the second balance modulation signal. Of course, if the bus voltage difference is greater than the second voltage threshold Y and less than the third voltage threshold X when the control circuit 03 first detects the bus voltage difference, the control circuit 03 can be used to output any one of the first balance modulation signal and the second balance modulation signal to the balance bridge arm 01.

[0069] Exemplarily, for the embodiment where the bus voltage difference is greater than the second voltage threshold Y and less than the third voltage threshold X, in the embodiment of the present application, the control circuit 03 can also be used for:

[0070] When the bus voltage difference is greater than or equal to the first voltage threshold Z and less than or equal to the second voltage threshold Y, set the control mode flag to the first mode flag A. And this first mode flag A can correspond to the first balance modulation signal.

[0071] Based on the bus voltage difference being greater than or equal to the third voltage threshold X, set the control mode flag to the second mode flag B. And this second mode flag B can correspond to the second balance modulation signal.

[0072] Based on the bus voltage difference being greater than the second voltage threshold Y and less than the third voltage threshold X, output to the balance bridge arm 01 the balance modulation signal corresponding to the control mode flag.

[0073] That is, the control circuit 03 can preset the control mode flag based on the bus voltage difference, so that when the bus voltage difference is between the second voltage threshold Y and the third voltage threshold X, directly output the corresponding balance modulation signal to the balance bridge arm 01 to balance the voltages on the positive and negative buses more quickly.

[0074] Optionally, in the embodiments of the present application, the control mode flag may further include: an initial mode flag C. The control circuit 03 may be configured to: adjust the initial mode flag C to a first mode flag A or a second mode flag B based on the bus voltage difference.

[0075] Optionally, the control mode flag may be identified in binary. For example, the initial mode flag C may be 00; the first mode flag A may be 10; and the second mode flag B may be 01.

[0076] Optionally, in the embodiments of the present application, the control circuit 03 may pre-store the processing logics of the first mode flag A and the second mode flag B, and the processing logics of the two mode flags are different. By executing the processing logic of the first mode flag A, the control circuit 03 may correspondingly output a first balance modulation signal to the balance bridge arm 01, and by executing the processing logic of the second mode flag B, the control circuit 03 may correspondingly output a second balance modulation signal to the balance bridge arm 01. Moreover, when the bus voltage difference is between a third voltage threshold X and a second voltage threshold Y, the control circuit 03 may directly execute the processing logic of the current control mode flag to output a corresponding balance modulation signal to the balance bridge arm 01.

[0077] For example, when the bus voltage difference is between the third voltage threshold X and the second voltage threshold Y, if the current control mode flag is the first mode flag A, the control circuit 03 may output a corresponding first balance modulation signal to the balance bridge arm 01 to control the balance bridge arm 01 to adjust the DCV component of the target output port. If the current control mode flag is the second mode flag B, the control circuit 03 may output a corresponding second balance modulation signal to the balance bridge arm 01 to control the balance bridge arm 01 to adjust the bus voltage difference.

[0078] Optionally, in the embodiments of the present application, the first balance modulation signal may be a pulse width modulation (PWM) signal. The second balance modulation signal may also be a PWM signal. The control circuit 03 outputting the first balance modulation signal and the second balance modulation signal may also be referred to as: PWM wave generation.

[0079] Moreover, it can be understood that the first balance modulation signal and the second balance modulation signal may be different. For example, taking the case where both the first balance modulation signal and the second balance modulation signal are PWM signals, the difference between the two may refer to: different duty cycles of the PWM signals, different frequencies of the PWM signals, and / or different resolutions of the PWM signals.

[0080] In the embodiments of the present application, the control circuit 03 can not only output a corresponding balance modulation signal to the balance bridge arm 01 based on the magnitude of the bus voltage difference, but also output a corresponding balance modulation signal to the balance bridge arm 01 based on the current control mode flag, with better flexibility. Correspondingly, as Figure 3 shown, the control circuit 03 can be used to perform the following steps:

[0081] Step A1: After the control circuit 03 starts to work, obtain the bus voltage difference and the DCV component of the target output port.

[0082] Step A2: Determine whether the bus voltage difference is greater than or equal to the third voltage threshold X; or (marked as "||" in the figure), whether the control mode flag is the second mode flag B.

[0083] Step A3: Determine whether the bus voltage difference is less than or equal to the second voltage threshold Y and greater than or equal to the first voltage threshold Z; or, whether the control mode flag is the first mode flag A.

[0084] Step A4: If the condition in Step A2 is satisfied, switch to the second mode flag B, and output the second balance modulation signal by executing the processing logic of the second mode flag B, that is, perform the PWM wave generation in Step A6.

[0085] Step A5: If the condition in Step A3 is satisfied, switch to the first mode flag A, and output the first balance modulation signal by executing the processing logic of the first mode flag A, that is, perform the PWM wave generation in Step A6.

[0086] It can be understood that in some embodiments, if the control circuit 03 determines the bus voltage difference in Step A2, the control circuit 03 can also first set the control mode flag to (for example, adjust it to) the second mode flag B in Step A4. Then, execute the processing logic of the second mode flag B (that is, switch to the second mode flag B) to output the second balance modulation signal to the balance bridge arm 01.

[0087] Similarly, if the control circuit 03 determines the bus voltage difference in Step A3, the control circuit 03 can also first set the control mode flag to (for example, adjust it to) the first mode flag A in Step A5. Then, execute the processing logic of the first mode flag A (that is, switch to the first mode flag A) to output the first balance modulation signal to the balance bridge arm 01.

[0088] Optionally, the control circuit 03 may not need to set the control mode flag either. Moreover, the control circuit 03 may also directly output a second balance modulation signal to the balance bridge arm 01 based on the bus voltage difference being greater than the second voltage threshold Y and less than the third voltage threshold X. That is, the control circuit 03 may continuously output the second balance modulation signal to the balance bridge arm 01 until the bus voltage difference is less than the second voltage threshold Y.

[0089] Optionally, continue to refer to Figure 2 It can be seen that the balance bridge arm 01 may include: two first switching tubes T11 and T12;

[0090] Among them, the two first switching tubes T11 and T12 may be connected in series between the positive bus BUS+ and the negative bus BUS-, and the series connection node of the two first switching tubes T11 and T12 may be connected to the first inductor L1. For example, the series connection node of the two first switching tubes T11 and T12 may be connected to one end of the first inductor L1, and the other end of the first inductor L1 may be connected to the bus midpoint N.

[0091] It can be understood that the control circuit 03 may be connected to the gates of the two first switching tubes T11 and T12.

[0092] Optionally, continue to refer to Figure 2 It can be seen that the switching bridge arm 02 may have two output terminals U and W. Correspondingly, the inverter 00 may have a pair of output ports UO formed by the output terminal U and the bus midpoint N, and another pair of output ports UO formed by the output terminal W and the bus midpoint N. That is, the inverter 00 may have two pairs of output ports UO and WO. The inverter 00 with this structure may refer to a single-phase inverter. And on this basis, the switching bridge arm 02 may include: two second switching tubes T21 and T22, two third switching tubes T31 and T32, and two fourth switching tubes T41 and T42.

[0093] Among them, the two second switching tubes T21 and T22 may be connected in series between the positive bus BUS+ and the negative bus BUS-, and the series connection node of the two second switching tubes T21 and T22 may correspond to one of the two output terminals U and W. For example, the output terminal U.

[0094] The two third switching tubes T31 and T32 may be connected in series between the positive bus BUS+ and the negative bus BUS-, and the series connection node of the two third switching tubes T31 and T32 corresponds to the other of the two output terminals U and W. For example, the output terminal W.

[0095] The two fourth switching tubes T41 and T42 may be connected in series between the two output terminals U and W.

[0096] Of course, in some embodiments, the switching bridge arm 02 may also have three or more output terminals. Correspondingly, the inverter 00 may also have three or more pairs of output ports. That is, the inverter 00 is not limited to the single-phase inverter described in the embodiments of the present application. And, Figure 2 It is only an example illustration of the structures of the balancing bridge arm 01 and the switching bridge arm 02.

[0097] Optionally, Figure 4 It is a schematic structural diagram of another inverter provided by the embodiments of the present application. As Figure 4 shown, the control circuit 03 may further include: a first sampling circuit 04 and a second sampling circuit 05.

[0098] The first sampling circuit 04 may be respectively connected to the positive bus BUS+, the negative bus BUS−, and the control circuit 03.

[0099] The second sampling circuit 05 may be respectively connected to the target output port (e.g., the output port UO or the output port WO) and the control circuit 03.

[0100] The first sampling circuit 04 may be configured to: collect the bus voltage difference.

[0101] The second sampling circuit 05 may be configured to: collect the DCV component of the target output port.

[0102] The control circuit 03 may be configured to: obtain the bus voltage difference through the first sampling circuit 04, and obtain the DCV component of the target output port through the second sampling circuit 05.

[0103] Optionally, in the embodiments of the present application, both the first sampling circuit 04 and the second sampling circuit 05 may include: at least one sampling resistor.

[0104] Optionally, in the embodiments of the present application, the control circuit 03 may include: a digital signal processor (DSP) chip.

[0105] Optionally, continuing to refer to Figure 2 and Figure 4 it can be seen that the inverter 00 described in the embodiments of the present application may further include: a plurality of second inductors L2 corresponding one-to-one to the multiple output terminals of the switching bridge arm 02. Each of the plurality of second inductors L2 may be connected to a corresponding output terminal. And, the second inductor L2 and the first inductor L1 described above may both be coupled inductors, and both may be used for filtering signals.

[0106] For example, in combination with Figure 2 and Figure 4, on the premise that the inverter 00 includes two output terminals U and W, the inverter 00 may further include: a second inductor L2 connected to the output terminal U, and another second inductor L2 connected to the output terminal W. That is, the inverter 00 may include two second inductors L2.

[0107] It can be understood that in the embodiment of the present application, the inverter 00 may include an inverter-side device and a balance-side device. And, in combination with Figure 2 and Figure 4 , the two capacitors C1 and C2, the switch bridge arm 02, and the multiple second inductors L2 in the inverter 00 may belong to the inverter-side device. The balance bridge arm 01 and the first inductor L1 in the inverter 00 may belong to the balance-side device.

[0108] In some embodiments, it is also considered to replace the second inductor L2 in the inverter-side device with a discrete inductor to directly adjust the DCV component of the target output port through the inverter-side device to balance the voltages on the positive and negative buses. However, compared with the coupled inductor, the hardware cost of the discrete inductor is relatively high, which is not conducive to the mass production of the inverter. It can be seen that by outputting a first balance modulation signal from the control circuit 03 to the balance bridge arm 01 to adjust the DCV component of the target output port, the use of the inductor can be made more flexible. For example, the inverter may not need to be provided with a discrete inductor with a high cost, and correspondingly, the hardware cost of the inverter can be reduced, which is conducive to the mass production of the inverter.

[0109] In summary, the embodiment of the present disclosure provides an inverter, which has multiple pairs of output ports, and the inverter includes: a balance bridge arm, a switch bridge arm, two capacitors, a first inductor, and a control circuit. The two capacitors are connected in series between the positive and negative buses, and each pair of output ports is connected to the series node of the two capacitors (i.e., the midpoint of the bus). The control circuit can obtain the DCV component of the target output port among the multiple pairs of output ports and the bus voltage difference between the positive and negative buses, and can output a balance modulation signal to the balance bridge arm when the bus voltage difference is greater than or equal to the first voltage threshold and less than or equal to the second voltage threshold, so as to control the balance bridge arm to reduce the DCV component of the target output port to the target range by adjusting the current flowing through the first inductor, so that the bus voltage difference is reduced to less than the first voltage threshold. That is, the bus voltage difference can be reduced, so that the voltages on the positive and negative buses can be balanced.

[0110] The embodiment of the present application also provides a voltage control method for an inverter, such as Figure 2 or Figure 4As shown, the inverter 00 has multiple pairs of output ports (e.g., output ports UO and WO), and the inverter 00 includes: a balance bridge arm 01, a switching bridge arm 02, two capacitors C1 and C2, and a first inductor L1. The two capacitors C1 and C2 are connected in series between the positive bus BUS+ and the negative bus BUS-, and the series node between the two capacitors C1 and C2 is the bus midpoint N; the positive bus BUS+ and the negative bus BUS- are used to connect to the DC power supply device 10. The balance bridge arm 01 is respectively connected to the positive bus BUS+ and the negative bus BUS-, and is connected to the bus midpoint N through the first inductor L1. The switching bridge arm 02 is respectively connected to the positive bus BUS+ and the negative bus BUS-, and the switching bridge arm 02 has multiple output terminals (e.g., two output terminals U and W), and each output terminal in the multiple output terminals forms a pair of the output ports with the bus midpoint N. Thus, multiple output terminals can form multiple pairs of output ports with the bus midpoint N. This method can be applied to the control circuit 03 included in the inverter 00. As Figure 5 As shown, the method includes:

[0111] Step 501, obtain the DC voltage DCV component of the target output port among the multiple pairs of output ports of the inverter, and the bus voltage difference between the positive bus and the negative bus.

[0112] Optionally, as Figure 4 As shown, the control circuit 03 may include a first sampling circuit 04, a second sampling circuit 05, and a control circuit 03. Among them, the control circuit 03 can obtain the DCV component of the target output port through the first sampling circuit 04, and can obtain the bus voltage difference through the second sampling circuit 05.

[0113] Step 502, when the bus voltage difference is greater than or equal to the first voltage threshold and less than or equal to the second voltage threshold, output a first balance modulation signal to the balance bridge arm.

[0114] Among them, the first balance modulation signal is used to control the balance bridge arm 01 to adjust the current flowing through the first inductor L1, so as to reduce the DCV component of the target output port to the target range, make the bus voltage difference less than the first voltage threshold, and further make the voltages on the positive and negative buses balanced.

[0115] Optionally, Figure 6 is a flowchart of another voltage control method for an inverter provided by an embodiment of the present application. As Figure 6 As shown, the voltage control method may further include:

[0116] Step 503, when the bus voltage difference is greater than or equal to the third voltage threshold, output a second balance modulation signal to the balance bridge arm.

[0117] Among them, the second balanced modulation signal can be used to control the balanced bridge arm to adjust the current flowing through the first inductor L1, so as to reduce the bus voltage difference. For example, the bus voltage difference is reduced to less than a third voltage threshold. And this third voltage threshold can be greater than the second voltage threshold.

[0118] Optionally, continue to refer to Figure 6 It can be seen that this voltage control method can also include:

[0119] Step 504, when the bus voltage difference increases from being less than or equal to the second voltage threshold to being greater than the second voltage threshold and less than the third voltage threshold, output a first balanced modulation signal to the balanced bridge arm.

[0120] That is, after the control circuit 03 outputs the first balanced modulation signal to the balanced bridge arm 01, if the bus voltage difference becomes greater than the second voltage threshold and less than the third voltage threshold, the control circuit 03 continues to output the first balanced modulation signal to the balanced bridge arm 01 to balance the voltages on the positive and negative buses.

[0121] Step 505, when the bus voltage difference decreases from being greater than or equal to the third voltage threshold to being less than the third voltage threshold and greater than the second voltage threshold, output a second balanced modulation signal to the balanced bridge arm.

[0122] That is, after the control circuit 03 outputs the second balanced modulation signal to the balanced bridge arm 01, if the bus voltage difference becomes greater than the second voltage threshold and less than the third voltage threshold, the control circuit 03 continues to output the second balanced modulation signal to the balanced bridge arm 01 to balance the voltages on the positive and negative buses.

[0123] Combined with Figure 6 , it can be understood that if the bus voltage difference is greater than or equal to the third voltage threshold, the control circuit 03 can first execute step 503 after executing step 501, that is, first output a second balanced modulation signal to the balanced bridge arm 01 to control the balanced bridge arm 01 to directly reduce the bus voltage difference to less than the third voltage threshold, that is, first roughly adjust the bus voltage difference to balance the voltages on the positive and negative buses. Then, if the bus voltage difference is still less than or equal to the second voltage threshold Y and greater than or equal to the first voltage threshold Z, the control circuit 03 can then execute step 502, that is, output a first balanced modulation signal to the balanced bridge arm 01 again to control the balanced bridge arm 01 to reduce the DCV component of the target output port so that the bus voltage difference can be further less than the smaller first voltage threshold Z, that is, further finely adjust the DCV component of the target output port to further balance the voltages on the positive and negative buses.

[0124] And, combined with Figure 6It can also be understood that after the control circuit 03 executes step 503, that is, after outputting the second balanced modulation signal to the balanced bridge arm 01, if the bus voltage difference is greater than the second voltage threshold and less than the third voltage threshold, then step 505 can be executed, that is, the second balanced modulation signal can be continuously output to the balanced bridge arm 01. After the control circuit 03 executes step 502, that is, after outputting the first balanced modulation signal to the balanced bridge arm 01, if the bus voltage difference is greater than the second voltage threshold and less than the third voltage threshold, then step 504 can be executed, that is, the first balanced modulation signal can be continuously output to the balanced bridge arm 01.

[0125] Of course, the order of the steps of the voltage control method provided in the embodiment of the present application can be appropriately adjusted, and the steps can also be increased or decreased accordingly according to the situation. For example, the above steps 504 and 505 can be deleted according to the situation. That is, the control circuit can also directly output a second balanced modulation signal to the balancing bridge arm based on the bus voltage difference being greater than the second voltage threshold and less than the third voltage threshold. Alternatively, step 503 can be deleted according to the situation. That is, the control circuit can directly control the balancing bridge arm to adjust the DCV component of the target output port to fine-tune the bus voltage difference to balance the voltage on the positive and negative buses.

[0126] It can also be understood that since the voltage control method of the inverter has basically the same implementation method and technical effects as the inverter described in the above embodiments, for the purpose of brevity, the implementation method and technical effects of the voltage control method of the inverter will not be repeated here.

[0127] In the embodiments of the present application, the terms "first", "second" and "third" are used for descriptive purposes only and should not be understood as indicating or implying relative importance. The term "at least one" means one or more, and "plurality" means two or more.

[0128] In the embodiments of the present application, the term "and / or" is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0129] The above is only an optional implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. An inverter, characterized in that, The inverter has multiple pairs of output ports, and the inverter includes: a balancing bridge arm, a switching bridge arm, two capacitors, a first inductor, and a control circuit; The two capacitors are connected in series between the positive bus and the negative bus, and the series node between the two capacitors is the midpoint of the bus; the positive bus and the negative bus are used to connect a DC power supply device; The balancing bridge arm is respectively connected to the positive bus and the negative bus, and is connected to the midpoint of the bus through the first inductor; The switching bridge arm is respectively connected to the positive bus and the negative bus, and the switching bridge arm has multiple output terminals, and each output terminal among the multiple output terminals forms a pair of the output ports with the midpoint of the bus; The control circuit is used for: Obtaining the DC voltage (DCV) component of a target output port among multiple pairs of the output ports, and the bus voltage difference between the positive bus and the negative bus; When the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, outputting a first balancing modulation signal to the balancing bridge arm, where the first balancing modulation signal is used to control the balancing bridge arm to adjust the current flowing through the first inductor so as to reduce the DCV component of the target output port to within a target range.

2. The inverter according to claim 1, characterized in that, The control circuit is further used for: When the bus voltage difference is greater than or equal to a third voltage threshold, outputting a second balancing modulation signal to the balancing bridge arm, where the second balancing modulation signal is used to control the balancing bridge arm to adjust the current flowing through the first inductor so as to reduce the bus voltage difference; where the third voltage threshold is greater than the second voltage threshold.

3. The inverter according to claim 2, characterized in that, The control circuit is further used for: When the bus voltage difference increases from being less than or equal to the second voltage threshold to being greater than the second voltage threshold and less than the third voltage threshold, outputting the first balancing modulation signal to the balancing bridge arm; When the bus voltage difference decreases from being greater than or equal to the third voltage threshold to being less than the third voltage threshold and greater than the second voltage threshold, outputting the second balancing modulation signal to the balancing bridge arm.

4. The inverter according to any one of claims 1 to 3, characterized in that, The balancing bridge arm includes: two first switching tubes; The two first switching tubes are connected in series between the positive bus and the negative bus, and the series node of the two first switching tubes is connected to the first inductor.

5. The inverter according to any one of claims 1 to 4, characterized in that, The switching bridge arm has two of the output terminals; the switching bridge arm includes: two second switching tubes, two third switching tubes, and two fourth switching tubes; The two second switching tubes are connected in series between the positive bus and the negative bus, and the series node of the two second switching tubes corresponds to one of the two output terminals; The two third switching tubes are connected in series between the positive bus and the negative bus, and the series node of the two third switching tubes corresponds to the other of the two output terminals; The two fourth switching tubes are connected in series between the two output terminals.

6. The inverter according to any one of claims 1 to 5, characterized in that, The inverter further includes: a first sampling circuit and a second sampling circuit; The first sampling circuit is respectively connected to the positive bus, the negative bus, and the control circuit; The second sampling circuit is respectively connected to the target output port and the control circuit; The first sampling circuit is configured to: collect the bus voltage difference; The second sampling circuit is configured to: collect the DCV component of the target output port; The control circuit is configured to: obtain the bus voltage difference through the first sampling circuit, and obtain the DCV component of the target output port through the second sampling circuit.

7. The inverter according to claim 6, characterized in that, Both the first sampling circuit and the second sampling circuit include: at least one sampling resistor.

8. The inverter according to any one of claims 1 to 7, characterized in that, The inverter further includes: a plurality of second inductors corresponding one-to-one to the multiple output terminals of the switching bridge arm; Each of the plurality of second inductors is connected to a corresponding one of the output terminals; Moreover, both the second inductor and the first inductor are coupled inductors.

9. A voltage control method for an inverter, characterized in that, The inverter has multiple pairs of output ports, and the inverter includes: a balancing bridge arm, a switching bridge arm, two capacitors, and a first inductor; The two capacitors are connected in series between the positive bus and the negative bus, and the series node between the two capacitors is the bus midpoint; the positive bus and the negative bus are used to connect to a DC power supply device; The balancing bridge arm is respectively connected to the positive bus and the negative bus, and is connected to the bus midpoint through the first inductor; The switching bridge arm is respectively connected to the positive bus and the negative bus, and the switching bridge arm has multiple output terminals, and each of the multiple output terminals and the bus midpoint form a pair of the output ports; The method includes: Obtain the DC voltage (DCV) component of the target output port among the multiple pairs of output ports of the inverter, and the bus voltage difference between the positive bus and the negative bus; When the bus voltage difference is greater than or equal to a first voltage threshold and less than or equal to a second voltage threshold, output a first balancing modulation signal to the balancing bridge arm, and the first balancing modulation signal is used to control the balancing bridge arm to adjust the current flowing through the first inductor to reduce the DCV component of the target output port to within a target range.

10. The method according to claim 9, wherein The method further includes: When the bus voltage difference is greater than or equal to a third voltage threshold, output a second balancing modulation signal to the balancing bridge arm, and the second balancing modulation signal is used to control the balancing bridge arm to adjust the current flowing through the first inductor to reduce the bus voltage difference; wherein, the third voltage threshold is greater than the second voltage threshold.

11. The method according to claim 10, characterized in that, The method further includes: When the bus voltage difference increases from being less than or equal to the second voltage threshold to being greater than the second voltage threshold and less than the third voltage threshold, output the first balancing modulation signal to the balancing bridge arm; When the bus voltage difference decreases from being greater than or equal to the third voltage threshold to being less than the third voltage threshold and greater than the second voltage threshold, output the second balancing modulation signal to the balancing bridge arm.

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