A power-on reset circuit

Abstract

This invention discloses a power-on reset circuit, relating to the field of integrated circuit technology, to eliminate static power consumption and reduce power consumption in power-on reset circuits. The circuit includes a discharge delay circuit, a current mirror circuit, and a buffer circuit. The discharge delay circuit includes a capacitor and an NMOS transistor M4, with the NMOS transistor M4 discharging the capacitor. The current mirror circuit includes NMOS transistors M2, M3, and M9. The gates of NMOS transistor M2 and M9 are connected to the output of the buffer circuit, and the gate of NMOS transistor M3 is connected to the source of PMOS transistor M9, the drain of NMOS transistor M2, and the gate of NMOS transistor M4. After the reset signal is received, the current mirror circuit turns off NMOS transistor M2 and pulls up the drain voltage of NMOS transistor M3 to the power supply voltage via PMOS transistor M9, causing NMOS transistor M3 to enter the deep linear region and cutting off the DC path from the power supply to ground in the current mirror circuit. The buffer circuit outputs a reset signal based on the voltage change of the capacitor in the discharge delay circuit.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a power-on reset circuit. Background Technology

[0002] For digital integrated circuits and mixed-signal integrated circuits, the power-on reset circuit is an essential component. The power-on reset circuit is responsible for resetting the system to a certain state in the initial stage when the chip starts to be powered on, thereby ensuring the reliable startup of the chip. Since the power-on reset circuit is always in working state after power-on, even after the reset is completed, the traditional power-on reset circuit still has a DC path from the power supply to ground, which makes it impossible to eliminate static power consumption.

[0003] Therefore, how to eliminate the static power consumption of the power-on reset circuit and reduce its power consumption has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the above-mentioned technical status, the present invention provides a power-on reset circuit to eliminate the static power consumption of the power-on reset circuit.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A power-on reset circuit includes: a discharge delay circuit, a current mirror circuit, and a buffer circuit;

[0007] The discharge delay circuit includes a capacitor and an NMOS transistor M4, wherein the NMOS transistor M4 is used to discharge the capacitor;

[0008] The current mirror circuit includes: NMOS transistor M2, NMOS transistor M3, and PMOS transistor M9; wherein the gate of NMOS transistor M2 and the gate of PMOS transistor M9 are respectively connected to the output terminal of the buffer circuit, and the gate of NMOS transistor M3 is respectively connected to the source of PMOS transistor M9, the drain of NMOS transistor M2, and the gate of NMOS transistor M4.

[0009] The current mirror circuit is used to turn off the NMOS transistor M2 after the reset signal ends, and pull up the drain voltage of the NMOS transistor M3 to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region and cuts off the DC path from the power supply to ground in the current mirror circuit.

[0010] The buffer circuit includes two inverters, which are used to output a reset signal based on the voltage change of the capacitor in the discharge delay circuit.

[0011] In one optional embodiment of this application, the NMOS transistors M3 and M4 are used to form a current mirror to delay the discharge time of the capacitor before power-on is completed, until the inversion threshold of the two-stage inverter in the buffer circuit is reached.

[0012] In one optional embodiment of this application, in the current mirror, the ratio of the current flowing through the NMOS transistor M3 to the current flowing through the NMOS transistor M4 is N:1, where N is an integer greater than 1.

[0013] In one optional embodiment of this application, after the reset signal ends, the gate voltage of the NMOS transistor M4 is pulled up to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M4 enters the deep linear region and the capacitor is quickly discharged to zero potential.

[0014] In one optional embodiment of this application, the current mirror circuit further includes: a PMOS transistor M1 with an inverting ratio transistor structure;

[0015] The gate of the PMOS transistor M1 is grounded, the drain is connected to the power supply, and the source is connected to the source of the PMOS transistor M9, the drain of the NMOS transistor M2, and the gate of the NMOS transistor M4, respectively.

[0016] In one optional embodiment of this application, the two-stage inverter includes a first inverter and a second inverter;

[0017] The first inverter includes an NMOS transistor M5 and a PMOS transistor M6, and the second inverter includes an NMOS transistor M7 and a PMOS transistor M8;

[0018] The gate of the NMOS transistor M5 is connected to the gate of the PMOS transistor M6 and the output terminal of the discharge delay circuit, respectively; the source of the NMOS transistor M5 is grounded, and the drain of the PMOS transistor M6 is connected to the power supply; the drain of the NMOS transistor M5 is connected to the source of the PMOS transistor M6.

[0019] The gate of the NMOS transistor M7 is connected to the gate of the PMOS transistor M8 and the drain of the NMOS transistor M5, respectively; the source of the NMOS transistor M7 is grounded, and the drain of the PMOS transistor M8 is connected to the power supply; the drain of the NMOS transistor M7 is connected to the source of the PMOS transistor M8, and serves as the output terminal of the buffer circuit to output a reset signal.

[0020] In one optional embodiment of this application, one end of the capacitor is connected to the drain of the NMOS transistor M4 and the input terminal of the buffer circuit, respectively, and the other end of the capacitor is connected to the power supply.

[0021] The source of the NMOS transistor M4 is grounded.

[0022] Compared with the prior art, the power-on reset circuit provided by the present invention introduces an automatic switching mechanism controlled by NMOS transistor M2 and PMOS transistor M9 in the current mirror circuit. After the reset is completed, M9 is turned on and M2 is turned off. The drain voltage of NMOS transistor M3 is pulled up to the power supply voltage by the PMOS transistor M9, so that NMOS transistor M3 enters the deep linear region, cuts off the DC path from the power supply to ground in the current mirror circuit, and thus reduces the static power consumption to zero, thereby reducing the power consumption of the power-on reset circuit. Attached Figure Description

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 Structure of the power-on reset circuit provided in the embodiments of this application Figure 1 ;

[0025] Figure 2 Structure of the power-on reset circuit provided in the embodiments of this application Figure 2 ;

[0026] Figure 3 The voltage waveform diagram during the power-on process is provided for an embodiment of this application. Detailed Implementation

[0027] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0030] In the description of this invention, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0031] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0032] For digital integrated circuits and mixed-signal integrated circuits, the power-on reset circuit is an essential component. The power-on reset circuit is responsible for resetting the system to a certain state in the initial stage when the chip starts to be powered on, thereby ensuring the reliable startup of the chip. Since the power-on reset circuit is always in working state after power-on, even after the reset is completed, the traditional power-on reset circuit still has a DC path from the power supply to ground, which makes it impossible to eliminate static power consumption.

[0033] Therefore, how to eliminate the static power consumption of the power-on reset circuit and reduce its power consumption has become a technical problem that urgently needs to be solved by those skilled in the art.

[0034] To solve the above-mentioned technical problems, this application provides a power-on reset circuit.

[0035] Please refer to Figure 1 , Figure 1 Structure of the power-on reset circuit provided in the embodiments of this application Figure 1 .

[0036] like Figure 1 As shown, the power-on reset circuit includes: a discharge delay circuit, a current mirror circuit, and a buffer circuit.

[0037] The discharge delay circuit includes a capacitor and an NMOS transistor M4, wherein the NMOS transistor M4 is used to discharge the capacitor.

[0038] The current mirror circuit includes: NMOS transistor M2, NMOS transistor M3, and PMOS transistor M9; wherein the gate of NMOS transistor M2 and the gate of PMOS transistor M9 are respectively connected to the output terminal of the buffer circuit, and the gate of NMOS transistor M3 is connected to the source of PMOS transistor M9, the drain of NMOS transistor M2, and the gate of NMOS transistor M4.

[0039] The current mirror circuit is used to turn off the NMOS transistor M2 after the reset signal ends, and pull up the drain voltage of the NMOS transistor M3 to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region and cuts off the DC path from the power supply to ground in the current mirror circuit.

[0040] The buffer circuit includes two inverters, which are used to output a reset signal based on the voltage change of the capacitor in the discharge delay circuit.

[0041] To facilitate understanding of the power-on reset circuit provided in this application, the following provides a detailed description of the power-on reset circuit in conjunction with the circuit structures of the discharge delay circuit, current mirror circuit, and buffer circuit.

[0042] Please refer to Figure 2 , Figure 2 Structure of the power-on reset circuit provided in the embodiments of this application Figure 2 .

[0043] like Figure 2 As shown, the current mirror circuit includes: M1 (i.e., PMOS transistor M1), NMOS transistor M2 (i.e., NMOS transistor M2), M3 (i.e., NMOS transistor M3) and M9 (i.e., PMOS transistor M9).

[0044] In the embodiments of this application, M1 is specifically an inverted ratio tube structure (the channel width is much smaller than the channel length), which can be regarded as a resistor with a large resistance value in practical applications.

[0045] The gate of M1 is grounded, the drain is connected to the power supply Vdd, and the source is connected to the source of M9, the drain of M2, and the gate of M3, respectively.

[0046] The gate of M2 is connected to the gate of M9 and the output of the buffer circuit, respectively; the source of M2 is connected to the drain of M3, and the drain of M2 is connected to the source of M1, the source of M9 and the gate of M3, respectively.

[0047] The drain of M9 is connected to the power supply Vdd. The source of M9 is connected to the source of M1, the drain of M2, and the gate of M3. The gate of M9 is connected to the gate of M2 and the output terminal of the buffer circuit.

[0048] The source of M3 is grounded, the drain of M3 is connected to the source of M2, and the gate of M3, as the output of the current mirror circuit, is connected to the source of M1, the drain of M2, the source of M9, and the input of the discharge delay circuit.

[0049] The discharge delay circuit includes: capacitor C1 and M4 (i.e., NMOS transistor M4).

[0050] Among them, the first end of C1 is connected to the power supply Vdd, and the second end is connected to the drain of M4 and the input of the buffer circuit.

[0051] The source of M4 is grounded, and the gate of M4 is connected to the input of the discharge delay circuit and the input of the current mirror circuit.

[0052] The buffer circuit includes: M5 (i.e., NMOS transistor M5), M6 (i.e., PMOS transistor M6), M7 (i.e., NMOS transistor M7), and M8 (i.e., PMOS transistor M8).

[0053] In this circuit, M5 and M6 form the first inverter; the gates of M5 and M6 are connected and serve as the input of the buffer circuit, which is connected to the output of the discharge delay circuit; the source of M5 is grounded, and the source of M6 is connected to the power supply Vdd; the drains of M5 and M6 are connected and serve as the output of the first inverter, which is connected to the gates of M7 and M8.

[0054] M7 and M8 form the second inverter; the gates of M7 and M8 are connected; the source of M7 is grounded, and the source of M8 is connected to the power supply Vdd; the drains of M7 and M8 are connected and, as the output of the buffer circuit, are connected to the gates of M9 and M2 in the current mirror circuit.

[0055] Furthermore, to facilitate understanding of the working principle of the power-on reset circuit described above, the reset process of the power-on reset circuit will be described in detail below.

[0056] To facilitate understanding of the power-on process of the power-on reset circuit, the node at the drain of M2, the source of M9, the source of M1, and the gate of M3 will be referred to as node X; the node at the second terminal of capacitor C1 and the drain of M4 will be referred to as node Y; and the output terminal of the buffer circuit will be referred to as node Z.

[0057] For further details, please refer to... Figure 3 , Figure 3 The voltage waveform diagram during the power-on process is provided for an embodiment of this application.

[0058] like Figure 3As shown, at time T0, the voltages of nodes X, Y, and Z are all 0. Afterward, the power supply Vdd is powered on. Due to the influence of capacitor C1, node Y is in a high-impedance state at this time, and the voltage across capacitor C1 cannot change abruptly. The voltage of node Y will gradually rise with the power supply voltage VDD, causing the voltage of node Z at the output of the buffer circuit to also rise with the power supply voltage VDD. Before the power supply voltage VDD rises to the threshold voltages of M1, M2, and M3, M1, M2, M3, and M9 are all in the off state. At this time, node X remains at zero.

[0059] At time T1, the power supply voltage is higher than the threshold voltage of M1, M2, and M3, so M1, M2, and M3 are turned on. The voltage at node X rises to the gate-source voltage V1 when M3 is operating in the saturation region. At the same time, M4 is turned on to discharge capacitor C1.

[0060] In practical applications, in order to ensure effective reset, capacitor C1 is usually designed to be a large capacitor, thereby extending the reset time. However, this will occupy a large amount of layout area, which will increase the chip cost.

[0061] In one optional embodiment of this application, in order to save chip manufacturing costs, M3 and M4 in the embodiments of this application are designed as electron microscope flow structures so that the current ratio flowing through M3 and M4 is N:1 (where N is an integer greater than 1).

[0062] In practical applications, this electron microscope flow structure can be constructed by increasing the aspect ratio of M3, thereby reducing the current flowing through M4 by a factor of N during discharge, and thus extending the reset time. For example... Figure 3 As shown, Figure 3 The voltage waveform is shown after applying the electron microscope flow structure.

[0063] Before power-on is complete, the voltage at node Y increases with the voltage of the power supply VDD, but the rate of increase decreases.

[0064] At time T2, the power supply is powered on. Afterward, the voltage at node Y is determined by the discharge current of M4. Because the discharge current is relatively small, the voltage at node Y will decrease slowly at a constant rate until it reaches the inversion threshold of the first inverter in the buffer circuit. The duration of this process is the duration of the reset signal.

[0065] At time T3, the voltage at node Y reaches the inversion threshold of the first inverter in the buffer circuit, causing the voltage at node Z to flip from the power supply voltage VDD (i.e., logic 1) to zero potential (i.e., logic 0).

[0066] At time T4, the voltage of node Z is zero, M9 is turned on, and M2 is turned off. Through M9, the drain voltage of M3 (i.e., the voltage of node X) is quickly pulled up from V1 to the power supply voltage. The operating state of M3 changes from the saturation region to the deep linear region, cutting off the DC path from the power supply to ground in the current mirror circuit.

[0067] At time T5, the voltage at node X is the power supply voltage. The operating state of M4 changes from the saturation region to the deep linear region. Capacitor C1 discharges rapidly, and the voltage at node Y is quickly pulled down to zero by M4.

[0068] In summary, the power-on reset circuit provided in this application introduces an automatic switching mechanism controlled by an NMOS transistor M2 and a PMOS transistor M9 in the current mirror circuit. After the reset is completed, M9 is turned on and M2 is turned off. The drain voltage of the NMOS transistor M3 is pulled up to the power supply voltage by the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region, cutting off the DC path from the power supply to ground in the current mirror circuit, thereby reducing the static power consumption to zero and reducing the power consumption of the power-on reset circuit.

[0069] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A power-on reset circuit, characterized in that, include: Discharge delay circuit, current mirror circuit, and buffer circuit; The discharge delay circuit includes a capacitor and an NMOS transistor M4. The NMOS transistor M4 is used to discharge the capacitor. One end of the capacitor is connected to the drain of the NMOS transistor M4 and the input terminal of the buffer circuit, respectively. The other end of the capacitor is connected to the power supply. The source of the NMOS transistor M4 is grounded. The current mirror circuit includes: NMOS transistor M2, NMOS transistor M3, and PMOS transistor M9; wherein, the gate of NMOS transistor M2 and the gate of PMOS transistor M9 are respectively connected to the output terminal of the buffer circuit, the source of NMOS transistor M2 is connected to the drain of NMOS transistor M3, the gate of NMOS transistor M3 is connected to the source of PMOS transistor M9, the drain of NMOS transistor M2, and the gate of NMOS transistor M4, the source of NMOS transistor M3 is grounded, and the drain of PMOS transistor M9 is connected to the power supply; The current mirror circuit is used to turn off the NMOS transistor M2 after the reset signal ends, and pull up the drain voltage of the NMOS transistor M3 to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M3 enters the deep linear region and cuts off the DC path from the power supply to ground in the current mirror circuit. The buffer circuit includes two inverters, which are used to output a reset signal based on the voltage change of the capacitor in the discharge delay circuit.

2. The power-on reset circuit according to claim 1, characterized in that, The NMOS transistors M3 and M4 are used to form a current mirror to delay the discharge time of the capacitor before power-on is completed, until the inversion threshold of the two-stage inverter in the buffer circuit is reached.

3. The power-on reset circuit according to claim 2, characterized in that, In the current mirror, the ratio of the current flowing through the NMOS transistor M3 to the current flowing through the NMOS transistor M4 is N:1, where N is an integer greater than 1.

4. The power-on reset circuit according to claim 2 or 3, characterized in that, After the reset signal ends, the gate voltage of the NMOS transistor M4 is pulled up to the power supply voltage through the PMOS transistor M9, so that the NMOS transistor M4 enters the deep linear region and the capacitor is quickly discharged to zero potential.

5. The power-on reset circuit according to claim 1, characterized in that, The current mirror circuit also includes: a PMOS transistor M1 with an inverted ratio transistor structure; The gate of the PMOS transistor M1 is grounded, the drain is connected to the power supply, and the source is connected to the source of the PMOS transistor M9, the drain of the NMOS transistor M2, and the gate of the NMOS transistor M4, respectively.

6. The power-on reset circuit according to claim 1, characterized in that, The two-stage inverter includes a first inverter and a second inverter; The first inverter includes an NMOS transistor M5 and a PMOS transistor M6, and the second inverter includes an NMOS transistor M7 and a PMOS transistor M8; The gate of the NMOS transistor M5 is connected to the gate of the PMOS transistor M6 and the output terminal of the discharge delay circuit, respectively; the source of the NMOS transistor M5 is grounded, and the drain of the PMOS transistor M6 is connected to the power supply; the drain of the NMOS transistor M5 is connected to the source of the PMOS transistor M6. The gate of the NMOS transistor M7 is connected to the gate of the PMOS transistor M8 and the drain of the NMOS transistor M5, respectively; the source of the NMOS transistor M7 is grounded, and the drain of the PMOS transistor M8 is connected to the power supply; the drain of the NMOS transistor M7 is connected to the source of the PMOS transistor M8, and serves as the output terminal of the buffer circuit to output a reset signal.

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