A digital-to-analog converter chip

Abstract

The application discloses a digital-to-analog converter chip, which comprises an analog power supply for supplying power for an analog power supply domain, a digital power supply for supplying power for a digital power supply domain and a clock power supply for supplying power for a clock power supply domain, the digital power supply domain comprises a first linear voltage stabilizer, the clock power supply domain comprises a second linear voltage stabilizer, and the power supply output ends of the analog power supply, the digital power supply and the clock power supply are respectively connected with a power supply detection circuit, and the power supply detection circuit is used for outputting a power supply establishment signal; the digital power supply domain comprises a second AND gate unit, and the clock power supply domain comprises a third AND gate unit; wherein, the second AND gate unit is used for enabling the first linear voltage stabilizer to start; and the third AND gate unit is used for enabling the second linear voltage stabilizer to start. The application solves the problem that the time difference of voltage establishment of the LDO of the digital power supply domain and the clock power supply domain in the power-on starting process in the prior art may cause overvoltage of low-voltage devices, and improves the reliability of the digital-to-analog converter chip.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more specifically to digital-to-analog converter chips. Background Technology

[0002] Digital-to-analog converter (DAC) chips are widely used in wireless communication, direct digital synthesis, and instrumentation. Existing DAC chips typically employ... Figure 1 The architecture diagram shown uses analog power supplies (AVDD / AVSS), digital power supplies (DVDD / DVSS), and clock power supplies (CVDD / CVSS) for power supply, and is divided into three power domains accordingly. The analog power supply is used to power the current source array and bias circuit. The digital power supply generates logic voltage through internal LDO to power the decoding logic and other auxiliary digital circuits. The clock power supply generates logic voltage through internal LDO to power the clock circuit and latches.

[0003] In the existing technology, Figure 1 In the analog-to-digital converter chip with the architecture shown, there is an overvoltage problem at the connection of low-voltage devices between different power domains. For example, at the connection between the decoding logic and the latch, the voltage establishment time of the LDOs in the digital power domain and the clock power domain may differ during the power-on startup process. This causes the LDO (linear regulator) in one voltage domain to establish voltage before the LDO in the other. Such timing difference will cause a voltage difference between the gate and source-drain of the latch input transistor that exceeds the maximum withstand voltage of the low-voltage device, thus causing an overvoltage problem, which may lead to device damage or unstable operation.

[0004] Therefore, a new technological solution is needed. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a digital-to-analog converter chip to at least solve the problem of overvoltage at the low-voltage device connection between different power domains in existing digital-to-analog converters.

[0006] The embodiments of the present invention provide the following technical solutions:

[0007] This invention provides a digital-to-analog converter chip, including an analog power supply for an analog power domain, a digital power supply for a digital power domain, and a clock power supply for a clock power domain. The digital power domain includes a first linear regulator, and the clock power domain includes a second linear regulator. The power output terminals of the analog power supply, the digital power supply, and the clock power supply are respectively connected to a power detection circuit. The power detection circuit outputs a power establishment signal after the power supply voltage of the power supply to which it is connected is established.

[0008] The digital power domain further includes a second AND gate unit connected in series with the input terminal of the first linear regulator, and the clock power domain includes a third AND gate unit connected in series with the input terminal of the second linear regulator. Both the second AND gate unit and the third AND gate unit are used to acquire the power establishment signal sent by the power detection circuit.

[0009] The second AND gate unit is used to enable the first linear regulator to start when a power establishment signal is obtained from the output of each of the power detection circuits; the third AND gate unit is used to enable the second linear regulator to start when a power establishment signal is obtained from the output of each of the power detection circuits.

[0010] Furthermore, the analog power supply domain includes a current source unit, which includes MOSFETs PM1, PM2, PM3a, PM3b, PM4a, and PM4b.

[0011] The source of MOSFET PM1 is connected to the positive power supply voltage of the analog power supply. The gate of MOSFET PM1 is connected to the bias voltage. The drain of MOSFET PM1 is connected to the source of MOSFET PM2. The sources of MOSFETs PM3a and PM3b are connected together and then connected to the drain of MOSFET PM2. The drain of MOSFET PM3a is connected to the source of MOSFET PM4a. The drain of MOSFET PM3b is connected to the source of MOSFET PM4b. The gates of MOSFET PM4a and PM4b are connected to each other. The drains of MOSFET PM4a and PM4b are the two output terminals of the current source unit.

[0012] The gates of the MOS transistor PM3a and PM3b are respectively connected to latches in the clock power domain.

[0013] Furthermore, the analog power domain includes a first AND gate unit, a first protection circuit, and a first bias circuit, wherein the first protection circuit and the first bias circuit are respectively connected to the output terminal of the first AND gate unit;

[0014] The clock power domain also includes an undervoltage lockout circuit, which is connected between the clock power ground voltage of the second linear regulator and the input of the first AND gate unit.

[0015] Wherein, after the second linear regulator is started, its clock power ground voltage passes through the undervoltage lockout circuit and the undervoltage lockout circuit outputs a control signal; after the first AND gate unit obtains the power establishment signal output by the power detection circuit connected to the analog power supply and the control signal, it starts and controls the first protection circuit and the first bias circuit.

[0016] Furthermore, the first AND gate unit also includes a NOT gate unit and a delay unit. The NOT gate unit is connected in series to the output terminal of the first AND gate unit, and the delay unit is connected in series to the output terminal of the NOT gate unit. Both the NOT gate unit and the delay unit are connected to the first bias circuit and the first protection circuit.

[0017] After acquiring the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply, the first AND gate unit outputs a first switch signal, the NOT gate unit outputs a second switch signal, and the delay unit outputs a third switch signal. The first switch signal, the second switch signal, and the third switch signal are used to control the activation of the first bias circuit and the first protection circuit.

[0018] Furthermore, the first protection circuit includes MOSFET PM5, MOSFET NM2, MOSFET NM1, a first switch, a second switch, a third switch, a first capacitor, and a first resistor;

[0019] The source of MOSFET PM5 is connected to the drain of MOSFET PM1 and the gate of MOSFET PM5, respectively, and the gate of MOSFET PM5 is used to connect to the control voltage; the drain of MOSFET NM2 is connected to the source of MOSFET PM5, and the gate of MOSFET NM2 is connected to the drain of MOSFET PM5; the drain of MOSFET NM1 is connected to the drain of MOSFET PM5 and the gate of MOSFET NM2, respectively, and the gate of MOSFET NM1 is used to connect to the control voltage, and the source of MOSFET NM1 is connected to the negative power supply voltage of the analog power supply;

[0020] The first capacitor is connected between the gate of the MOSFET PM2 and the positive power supply voltage of the analog power supply. The common input terminal of the first switch and the first resistor connected in series is connected to the first capacitor, and the common output terminal is connected to the bias voltage. The second switch is connected in parallel with the structure formed by the first switch and the first resistor connected in series. One end of the third switch is connected to the input terminal of the second switch, and the other end is connected to the negative power supply voltage of the analog power supply.

[0021] Wherein, the first switch is used to open and close under the action of the first switch signal, the second switch is used to open and close under the action of the third switch signal, and the third switch is used to open and close under the action of the second switch signal.

[0022] Further, the first bias circuit includes MOSFET NM0, a second resistor, MOSFET NM9, MOSFET NM10, MOSFET NM6, MOSFET NM4a, MOSFET NM4b, MOSFET NM7, MOSFET PM6, MOSFET PM11, MOSFET PM0, MOSFET NM3a, MOSFET NM3b, MOSFET NM3c, MOSFET PM7a, MOSFET PM7b, MOSFET PM8a, MOSFET PM8b, MOSFET NM5a, MOSFET NM5b, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a second capacitor, a third resistor, MOSFET PM9, MOSFET PM10, and MOSFET NM8;

[0023] The gates of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are interconnected. The sources of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are all connected to the negative power supply voltage of the analog power supply.

[0024] The drain of MOSFET NM0 is connected to the gate of MOSFET NM0. The second resistor is connected between the drain of MOSFET NM0 and the positive power supply voltage of the analog power supply. The drain of MOSFET PM6 is connected to the gate of MOSFET NM6 and the drain of MOSFET NM9. The drain of MOSFET PM11 is connected to the source of MOSFET NM6. The gate of MOSFET PM11 is connected to the gate of MOSFET NM6. The source of MOSFET PM11 is connected to the positive power supply voltage of the analog power supply. The drain of MOSFET PM0 is connected to the drain of MOSFET NM10 and the gate of MOSFET NM0. The source of MOSFET PM0 is connected to the positive power supply voltage of the analog power supply.

[0025] The gate of MOSFET NM3a is connected to the low-noise regulated output voltage of the second linear regulator. The drain of MOSFET NM3a is connected to the drain of MOSFET NM3b. The source of MOSFET NM3a is connected to the source of MOSFET NM3b. The gate of MOSFET NM3b is connected to the given voltage VBC. The sources of MOSFET NM3b and NM3c are both connected to the drain of MOSFET NM6. The gate of MOSFET NM3c is connected to the drain of MOSFET NM8. The drain of MOSFET NM3c is connected to the drain of MOSFET PM7b. The drain of MOSFET NM3b is connected to the drain of MOSFET PM8a.

[0026] The sources of MOSFET PM8a and PM8b are both connected to the positive power supply voltage of the analog power supply. The gates of MOSFET PM8a and PM8b are connected to the gates of MOSFETs PM0 and PM9. The drain of MOSFET PM8a is also connected to the source of MOSFET PM7a, and the drain of MOSFET PM8b is also connected to the source of MOSFET PM7b. The gates of MOSFETs PM7a, PM7b, and PM6 are interconnected. The drain of MOSFET PM7a is connected to the drain of MOSFET NM5a, the drain of MOSFET PM7b is connected to the drain of MOSFET NM5b, the gate of MOSFET NM5a is connected to the drain of MOSFET NM5a and the gate of MOSFET NM5b, the source of MOSFET NM5a and MOSFET NM5b are both connected to the negative power supply voltage of the analog power supply, and the gate of MOSFET NM5a and the gate of MOSFET NM5b are both connected to the drain of MOSFET NM4a.

[0027] The drain of MOSFET NM4b is connected to the drain of MOSFET NM5b. One end of the fourth switch is connected to the drain of MOSFET NM4b, and the other end is connected to the negative power supply voltage of the analog power supply. One end of the fifth switch is connected to the drain of MOSFET PM7b, and the other end is connected to the gate of MOSFET PM10. The sixth switch is connected between the other end of the fifth switch and the positive power supply voltage of the analog power supply. The series structure formed by the third resistor and the seventh switch is connected between the positive power supply voltage of the analog power supply and the gate of MOSFET PM10. One end of the second capacitor is connected to the other end of the fifth switch, and the other end is connected to the negative power supply voltage of the analog power supply.

[0028] The source of MOSFET PM9 is connected to the positive power supply voltage of the analog power supply. The drain of MOSFET PM9 is connected to the source of MOSFET PM10 and the gate of MOSFET NM3c. The gate of MOSFET PM10 is connected to the source of MOSFET PM10. The drain of MOSFET PM10 is connected to the drain of MOSFET NM7 and the gate of MOSFET NM8. The source of MOSFET NM8 is connected to the negative power supply voltage of the analog power supply.

[0029] The gate of MOS transistor PM10 is connected to the gate of MOS transistor PM5, and the gate of MOS transistor NM7 is connected to the gate of MOS transistor NM1.

[0030] Furthermore, the given voltage VBC is generated by the bandgap reference of the analog power supply domain, and the difference between the given voltage VBC and the negative power supply voltage of the analog power supply is equal to the standard operating voltage of the low-voltage device.

[0031] Furthermore, the analog power domain also includes a second protection circuit, which includes a PMOS transistor M1, an NMOS transistor m2, and an NMOS transistor m1.

[0032] The source of PMOS transistor M1 is connected to the source of MOS transistor PM3a. The gate of PMOS transistor M1 is connected to the positive power supply voltage and control voltage of the analog power supply. The drain of PMOS transistor M1 is connected to the gate of NMOS transistor m2. The drain of NMOS transistor m2 is connected to the source of PMOS transistor M1. The source of MOS transistor M2 is connected to the negative power supply voltage of the analog power supply. The drain of NMOS transistor m1 is connected to the drain of PMOS transistor M1. The source of NMOS transistor m1 is connected to the negative power supply voltage of the analog power supply. The gate of NMOS transistor m1 is connected to the control voltage.

[0033] Furthermore, the analog power supply domain also includes a second bias circuit, which includes NMOS transistors m5, m4, m3, M5, M4, a fourth resistor, a first operational amplifier OTA2, M2, M3, M6, a second operational amplifier OTA1, and a fifth resistor.

[0034] The gates of NMOS transistors m5, m4, m3, and m1 are interconnected, and the sources of NMOS transistors m5, m4, and m3 are connected to the negative power supply voltage of the analog power supply.

[0035] The drain of the NMOS transistor m5 is connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the gate of the PMOS transistor M5, the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M1 and the positive power supply voltage of the analog power supply, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M4, the source of the PMOS transistor M4 is connected to the positive power supply voltage of the analog power supply, the drain of the PMOS transistor M4 is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the NMOS transistor m4.

[0036] The gate of the PMOS transistor M4 is connected to the output terminal of the first operational amplifier OTA2, the positive input terminal of the first operational amplifier OTA2 is connected to the other end of the fourth resistor, and the negative input terminal is connected to the negative voltage source of the clock power supply.

[0037] The drain of NMOS transistor m3 is connected to the gate of NMOS transistor m3 and the drain of PMOS transistor M2. The sources of PMOS transistor M2 and PMOS transistor M3 are both connected to the positive power supply voltage of the analog power supply. The gates of PMOS transistor M2 and PMOS transistor M3 are interconnected and then connected to the drain of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor m6. The source of NMOS transistor M6 is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the negative power supply voltage of the analog power supply. The output terminal of the second operational amplifier OTA1 is connected to the gate of NMOS transistor m6. The negative input terminal of the second operational amplifier OTA1 is connected to one end of the fifth resistor.

[0038] Furthermore, the positive input terminal of the second operational amplifier OTA1 is connected to the reference voltage generated by the on-chip bandgap reference.

[0039] Compared with the prior art, the beneficial effects that the at least one technical solution adopted in the embodiments of the present invention can achieve include at least:

[0040] The present invention discloses a digital-to-analog converter chip. When the second AND gate unit and the third AND gate unit both obtain the power establishment signal output by the power detection circuit with different power supply connections, the second AND gate unit enables the first linear regulator to start, and the third AND gate unit enables the second linear regulator to start. This allows the corresponding linear regulator to start when both the digital power supply voltage and the clock power supply are established, thus avoiding the linear regulator in the digital power domain from establishing voltage before the linear regulator in the clock power domain. This solves the problem in the prior art where the voltage establishment time of LDOs in the digital power domain and the clock power domain may differ, leading to overvoltage of low-voltage devices, and improves the reliability of the digital-to-analog converter chip. Attached Figure Description

[0041] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0042] Figure 1 A simplified diagram of the conventional architecture of existing digital-to-analog converter chips;

[0043] Figure 2 The connection between the P-terminal current source and the external circuit in the existing digital-to-analog converter chip;

[0044] Figure 3 This is a simplified architecture diagram of a digital-to-analog converter chip according to an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram showing the connection of the current source unit, the first protection circuit, and the first bias circuit according to an embodiment of the present invention;

[0046] Figure 5 This is a schematic diagram showing the connection of the current source unit, the second protection circuit, and the second bias circuit in an embodiment of the present invention. Detailed Implementation

[0047] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0048] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. This application can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this application, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using structures and / or functionalities other than one or more of the aspects set forth herein.

[0050] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] Additionally, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that practice can be carried out without these specific details.

[0052] High-speed, high-precision current-controlled DAC chips (digital-to-analog converter chips) are widely used in wireless communication, direct digital synthesis, and instrumentation. Their AC linearity and dynamic performance are key performance indicators limiting system applications. To improve their high-frequency dynamic performance, traditional designs use only high-voltage devices as the current source transistor and output cascode transistor for the current source unit, while employing low-voltage devices operating in the saturation region as switching transistors. By utilizing the high cutoff frequency and low capacitance parasitic characteristics of the low-voltage devices, the switching speed is increased and the energy of glitch impulses during a single switch is reduced, thereby improving the spurious-free dynamic range (SFDR) and noise spectrum (NSD) of the output signal at high frequencies.

[0053] Figure 1A simplified architecture diagram of a DAC chip using a traditional design is presented. The DAC chip is powered by three power supplies: analog power (AVDD / AVSS), digital power (DVDD / DVSS), and clock power (CVDD / CVSS). The analog power supply powers the current source array and bias circuitry; the digital power supply generates logic voltages through an internal LDO (linear regulator) to power the decoding logic and other auxiliary digital circuits; and the clock power supply generates logic voltages through an internal LDO to power the clock circuit and latches. The three power supplies are connected to the external chip via different pads to prevent interference between different modules during data conversion. AVSS, DVSS, and CVSS are connected to the external ground via EP pads on the package. The N-bit binary input digital signal BI (N-1:0) first generates appropriate digital codes (Codes) through the decoding logic in the DVDD power domain, and then generates control signals SWN / SWP for the current source unit switches via the latch array, thereby controlling the current flow of different current source units. The decoding logic, latches, and current source switches are all directly coupled through their gates.

[0054] Figure 2 A schematic diagram of the connection between a P-terminal current source unit and the surrounding circuitry in a current-output DAC is given. Figure 2 MOSFETs PM1, PM2, PM3a, PM3b, PM4a, and PM4b constitute the current source unit. MOSFETs PM1 and PM2 are current source transistors, while PM4a and PM4b are output cascode transistors. The circuit on the right is the bias circuit for generating the bias voltages for MOSFETs PM1, PM2, PM4a, and PM4b. MOSFETs PM3a and PM3b are switching transistors, with high and low operating logic voltages VDDC and VSSC, respectively. These values ​​are generated by the analog power supply through a global bias circuit, and the difference between the two is the standard operating voltage of the low-voltage device. The gate of the switching transistor is directly coupled to the latch output. The LDO operating in the CVDD power domain generates the internal power supply CVDDC / CVSSC from VDDC / VSSC to power the latch. The LDO operating in the DVDD power domain generates an internal power supply, DVDDC / DVSSC, which powers the decoding logic and other auxiliary digital circuits.

[0055] Figure 1 and 2 The circuit scheme shown presents a potential overvoltage problem at the connection points of low-voltage devices across different power domains. Specifically:

[0056] 1. At the connection between the decoding logic and the latch, overvoltage occurs during the power-on startup process. If there is a time difference between the DVDD and CVDD establishment processes, causing the LDO in one voltage domain to be established before the LDO in the other, then in the worst case, the voltage difference between the gate and source-drain of the latch input transistor will reach VDDC-VSS, exceeding the maximum withstand voltage of the low-voltage device, and an overvoltage process will occur.

[0057] 2. At the connection between the latch and the switching transistor, if the output pins IOUTP / IOUTN are open (e.g., due to poor soldering or the externally connected differential transimpedance amplifier not being powered on), the current source output is open, and the source potential of MOSFET PM3a / PM3b will track the power supply voltage AVDD. The gate-source voltage difference of the switching transistor is AVDD-VSSC, resulting in an overvoltage phenomenon. This overvoltage problem may be more severe during power-on startup because if AVDD is established before CVDD, the voltage value of CVSSC is no longer VSSC but VSS, and the gate-source voltage of MOSFET PM3a / PM3b will directly reach AVDD-VSS, resulting in a more severe overvoltage process.

[0058] Regarding the chip reliability issues caused by overvoltage, most of the currently reported literature does not mention how to solve them.

[0059] Based on this, the embodiments of this specification propose a processing solution: such as Figure 3 As shown, the present invention provides a digital-to-analog converter (D / A converter) chip that offers a power-on timing scheme for low-dropout linear regulators (LDOs) powering digital logic circuits and latches. By using a second AND gate unit 40 and a third AND gate unit 50 to simultaneously acquire analog power supply voltage establishment signals, clock power supply voltage establishment signals, and digital power supply voltage establishment signals, the first linear regulator 10 in the digital power domain and the second linear regulator 20 in the clock power domain are enabled to start simultaneously. This avoids potential differences in voltage establishment time between the LDOs in the digital and clock power domains during power-on startup, solving the overvoltage problem at the low-voltage device connections between different power domains in existing D / A converters and improving the reliability of the D / A converter chip. Furthermore, during power-on, it also avoids the overvoltage problem caused by the gate-source voltage of the current source transistor PM3a / MOSFET PM3b directly reaching AVDD-VSS due to AVDD establishing before CVDD.

[0060] The present invention also provides a power-on protection circuit and a bias circuit to protect the safety of the switching transistor when the analog power supply, digital power supply and clock power supply are powered on in different sequences.

[0061] The present invention also provides another power-on protection circuit and bias circuit for protecting the current source unit switching transistor when the output pin of the digital-to-analog converter chip is in an open circuit state.

[0062] The technical solutions provided by the various embodiments of this application are described below with reference to the accompanying drawings.

[0063] like Figure 3 As shown, a digital-to-analog converter chip of the present invention includes an analog power supply for powering the analog power domain, a digital power supply for powering the digital power domain, and a clock power supply for powering the clock power domain. The digital power domain includes a first linear regulator 10, and the clock power domain includes a second linear regulator 20.

[0064] The linear regulator 20 described in this invention is a low dropout linear regulator (LDO).

[0065] In this application, the analog power supply, digital power supply, and clock power supply in the digital-to-analog converter chip are the same as those in the prior art, and are mainly used to supply power to the analog power domain, digital power domain, and clock power domain, respectively.

[0066] Furthermore, the clock power domain also includes latch arrays, the digital power domain includes decoding logic, and the analog power domain includes circuit structures such as current source arrays.

[0067] The connection methods for different power domains are the same as those in the prior art and will not be described in detail here. This application mainly focuses on protecting the power-on logic and current source array protection circuits, bias circuits, etc. of low dropout linear regulators in the digital power domain and clock power domain.

[0068] Specifically, the power output terminals of the analog power supply, digital power supply, and clock power supply are each connected to a power detection circuit. The power detection circuit outputs a power establishment signal after the power supply voltage of the power supply it is connected to is established.

[0069] The output of the analog power supply is connected to a power detection circuit. When the voltage of the analog power supply is higher than a given threshold, the output of the power detection circuit changes with the voltage of the analog power supply. When the voltage of the analog power supply is lower than the given threshold, the output of the analog power supply is VSS (ground voltage or negative power supply voltage).

[0070] The power supply detection circuit has the same circuit structure as the existing circuit structure. It is mainly used to output a power supply establishment signal AVDDOK when the power supply voltage of the analog power supply reaches a given threshold, so as to indicate that the voltage of the analog power supply has been established.

[0071] The power detection circuits for the digital power supply connection and the clock power supply connection operate on the same principle as the power detection circuits for the analog power supply connection, and are used to output the power establishment signal DVDDOK (to indicate the power voltage establishment of the digital power supply) and the power establishment signal CVDDOK (to indicate the power voltage establishment of the clock power supply), respectively.

[0072] Furthermore, the digital power domain also includes a second AND gate unit 40 connected in series with the input of the first linear regulator 10, and the clock power domain includes a third AND gate unit 50 connected in series with the input of the second linear regulator 20. Both the second AND gate unit 40 and the third AND gate unit 50 are used to acquire the power-on signal sent by the power detection circuit. Specifically, the second AND gate unit 40 is used to enable the first linear regulator 10 to start when it acquires the power-on signal output by each power detection circuit; the second AND gate unit 40 is used to enable the second linear regulator 20 to start when it acquires the power-on signal output by each power detection circuit.

[0073] The second AND gate unit 40 is powered by a digital power supply, and the third AND gate unit 50 is powered by a clock power supply.

[0074] Specifically, when the second AND gate unit 40 simultaneously acquires AVDDOK, DVDDOK, and CVDDOK, the second AND gate unit 40 generates an enable signal for the first linear regulator 10 in the digital power domain. When the enable signal is high, the first linear regulator 10 is started; otherwise, regardless of whether the digital power is established or not, the output signal DVDDC (digital power positive voltage) and the output signal DVSSC (digital power ground voltage) of the first linear regulator 10 are both VSS.

[0075] When the third AND gate unit 50 simultaneously acquires AVDDOK, DVDDOK, and CVDDOK, the third AND gate unit 50 generates an enable signal for the second linear regulator 20 under clock power. When the enable signal is high, the second linear regulator 20 starts; otherwise, regardless of whether the clock power is established or not, the output signal CVDDC (clock power positive voltage) and the output signal CVSSC (clock power ground voltage) of the second linear regulator 20 are both VSS.

[0076] This application enables mutual control between the digital power supply and the clock power supply through the second AND gate unit 40 and the third AND gate unit 50, thereby allowing the first linear regulator 10 in the digital power supply and the second linear regulator 20 in the clock power supply to be established synchronously, ensuring the safety of the low-voltage devices directly coupled at the interface between the digital power domain and the clock power domain.

[0077] Furthermore, such as Figures 4-5As shown, the analog power supply domain includes a current source unit, which includes MOSFETs PM1, PM2, PM3a, PM3b, PM4a, and PM4b. The source of MOSFET PM1 is connected to the positive power supply voltage of the analog power supply, the gate of MOSFET PM1 is connected to the control voltage, the drain of MOSFET PM1 is connected to the source of MOSFET PM2, the sources of MOSFETs PM3a and PM3b are connected together and then connected to the drain of MOSFET PM2, the drain of MOSFET PM3a is connected to the source of MOSFET PM4a, the drain of MOSFET PM3b is connected to the source of MOSFET PM4b, the gates of MOSFET PM4a and PM4b are interconnected, and the drains of MOSFETs PM4a and PM4b are the two output terminals of the current source unit. The gates of MOSFETs PM3a and PM3b are respectively connected to latches in the clock power supply domain.

[0078] The current source unit in this application is powered by an analog power supply and is mainly used to provide a stable current.

[0079] like Figures 3-4 As shown, the analog power domain includes a first AND gate unit 30, a first protection circuit, and a first bias circuit. The first protection circuit and the first bias circuit are respectively connected to the output terminal of the first AND gate unit 30. The clock power domain also includes an undervoltage lockout circuit 60, which is connected between the clock power ground voltage of the second linear regulator 20 and the input of the first AND gate unit 30. After the second linear regulator 20 is started, its clock power ground voltage outputs a control signal through the undervoltage lockout circuit 60. After acquiring the power establishment signal and control signal output by the power detection circuit connected to the analog power supply, the first AND gate unit 30 starts and controls the first protection circuit and the first bias circuit.

[0080] The negative power supply voltage of the clock power supply output by the second linear regulator 20 generates a control signal CLDOOK under the action of the undervoltage lockout circuit 60. After the first AND gate unit 30 simultaneously obtains the power establishment signal AVDDOK and the control signal CLDOOK output by the power detection circuit connected to the analog power supply, the first AND gate unit 30 starts and controls the first protection circuit and the first bias circuit so that the first protection circuit and the first bias circuit provide bias voltage and protection for the current source unit.

[0081] like Figures 3-4As shown, the first AND gate unit 30 also includes a NOT gate unit 70 and a delay unit 80. The NOT gate unit 70 is connected in series to the output terminal of the first AND gate unit 30, and the delay unit 80 is connected in series to the output terminal of the NOT gate unit 70. Both the NOT gate unit 70 and the delay unit 80 are connected to the first bias circuit and the first protection circuit. After acquiring the power establishment signal and control signal output by the power detection circuit connected to the analog power supply, the first AND gate unit 30 outputs a first switch signal F1, the NOT gate unit 70 outputs a second switch signal NF1, and the delay unit 80 outputs a third switch signal F1D. The first switch signal F1, the second switch signal NF1, and the third switch signal F1D are used to control the start of the first bias circuit and the first protection circuit.

[0082] Specifically, the first protection circuit includes MOSFET PM5, MOSFET NM2, MOSFET NM1, a first switch K1, a second switch K2, a third switch K3, a first capacitor C1, and a first resistor R1. The source of MOSFET PM5 is connected to the drain of MOSFET PM1 and the gate of MOSFET PM5, respectively, and the gate of MOSFET PM5 is used to connect to the control voltage. The drain of MOSFET NM2 is connected to the source of MOSFET PM5, and the gate of MOSFET NM2 is connected to the drain of MOSFET PM5. The drain of MOSFET NM1 is connected to the drain of MOSFET PM5 and the gate of MOSFET NM2, respectively, and the gate of MOSFET NM1 is used to connect to the control voltage. The source is connected to the negative power supply voltage of the analog power supply; the first capacitor C1 is connected between the gate of the MOSFET PM2 and the positive power supply voltage of the analog power supply; the common input terminal of the first switch K1 and the first resistor R1 connected in series is connected to the first capacitor C1, and the common output terminal is connected to the bias voltage; the second switch K2 is connected in parallel with the structure of the first switch K1 and the first resistor R1 connected in series; one end of the third switch K3 is connected to the input terminal of the second switch K2, and the other end is connected to the negative power supply voltage of the analog power supply; wherein, the first switch K1 is used to open and close under the action of the first switch signal F1, the second switch K2 is used to open and close under the action of the third switch signal F1D, and the third switch K3 is used to open and close under the action of the second switch signal NF1.

[0083] Among them, MOSFETs NM1, NM2, and PM5 form a super source follower and are connected to the drain of MOSFET PM1. Meanwhile, a first switch K1, a second switch K2, a third switch K3, a first resistor R1, and a first capacitor C1 are inserted between the gate of MOSFET PM2 and the bias voltage.

[0084] The first protection circuit is used to protect the current source unit.

[0085] like Figure 4As shown, the first bias circuit includes MOSFET NM0, second resistor R2, MOSFETs NM9, NM10, NM6, NM4a, NM4b, NM7, PM6, PM11, PM0, NM3a, NM3b, NM3c, PM7a, PM7b, PM8a, PM8b, NM5a, NM5b, fourth switch K4, fifth switch K5, sixth switch K6, seventh switch K7, second capacitor C2, and third... Resistor R3, MOSFETs PM9, PM10, and NM8; the gates of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are interconnected. The sources of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are all connected to the negative power supply voltage of the analog power supply. The drain of MOSFET NM0 is connected to the gate of the analog power supply. The gate of MOSFET NM0 is connected to the analog power supply. The second resistor R2 is connected between the drain of MOSFET NM0 and the positive power supply voltage of the analog power supply. The drain of MOSFET PM6 is connected to the gate of MOSFET NM6 and the drain of MOSFET NM9. The drain of MOSFET PM11 is connected to the source of MOSFET NM6, the gate of MOSFET PM11 is connected to the gate of MOSFET NM6, and the source of MOSFET PM11 is connected to the positive power supply voltage of the analog power supply. The drain of MOSFET PM0 is connected to the drain of MOSFET NM10 and the gate of MOSFET NM0, and the source of MOSFET PM0 is connected to the positive power supply voltage of the analog power supply. The gate of S-channel transistor NM3a is connected to the low-noise regulated output voltage of the second linear regulator 20. The drain of MOSFET NM3a is connected to the drain of MOSFET NM3b. The source of MOSFET NM3a is connected to the source of MOSFET NM3b. The gate of MOSFET NM3b is connected to the given voltage VBC. The sources of MOSFET NM3b and MOSFET NM3c are both connected to the drain of MOSFET NM6. The gate of MOSFET NM3c is connected to the drain of MOSFET NM8. The drain of MOSFET NM3c is connected to the drain of MOSFET PM7b. The drain of MOSFET NM3b is connected to the drain of MOSFET PM8a.The sources of MOSFET PM8a and PM8b are both connected to the positive power supply voltage of the analog power supply. The gates of MOSFET PM8a and PM8b are connected, and then connected to the gates of MOSFETs PM0 and PM9. The drain of MOSFET PM8a is also connected to the source of MOSFET PM7a, and the drain of MOSFET PM8b is also connected to the source of MOSFET PM7b. The gates of MOSFETs PM7a, PM7b, and PM6 are interconnected. The drain of MOSFET PM7a is connected to the source of MOSFET NM. The drain of MOSFET 5a is connected; the drain of MOSFET PM7b is connected to the drain of MOSFET NM5b; the gate of MOSFET NM5a is connected to the drain of MOSFET NM5a and the gate of MOSFET NM5b; the sources of MOSFETs NM5a and NM5b are both connected to the negative power supply voltage of the analog power supply; the gates of MOSFETs NM5a and NM5b are both connected to the drain of MOSFET NM4a; the drain of MOSFET NM4b is connected to the drain of MOSFET NM5b; one end of the fourth switch K4 is connected to MOSFET NM4a. The drain of MOSFET PM7b is connected, and the other end is connected to the negative power supply voltage of the analog power supply. One end of the fifth switch K5 is connected to the drain of MOSFET PM7b, and the other end is connected to the gate of MOSFET PM10. The sixth switch K6 is connected between the other end of the fifth switch K5 and the positive power supply voltage of the analog power supply. The series structure formed by the third resistor R3 and the seventh switch K7 is connected between the positive power supply voltage of the analog power supply and the gate of MOSFET PM10. One end of the second capacitor C2 is connected to the other end of the fifth switch K5, and the other end is connected to the negative power supply voltage of the analog power supply. The source of MOSFET PM9 is connected to the positive power supply voltage of the analog power supply. The drain of MOSFET PM9 is connected to the source of MOSFET PM10 and the gate of MOSFET NM3c. The gate of MOSFET PM10 is connected to the source of MOSFET PM10. The drain of MOSFET PM10 is connected to the drain of MOSFET NM7 and the gate of MOSFET NM8. The source of MOSFET NM8 is connected to the negative power supply voltage of the analog power supply. The gate of MOSFET PM10 is connected to MOSFET PM5, and the gate of MOSFET NM7 is connected to the gate of MOSFET NM1.

[0086] Furthermore, the given voltage VBC is generated by the bandgap reference of the analog power supply domain, and the difference between the given voltage VBC and the negative power supply voltage of the analog power supply is equal to the standard operating voltage of the low-voltage device.

[0087] like Figure 4 As shown, Figure 4The upper half of the dashed box represents the bias circuit for generating the gate control voltages VBNPON / VBPPON for MOSFETs NM1 and PM5. Here, VBNPON is the control voltage connected to MOSFET PM5, and VBPPON is the control voltage connected to MOSFET NM1.

[0088] MOSFETs NM3a, NM3b, NM3c, NM5a, NM5b, NM6, PM7a, PM7b, PM8a, and PM8b form a folded operational amplifier with two positive inputs and one negative input. During the power-on process of the analog power supply AVDD, the first switching signals F1 and F1D are both low, the second switching signal NF1 is high, and the gate of MOSFET PM10 is connected to the output point of the folded operational amplifier.

[0089] After the power supply voltage of the analog power supply exceeds the threshold voltage of MOSFET NM0, the branch containing MOSFET NM0 and the second resistor R2 is turned on, activating all current sources whose gates are connected to the gate of MOSFET NM0, as well as MOSFETs PM0, PM8a, PM8b, and PM9. However, MOSFET PM6 is in an off state at this time, so the current flowing down from MOSFET PM7b is 0. MOSFET NM4b pulls down the gate voltage of MOSFET PM10 to VSS.

[0090] As the analog power supply voltage increases further, MOSFET PM6 turns on, activating the folded op-amp. The negative feedback effect causes the source potential of MOSFET PM10 to track the maximum of the gate potentials of MOSFETs NM3a and NM3b. The voltage of MOSFET NM3a is connected to the output CVDDC of the third linear regulator in the clock power domain, while the voltage of MOSFET NM3b is connected to the given voltage VBC. VBC is generated by the bandgap reference in the analog power domain, and the voltage difference between its value and VSS is exactly equal to the standard operating voltage of the low-voltage device. When the analog power supply voltage amplitude does not activate the bandgap reference, the given voltage VBC remains at VSS. However, when the analog power supply increases to the point where the bandgap reference is activated, the given voltage VBC is established to the preset value without overshoot (not exceeding the target value).

[0091] The gate voltages of MOSFETs PM10 and NM7, output from the first bias circuit, are applied to the gates of MOSFETs PM5 and NM1 in the super source follower, respectively. During the period when the first switching signal F1 is low, the first bias circuit ensures that the drain voltage of MOSFET PM1 is always the maximum value between the output voltage CVDDC of the second linear regulator 20 and the given voltage VBC. Simultaneously, the gate of MOSFET PM2 is connected to VSS, placing it in the linear region, and the sources of MOSFETs PM3a / PM3b are connected to the drain of MOSFET PM1. Thus, the voltage difference between the gate and source / drain of MOSFETs PM3a / PM3b ensures that an overvoltage process will never occur during the period when the first switching signal F1 is low.

[0092] when Figure 3 When the output of UVLO (undervoltage lockout circuit 60) suspended under CVSSC is high, it indicates that the second linear regulator 20 under the clock power domain has been established. At this time, the first switch signal F1 becomes high, the first switch K1 is closed, and the gate of MOS transistor PM2 is connected to VBP2 through the first resistor R1. The gate potential is disconnected from VSS and exponentially established from VSS to VBP2 through the first resistor R1 and the first capacitor C1. Its time constant is R1C1. At the same time, the fourth switch K4 and the seventh switch K7 are closed, and the fifth switch K5 is open. The gate of MOS transistor PM10 is disconnected from the output of the folded op-amp and exponentially established from AVDD through the third resistor R3 and the second capacitor C2. Its time constant is R2C2. After the gate potentials of MOSFETs PM2 and PM10 have reached a sufficiently suitable amplitude, the second switching signal NF1 goes high, and the second switch K2 and the sixth switch K6 open, further providing a low-impedance path between the gate of MOSFET PM10 and the analog power supply, and between the gate of MOSFET PM2 and the bias voltage VBP2. After this, MOSFET PM5 is completely turned off, while the gate of MOSFET PM2 is fully connected to the bias voltage VBP2, and the current source unit enters normal operating mode.

[0093] The present invention, through the above-described two-step switching method, can effectively ensure that the source potentials of MOSFETs PM3a and PM3b will not experience a brief overvoltage process due to parasitic capacitance at the moment the switch is turned on, thereby solving the problem of existing current sources being prone to overvoltage during power-on.

[0094] like Figure 5As shown, the analog power domain also includes a second protection circuit, which includes a PMOS transistor M1, an NMOS transistor m2, and an NMOS transistor m1. The source of PMOS transistor M1 is connected to the source of MOS transistor PM3a, the gate of PMOS transistor M1 is connected to the positive power supply voltage and control voltage of the analog power supply, the drain of PMOS transistor M1 is connected to the gate of NMOS transistor m2, the drain of NMOS transistor m2 is connected to the source of PMOS transistor M1, the source of MOS transistor M2 is connected to the negative power supply voltage of the analog power supply, the drain of NMOS transistor m1 is connected to the drain of PMOS transistor M1, the source of NMOS transistor m1 is connected to the negative power supply voltage of the analog power supply, and the gate of NMOS transistor m1 is connected to the control voltage.

[0095] Figure 5 A protection circuit is provided for the current output pin of a digital-to-analog converter chip when it is in an open-circuit state. A super source follower composed of PMOS transistors M1, M2, and M1 is connected to the source of MOS transistors PM3a and PM3b. Under normal operation, PMOS transistor M1 is in the cutoff region, and the current source current only flows to the off-chip through MOS transistors PM3a and PM3b. When the output pin is open, PMOS transistor M1 is turned on, and the current source current flows to AVSS through NMOS transistor M2. The source potential of MOS transistors PM3a and PM3b is controlled at the gate potential of PMOS transistor M1 minus the gate-source voltage difference in its on-state. In the design, it is only necessary to ensure that the gate-source voltage difference of MOS transistors PM3a / PM3b in this state is less than or equal to the standard operating voltage of the low-voltage device.

[0096] Furthermore, the analog power supply domain also includes a second bias circuit, which includes NMOS transistors m5, m4, m3, M5, M4, a fourth resistor R4, a first operational amplifier OTA2, a PMOS transistor M2, M3, an NMOS transistor m6, a second operational amplifier OTA1, and a fifth resistor R5; the gates of NMOS transistors m5, m4, m3, and m1 are interconnected, and the source of NMOS transistor m5 is... The sources of NMOS transistors m4 and m3 are connected to the negative power supply voltage of the analog power supply. The drain of NMOS transistor m5 is connected to the drain of PMOS transistor M5, and the drain of PMOS transistor M5 is connected to its gate. The gate of PMOS transistor M5 is connected to the gate of PMOS transistor M1 and the positive power supply voltage of the analog power supply. The source of PMOS transistor M5 is connected to the drain of PMOS transistor M4, and the source of PMOS transistor M4 is connected to the positive power supply voltage of the analog power supply. The drain of PMOS transistor M4 is connected to one end of the fourth resistor R4. The connections are as follows: the other end of the fourth resistor R4 is connected to the drain of NMOS transistor M4; the gate of PMOS transistor M4 is connected to the output of the first operational amplifier OTA2; the positive input of the first operational amplifier OTA2 is connected to the other end of the fourth resistor R4, and the negative input is connected to the negative voltage source of the clock power supply; the drain of NMOS transistor M3 is connected to the gate of NMOS transistor M3 and the drain of PMOS transistor M2; the source of PMOS transistor M2 and the source of PMOS transistor M3 are both connected to the positive power supply voltage of the analog power supply; the gate of PMOS transistor M2 and the PMOS transistor M4 are connected to the output of the first operational amplifier OTA2. The gates of MOSFET M3 are interconnected and then connected to the drain of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor m6. The source of MOSFET M6 is connected to one end of the fifth resistor R5. The other end of the fifth resistor R5 is connected to the negative power supply voltage of the analog power supply. The output terminal of the second operational amplifier OTA1 is connected to the gate of NMOS transistor m6. The negative input terminal of the second operational amplifier OTA1 is connected to one end of the fifth resistor R5. The positive input terminal of the second operational amplifier OTA1 is connected to the reference voltage generated by the on-chip bandgap reference.

[0097] The dashed box in the diagram shows the bias circuits for the gate voltages of PMOS transistors M1 and M1. VREF is the reference voltage generated by the on-chip bandgap reference. This reference voltage generates current through the fifth resistor R5. This current flows through two pairs of current mirrors—PMOS transistors M2 and M3, and NMOS transistors m3 and m4—before flowing through the fourth resistor R4. The first operational amplifier OTA2 forces the drain voltage of PMOS transistor M5 to be equal to the sum of the voltage difference between VSSC and the fourth resistor R4. By adjusting the ratio between the fourth resistor R4 and the fifth resistor R5, the voltage difference between the source voltage of PMOS transistor M5 and VSSC can be precisely adjusted, thereby reasonably setting the gate control voltage of PMOS transistor M1.

[0098] This invention discloses a digital-to-analog converter chip, proposing a power-on timing scheme for the low-dropout linear regulator used to power digital logic circuits and latches within the chip. This avoids overvoltage issues in low-voltage devices caused by different power-on times for linear regulators connected to digital and clock power supplies. The invention also protects the current source unit during power-on through a first protection circuit and a first bias circuit, and protects the current source switching transistor even when the analog, digital, and clock power supplies are powered on in different sequences. Furthermore, the invention protects the switching transistor of the current source unit when the current source output transistor is in an open-circuit state through a second protection circuit and a second bias circuit.

[0099] In this specification, the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the product embodiments described later, since they correspond to the methods, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions in the system embodiments.

[0100] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital-to-analog converter chip, comprising an analog power supply for an analog power domain, a digital power supply for a digital power domain, and a clock power supply for a clock power domain, wherein the digital power domain includes a first linear regulator, and the clock power domain includes a second linear regulator, characterized in that, The power output terminals of the analog power supply, the digital power supply, and the clock power supply are respectively connected to a power detection circuit. The power detection circuit outputs a power establishment signal after the power supply voltage of the power supply to which it is connected is established. The digital power domain further includes a second AND gate unit connected in series with the input terminal of the first linear regulator, and the clock power domain includes a third AND gate unit connected in series with the input terminal of the second linear regulator. Both the second AND gate unit and the third AND gate unit are used to acquire the power establishment signal sent by the power detection circuit. The second AND gate unit is used to enable the first linear regulator to start when a power establishment signal is received from each of the power detection circuits; the third AND gate unit is used to enable the second linear regulator to start when a power establishment signal is received from each of the power detection circuits.

2. The digital-to-analog converter chip according to claim 1, characterized in that, The analog power domain includes a current source unit, which includes MOSFETs PM1, PM2, PM3a, PM3b, PM4a, and PM4b. The source of MOSFET PM1 is connected to the positive power supply voltage of the analog power supply. The gate of MOSFET PM1 is connected to the bias voltage. The drain of MOSFET PM1 is connected to the source of MOSFET PM2. The sources of MOSFETs PM3a and PM3b are connected together and then connected to the drain of MOSFET PM2. The drain of MOSFET PM3a is connected to the source of MOSFET PM4a. The drain of MOSFET PM3b is connected to the source of MOSFET PM4b. The gates of MOSFET PM4a and PM4b are connected to each other. The drains of MOSFET PM4a and PM4b are the two output terminals of the current source unit. The gates of the MOS transistor PM3a and PM3b are respectively connected to latches in the clock power domain.

3. The digital-to-analog converter chip according to claim 2, characterized in that, The analog power domain includes a first AND gate unit, a first protection circuit, and a first bias circuit, wherein the first protection circuit and the first bias circuit are respectively connected to the output terminal of the first AND gate unit. The clock power domain also includes an undervoltage lockout circuit, which is connected between the clock power ground voltage of the second linear regulator and the input of the first AND gate unit. Wherein, after the second linear regulator is started, its clock power ground voltage passes through the undervoltage lockout circuit and the undervoltage lockout circuit outputs a control signal; after the first AND gate unit obtains the power establishment signal output by the power detection circuit connected to the analog power supply and the control signal, it starts and controls the first protection circuit and the first bias circuit.

4. The digital-to-analog converter chip according to claim 3, characterized in that, The first AND gate unit further includes a NOT gate unit and a delay unit. The NOT gate unit is connected in series to the output terminal of the first AND gate unit, and the delay unit is connected in series to the output terminal of the NOT gate unit. Both the NOT gate unit and the delay unit are connected to the first bias circuit and the first protection circuit. After acquiring the power establishment signal and the control signal output by the power detection circuit connected to the analog power supply, the first AND gate unit outputs a first switch signal, the NOT gate unit outputs a second switch signal, and the delay unit outputs a third switch signal. The first switch signal, the second switch signal, and the third switch signal are used to control the activation of the first bias circuit and the first protection circuit.

5. The digital-to-analog converter chip according to claim 4, characterized in that, The first protection circuit includes MOSFET PM5, MOSFET NM2, MOSFET NM1, a first switch, a second switch, a third switch, a first capacitor, and a first resistor; The source of MOSFET PM5 is connected to the drain of MOSFET PM1 and the gate of MOSFET PM5, respectively, and the gate of MOSFET PM5 is used to connect to the control voltage; the drain of MOSFET NM2 is connected to the source of MOSFET PM5, and the gate of MOSFET NM2 is connected to the drain of MOSFET PM5; the drain of MOSFET NM1 is connected to the drain of MOSFET PM5 and the gate of MOSFET NM2, respectively, and the gate of MOSFET NM1 is used to connect to the control voltage, and the source of MOSFET NM1 is connected to the negative power supply voltage of the analog power supply; The first capacitor is connected between the gate of the MOS transistor PM2 and the positive power supply voltage of the analog power supply. The common input terminal of the first switch and the first resistor connected in series is connected to the first capacitor, and the common output terminal is connected to the bias voltage. The second switch is connected in parallel with the structure formed by the series connection of the first switch and the first resistor; one end of the third switch is connected to the input terminal of the second switch, and the other end is connected to the negative power supply voltage of the analog power supply. Wherein, the first switch is used to open and close under the action of the first switch signal, the second switch is used to open and close under the action of the third switch signal, and the third switch is used to open and close under the action of the second switch signal.

6. The digital-to-analog converter chip according to claim 5, characterized in that, The first bias circuit includes MOSFET NM0, a second resistor, MOSFET NM9, MOSFET NM10, MOSFET NM6, MOSFET NM4a, MOSFET NM4b, MOSFET NM7, MOSFET PM6, MOSFET PM11, MOSFET PM0, MOSFET NM3a, MOSFET NM3b, MOSFET NM3c, MOSFET PM7a, MOSFET PM7b, MOSFET PM8a, MOSFET PM8b, MOSFET NM5a, MOSFET NM5b, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a second capacitor, a third resistor, MOSFET PM9, MOSFET PM10, and MOSFET NM8; The gates of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are interconnected. The sources of MOSFETs NM0, NM9, NM10, NM6, NM4a, NM4b, and NM7 are all connected to the negative power supply voltage of the analog power supply. The drain of MOSFET NM0 is connected to the gate of MOSFET NM0. The second resistor is connected between the drain of MOSFET NM0 and the positive power supply voltage of the analog power supply. The drain of MOSFET PM6 is connected to the gate of MOSFET NM6 and the drain of MOSFET NM9. The drain of MOSFET PM11 is connected to the source of MOSFET NM6. The gate of MOSFET PM11 is connected to the gate of MOSFET NM6. The source of MOSFET PM11 is connected to the positive power supply voltage of the analog power supply. The drain of MOSFET PM0 is connected to the drain of MOSFET NM10 and the gate of MOSFET NM0. The source of MOSFET PM0 is connected to the positive power supply voltage of the analog power supply. The gate of MOSFET NM3a is connected to the low-noise regulated output voltage of the second linear regulator. The drain of MOSFET NM3a is connected to the drain of MOSFET NM3b. The source of MOSFET NM3a is connected to the source of MOSFET NM3b. The gate of MOSFET NM3b is connected to the given voltage VBC. The sources of MOSFET NM3b and NM3c are both connected to the drain of MOSFET NM6. The gate of MOSFET NM3c is connected to the drain of MOSFET NM8. The drain of MOSFET NM3c is connected to the drain of MOSFET PM7b. The drain of MOSFET NM3b is connected to the drain of MOSFET PM8a. The sources of MOSFET PM8a and PM8b are both connected to the positive power supply voltage of the analog power supply. The gates of MOSFET PM8a and PM8b are connected to the gates of MOSFETs PM0 and PM9. The drain of MOSFET PM8a is also connected to the source of MOSFET PM7a, and the drain of MOSFET PM8b is also connected to the source of MOSFET PM7b. The gates of MOSFETs PM7a, PM7b, and PM6 are interconnected. The drain of MOSFET PM7a is connected to the drain of MOSFET NM5a, the drain of MOSFET PM7b is connected to the drain of MOSFET NM5b, the gate of MOSFET NM5a is connected to the drain of MOSFET NM5a and the gate of MOSFET NM5b, the source of MOSFET NM5a and MOSFET NM5b are both connected to the negative power supply voltage of the analog power supply, and the gate of MOSFET NM5a and the gate of MOSFET NM5b are both connected to the drain of MOSFET NM4a. The drain of MOSFET NM4b is connected to the drain of MOSFET NM5b. One end of the fourth switch is connected to the drain of MOSFET NM4b, and the other end is connected to the negative power supply voltage of the analog power supply. One end of the fifth switch is connected to the drain of MOSFET PM7b, and the other end is connected to the gate of MOSFET PM10. The sixth switch is connected between the other end of the fifth switch and the positive power supply voltage of the analog power supply. The series structure formed by the third resistor and the seventh switch is connected between the positive power supply voltage of the analog power supply and the gate of MOSFET PM10. One end of the second capacitor is connected to the other end of the fifth switch, and the other end is connected to the negative power supply voltage of the analog power supply. The source of the MOSFET PM9 is connected to the positive power supply voltage of the analog power supply. The drain of the MOSFET PM9 is connected to the source of the MOSFET PM10 and the gate of the MOSFET NM3c. The gate of the MOSFET PM10 is connected to the source of the MOSFET PM10. The drain of the MOSFET PM10 is connected to the drain of the MOSFET NM7 and the gate of the MOSFET NM8. The source of the MOSFET NM8 is connected to the negative power supply voltage of the analog power supply. The gate of MOS transistor PM10 is connected to the gate of MOS transistor PM5, and the gate of MOS transistor NM7 is connected to the gate of MOS transistor NM1.

7. The digital-to-analog converter chip according to claim 6, characterized in that, The given voltage VBC is generated by the bandgap reference of the analog power supply domain, and the difference between the given voltage VBC and the negative power supply voltage of the analog power supply is equal to the standard operating voltage of the low-voltage device.

8. The digital-to-analog converter chip according to claim 2, characterized in that, The analog power domain also includes a second protection circuit, which includes a PMOS transistor M1, an NMOS transistor m2, and an NMOS transistor m1. The source of PMOS transistor M1 is connected to the source of MOS transistor PM3a. The gate of PMOS transistor M1 is connected to the positive power supply voltage and control voltage of the analog power supply. The drain of PMOS transistor M1 is connected to the gate of NMOS transistor m2. The drain of NMOS transistor m2 is connected to the source of PMOS transistor M1. The source of MOS transistor M2 is connected to the negative power supply voltage of the analog power supply. The drain of NMOS transistor m1 is connected to the drain of PMOS transistor M1. The source of NMOS transistor m1 is connected to the negative power supply voltage of the analog power supply. The gate of NMOS transistor m1 is connected to the control voltage.

9. The digital-to-analog converter chip according to claim 8, characterized in that, The analog power domain further includes a second bias circuit, which includes NMOS transistors m5, m4, m3, M5, M4, a fourth resistor, a first operational amplifier OTA2, M2, M3, M6, a second operational amplifier OTA1, and a fifth resistor. The gates of NMOS transistors m5, m4, m3, and m1 are interconnected, and the sources of NMOS transistors m5, m4, and m3 are connected to the negative power supply voltage of the analog power supply. The drain of the NMOS transistor m5 is connected to the drain of the PMOS transistor M5, the drain of the PMOS transistor M5 is connected to the gate of the PMOS transistor M5, the gate of the PMOS transistor M5 is connected to the gate of the PMOS transistor M1 and the positive power supply voltage of the analog power supply, the source of the PMOS transistor M5 is connected to the drain of the PMOS transistor M4, the source of the PMOS transistor M4 is connected to the positive power supply voltage of the analog power supply, the drain of the PMOS transistor M4 is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the NMOS transistor m4. The gate of the PMOS transistor M4 is connected to the output terminal of the first operational amplifier OTA2, the positive input terminal of the first operational amplifier OTA2 is connected to the other end of the fourth resistor, and the negative input terminal is connected to the negative voltage source of the clock power supply. The drain of NMOS transistor m3 is connected to the gate of NMOS transistor m3 and the drain of PMOS transistor M2. The sources of PMOS transistor M2 and PMOS transistor M3 are both connected to the positive power supply voltage of the analog power supply. The gates of PMOS transistor M2 and PMOS transistor M3 are interconnected and then connected to the drain of PMOS transistor M3. The drain of PMOS transistor M3 is connected to the drain of NMOS transistor m6. The source of NMOS transistor M6 is connected to one end of the fifth resistor. The other end of the fifth resistor is connected to the negative power supply voltage of the analog power supply. The output terminal of the second operational amplifier OTA1 is connected to the gate of NMOS transistor m6. The negative input terminal of the second operational amplifier OTA1 is connected to one end of the fifth resistor.

10. The digital-to-analog converter chip according to claim 9, characterized in that, The positive input terminal of the second operational amplifier OTA1 is connected to the reference voltage generated by the on-chip bandgap reference.

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