Phase interpolator and memory device including the same

Abstract

A phase interpolator and a memory device including the same are provided. The phase interpolator provides a pair of differential outputs according to a plurality of inputs having a plurality of phases, the phase interpolator including: a main digital-to-analog converter (DAC) circuit configured to phase interpolate a first input and a second input having a quadrature phase among the plurality of inputs according to a main code to generate a main output signal; an auxiliary DAC circuit configured to: phase interpolate the first input and the second input according to an auxiliary code corresponding to the main code to generate an auxiliary output signal; and an output buffer configured to generate the pair of differential outputs according to a differential input based on a phase output signal, the phase output signal being a sum of the main output signal and the auxiliary output signal.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0195419, filed with the Korean Intellectual Property Office on December 28, 2023, and Korean Patent Application No. 10-2024-0032750, filed with the Korean Intellectual Property Office on March 7, 2024, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0002] The disclosure relates to a phase interpolator and a memory device including the phase interpolator. Background Art

[0003] As defined by the Joint Electron Device Engineering Council (JEDEC) standard, a register clock driver (RCD) integrated circuit (IC) for driving a memory device needs a 1 / 64-step phase interpolation function to achieve optimal timing control between memory devices. To support a data processing rate of 7.2 Gbps at double data rate (DDR) 5, the RCD should provide a phase interpolation function with high linear characteristics at a clock frequency of up to 3.6 GHz. Multiple phase interpolators are required to support memory devices, and current-mode phase interpolators are generally used to avoid power interference and frequency pulling.

[0004] However, since a current-mode phase interpolator uses a first-order linear code to adjust the current output of a digital-to-analog converter (DAC), significant phase and amplitude errors may occur at the current-mode logic (CML) level during the interpolation process. In addition, when converting the output signal from the CML level to the complementary metal-oxide-semiconductor (CMOS) level, these amplitude errors may cause amplitude-to-phase modulation (AM-to-PM) distortion. This AM-to-PM distortion can reduce the linear characteristics of the current-mode phase interpolator. Summary of the Invention

[0005] The disclosure provides a phase interpolator and a memory device including the phase interpolator that can minimize phase and amplitude errors in a phase interpolation process at the current-mode logic (CML) level.

[0006] According to an exemplary embodiment, a phase interpolator is provided that provides a pair of differential outputs based on a plurality of inputs having multiple phases. The phase interpolator includes: a main digital-to-analog converter (DAC) circuit configured to perform phase interpolation on a first input and a second input having quadrature phases among the plurality of inputs according to a main code to generate a main output signal; an auxiliary DAC circuit configured to perform phase interpolation on the first input and the second input according to an auxiliary code corresponding to the main code to generate an auxiliary output signal; and an output buffer configured to generate the pair of differential outputs based on a differential input based on a phase output signal, which is a sum of the main output signal and the auxiliary output signal.

[0007] According to an exemplary embodiment, a phase interpolator is provided, including: a main DAC circuit configured to provide a first phase current based on a first input having a first weight and a second phase current based on a second input orthogonal to the first input having a second weight to a first node; an auxiliary DAC circuit configured to provide a third phase current based on the first input having a third weight and a fourth phase current based on the second input to the first node; an output buffer configured to generate an output signal based on a voltage of the first node; and an auxiliary DAC controller configured to determine the third weight based on an auxiliary code corresponding to a main code indicating the first weight and the second weight.

[0008] According to an exemplary embodiment, a memory device is provided, including: a plurality of memory modules; and a phase interpolator configured to buffer command, address, and clock signals provided from an external source and send the buffered command, address, and clock signals to the plurality of memory modules, wherein the phase interpolator includes: a main DAC circuit configured to perform phase interpolation on a first input and a second input having quadrature phases representing each of the command, the address, and the clock signal based on a main code to generate a main output signal; an auxiliary DAC circuit configured to perform phase interpolation on the first input and the second input based on an auxiliary code corresponding to the main code to generate an auxiliary output signal; and an output buffer configured to generate a pair of differential outputs based on a differential input based on a phase output signal, which is a sum of the main output signal and the auxiliary output signal.

[0009] The phase interpolator and the memory device including the phase interpolator are designed to minimize phase and amplitude errors in a current-mode logic (CML) level phase interpolation process. By improving the linearity of the phase interpolator, the memory device can capture data with optimal timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0011] Figure 2 is a diagram showing a register clock driver according to an disclosed embodiment.

[0012] Figure 3 is a block diagram showing the configuration of a main digital-to-analog converter (DAC) circuit according to an disclosed embodiment.

[0013] Figure 4 is the phase constellation of the main output signal of the main DAC circuit according to an disclosed embodiment.

[0014] Figure 5 is a block diagram showing the configuration of an auxiliary DAC circuit according to an disclosed embodiment.

[0015] Figure 6 is the phase constellation of the phase output signal according to an disclosed embodiment.

[0016] Figure 7 is a diagram showing the first quadrant of the phase constellations of the main output signal and the phase output signal according to an disclosed embodiment.

[0017] Figure 8 is a circuit diagram showing one of a plurality of main DAC circuits according to an disclosed embodiment.

[0018] Figure 9 is a circuit diagram showing one of a plurality of auxiliary DAC circuits according to an disclosed embodiment.

[0019] Figure 10 is a circuit diagram showing one of a plurality of auxiliary DAC circuits according to an disclosed embodiment.

[0020] Figure 11A and Figure 11B is a graph showing the improved integral nonlinearity in the case of adding an auxiliary DAC circuit.

[0021] Figure 12A and Figure 12B is a graph showing the improved differential linearity in the case of adding an auxiliary DAC circuit.

[0022] Figure 13A and Figure 13B is a graph showing the improved amplitude and amplitude-to-phase modulation (AM to PM) distortion of the phase output signal in the case of adding an auxiliary DAC circuit. Detailed Description

[0023] The present disclosure relates to phase and amplitude compensation for improving the linearity of a current-mode phase interpolator. Some disclosed embodiments may include a main digital-to-analog converter (DAC) circuit and an auxiliary DAC circuit that adjust the current output of a current-mode phase interpolator. In response to a main code, the main DAC circuit controls the current output, and the auxiliary DAC circuit may control an additional current output. By this method, the output current of the current-mode phase interpolator can be adjusted to a target current. The target current is a current having a desired phase and amplitude according to the main code.

[0024] In the following description, a signal level may be defined as a current-mode logic (CML) level or a complementary metal-oxide semiconductor (CMOS) level. Each of the CML level and the CMOS level corresponds to a signal having a specific amplitude based on a corresponding DC level. The reference DC level and amplitude of the CML level are less than those of the CMOS level.

[0025] Figure 1 is a block diagram showing an electronic device according to an embodiment of the disclosure.

[0026] The electronic device 1 may include a memory controller 11 and a memory device 12. For example, the electronic device 1 may be a mobile system (such as a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device) or may be included in a mobile system (such as a mobile phone, a smartphone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of Things (IoT) device). The electronic device 1 may be an automotive device (such as a personal computer, a laptop computer, a server, a media player, or a navigation device) or may be included in an automotive device (such as a personal computer, a laptop computer, a server, a media player, or a navigation device).

[0027] The memory controller 11 may be configured to store data in the memory device 12 or read data stored in the memory device 12. For example, the memory controller 11 may send a command CMD, an address ADDR, and a clock signal CLK to the memory device 12. In some embodiments, the memory controller 11 may be a system-on-chip (SoC) or may be included in a system-on-chip (SoC). The memory controller 11 may generate a command CMD and an address ADDR for the memory device 12 in response to a request from an internal processor of a host. The memory device 12 may operate as a buffer memory, a working memory, or a main memory of the host. The host may include the memory controller 11 or may be a higher-level controller for the memory controller 11.

[0028] The memory device 12 may operate under the control of the memory controller 11. In response to a command CMD, an address ADDR, and a clock signal CLK received from the memory controller 11, the memory device 12 may store data received through data signals DQ and a data strobe signal DQS or output data stored in the memory device 12 to the memory controller 11 through the data signals DQ and the data strobe signal DQS.

[0029] The memory device 12 may include a register clock driver 13, and the register clock driver 13 includes a phase interpolator and a plurality of memory modules 14. Each of the memory modules 14 may be a dynamic random access memory (DRAM) device. However, the disclosed scope is not limited thereto. In response to a command CMD, an address ADDR, and a clock signal CLK provided through the register clock driver 13, the plurality of memory modules 14 may write data received through the data signals DQ and the data strobe signal DQS into the plurality of memory modules 14, or output data stored in the plurality of memory modules 14 to the memory controller 11 through the data signals DQ and the data strobe signal DQS.

[0030] The register clock driver 13 may be connected to the plurality of memory modules 14 and drive the plurality of memory modules 14. The register clock driver 13 may include a phase interpolator 31. The phase interpolator 31 may be implemented as a current-mode phase interpolator. The register clock driver 13 may use the current-mode phase interpolator 31 to receive a command CMD, an address ADDR, and a clock signal CLK from the memory controller 11, buffer the command CMD, the address ADDR, and the clock signal CLK, and send the buffered command CMD, address ADDR, and clock signal CLK to the plurality of memory modules 14.

[0031] During the buffering of the control register clock driver 13, phase interpolation may be provided. Phase interpolation refers to generating an input having a specific phase between two mutually orthogonal phase signals using two mutually orthogonal phase signals. The register clock driver 13 may provide phase interpolation for each of the command CMD, the address ADDR, and the clock signal CLK. The register clock driver 13 may include a current-mode phase interpolator 31 that provides phase interpolation. The output signal of the current-mode phase interpolator 31 may be a differential signal having an inverted phase.

[0032] The current-mode phase interpolator 31 may generate a differential input through phase interpolation using two mutually orthogonal phase signals under the control of the register clock driver 13, and generate a differential signal based on the differential input. The current-mode phase interpolator 31 may generate a plurality of phase currents for generating a differential input of a voltage level. The sum of the phase currents corresponding to the same phase signal among the plurality of phase currents is referred to as an output signal of the corresponding phase (hereinafter, a phase output signal).

[0033] The positive input among the differential inputs is determined by a combination of two phase output signals corresponding to each of two mutually orthogonal phase signals, and the negative input among the differential inputs can be determined by a combination of two inverted phase output signals corresponding to each of two inverted phase signals of the two mutually orthogonal phase signals.

[0034] In the following description, phase interpolation using two mutually orthogonal phase signals is described.

[0035] The memory controller 11 may provide a main code (M-CODE) to the current-mode phase interpolator 31 to control the phase interpolation of the main DAC circuit 130. The current-mode phase interpolator 31 may determine an auxiliary code (A-CODE) corresponding to the M-CODE to control the phase interpolation of the auxiliary DAC circuit 140. Then, the phase interpolation of the current-mode phase interpolator 31 may be controlled based on both the M-CODE and the A-CODE. The current-mode phase interpolator 31 may generate a differential input by combining the phase interpolation according to the M-CODE and the phase interpolation according to the A-CODE, and then generate a differential output based on the differential input. The differential output may indicate a command CMD, an address ADDR, and a clock signal CLK received by the memory device 12.

[0036] The memory controller 11 may perform training to determine the M-CODE. During this training, the memory controller 11 may sample the output signal of the current-mode phase interpolator 31 while changing the M-CODE. The M-CODE at which the sampled output signal reaches the optimal level may then be determined.

[0037] Figure 2 is a diagram showing a register clock driver according to an exemplary embodiment.

[0038] As Figure 2 shown, the register clock driver 13 may include a current-mode phase interpolator 31 and a controller interface 32. The current-mode phase interpolator 31 may include a main DAC (M-DAC) controller 33, a mapping table 35, an auxiliary DAC (A-DAC) controller 34, a load circuit 110, an output buffer 120, a main DAC circuit (M-DAC circuit) 130, and an auxiliary DAC circuit (A-DAC circuit) 140.

[0039] The controller interface 32 can generate phase signals f000, f090, f180, and f270 for each of the command CMD, address ADDR, and clock signal CLK provided from the memory controller 11. Each of the phase signals f000, f090, f180, and f270 can correspond to the respective phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. For example, the phase of the phase signal f000 can be 0 degrees, the phase of the phase signal f090 can be 90 degrees, the phase of the phase signal f180 can be 180 degrees, and the phase of the phase signal f270 can be 270 degrees. The phase signals f000, f090, f180, and f270 can be provided as input signals to the main DAC circuit 130 and the auxiliary DAC circuit 140.

[0040] The main DAC controller 33 can control the phase interpolation of the main DAC circuit 130 according to the M-CODE. The main DAC controller 33 can select two orthogonal phase signals from the phase signals f000, f090, f180, and f270 based on the M-CODE, and determine the respective weights of each of the selected phase signals. The M-CODE can include a phase region code and a phase control code. The phase region code indicates which two orthogonal phase signals are selected from the four phase signals f000, f090, f180, and f270, and the phase control code specifies the weights of each of the two orthogonal phase signals. Using the phase region code of the M-CODE, the main DAC controller 33 can select two orthogonal phase signals and generate a plurality of main control signals MSW_1 to MSW_16 to control the phase interpolation of the main DAC circuit 130 based on the two weights provided by the phase control code.

[0041] The phase region defined by the two orthogonal phase signals selected from the four phase signals f000, f090, f180, and f270 can correspond to one of the first quadrant of 0 degrees to 90 degrees, the second quadrant of 180 degrees to 270 degrees, the third quadrant of 180 degrees to 270 degrees, and the fourth quadrant of 0 degrees to 270 degrees. Figure 2 The main DAC circuit 130 shown can include 16 DACs. To control the phase output signals of the 16 DACs, the main DAC controller 33 can generate a plurality of main control signals MSW_1 to MSW_16. The number of the main control signals MSW_1 to MSW_16 depends on the number of DACs constituting the main DAC circuit 130, but the number of DACs and the number of main control signals are not limited thereto.

[0042] The auxiliary DAC controller 34 may control the phase interpolation of the auxiliary DAC circuit 140 based on the M-CODE. The auxiliary DAC controller 34 may determine an A-CODE that specifies the weight of each of two orthogonal phase signals selected from the phase signals f000, f090, f180, and f270 according to the M-CODE. The auxiliary DAC controller 34 may generate a plurality of auxiliary control signals ASW_1 to ASW_8 based on the two weights. The number of the auxiliary control signals ASW_1 to ASW_8 depends on the number of DACs that constitute the auxiliary DAC circuit 140, and the number of DACs and the number of auxiliary control signals are not limited thereto.

[0043] The load circuit 110 is connected between the power supply voltage VDD and two nodes MXP and MXN. The main output signal of the main DAC circuit 130 and the auxiliary output signal of the auxiliary DAC circuit 140 are concentrated in the load circuit 110. The voltage at the node MXP (the first output voltage VXP) is determined by the voltage drop in the load circuit 110, which is caused by the main output signal and the auxiliary output signal flowing between the node MXP and the power supply voltage VDD. The voltage of the node MXN (the second output voltage VXN) is determined by the voltage drop in the load circuit 110, which is caused by the main output signal and the auxiliary output signal flowing between the node MXN and the power supply voltage VDD. The load circuit 110 includes a resistor RL connected between the power supply voltage VDD and the node MXP and another resistor RL connected between the power supply voltage VDD and the node MXN. In Figure 2 , two capacitors CL are connected in parallel in the load circuit 110. The two capacitors CL may form a capacitor bank that performs harmonic filtering for each band, thereby supporting a wide frequency band for each of the first output voltage VXP and the second output voltage VXN.

[0044] The output buffer 120 can generate two output signals OUTP and OUTN with CMOS levels by inverting a first output voltage VXP and a second output voltage VXN with CML levels, respectively. The output buffer 120 can include two capacitors 121 and 122, two resistors 123 and 124, and an inverter 125. The capacitor 121 can provide an AC coupling between the node MXP and the input node N1 to filter out the DC component of the first output voltage VXP. The capacitor 122 can provide an AC coupling between the node MXN and the input node N2 to filter out the DC component of the second output voltage VXN. The resistor 123 can be connected between the output node N3 of the inverter 125 and the input node N1 to feedback the output signal OUTP back to the input node N1. The resistor 124 can be connected between the output node N4 of the inverter 125 and the input node N2 to feedback the output signal OUTN back to the input node N2.

[0045] The output buffer 120 can invert a first output signal VXP with CML level to generate an output signal OUTP with CMOS level, and invert a second output signal VXN with CML level to generate an output signal OUTN with CMOS level. The first output signal OUTP and the second output signal OUTN can be differential outputs representing a command CMD, an address ADDR, and a clock signal CLK input to the current-mode phase interpolator 31.

[0046] Figure 3 is a block diagram showing the configuration of the main DAC circuit according to the disclosed embodiments.

[0047] As Figure 3 shown, the main DAC circuit 130 can include 16 DACs: M-DAC_1 to M-DAC_16 (130_1 to 130_16). Each of M-DAC_1 to M-DAC_16 (130_1 to 130_16) can provide phase currents flowing from two nodes MXP and MXN to each of M-DAC_1 to M-DAC_16 (130_1 to 130_16) according to each of a plurality of main control signals MSW_1 to MSW_16. The main DAC circuit 130 can provide two main output signals for each of the two nodes MXP and MXN. One of the two main output signals can be the sum of the phase currents flowing from the node MXP to M-DAC_1 to M-DAC_16 (130_1 to 130_16), and the other can be the sum of the phase currents flowing from the node MXN to M-DAC_1 to M-DAC_16 (130_1 to 130_16).

[0048] The phase of the voltages at nodes MXP and MXN, which are differential inputs, can be controlled according to the phase currents of M-DAC_1 to M-DAC_16 (130_1 to 130_16). Each of M-DAC_1 to M-DAC_16 (130_1 to 130_16) can control the phase currents from the two nodes MXP and MXN based on one of two orthogonal phase signals as determined by the corresponding main control signals MSW_1 to MSW_16. The on-off level combinations of each of the multiple main control signals MSW_1 to MSW_16 can vary according to the weights of each of the two orthogonal phase signals. Each of the multiple main control signals MSW_1 to MSW_16 can include multiple switch signals, and each of the multiple switch signals is at either a closed level (ON level) or an open level (OFF level). The closed-open level combination of each main control signal represents the combination of the closed levels and open levels of the multiple switch signals.

[0049] According to some embodiments, the 1 / 64 interval phase interpolation provided by the main DAC circuit 130 utilizes two orthogonal phase signals from four phase signals f000, f090, f180, and f270 having phases of 0 degrees, 90 degrees, 180 degrees, and 270 degrees. Specifically, the available combinations of the two orthogonal phase signals can include (0°, 90°), (180°, 90°), (180°, 270°), and (0°, 270°). The main DAC circuit 130 can generate the main output signal V PI [n] by combining the two orthogonal phase signals sin(2πft) and cos(2πft) as a first-order linear sum as shown in Equation 1. By adjusting the weights w I [n] and w Q [n] of the two orthogonal phase signals at 1 / 16 intervals, the main DAC circuit 130 can generate the nth phase current V PI [n] interpolated between the two orthogonal phase signals. Thus, the main DAC circuit 130 can achieve phase interpolation at 1 / 64 intervals between 0° and 360°.

[0050] [Equation 1]

[0051]

[0052] In Equation 1, the two phase signals sin(2πft) and cos(2πft) that are orthogonal to each other are sine signals. To make the main output signal V PI [n] have a constant amplitude and be phase-interpolated at regular intervals, the weights w I [n] and w Q [n] should respectively have as The orthogonal sine relationship. In Equation 1, A PI [n]=K, and K = constant.

[0053] However, implementing weights with an orthogonal sine relationship requires a high-resolution current DAC, which increases the circuit size due to high implementation complexity. To reduce the resolution of the current DAC, the current-mode phase interpolator 31 can use two weights w I [n]+w Q [n]=K to interpolate the phases such that their first-order linearity and constancy are maintained.

[0054] Figure 4 is the phase constellation of the main output signal of the main DAC circuit according to the disclosed embodiments.

[0055] Figure 4 The phase constellation follows the horizontal and vertical coordinate systems that respectively indicate the I signal and the Q signal constituting the main output signal. In this phase constellation, points (referred to as "output points") (such as point 310) indicate the phase and amplitude of the main output signal for each of the 64 codes, forming a rhombus 320. When the main DAC circuit 130 generates the main output signal by using phase interpolation with two weights having first-order linearity and constancy, the phase constellation 320 of the main output signal has a rhombus shape.

[0056] As Figure 4 shown, for each of the 64 codes, there is a phase or / and amplitude difference between the phase constellation 320 and the circle 300. The circle 300 represents the phase constellation when the main output signal is generated with a constant amplitude and a constant phase interval. For example, during the 8 / 64 phase interpolation step in the first quadrant, the maximum amplitude difference AM3 appears between the amplitude AM1 of the main output signal and the corresponding reference amplitude AM2 on the circle 300. During the 44 / 64 phase interpolation step in the third quadrant, the maximum phase difference PM3 appears between the phase PM1 of the main output signal and the corresponding reference phase PM2 on the circle 300.

[0057] When the first-order linearity and constancy of the two weights for each code are maintained, as Figure 4 shown, the phase differences (such as PD1, PD2) between the main output signals for each code are not constant. This non-constancy results in a large differential nonlinearity (DNL) and a large integral nonlinearity (INL) with respect to the phase of the main output signal. In addition, the amplitude variations (such as AM0 - AM1) of the main output signals for each code are large, resulting in AM to PM distortion when the output signal at the CML level is converted to the CMOS level through the output buffer 120.

[0058] According to some embodiments, the current mode phase interpolator 31 may further include an auxiliary DAC circuit 140 that provides each of two additional auxiliary weights to each of two weights to improve the linearity of the main DAC circuit 130.

[0059] Figure 5 is a block diagram showing a configuration of an auxiliary DAC circuit according to an embodiment disclosed.

[0060] As Figure 5 shown, the auxiliary DAC circuit 140 may include eight DACs: A-DAC_1 to A-DAC_8 (140_1 to 140_8). Each of A-DAC_1 to A-DAC_8 (140_1 to 140_8) may provide phase currents flowing from two nodes MXP and MXN to A-DAC_1 to A-DAC_8 (140_1 to 140_8) respectively according to a plurality of auxiliary control signals ASW_1 to ASW_8. The auxiliary DAC circuit 140 may provide two auxiliary output signals for each of the two nodes MXP and MXN. One of the two auxiliary output signals may be the sum of the phase currents flowing from the node MXP to A-DAC_1 to A-DAC_8 (140_1 to 140_8), and the other may be the sum of the phase currents flowing from the node MXN to A-DAC_1 to A-DAC_8 (140_1 to 140_8).

[0061] The voltage phases at the nodes MXP and MXN representing the phase of the differential input may be controlled according to the phase currents of A-DAC_1 to A-DAC_8 (140_1 to 140_8). Each of A-DAC_1 to A-DAC_8 (140_1 to 140_8) may control the phase currents from the two nodes MXP and MXN based on one of two orthogonal phase signals determined by the corresponding auxiliary control signals ASW_1 to ASW_8. The closed-open level combinations of each of the plurality of auxiliary control signals ASW_1 to ASW_8 may vary according to the weights of each of the two orthogonal phase signals. Each of the plurality of auxiliary control signals ASW_1 to ASW_8 may include a plurality of switch signals, and each switch signal is at a conductive level or a cutoff level. The closed-open level combination of each auxiliary control signal represents the combination of the closed levels and the open levels of the plurality of switch signals.

[0062] For each of the two nodes MXP and MXN, when the auxiliary output signals provided by the auxiliary DAC circuit 140 are added to the main output signals provided by the main DAC circuit 130, a phase output signal having a phase constellation of a circle 300 close to Figure 4 may be provided.

[0063] Figure 6is the phase constellation of the phase output signal according to the disclosed embodiments.

[0064] Figure 6 The phase constellation follows the horizontal and vertical coordinate systems indicating the I-signal and Q-signal that constitute the phase output signal. This constellation showing 64 output points (e.g., 610) for each code is depicted as an octagon. The phase constellation 600 where the auxiliary output signal is superimposed on the main output signal is more closely similar to the circle 300 than Figure 4 the phase constellation 320 shown in

[0065] As Figure 6 shown in Figure 4 for each of the 64 codes, the phase and / or amplitude difference between the phase constellation 600 and the circle 300 is less than Figure 4 the phase and / or amplitude difference shown in

[0066] Thus, Figure 6 the phase constellation 600 in

[0067] shows a reduced phase difference between the phase output signals for each code, resulting in a reduced differential non-linearity (DNL) and integral non-linearity (INL) with respect to the phase of the phase output signal. In addition, when the output signal with CML level passes through the buffer to be converted to CMOS level, the amplitude variation of the phase output signal for each code is reduced, thereby reducing the AM to PM distortion.

[0068] First, Table 1 shows the M-CODE and the corresponding A-CODE. The M-CODE and the corresponding A-CODE indicate phase interpolation using two orthogonal phase signals f000 and f090 among the multiple phase signals f000, f090, f180, and f270. The phase output signal generated using the two phase signals f000 and f090 according to the M-CODE and A-CODE is in the phase region of the first quadrant.

[0069] [Table 1]

[0070]

[0071] In Table 1, the M-CODE can be a 6-bit signal. The higher 2 bits (MSB<1:0>) of the M-CODE are the phase region codes indicating which two orthogonal phase signals will be used for phase interpolation. The main DAC controller 33 can determine the two orthogonal phase signals for the main DAC circuit 130 based on the phase region code. The lower 4 bits (LSB<3:0>) of the M-CODE are the phase control codes indicating the weight of each of the two orthogonal phase signals, the I signal and the Q signal, that make up the main output signal. The weight of the I signal reflects the number of phase currents corresponding to the I signal, and the weight of the Q signal reflects the number of phase currents corresponding to the Q signal. According to the LSB<3:0> value, the weights of the I signal and the Q signal in the corresponding quadrant can be set. The "main DAC code" can indicate the number of phase currents provided by the main DAC circuit 130 for each phase. The "auxiliary DAC code" can indicate the number of phase currents provided by the auxiliary DAC circuit 140 for each phase.

[0072] As can be seen from Table 1, MSB<1:0> "00" indicates the first quadrant, where 16 codes from 0 to 15 represent phase interpolation in the first quadrant. In the first quadrant, the I signal can be in phase at 0 degrees, and the Q signal can be in phase at 90 degrees. LSB<3:0> "0000" in the first quadrant represents the maximum weight of the I signal and the minimum weight of the Q signal. As the value of LSB<3:0> increases, the weight of the I signal can decrease and the weight of the Q signal can increase. LSB<3:0> "1111" in the first quadrant represents the minimum weight of the I signal and the maximum weight of the Q signal. In the first quadrant, according to LSB<3:0> "0000", the main DAC controller 33 can control the main DAC circuit 130 to provide 16 zero-degree phase currents. In the first quadrant, according to LSB<3:0> "0001", the main DAC controller 33 can control the main DAC circuit 130 to provide 15 phase currents for 0 degrees of phase and 1 phase current for 90 degrees of phase. In the first quadrant, according to LSB<3:0> "1111", the main DAC controller 33 can control the main DAC circuit 130 to provide 1 phase current for 0 degrees of phase and 15 phase currents for 90 degrees of phase.

[0073] The auxiliary DAC controller 34 can determine two orthogonal phase signals to be used by the auxiliary DAC circuit 140 according to the phase region code. For example, when MSB<1:0> is "00", the auxiliary DAC controller 34 can select the orthogonal phase signals f000 and f090. The auxiliary DAC controller 34 can determine the A-CODE according to the phase control code LSB<3:0>. In the range of the phase control code LSB<3:0> from "0000" to "1000", according to the mapping table 35 implemented as shown in Table 1, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that the A-CODE is larger (for example, the larger the phase control code LSB<3:0>, the larger the A-CODE). Then, since the phase control code LSB<3:0> is larger, the weights of the I signal and the Q signal that make up the auxiliary output signal are larger (for example, the larger the phase control code LSB<3:0>, the larger the weights of the I signal and the Q signal that make up the auxiliary output signal). In the range of the phase control code LSB<3:0> from "1001" to "1111", according to the mapping table 35 implemented as shown in Table 1, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that the A-CODE is smaller (for example, the larger the phase control code LSB<3:0>, the smaller the A-CODE). Then, since the phase control code LSB<3:0> is larger, the weights of the I signal and the Q signal that make up the auxiliary output signal are smaller (for example, the larger the phase control code LSB<3:0>, the smaller the weights of the I signal and the Q signal that make up the auxiliary output signal).

[0074] In the first quadrant, between the 0-degree phase and the 90-degree phase indicated by the higher 2 bits MSB<0:0> of the M-CODE, when the M-CODE includes the LSB<3:0> "1000", the auxiliary DAC controller 34 can determine that the weights of the I signal and the Q signal in the auxiliary output signal have the maximum values, and the LSB<3:0> "1000" indicates the midpoint between 0 degrees and 90 degrees (e.g., 45 degrees). The auxiliary DAC controller 34 can determine the auxiliary code such that the weights of the I signal and the Q signal of the auxiliary output signal decrease as the phase indicated by the M-CODE moves away from 45 degrees. Thus, as Figure 6 shown in, when the auxiliary DAC circuit 140 provides phase interpolation according to the A-CODE based on the M-CODE, the phase constellation 600 of the phase output current can form an octagon.

[0075] Figure 7 is a diagram showing the first quadrant of the phase constellations of the main output signal and the phase output signal according to the disclosed embodiments.

[0076] In Figure 7 the main output signal, the auxiliary output signal, and the phase output signal are quantized using arbitrary units. In other words, the magnitude of each of the I signal and the Q signal of each signal can be represented by numbers (such as "8" and "3.2" in arbitrary units).

[0077] According to the M-CODE "001000", the main DAC circuit 130 can provide a main output signal interpolated in 8 / 64 steps corresponding to a phase of 45°. The main DAC circuit 130 can generate the sum of the phase currents of the I signal at 0 degrees and the Q signal at 90 degrees, both of which are "8". According to the A-CODE "1000" corresponding to the M-CODE "001000", the auxiliary DAC circuit 140 can provide an auxiliary output signal having a phase of 45° also interpolated in 8 / 64 steps. The auxiliary DAC circuit 140 can generate the sum of the phase currents of the I signal at 0 degrees and the Q signal at 90 degrees, both of which are "3.2".

[0078] Then, as Figure 7 shown in, the amplitude attenuation of the phase output signal can be minimized. According to the vector sum of the main output signal 71 of (8, 8) and the auxiliary output signal 72 of (3.2, 3.2), the phase output signal has a phase and amplitude of (11.2, 11.2). The amplitude of the phase output signal of (11.2, 11.2) is approximately 15.84, and a phase output signal with a small amplitude attenuation at 45° can be provided.

[0079] As shown in Table 1, for the A-CODE “0000” in the first quadrant, the auxiliary DAC controller 34 controls the auxiliary DAC circuit 140 not to generate an auxiliary output signal. The auxiliary DAC controller 34 can control the auxiliary DAC circuit 140 such that the auxiliary output signal is maximum at 8 / 64 steps corresponding to a phase of 45 degrees and minimum at 0 / 64 steps. The auxiliary DAC controller 34 can control the auxiliary DAC circuit 140 such that each of the I signal and Q signal of the auxiliary output signal changes in units of “0.4” per step.

[0080] Table 2 shows the M-CODE and the corresponding A-CODE, and the M-CODE and the corresponding A-CODE indicate phase interpolation using two orthogonal phase signals f180 and f090 from among the multiple phase signals f000, f090, f180, and f270. The phase output signal generated using the two phase signals f180 and f090 according to the M-CODE and A-CODE is in the phase region of the second quadrant.

[0081] [Table 2]

[0082]

[0083] As can be seen from Table 2, the MSB <1:0> “01” indicates the second quadrant, and 16 codes from 16 to 31 among the 64 codes can indicate phase interpolation in the second quadrant. The LSB <3:0> “0000” in the second quadrant can indicate the maximum weight of the Q signal and the minimum weight of the I signal. As the value of the LSB <3:0> increases, the weight of the I signal can increase and the weight of the Q signal can decrease. The LSB <3:0> “1111” in the second quadrant can indicate the minimum weight of the Q signal and the maximum weight of the I signal. In the second quadrant, according to the LSB <3:0> “0000”, the main DAC controller 33 can control the main DAC circuit 130 to provide 16 90-degree phase currents. In the second quadrant, according to the LSB <3:0> “0001”, the main DAC controller 33 can control the main DAC circuit 130 to provide 15 phase currents for a 90-degree phase and 1 phase current for a 180-degree phase. In the second quadrant, according to the LSB <3:0> “1111”, the main DAC controller 33 controls the main DAC circuit 130 to provide 1 phase current for a 90-degree phase and 15 phase currents for a 180-degree phase.

[0084] When MSB<1:0> is "01", the auxiliary DAC controller 34 can select two orthogonal phase signals f180 and f090. The auxiliary DAC controller 34 can determine A-CODE according to the phase control code LSB<3:0>. In the range of the phase control code LSB<3:0> from "0000" to "1000", according to the mapping table 35 implemented as shown in Table 2, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that A-CODE is larger. Then, since the phase control code LSB<3:0> is larger, the weights of the I signal and the Q signal that make up the auxiliary output signal are larger. In the range of the phase control code LSB<3:0> from "1001" to "1111", according to the mapping table 35 implemented as shown in Table 2, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that A-CODE is smaller. Then, as the phase control code LSB<3:0> increases, the weights of the I signal and the Q signal that make up the auxiliary output signal are smaller.

[0085] In the second quadrant between the 90-degree phase and the 180-degree phase indicated by the higher 2 bits MSB<0:1> of M-CODE, the auxiliary DAC controller 34 can determine the auxiliary code such that when M-CODE includes the LSB<3:0> "1000" indicating the midpoint (i.e., 135 degrees) between 90 degrees and 180 degrees, the weights of the I signal and the Q signal that make up the auxiliary output signal have the maximum value.

[0086] The auxiliary DAC controller 34 can determine the auxiliary code such that when the phase indicated by M-CODE is far from 135 degrees, the weights of the I signal and the Q signal of the auxiliary output signal have small values.

[0087] Table 3 shows the M-CODE indicating the phase interpolation using two orthogonal phase signals f180 and f270 among the multiple phase signals f000, f090, f180, and f270, and the corresponding A-CODE. The phase output signal generated using the two phase signals f180 and f270 according to M-CODE and A-CODE is in the phase region of the third quadrant.

[0088] [Table 3]

[0089]

[0090] As can be seen from Table 3, MSB<1:0> "01" indicates the third quadrant, and among the 64 codes, 16 codes from 32 to 47 can indicate phase interpolation in the third quadrant. LSB<3:0> "0000" in the third quadrant can indicate the maximum weight of the I signal and the minimum weight of the Q signal. Since the value of LSB<3:0> is large, the weight of the I signal can be reduced and the weight of the Q signal can be increased. LSB<3:0> "1111" in the third quadrant can indicate the minimum weight of the I signal and the maximum weight of the Q signal. In the third quadrant, according to LSB<3:0> "0000", the main DAC controller 33 can control the main DAC circuit 130 to provide 16 180-degree phase currents. In the third quadrant, according to LSB<3:0> "0001", the main DAC controller 33 can control the main DAC circuit 130 to provide 15 phase currents for the 180-degree phase and 1 phase current for the 270-degree phase. In the third quadrant, according to LSB<3:0> "1111", the main DAC controller 33 can control the main DAC circuit 130 to provide 1 phase current for the 180-degree phase and 15 phase currents for the 270-degree phase.

[0091] When MSB<1:0> is "10", the auxiliary DAC controller 34 can select two orthogonal phase signals f180 and f270. The auxiliary DAC controller 34 can determine A-CODE according to the phase control code LSB<3:0>. In the range of the phase control code LSB<3:0> from "0000" to "1000", according to the mapping table 35 implemented as shown in Table 3, since the phase control code LSB<3:0> is large, the auxiliary DAC controller 34 can determine that A-CODE is large. Then, since the phase control code LSB<3:0> is large, the weights of the I signal and the Q signal that make up the auxiliary output signal are large. In the range of the phase control code LSB<3:0> from "1001" to "1111", according to the mapping table 35 implemented as shown in Table 3, since the phase control code LSB<3:0> is large, the auxiliary DAC controller 34 can determine that A-CODE is small. Then, as the phase control code LSB<3:0> increases, the weights of the I signal and the Q signal that make up the auxiliary output signal are small.

[0092] In the third quadrant between the 180-degree phase and the 270-degree phase indicated by the higher 2-bit MSB<1:0> of the M-CODE, when the M-CODE includes the LSB<3:0> "1000" indicating the midpoint between 180 degrees and 270 degrees (i.e., 225 degrees), the auxiliary DAC controller 34 can determine that the weight of the I signal and the weight of the Q signal constituting the auxiliary output signal have the maximum values. The auxiliary DAC controller 34 can determine the auxiliary code such that when the phase indicated by the M-CODE is away from 225 degrees, the weight of the I signal and the weight of the Q signal of the auxiliary output signal have smaller values.

[0093] Table 4 shows the M-CODE indicating phase interpolation using two orthogonal phase signals f000 and f270 from among the multiple phase signals f000, f090, f180, and f270, and the corresponding A-CODE. The phase output signal generated using the two phase signals f000 and f270 according to the M-CODE and A-CODE is in the phase region of the fourth quadrant.

[0094] [Table 4]

[0095]

[0096] As can be seen from Table 4, the MSB<1:0> "11" indicates the fourth quadrant, and among 64 codes, 16 codes from 48 to 63 can indicate phase interpolation in the fourth quadrant. The LSB<3:0> "0000" in the fourth quadrant can indicate the maximum weight of the Q signal and the minimum weight of the I signal. Since the value of the LSB<3:0> is large, the weight of the I signal can increase and the weight of the Q signal can decrease. The LSB<3:0> "1111" in the fourth quadrant can indicate the minimum weight of the Q signal and the maximum weight of the I signal. In the fourth quadrant, according to the LSB<3:0> "0000", the main DAC controller 33 can control the main DAC circuit 130 to provide 16 270-degree phase currents. In the fourth quadrant, according to the LSB<3:0> "0001", the main DAC controller 33 can control the main DAC circuit 130 to provide 15 phase currents for the 270-degree phase and 1 phase current for the 0-degree phase. In the fourth quadrant, according to the LSB<3:0> "1111", the main DAC controller 33 can control the main DAC circuit 130 to provide 15 phase currents for the 0-degree phase and 1 phase current for the 270-degree phase.

[0097] When MSB<1:0> is "11", the auxiliary DAC controller 34 can select two orthogonal phase signals f000 and f270. The auxiliary DAC controller 34 can determine A-CODE according to the phase control code LSB<3:0>. In the range of the phase control code LSB<3:0> from "0000" to "1000", according to the mapping table 35 implemented as shown in Table 4, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that A-CODE is larger. Then, since the phase control code LSB<3:0> is larger, the weight of the I signal and the weight of the Q signal that constitute the auxiliary output signal become larger. In the range of the phase control code LSB<3:0> from "1001" to "1111", according to the mapping table 35 implemented as shown in Table 4, since the phase control code LSB<3:0> is larger, the auxiliary DAC controller 34 can determine that A-CODE is small. Then, since the phase control code LSB<3:0> is larger, the weight of the I signal and the weight of the Q signal that constitute the auxiliary output signal are small.

[0098] In the second quadrant between the 270-degree phase and the 0-degree phase indicated by the higher 2 bits MSB<0:1> of M-CODE, the auxiliary DAC controller 34 can determine the auxiliary code such that when M-CODE includes the LSB<3:0> "1000" indicating the middle (i.e., 315 degrees) between 270 degrees and 0 degrees, the weight of the I signal and the weight of the Q signal that constitute the auxiliary output signal have the maximum value. The auxiliary DAC controller 34 can determine the auxiliary code such that when the phase indicated by M-CODE is away from 315 degrees, the weight of the I signal and the weight of the Q signal of the auxiliary output signal have a smaller value.

[0099] In this way, when the auxiliary DAC circuit 140 provides phase interpolation according to A-CODE based on M-CODE, as Figure 6 shown, the phase constellation 600 of the phase output current can form an octagon.

[0100] Figure 8 is a circuit diagram showing one of the main DAC circuits according to the disclosed embodiment.

[0101] In Figure 8 shown, the main circuit (130_i, where i is one of the natural numbers from 1 to 16) as one of the multiple main DAC circuits 130 includes four transconductance stages 131, 132, 133, and 134, four switches SW1, SW2, SW3, and SW4, a bias current source 139, two dummy stages 135 and 136, and four CML buffers 137_1, 137_2, 138_1, and 138_2.

[0102] Four CML buffers 137_1, 137_2, 138_1, and 138_2 buffer four phase signals f000, f180, f090, and f270 with CMOS levels into CML levels respectively to generate four phase signals C000, C180, C090, and C270. Hereinafter, each of the four phase signals C000, C090, C180, and C270 with CML levels is referred to as a phase input signal.

[0103] Each of the four transconductance stages 131 to 134 can adjust the phase current of each of the two nodes MXP and MXN according to two corresponding phase input signals that are inverted with respect to each other. Each of the four transconductance stages 131 to 134 can include two differential input transistors connected to each of the two nodes MXP and MXN.

[0104] For example, the transconductance stage 131 can adjust each of the phase currents flowing from the load circuit 110 to the node MXP and the node MXN according to the phase input signal C000 and the phase input signal C180. The transconductance stage 131 can include a transistor M1 connected to the node MXP and a transistor M3 connected to the node MXN. The transistor M1 can include a drain connected to the node MXP, a gate input with the phase input signal C000, and a source connected to one end of the switch SW1. The transistor M3 can include a drain connected to the node MXN, a gate input with the phase input signal C180, and a source connected to one end of the switch SW1. The phase current I000_P according to the product of the phase input signal C000 and the effective transconductance of the transistor M1 can flow to the transistor M1, and the phase current I180_N according to the product of the phase input signal C180 and the effective transconductance of the transistor M3 can flow to the transistor M3.

[0105] The transconductance stage 132 can adjust the phase currents flowing from the load circuit 110 to the node MXP and the node MXN according to the phase input signal C180 and the phase input signal C000 respectively. The transconductance stage 132 can include a transistor M4 connected to the node MXP and a transistor M2 connected to the node MXN. The transistor M4 can include a drain connected to the node MXP, a gate input with the phase input signal C180, and a source connected to one end of the switch SW2. The transistor M2 can include a drain connected to the node MXN, a gate input with the phase input signal C000, and a source connected to one end of the switch SW2. The phase current I180_P according to the product of the phase input signal C180 and the effective transconductance of the transistor M4 can flow to the transistor M4, and the phase current I000_N corresponding to the product of the phase input signal C000 and the effective transconductance of the transistor M2 can flow to the transistor M2.

[0106] The transconductance stage 133 can adjust each of the phase currents flowing from the load circuit 110 to each of the nodes MXP and MXN according to the phase input signal C090 and the phase input signal C270. The transconductance stage 133 can include a transistor M5 connected to the node MXP and a transistor M7 connected to the node MXN. The transistor M5 can include a drain connected to the node MXP, a gate input with the phase input signal C090, and a source connected to one end of the switch SW3. The transistor M7 can include a drain connected to the node MXN, a gate input with the phase input signal C270, and a source connected to one end of the switch SW3. The phase current Q090_P according to the product of the phase input signal C090 and the effective transconductance of the transistor M5 flows to the transistor M5, and the phase current Q270_N according to the product of the phase input signal C270 and the effective transconductance of the transistor M7 can flow to the transistor M7.

[0107] The transconductance stage 134 can adjust each of the phase currents flowing from the load circuit 110 to each of the nodes MXP and MXN according to the phase input signal C270 and the phase input signal C090. The transconductance stage 134 can include a transistor M8 connected to the node MXP and a transistor M6 connected to the node MXN. The transistor M8 can include a drain connected to the node MXP, a gate input with the phase input signal C270, and a source connected to one end of the switch SW4. The transistor M6 can include a drain connected to the node MXN, a gate input with the phase input signal C090, and a source connected to one end of the switch SW4. The phase current Q270_P according to the product of the phase input signal C270 and the effective transconductance of the transistor M8 flows to the transistor M8, and the phase current Q090_N according to the product of the phase input signal C090 and the effective transconductance of the transistor M6 can flow to the transistor M6.

[0108] The other end of the switch SW1 is connected to the bias current source 139, and the other end of the switch SW2 is connected to the bias current source 139. The other end of the switch SW3 is connected to the bias current source 139, and the other end of the switch SW4 is connected to the bias current source 139. The switch SW1 can perform a switching operation according to the switch signal SC1, the switch SW2 can perform a switching operation according to the switch signal SC2, the switch SW3 can perform a switching operation according to the switch signal SC3, and the switch SW4 can perform a switching operation according to the switch signal SC4.

[0109] For example, the main DAC controller 33 may supply the closing level switch signal SC1 and the opening level switch signals SC2 to SC4 to the plurality of switches SW1 to SW4 according to the M-CODE. Then, the switch SW1 may be closed and the plurality of switches SW2 to SW4 may be opened. The bias current source 139 may be connected to the transconductance stage 131, and the phase current I000_P according to the product of the phase input signal C000 and the effective transconductance of the transistor M1 may flow to the transistor M1, and the phase current I180_N according to the product of the phase input signal C180 and the effective transconductance of the transistor M3 may flow to the transistor M3. The sum of the phase current I000_P and the phase current I180_N may be equal to the current absorbed by the bias current source 139. When the phase input signal C000 is at a high level with respect to the phase input signal C180, the phase current I000_P may be greater than the phase current I180_N. Conversely, the phase current I180_N may be greater than the phase current I000_P.

[0110] In the same manner as described above, when each of the switch signals SC2 to SC4 is at the closing level, the corresponding phase current signal may flow.

[0111] The dummy stage 135 may include two transistors M9 and M10 and a switch SW5. The gate of the transistor M9 is connected to the gates of the transistor M1 and the transistor M2, and the source and the drain of the transistor M9 are connected to each other. The gate of the transistor M10 is connected to the gates of the transistor M3 and the transistor M4, and the source and the drain of the transistor M10 are connected to each other. The switch SW5 is connected between the source / drain of the transistor M9 and the source / drain of the transistor M10. The switch SW5 may perform a switching operation according to the switch signal SC5.

[0112] The dummy stage 136 may include two transistors M11 and M12 and a switch SW6. The gate of the transistor M11 is connected to the gates of the transistor M7 and the transistor M8, and the source and the drain of the transistor M11 are connected to each other. The gate of the transistor M12 is connected to the gates of the transistor M5 and the transistor M6, and the source and the drain of the transistor M12 are connected to each other. The switch SW6 is connected between the source / drain of the transistor M11 and the source / drain of the transistor M12. The switch SW6 may perform a switching operation according to the switch signal SC6.

[0113] The operating region of each of the four pairs of transistors M1 / M2, M3 / M4, M5 / M6, and M7 / M8 varies according to each of the four-phase input signals C000, C090, C180, and C270. Accordingly, the parasitic capacitance between the gate and the source of each of the four pairs of transistors M1 / M2, M3 / M4, M5 / M6, and M7 / M8 can be changed. To increase the nonlinearity generated by the changed parasitic capacitance, dummy transistors M9 to M12 can be provided.

[0114] For example, when the main DAC circuit 130_i provides a 0-degree phase current or a 180-degree phase current, the main DAC controller 33 generates a closed-level switch signal SC6 and an open-level switch signal SC5. Then, the switch SW6 can be closed to enable the capacitance compensation for the transistors M5 to M8 using the transistors M11 and M12. When the main DAC circuit 130_i provides a 0-degree phase current or a 180-degree phase current, the switches SW3 and SW4 are in an open state, such that the transistors M5 to M8 are in an open state. The Cgs of a transistor operating in the saturation region is 2 / 3WLCox (W: transistor channel width, L: transistor channel length, Cox: transistor oxide capacitance) larger than the Cgs of a transistor in an open state (hereinafter referred to as Cgs). To compensate for the difference, the transistors M9 to M12 having half of the channel width (0.5W) of the transistors M1 to M8 can be used. When the switch SW6 is closed, each of the transistors M11 and M12 operates in the linear region (triode) to provide an additional gate-source parasitic capacitance of "1 / 2(0.5W)LCox+(0.5W)Cov" and a gate-drain parasitic capacitance of "1 / 2(0.5W)LCox" to the gates of the cutoff transistors M5 to M8 (where Cov: overlap capacitance). This compensates for the variation caused by the difference between the input loads of the plurality of transistors M1 to M8.

[0115] In contrast, when the main DAC (130_i) circuit provides a 90-degree phase current or a 270-degree phase current, the main DAC controller 33 can generate a closed-level switch signal SC5 and an open-level switch signal SC6. The switch SW5 can be closed such that the capacitance compensation for the transistors M1 to M4 can be provided by the transistors M9 and M10.

[0116] The main DAC controller 33 may generate each of a plurality of main control signals MSW_1 to MSW_16 according to the M-CODE. Each of the plurality of main control signals MSW_1 to MSW_16 may include a plurality of switch signals SC1 to SC6. The main DAC controller 33 may generate each of the plurality of main control signals MSW_1 to MSW_16 based on the M-CODE according to the weights for each of the phase of the I signal and the phase of the Q signal. For example, when the M-CODE is "100111", according to the weight 9 of the I signal with a phase of 180 degrees and the weight 7 of the Q signal with a phase of 270 degrees in Table 3, the main DAC controller 33 may generate each of nine main control signals among the plurality of main control signals MSW_1 to MSW_16 to include the closed-level switch signals SC2 and SC6 and the open-level switch signals SC1, SC3, SC4, and SC5, and generate each of seven main control signals among the plurality of main control signals MSW_1 to MSW_16 to include the closed-level switch signals SC4 and SC5 and the open-level switch signals SC1, SC2, SC3, and SC6.

[0117] The plurality of DACs constituting the auxiliary DAC circuit 140 may also be implemented in the same manner as the DACs constituting the main DAC circuit 130. However, this is merely an example, and the auxiliary DAC circuit 140 may be implemented in a manner different from the Figure 8 circuit shown therein.

[0118] Figure 9 is a circuit diagram showing one of the auxiliary DAC circuits according to the disclosed embodiment.

[0119] The same as the description given above with reference to Figure 8 is omitted. In Figure 9 the reference numerals of each of the phase currents flowing in the auxiliary DAC are the same as those of the in-phase currents flowing in the main DAC. Figure 9 In

[0120] In Figure 9 the auxiliary circuit 140_j (j is one of natural numbers from 1 to 8) as one of the plurality of auxiliary DAC circuits 140 may include four transconductance stages 141, 142, 143, and 144, four switches SW11, SW12, SW13, and SW14, two bias current sources 149_1 and 149_2, two dummy stages 145 and 146, and four CML buffers 147_1, 147_2, 148_1, and 148_2.

[0121] Four CML buffers 147_1, 147_2, 148_1, and 148_2 can buffer four phase signals f000, f090, f180, and f270 with CMOS levels into CML levels to generate four phase input signals C000, C090, C180, and C270, respectively.

[0122] Each of the four transconductance stages 141 to 144 can adjust the phase current of each of the two nodes MXP and MXN according to two corresponding phase input signals that are inverted with respect to each other. Each of the four transconductance stages 141 to 144 can include each of two differential input transistors respectively connected to the two nodes MXP and MXN.

[0123] For example, the transconductance stage 141 can adjust each of the phase currents flowing from the load circuit 110 to the node MXP and the node MXN according to each of the phase input signal C000 and the phase input signal C180. The transconductance stage 131 can include a transistor T1 connected to the node MXP and a transistor T3 connected to the node MXN. The transistor T1 can include a drain connected to the node MXP, a gate input with the phase input signal C000, and a source connected to one end of the switch SW11. The transistor T3 can include a drain connected to the node MXN, a gate input with the phase input signal C180, and a source connected to one end of the switch SW11. The phase current I000_P according to the product of the phase input signal C000 and the effective transconductance of the transistor T1 can flow to the transistor T1, and the phase current I180_N according to the product of the phase input signal C180 and the effective transconductance of the transistor T3 can flow to the transistor T3.

[0124] The transconductance stage 142 can adjust the phase currents flowing from the load circuit 110 to the node MXP and the node MXN according to the phase input signal C180 and the phase input signal C000, respectively. The transconductance stage 142 can include a transistor T4 connected to the node MXP and a transistor T2 connected to the node MXN. The transistor T4 can include a drain connected to the node MXP, a gate input with the phase input signal C180, and a source connected to one end of the switch SW12. The transistor T2 can include a drain connected to the node MXN, a gate input with the phase input signal C000, and a source connected to one end of the switch SW12. The phase current I180_P according to the product of the phase input signal C180 and the effective transconductance of the transistor T4 can flow to the transistor T4, and the phase current I000_N according to the product of the phase input signal C000 and the effective transconductance of the transistor T2 can flow to the transistor T2.

[0125] The transconductance stage 143 can adjust each of the phase currents flowing from the load circuit 110 to each of the nodes MXP and MXN according to the phase input signal C090 and the phase input signal C270. The transconductance stage 143 can include a transistor T5 connected to the node MXP and a transistor T7 connected to the node MXN. The transistor T5 can include a drain connected to the node MXP, a gate input with the phase input signal C090, and a source connected to one end of the switch SW13. The transistor T7 can include a drain connected to the node MXN, a gate input with the phase input signal C270, and a source connected to one end of the switch SW13. The phase current Q090_P according to the product of the phase input signal C090 and the effective transconductance of the transistor T5 can flow to the transistor T5, and the phase current Q270_N according to the product of the phase input signal C270 and the effective transconductance of the transistor T7 can flow to the transistor T7.

[0126] The transconductance stage 144 can adjust each of the phase currents flowing from the load circuit 110 to each of the nodes MXP and MXN according to the phase input signal C270 and the phase input signal C090. The transconductance stage 144 can include a transistor T8 connected to the node MXP and a transistor T6 connected to the node MXN. The transistor T8 can include a drain connected to the node MXP, a gate input with the phase input signal C270, and a source connected to one end of the switch SW14. The transistor T6 can include a drain connected to the node MXN, a gate input with the phase input signal C090, and a source connected to one end of the switch SW14. The phase current Q270_P according to the product of the phase input signal C270 and the effective transconductance of the transistor T8 can flow to the transistor T8, and the phase current Q090_N according to the product of the phase input signal C090 and the effective transconductance of the transistor T6 can flow to the transistor T6.

[0127] The other end of the switch SW11 is connected to the bias current source 149_1, and the other end of the switch SW12 is connected to the bias current source 149_1. The other end of the switch SW13 is connected to the bias current source 149_2, and the other end of the switch SW14 is connected to the bias current source 149_2. The current of each of the two bias current sources 149_1 and 149_2 can be determined based on the degree of current compensation for the main output signal. For example, according to the current level of the compensated output signal as described above with reference to Figure 7 the current of each of the two bias current sources 149_1 and 149_2 can be set to 0.4 times the current provided by the bias current source 139 of the main DAC.

[0128] The switch SW11 can perform a switching operation according to the switch signal SC11, the switch SW12 can perform a switching operation according to the switch signal SC12, the switch SW13 can perform a switching operation according to the switch signal SC13, and the switch SW14 can perform a switching operation according to the switch signal SC14. For example, when two orthogonal phase inputs determined by M-CODE are 0 degrees and 90 degrees, the auxiliary DAC controller 34 can supply the closed-level switch signals SC11 and SC13 and the open-level switch signals SC12 and SC14 to the plurality of switches SW11 to SW14 according to A-CODE. Then, the switches SW11 and SW13 can be closed, and the switches SW12 and SW14 can be opened. The bias current source 149_1 is connected to the transconductance stage 141, the bias current source 149_2 is connected to the transconductance stage 143, the current of the bias current source 149_1 flows in the transconductance stage 141, and the current of the bias current source 149_2 flows in the transconductance stage 143.

[0129] The phase current I000_P according to the product of the phase input signal C000 and the effective transconductance of the transistor T1 can flow to the transistor T1, and the phase current I180_N according to the product of the phase input signal C180 and the effective transconductance of the transistor T3 can flow to the transistor T3. When the phase input signal C000 is at a high level relative to the phase input signal C180, the phase current I000_P can be greater than the phase current I180_N.

[0130] Conversely, the phase current I180_N can be greater than the phase current I000_P.

[0131] The phase current Q090_P determined by the product of the phase input signal C090 and the effective transconductance of the transistor T5 flows through the transistor T5. Similarly, the phase current Q270_N determined by the product of the phase input signal C270 and the effective transconductance of the transistor T7 flows through the transistor T7. When the phase input signal C090 is at a high level relative to the phase input signal C270, the phase current Q090_P can be greater than the phase current Q270_N. Conversely, the phase current Q270_N can be greater than the phase current Q090_P.

[0132] The phase current I000_P provided by the auxiliary DAC (140_j) can be superimposed on the phase current I000_P provided by the main DAC circuit 130, and the phase current I180_N provided by the auxiliary DAC (140_j) can be superimposed on the phase current I180_N provided by the main DAC circuit 130. The phase current Q090_P provided by the auxiliary DAC (140_j) can be superimposed on the phase current Q090_P provided by the main DAC circuit 130, and the phase current Q270_N provided by the auxiliary DAC (140_j) can be superimposed on the phase current Q270_N provided by the main DAC circuit 130.

[0133] When the two orthogonal phase inputs determined by the M-CODE are 0 degrees and 270 degrees, the auxiliary DAC controller 34 can supply the closing level switch signals SC11 and SC14 and the opening level switch signals SC12 and SC13 to the plurality of switches SW11 to SW14 according to the A-CODE. Optionally, when the two orthogonal phase inputs determined by the M-CODE are 180 degrees and 90 degrees, the auxiliary DAC controller 34 can supply the closing level switch signals SC12 and SC13 and the opening level switch signals SC11 and SC14 to the plurality of switches SW11 to SW14 according to the A-CODE. Optionally, when the two orthogonal phase inputs determined by the M-CODE are 180 degrees and 270 degrees, the auxiliary DAC controller 34 can supply the closing level switch signals SC12 and SC14 and the opening level switch signals SC11 and SC13 to the plurality of switches SW11 to SW14. When two of the plurality of switch signals SC11 to SC14 corresponding to the two orthogonal phases, namely SC11 / SC14, SC12 / SC13, and SC12 / S14, are at the closing level, the corresponding phase current signals can flow to the auxiliary DAC (140_j).

[0134] The dummy stage 145 may include two transistors T9 and T10 and a switch SW15. The gate of the transistor T9 is connected to the gates of the transistors T1 and T2, and the source and drain of the transistor T9 are connected to each other. The gate of the transistor T10 is connected to the gates of the transistors T3 and T4, and the source and drain of the transistor T10 are connected to each other. The switch SW15 is connected between the source / drain of the transistor T9 and the source / drain of the transistor T10. The switch SW15 can perform a switching operation according to the switch signal SC15.

[0135] The dummy stage 146 may include two transistors T11 and T12 and a switch SW16. The gate of the transistor T11 is connected to the gates of the transistors T7 and T8, and the source and drain of the transistor T11 are connected to each other. The gate of the transistor T12 is connected to the gates of the transistors T5 and T6, and the source and drain of the transistor T12 are connected to each other. The switch SW16 is connected between the source / drain of the transistor T11 and the source / drain of the transistor T12. The switch SW16 can perform a switching operation according to the switch signal SC16.

[0136] The auxiliary DAC controller 34 may generate each of a plurality of auxiliary control signals ASW_1 to ASW_8 according to the A-CODE. Each of the plurality of auxiliary control signals ASW_1 to ASW_8 may include a plurality of switch signals SC11 to SC16. The auxiliary DAC controller 34 may determine the phase of each of two orthogonal phase signals (I signal and Q signal) according to the M-CODE, and generate each of the plurality of auxiliary control signals ASW_1 to ASW_8 based on the weights of the phase of the I signal and the phase of the Q signal according to the A-CODE corresponding to the M-CODE. For example, when the M-CODE is "100111", the auxiliary DAC controller 34 may determine that the phase of the I signal is 180 degrees and the phase of the Q signal is 270 degrees according to the MSB<1:0> "10". The auxiliary DAC controller 34 may generate each of seven of the plurality of auxiliary control signals ASW_1 to ASW_8 based on the A-CODE of Table 3, according to the weight 7 of the I signal having a phase of 180 degrees and the weight 7 of the Q signal having a phase of 270 degrees, to include the closed-level switch signals SC12 and SC14 and the open-level switch signals SC11 and SC13. The auxiliary DAC controller 34 may generate the remaining auxiliary control signals among the plurality of auxiliary control signals ASW_1 to ASW_8 to include the open-level switch signals SC11 to SC14.

[0137] In the above description, different from the number of DAC circuits constituting the main DAC circuit 130, it is assumed that the number of auxiliary DAC circuits constituting the auxiliary DAC circuit is 8, but the disclosure is not limited thereto.

[0138] Figure 10 is a circuit diagram showing one of the auxiliary DAC circuits according to an embodiment of the disclosure.

[0139] In Figure 10 the auxiliary DAC shown, the auxiliary DAC circuit 140 may include the same number of auxiliary DACs as the number of main DACs included in the main DAC circuit 130. In Figure 9 the auxiliary DAC shown, each of two bias current sources is provided to each of two transconductance stages, but Figure 10 the auxiliary DAC 140k shown in Figure 9 may include only one bias current source 149. The description of the configuration of the auxiliary DAC 140k shown in Figure 10 having the same configuration as the auxiliary DAC 140j shown in

[0140] The other end of each of the plurality of switches SW11 to SW14 is connected to a bias current source 149. Since the number of auxiliary DACs constituting the auxiliary DAC circuit 140 is 16, only one of the plurality of switches SW11 to SW14 of each auxiliary DAC is closed.

[0141] When the two orthogonal phase inputs determined by the M-CODE are 0 degrees and 90 degrees, the auxiliary DAC controller 34 can provide the closing level switch signal SC11 and the opening level switch signals SC12 to SC14 to the number of auxiliary DACs corresponding to the A-CODE, and provide the closing level switch signal SC13 and the opening level switch signals SC11, SC12, and SC14 to a different number of auxiliary DACs according to the A-CODE. When the two orthogonal phase inputs determined by the M-CODE are 180 degrees and 90 degrees, the auxiliary DAC controller 34 can provide the closing level switch signal SC12 and the opening level switch signals SC11, SC13, and SC14 to the number of auxiliary DACs corresponding to the A-CODE, and provide the closing level switch signal SC13 and the opening level switch signals SC11, SC12, and SC14 to a different number of auxiliary DACs according to the A-CODE. When the two orthogonal phase inputs determined by the M-CODE are 180 degrees and 270 degrees, the auxiliary DAC controller 34 can provide the closing level switch signal SC12 and the opening level switch signals SC11, SC13, and SC14 to the number of auxiliary DACs corresponding to the A-CODE, and provide the closing level switch signal SC14 and the opening level switch signals SC11 to SC13 to a different number of auxiliary DACs according to the A-CODE. When the two orthogonal phase inputs determined by the M-CODE are 0 degrees and 270 degrees, the auxiliary DAC controller 34 can provide the closing level switch signal SC11 and the opening level switch signals SC12 to SC14 to the number of auxiliary DACs corresponding to the A-CODE, and provide the closing level switch signal SC14 and the opening level switch signals SC11 to SC13 to a different number of auxiliary DACs according to the A-CODE.

[0142] The auxiliary DAC controller 34 may generate each of the 16 auxiliary control signals according to the A-CODE. Each of the 16 auxiliary control signals may include a plurality of switch signals SC11 to SC16. The auxiliary DAC controller 34 may determine the phase of the I signal and the phase of the Q signal according to the M-CODE, and generate each of the 16 auxiliary control signals based on the weight of each of the phase of the I signal and the phase of the Q signal according to the A-CODE corresponding to the M-CODE. For example, when the M-CODE is "100111", the auxiliary DAC controller 34 may determine that the phase of the I signal is 180 degrees and the phase of the Q signal is 270 degrees according to the MSB<1:0> "10". The auxiliary DAC controller 34 may generate each of the seven auxiliary control signals among the 16 auxiliary control signals based on the weight 7 of the I signal having a phase of 180 degrees according to the A-CODE in Table 3, so as to include the closed-level switch signal SC12 and the open-level switch signals SC11, SC13, and SC14. The auxiliary DAC controller 34 may generate each of the other seven auxiliary control signals among the 16 auxiliary control signals based on the weight 7 of the I signal having a phase of 270 degrees according to the A-CODE in Table 3, so as to include the closed-level switch signal SC14 and the open-level switch signals SC11 to SC13. The auxiliary DAC controller 34 may generate the remaining 2 auxiliary control signals among the 16 auxiliary control signals, so as to include the open-level switch signals SC11 to SC14.

[0143] Figure 11A and Figure 11B is a graph showing the improved integral nonlinearity in the case of adding an auxiliary DAC circuit.

[0144] Figure 11A shows the integral nonlinearity (INL) of the phase output signal of each code when the frequency of the phase signal is 3.6 GHz, and Figure 11B shows the integral nonlinearity (INL) of the phase output signal of each code when the frequency of the phase signal is 1.4 GHz. In each graph, the horizontal axis represents the code indicating phase interpolation, and the vertical axis represents "LSB (Least Significant Bit)". "LSB" is used as a unit for representing the integral nonlinearity by normalizing the integral nonlinearity for each code. According to an embodiment including the auxiliary DAC circuit 140, the integral nonlinearity of the phase output signal of each code is indicated by black dots, and the integral nonlinearity when the auxiliary DAC circuit 140 does not exist is indicated by small circles.

[0145] As Figure 11AAs shown, the integral non-linearity 102 improved by the auxiliary DAC circuit 140 is 1.06 LSB, and the integral non-linearity 102 is less than the integral non-linearity 101 of 2.06 LSB without the auxiliary DAC circuit 140.

[0146] In addition, as Figure 11B shown, the integral non-linearity 104 improved by the auxiliary DAC circuit 140 is 1.26 LSB, and the integral non-linearity 104 is less than the integral non-linearity 103 of 2.44 LSB without the auxiliary DAC circuit 140.

[0147] Figure 12A and Figure 12B are graphs showing the improved differential linearity in the case of adding the auxiliary DAC circuit.

[0148] Figure 12A shows the differential non-linearity (DNL) of the phase output signal for each code when the frequency of the phase signal is 3.6 GHz, and Figure 12B shows the differential non-linearity (DNL) of the phase output signal for each code when the frequency of the phase signal is 1.4 GHz. In each graph, the horizontal axis represents the code indicating phase interpolation, and the vertical axis represents "LSB". "LSB" is used as the unit to represent the differential non-linearity by normalizing the differential non-linearity for each code. According to the embodiment including the auxiliary DAC circuit 140, the differential non-linearity of the phase output signal for each code is indicated by black dots, and the differential non-linearity when the auxiliary DAC circuit 140 is absent is indicated by small circles.

[0149] As Figure 12A shown, the differential non-linearity 112 improved by the auxiliary DAC circuit 140 is 0.66 LSB, and the differential non-linearity 112 is less than the differential non-linearity 111 of 0.92 LSB in the absence of the auxiliary DAC circuit 140.

[0150] In addition, as Figure 12B shown, the differential non-linearity 114 improved by the auxiliary DAC circuit 140 is 0.54 LSB, and the differential non-linearity 114 is less than the differential non-linearity 113 of 1.01 LSB without the auxiliary DAC circuit 140.

[0151] Figure 13A and Figure 13B are graphs showing the improved amplitude and AM to PM distortion of the phase output signal in the case of adding the auxiliary DAC circuit.

[0152] Figure 13AShows the amplitude change of the phase output signal for each code. The amplitude when the auxiliary DAC circuit 140 is present is indicated by black dots, and the amplitude change is 8.1%. The amplitude without the auxiliary DAC circuit 140 is indicated by small circles, and the amplitude change is 29.3%. In other words, it can be seen that: through the auxiliary DAC circuit 140, the amplitude change is reduced to 1 / 3 or less.

[0153] Figure 13B Is a graph showing the degree of AM to PM distortion of the phase output signal according to each code. The AM to PM distortion when the auxiliary DAC circuit 140 is present is indicated by black dots, and the AM to PM distortion is 0.76 ps. The AM to PM distortion without the auxiliary DAC circuit 140 is indicated by small circles, and the AM to PM distortion is 6.42 ps. In other words, it can be seen that: through the auxiliary DAC circuit 140, the AM to PM distortion is reduced to 81.2% or less. The unit "ps" represents picoseconds. When the frequency of the phase signal is 3.6 GHz, one period is 277.7 ps, and when interpolated at 1 / 64 intervals according to 64 codes, 1 step is 4.34 ps. When the 0.76 ps AM to PM distortion in the case of the auxiliary DAC circuit 140 is quantized in 1 step, the AM to PM distortion is 0.18 LSB (=0.76 ps / 4.34 ps), and when quantizing the 6.42 ps AM to PM distortion without the auxiliary DAC circuit 140, the AM to PM distortion is 1.48 LSB (=6.42 ps / 4.34 ps).

[0154] In this way, some embodiments can minimize the phase and amplitude changes between the output current generated by the existing phase interpolator and the target current. According to some embodiments, the reduction of the amplitude change by the current-mode phase interpolator can reduce the AM to PM distortion change occurring in the output buffer of the RCD by approximately 81.2%. Improve the linear characteristics of the enhanced RCD.

[0155] The current-mode phase interpolator according to an embodiment can support a wide frequency band, and improve the integral nonlinearity (INL) (an indicator of linear characteristics) from 2.06 LSB by 1.95 times to 1.06 LSB based on actual measurement. By using only four phase inputs of I, / I, Q, and / Q, such enhancement allows the current-mode phase interpolator to be superior to the conventional model using eight phase inputs. In addition, the current-mode phase interpolator according to some embodiments also only includes an auxiliary DAC circuit and does not include additional circuits. Therefore, the area and power consumption of the current-mode phase interpolator can be minimized.

[0156] Although the disclosure has been described in connection with specific embodiments, it will be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, the disclosure is intended to cover various modifications and equivalent arrangements falling within the spirit and scope of the appended claims.

Claims

1. A phase interpolator, the phase interpolator providing a pair of differential outputs according to a plurality of inputs having a plurality of phases, the phase interpolator comprising: A main digital-to-analog converter circuit is configured to: perform phase interpolation on a first input and a second input having an orthogonal phase among the plurality of inputs according to a main code to generate a main output signal; an auxiliary digital-to-analog converter circuit configured to: perform phase interpolation on the first input and the second input according to an auxiliary code corresponding to the primary code to generate an auxiliary output signal; as well as The output buffer is configured to generate the pair of differential outputs according to a differential input based on a phase output signal, the phase output signal being a sum of the main output signal and the auxiliary output signal.

2. The phase interpolator of claim 1, wherein: The main DAC circuit includes: A plurality of first digital-to-analog converters are configured to generate a plurality of phase currents based on one of a first input and a second input according to a plurality of main control signals based on a main code, and The master code includes information about the number of digital-to-analog converters based on the first input and the number of digital-to-analog converters based on the second input among the plurality of first digital-to-analog converters.

3. The phase interpolator of claim 2, wherein: Each of the plurality of first digital-to-analog converters comprises: Bias current source; a first transconductance stage configured to: control the transconductance based on a first input; a second transconductance stage configured to: control the transconductance based on a second input; a first switch connected between the first transconductance stage and the bias current source and configured to switch based on a first main control signal among the plurality of main control signals; and a second switch connected between the second transconductance stage and the bias current source and configured to switch based on a second main control signal among the plurality of main control signals, and The phase current of each of the plurality of first digital-to-analog converters includes a phase current flowing through a first transconductance stage and a phase current flowing through a second transconductance stage.

4. The phase interpolator of claim 3, wherein: The first transconductance stage includes: A first transistor including: a gate to which a first input is provided, a first terminal connected to a first terminal of a first switch, and a second terminal connected to a first node; and a second transistor including: a gate to which a first inverting input having an inverted phase relative to the first input is provided, a first end connected to the first end of the first switch, and a second end connected to a second node, and Wherein, the second transconductance stage comprises: a third transistor including: a gate to which the second input is provided, a first end connected to the first end of the second switch, and a second end connected to the first node; and The fourth transistor includes a gate to which a second inverting input having an inverted phase with respect to the second input is provided, a first end connected to the first end of the second switch, and a second end connected to the second node.

5. The phase interpolator of claim 4, wherein: Each of the plurality of first digital-to-analog converters comprises: a fifth transistor including a gate connected to the gate of the first transistor and a source and a drain connected to each other; a sixth transistor including a gate connected to the gate of the second transistor and a source and a drain connected to each other; a third switch connected between the source and drain of the fifth transistor and the source and drain of the sixth transistor; a seventh transistor including a gate connected to the gate of the third transistor and a source and a drain connected to each other; an eighth transistor including a gate connected to the gate of the fourth transistor and a source and a drain connected to each other; and a fourth switch connected between the source and drain of the seventh transistor and the source and drain of the eighth transistor, When the first switch is opened, the third switch is closed, and when the second switch is opened, the fourth switch is closed.

6. The phase interpolator of claim 3, further comprising: a master DAC controller configured to generate each of a plurality of first master control signals and a plurality of second master control signals for each of the plurality of first DACs based on a master code, Wherein, in each of the plurality of first digital-to-analog converters, When the first switch is closed based on each of the plurality of first main control signals, the second switch is opened based on each of the plurality of second main control signals, and When the first switch is opened based on each of the plurality of first main control signals, the second switch is closed based on each of the plurality of second main control signals.

7. The phase interpolator of claim 1, wherein: The auxiliary digital-to-analog converter circuit includes: a plurality of second digital-to-analog converters configured to generate a plurality of phase currents based on the first input and the second input according to a plurality of auxiliary control signals based on the auxiliary code, and The auxiliary code includes information on the number of digital-to-analog converters based on the first input and the second input among the plurality of second digital-to-analog converters.

8. The phase interpolator of claim 7, wherein: Each of the plurality of second digital-to-analog converters comprises: a first bias current source and a second bias current source; a first transconductance stage configured to: control the transconductance based on a first input; a second transconductance stage configured to: control the transconductance based on a second input; a first switch connected between the first transconductance stage and the first bias current source and configured to switch based on a first auxiliary control signal among the plurality of auxiliary control signals; and a second switch connected between the second transconductance stage and the second bias current source and configured to switch based on the first auxiliary control signal, and The phase current of each of the plurality of second digital-to-analog converters includes a phase current flowing through the first transconductance stage and a phase current flowing through the second transconductance stage.

9. The phase interpolator of claim 8, wherein: The first transconductance stage includes: A first transistor including: a gate to which a first input is provided, a first terminal connected to a first terminal of a first switch, and a second terminal connected to a first node; and a second transistor including: a gate to which a first inverting input having an inverted phase relative to the first input is provided, a first end connected to the first end of the first switch, and a second end connected to a second node, and The second transconductance stage includes: a third transistor including: a gate to which the second input is provided, a first end connected to the first end of the second switch, and a second end connected to the first node; and The fourth transistor includes a gate to which a second inverting input having an inverted phase with respect to the second input is provided, a first end connected to the first end of the second switch, and a second end connected to the second node.

10. The phase interpolator of claim 8, further comprising: an auxiliary digital-to-analog converter controller configured to generate each of a plurality of auxiliary control signals for each of the plurality of second digital-to-analog converters based on an auxiliary code, and Wherein, in each of the plurality of second digital-to-analog converters, a switching operation of each of the first switch and the second switch is controlled based on each of the plurality of auxiliary control signals.

11. The phase interpolator according to any one of claims 1 to 10, wherein: The auxiliary digital-to-analog converter circuit includes: a plurality of second digital-to-analog converters configured to generate a plurality of phase currents based on one of the first input and the second input according to a plurality of auxiliary control signals based on the auxiliary code, and The auxiliary code includes information about the number of digital-to-analog converters according to the first input and the number of digital-to-analog converters according to the second input among the plurality of second digital-to-analog converters.

12. The phase interpolator according to any one of claims 1 to 10, wherein: When the phase of the main output signal based on the main code is an intermediate phase between a first phase corresponding to the first input and a second phase corresponding to the second input, the auxiliary DAC circuit generates an auxiliary output signal having a maximum amplitude based on the auxiliary code.

13. A phase interpolator, comprising: a main digital-to-analog converter circuit configured to: provide a first phase current based on a first input having a first weight and a second phase current based on a second input having a second weight orthogonal to the first input to a first node; an auxiliary digital-to-analog converter circuit configured to: provide a third phase current based on the first input having a third weight and a fourth phase current based on the second input having a third weight to the first node; an output buffer configured to: generate an output signal based on a voltage of the first node; as well as The auxiliary digital-to-analog converter controller is configured to determine a third weight based on an auxiliary code corresponding to a primary code indicating the first weight and the second weight.

14. The phase interpolator of claim 13, wherein: The auxiliary DAC controller determines the third weight to have a maximum value based on the auxiliary code when the phase interpolation based on the main code is a midpoint between the first phase and the second phase in a phase region between a first phase corresponding to the first input and a second phase corresponding to the second input.

15. The phase interpolator of claim 14, wherein: The auxiliary digital-to-analog converter circuit includes a plurality of second digital-to-analog converters, and A second digital-to-analog converter having a third weight among the plurality of second digital-to-analog converters provides a third phase current and a fourth phase current.

16. The phase interpolator of claim 13, further comprising: A main DAC controller determines a first phase corresponding to a first input and a second phase corresponding to a second input based on a main code, and determines a first weight and a second weight based on the main code.

17. The phase interpolator of claim 16, wherein: The main DAC circuit comprises a plurality of first DACs, Each of the first digital-to-analog converters with a first weight among the plurality of first digital-to-analog converters provides a first phase current, and each of the first digital-to-analog converters with a second weight among the plurality of first digital-to-analog converters provides a second phase current.

18. A memory device comprising: multiple memory modules; as well as a phase interpolator configured to: buffer command, address, and clock signals provided from an external source, and send the buffered command, address, and clock signals to the plurality of memory modules, The phase interpolator includes: a main digital-to-analog converter circuit configured to: phase interpolate first and second inputs having quadrature phases representing each of the command, the address, and the clock signal based on a main code to generate a main output signal; an auxiliary digital-to-analog converter circuit configured to: phase interpolate the first input and the second input based on an auxiliary code corresponding to the primary code to generate an auxiliary output signal; and An output buffer generates a pair of differential outputs based on a differential input based on a phase output signal, the phase output signal being a sum of a main output signal and an auxiliary output signal.

19. The memory device of claim 18, wherein: The auxiliary digital-to-analog converter circuit includes: a plurality of second digital-to-analog converters configured to generate a plurality of phase currents based on the first input and the second input according to a plurality of auxiliary control signals based on the auxiliary code, and The auxiliary code includes information on the number of digital-to-analog converters based on the first input and the second input among the plurality of second digital-to-analog converters.

20. The memory device of claim 18, wherein: The auxiliary digital-to-analog converter circuit includes: a plurality of second digital-to-analog converters configured to generate a plurality of phase currents based on the first input or the second input according to a plurality of auxiliary control signals based on the auxiliary code, and The auxiliary code includes information about the number of digital-to-analog converters corresponding to the first input and the number of digital-to-analog converters corresponding to the second input among the plurality of second digital-to-analog converters.

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