Signal multiplexing equipment and optical transmitter

Abstract

The invention discloses signal multiplexing equipment and an optical transmitter, which are used for solving the problem of high signal compensation difficulty in the prior art. The signal multiplexing device comprises a first multiplexer, a second multiplexer, a third multiplexer and an adder. The first multiplexer combines the received multiple paths of signals into one path of first signal and outputs the first signal to the third multiplexer; the second multiplexer combines the received multiple paths of signals into one path of second signal and outputs the second signal to the third multiplexer; the third multiplexer receives the first clock signal, outputs the first signal to the first input end of the adder and outputs the second signal to the second input end of the adder when the first clock signal is at a high level, and outputs the second signal to the first input end of the adder when the first clock signal is at a low level. The first signal is output to the second input end of the adder; and the adder performs addition processing on the two paths of signals received by the input end and outputs the two paths of signals.

Description

Technical Field

[0001] This application relates to the field of optical communication technologies, and particularly to a signal multiplexing device and an optical transmitter. Background Art

[0002] As the capacity of fiber optic transmission systems gradually increases, the requirements for the transmission rate of optical signals are also getting higher and higher. High baud rate signal transmission requires that the digital to analog converter (DAC) has a high sampling rate, a high output bandwidth, and a high vertical resolution. Complementary metal oxide semiconductor (CMOS) is the basic unit that makes up the DAC. Due to the limitations of the CMOS process, it is difficult for a single DAC's analog bandwidth to meet the requirements of high-speed transmission. Therefore, it is proposed to use an analog multiplexer (AMUX) to combine the signals output by multiple DACs into one signal to increase the signal transmission rate. Using the above method, as the signal transmission rate increases, the signal attenuation at the output of the AMUX also increases. Therefore, it is necessary to introduce a feed forward equalizer (FFE) on the output side of the AMUX for signal compensation. Currently, the industry generally uses two return-to-zero code (RZ) generators driven by complementary clocks and an adder for signal compensation and combination, which increases the difficulty of signal compensation. Summary of the Invention

[0003] This application provides a signal multiplexing device and an optical transmitter, which are used to solve the problem of high signal compensation difficulty of multiplexers in the prior art.

[0004] In a first aspect, an embodiment of this application provides a signal multiplexing device. The signal multiplexing device can be applied to a coherent optical transmission system and can perform multiplexing processing on the signals output by multiple DACs in an optical transmitter. The signal multiplexing device can include a first multiplexer, a second multiplexer, a third multiplexer, and an adder.

[0005] Wherein, the first multiplexer is coupled to the third multiplexer. The first multiplexer is configured to combine multiple received signals into one first signal and output it to the third multiplexer; the second multiplexer is coupled to the third multiplexer. The second multiplexer is configured to combine multiple received signals into one second signal and output it to the third multiplexer; the third multiplexer is respectively coupled to the first input terminal and the second input terminal of the adder. The third multiplexer is configured to receive a first clock signal. When the first clock signal is at a high level, the third multiplexer outputs the first signal to the first input terminal of the adder and outputs the second signal to the second input terminal of the adder. When the first clock signal is at a low level, the third multiplexer outputs the second signal to the first input terminal of the adder and outputs the first signal to the second input terminal of the adder. The rate of the signal output by the third multiplexer to the adder is twice the rate of the received signal; the adder is configured to perform addition processing on the two signals received at the input terminals and output the result.

[0006] With the above structure, the third multiplexer can output two signals with the same frequency and a phase difference of one unit time interval to the adder according to the level state of the clock signal. The above two signals can form two taps of the FFE. Therefore, the signal compensation can be completed only by performing addition processing on the signals of the two taps by the adder, and the difficulty of signal compensation can be reduced.

[0007] In a possible design, the third multiplexer includes a first load circuit, a second load circuit, a first Gilbert cell, and a second Gilbert cell.

[0008] Specifically, the first output terminal of the first Gilbert cell is coupled to the first load circuit, the second output terminal is coupled to the second load circuit, the signal input terminal is coupled to the first multiplexer, the clock input terminal is configured to receive the first clock signal. The first Gilbert cell is configured to output the signal output by the first multiplexer to the first load circuit when the first clock signal is at a high level, and output the signal output by the first multiplexer to the second load circuit when the first clock signal is at a low level; the first output terminal of the second Gilbert cell is coupled to the second load circuit, the second output terminal is coupled to the first load circuit, the signal input terminal is coupled to the second multiplexer, the clock input terminal is configured to receive the first clock signal. The second Gilbert cell is configured to output the signal output by the second multiplexer to the second load circuit when the first clock signal is at a high level, and output the signal output by the second multiplexer to the first load circuit when the first clock signal is at a low level.

[0009] With the above structure, two Gilbert cells form a 1-of-2 data selector, which can control one received signal to be output through the first load circuit or the second load circuit according to the level state of the first clock signal. Similarly, the second Gilbert cell forms a 1-of-2 data selector, which can control the other received signal to be output through the first load circuit or the second load circuit according to the level state of the first clock signal. Since the two data selectors receive the same clock signal and the load circuits for output at the same level state are different, the first load circuit and the second load circuit can output two signals with the same data and a signal delay of half of the first clock.

[0010] In a possible design, the first load circuit includes a first resistor, a second resistor, a first inductor, and a second inductor. The second end of the first resistor is coupled to the power supply through the first inductor, the second end of the second resistor is coupled to the power supply through the second inductor, and the first ends of the first resistor and the second resistor are coupled to the first output end of the first Gilbert cell, the second output end of the second Gilbert cell, and the first input end of the adder. The second load circuit includes a third resistor, a fourth resistor, a third inductor, and a fourth inductor. The second end of the third resistor is coupled to the power supply through the third inductor, the second end of the fourth resistor is coupled to the power supply through the fourth inductor, and the first ends of the third resistor and the fourth resistor are coupled to the second output end of the first Gilbert cell, the first output end of the second Gilbert cell, and the second input end of the adder. With the above design, the bandwidth of the third multiplexer can be increased by connecting inductors in series in the two load circuits.

[0011] In a possible design, the signal multiplexing device further includes a plurality of first linear equalizers coupled to the first multiplexer and a plurality of second linear equalizers coupled to the second multiplexer. Each first linear equalizer receives one signal, performs signal compensation on the received signal, and then outputs it to the first multiplexer; each second linear equalizer receives one signal, performs signal compensation on the received signal, and then outputs it to the second multiplexer. The signals received by each first linear equalizer and each second linear equalizer are different. With the above design, the signal received by the first multiplexer can be compensated by the first linear equalizer, and the signal received by the second multiplexer can be compensated by the second linear equalizer. Since the signal rates received by the first multiplexer and the second multiplexer are relatively low, it is beneficial to reduce the difficulty of signal compensation and the manufacturing requirements for the front-end devices.

[0012] In a possible design, the signal multiplexing device further includes: a frequency divider, a first delay unit, and a second delay unit.

[0013] Specifically, the frequency divider is coupled to the first multiplexer and the second multiplexer, and is configured to receive a second clock signal, split the second clock signal into a first sub-clock signal and a second sub-clock signal, and output them to the first multiplexer and the first delay unit respectively. The first sub-clock signal and the second sub-clock signal have the same frequency, and the phase difference between the first sub-clock signal and the second sub-clock signal is a preset threshold. The ratio between the frequency of the first sub-clock signal and the second clock signal is the ratio between the bandwidth of the first multiplexer and the bandwidth of the third multiplexer. The first delay unit is configured to perform a delay process on the second sub-clock signal so that the phase difference between the first sub-clock signal and the second sub-clock signal is the preset threshold. The second delay unit is configured to perform a delay process on the second clock signal to obtain the first clock signal, and output the first clock signal to the third multiplexer.

[0014] When the multiplexer combines the received signals using the above device, its transmission rate is related to the frequency of the clock signal, and a separate clock signal needs to be configured for it. The first sub-clock signal and the second sub-clock signal form an IQ clock to perform interleaved sampling on the signals received by the first multiplexer and the second multiplexer, so as to meet the interleaved sampling requirements of the two signals by the third multiplexer at the backend. In addition, the clock signal received by the multiplexer can be aligned with the received signal through the first delay unit and the second delay unit.

[0015] In a possible design, the signal multiplexing device further includes a third delay unit coupled between the first multiplexer and the third multiplexer. The third delay unit is configured to perform a delay process on the signal output by the first multiplexer so that the phase difference between the signal output by the first multiplexer and the signal output by the second multiplexer is the preset threshold. In the above design, when the third multiplexer combines the two signals output by the first multiplexer and the second multiplexer, it can output the signal output by one multiplexer in the high level state of the first clock signal, and output the signal output by the other multiplexer in the low level state of the first clock. In order to complete the interleaved output of the two signals, a delay unit needs to be used to adjust the phase difference between the signals of the first multiplexer and the second multiplexer to the preset threshold to complete the alignment of the data and the clock signal.

[0016] In a possible design, the adder is an adjustable gain analog adder, which is configured to perform gain adjustment on the two received signals respectively, perform an addition process on the circuit signals after gain adjustment, and output the result. With the above design, the tap coefficients of the compensator can be adjusted by adjusting the gains of the two signals received by the adder.

[0017] In a possible design, the adder includes a first switching transistor, a second switching transistor, a first differential pair coupled to the first switching transistor, a second differential pair coupled to the second switching transistor, a third differential pair coupled to a first output terminal of the first differential pair, a fourth differential pair coupled to a second output terminal of the first differential pair, a fifth differential pair coupled to a first output terminal of the second differential pair, a sixth differential pair coupled to a second output terminal of the second differential pair, a fifth resistor, and a sixth resistor.

[0018] Wherein, a control terminal of the switching transistor in the first differential pair is a first input terminal of the adder; a control terminal of the switching transistor in the second differential pair is a second input terminal of the adder; a first output terminal of the third differential pair is coupled to a first output terminal of the fourth differential pair and a second terminal of the fifth resistor, and a second output terminal of the third differential pair is coupled to a second output terminal of the fourth differential pair and a second terminal of the sixth resistor; a first output terminal of the fifth differential pair is coupled to a first output terminal of the sixth differential pair and a second terminal of the fifth resistor, and a second output terminal of the fifth differential pair is coupled to a second output terminal of the sixth differential pair and a second terminal of the sixth resistor; control terminals of the switching transistors in the third differential pair and the fourth differential pair receive a first adjustment signal, and adjust the conduction degree of the switching transistors in the third differential pair and the fourth differential pair through the first adjustment signal; control terminals of the switching transistors in the fifth differential pair and the sixth differential pair receive a second adjustment signal, and adjust the conduction degree of the switching transistors in the fifth differential pair and the sixth differential pair through the second adjustment signal.

[0019] In the above manner, the conduction degree of the switching transistors in the third differential pair and the fourth differential pair is adjusted through the first adjustment signal to adjust the gain of the signal received at the first input terminal, and the conduction degree of the switching transistors in the fifth differential pair and the sixth differential pair can be adjusted through the second adjustment circuit to adjust the gain of the signal received at the second input terminal. The adjustment of the gains of the above two signals is equivalent to configuring the coefficients of two taps of the FFE. Therefore, an appropriate compensation effect can be achieved by configuring appropriate adjustment signals. In addition, in the above manner, since there is no need to adjust the first switching transistor and the second switching transistor, the first switching transistor and the second switching transistor can be in a state of a constant current source.

[0020] In a possible design, a ratio between a rate of an output signal of the first multiplexer and a rate of a received signal is a number of signals received by the first multiplexer, and a ratio between a rate of an output signal of the second multiplexer and a rate of a received signal is a number of signals received by the second multiplexer.

[0021] Second aspect, an optical transmitter according to an embodiment of the present application. The optical transmitter includes a digital signal processor, a plurality of digital-to-analog converters (DACs), at least one signal multiplexing device provided in the first aspect and any possible design thereof in the present application, a driver corresponding to each signal multiplexing device one by one, at least one modulator, and a beam combiner.

[0022] Wherein, each DAC is used to convert a path of digital signal output by the digital signal processor into an analog signal and output it; each signal multiplexing device is coupled to a plurality of DACs, and is used to multiplex the analog signals output by the coupled plurality of DACs into one path of signal and output it; each driver is used to receive the signal output by the corresponding signal multiplexing device, perform power amplification, and then output it; each modulator is used to receive the signals output by two drivers, adjust the received signals into optical signals, and output them to the beam combiner for output.

[0023] The technical effects that can be achieved by the second aspect described above can refer to the description of the beneficial effects in the first aspect above, and will not be repeated here. Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of a coherent optical transmission system provided by an embodiment of the present application;

[0025] Figure 2 It is a schematic structural diagram of a signal multiplexing device provided by an embodiment of the present application Figure 1 ;

[0026] Figure 3 It is a schematic structural diagram of a signal multiplexing device provided by an embodiment of the present application Figure 2 ;

[0027] Figure 4 It is a schematic structural diagram of a signal multiplexing device provided by an embodiment of the present application Figure 3 ;

[0028] Figure 5 It is a schematic structural diagram of a signal multiplexing device provided by an embodiment of the present application Figure 4 ;

[0029] Figure 6 It is a schematic structural diagram of a first multiplexer provided by an embodiment of the present application;

[0030] Figure 7 It is a schematic structural diagram of a third multiplexer provided by an embodiment of the present application;

[0031] Figure 8 It is a schematic structural diagram of a two-tap FFE provided by an embodiment of the present application;

[0032] Figure 9Schematic diagram of an adder structure provided by an embodiment of the present application Figure 1 ;

[0033] Figure 10 Schematic diagram of an adder structure provided by an embodiment of the present application Figure 2 ;

[0034] Figure 11 Schematic diagram of a signal multiplexing device structure provided by an embodiment of the present application Figure 5 ;

[0035] Figure 12 Schematic diagram of a signal multiplexing device structure provided by an embodiment of the present application Figure 6 ;

[0036] Figure 13 Schematic diagram of a signal multiplexing device structure provided by an embodiment of the present application Figure 7 ;

[0037] Figure 14 Signal waveform diagram of a signal multiplexing device provided by an embodiment of the present application;

[0038] Figure 15 Schematic diagram of an optical transmitter structure provided by an embodiment of the present application. Detailed implementation manners

[0039] In order to make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. The terms used in the detailed implementation part of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0040] Before introducing the specific solutions provided by the embodiments of the present application, some terms in the present application are generally explained for the convenience of understanding by those skilled in the art, and the terms in the present application are not limited.

[0041] 1) Coherent light refers to an optical signal with a definite frequency and phase. Generally speaking, it can be laser light generated by a laser and having the characteristics of spatial superposition and mutual interference.

[0042] 2) A coherent optical transmission system, also known as a coherent optical communication system, is a fiber optic communication system. It uses a coherent light source with a single frequency and utilizes parameters in multiple dimensions such as the phase, frequency, and amplitude of light to carry more modulation information, so as to make full use of the fiber bandwidth and achieve ultra-high-capacity transmission. The basic structure of a coherent optical transmission system includes: an optical transmitter, an optical fiber, an optical receiver, etc. Among them, the optical transmitter is used to modulate the signal to be transmitted externally onto the optical carrier to meet the requirements of optical transmission. It can adopt direct modulation or external modulation methods to modulate the amplitude, frequency, and phase of the optical carrier. The optical receiver is used for coherent detection of the signal light and improves the receiving sensitivity by detecting the difference between the local oscillator light and the signal light. Here, the signal light refers to the optical signal transmitted in the coherent optical transmission system, and the local oscillator light refers to the laser generated by the local oscillator on the side of the optical receiver.

[0043] In the embodiments of the present application, "a plurality of" means two or more. In view of this, "a plurality of" in the embodiments of the present application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two, or more. For example, including at least one means including one, two, or more, and it does not limit which ones are included. For example, including at least one of A, B, and C, then what can be included are A, B, C, A and B, A and C, B and C, or A and B and C. "And / or" describes the association relationship of associated objects and indicates that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / ", unless otherwise specified, generally represents an "or" relationship between the front and rear associated objects.

[0044] Unless there is a contrary statement, the ordinal numbers such as "first" and "second" mentioned in the embodiments of the present application are used to distinguish multiple objects and are not used to limit the order, timing, priority, or importance of multiple objects.

[0045] The embodiments of the present application can be applied to a coherent optical transmission system or other devices that require multiplexing and compensation of multiple signals. See Figure 1As shown in the figure, it is a schematic structural diagram of a coherent optical transmission system. The coherent optical transmission system may include an optical transmitter, an optical receiver, and an optical fiber channel coupled between the optical transmitter and the optical receiver. The optical transmitter at least includes a digital signal processor (DSP), multiple DACs, multiple drivers DRV, and multiple IQ modulators. Among them, the DSP can convert the data to be transmitted into multiple digital signals, and the multiple digital signals are respectively the digital values of the in-phase (I) component and the quadrature (Q) component transmitted using polarized light. Each digital signal is converted into an analog signal by a DAC and then power-amplified by the driver DRV and output to the IQ modulator. Each IQ modulator can use the local oscillator light LD to adjust the received two signals into optical signals. The polarization beam combiner can combine the optical signals output by multiple IQ adjustment values and transmit them to the optical receiver through the optical fiber channel.

[0046] In practical applications, since the basic components of the DAC are CMOS, limited by the manufacturing process of CMOS, the analog bandwidth of a single DAC is limited. Therefore, a scheme of using an analog multiplexer AMUX for signal compensation on the output side is proposed. Currently, the compensation method of the existing technical scheme is to respectively set a complementary clock-driven RZ generator on the signal transmission paths of the two signals to be combined, and both RZ generators are coupled to an adder. The above-mentioned RZ generator and adder can form a FFE, and equalization is achieved by configuring different gain values for each RZ generator, thereby constituting two taps of the FFE. The gain value is the coefficient of the two taps. Therefore, the compensation effect of the FFE can be adjusted by adjusting the gain value of the RZ generator. In addition, since the clock signals received by the two RZ generators are complementary, the two RZ generators output alternately, thereby combining the two signals into one signal for output. In practical applications, the above signal compensation method is too complex, increasing the difficulty of signal compensation.

[0047] Based on this, the embodiments of the present application propose a new signal multiplexer scheme, which is used to reduce the signal compensation difficulty while realizing the combination of multiple signals to improve the signal transmission rate.

[0048] Please refer to Figure 2 , which is a schematic structural diagram of a signal multiplexing device provided by the embodiments of the present application. The signal multiplexing device can be applied to devices that need to combine multiple signals, can perform signal compensation on the combined single signal, and does not require adding complex devices, thereby reducing the signal compensation difficulty.

[0049] The signal multiplexing device provided by the embodiments of the present application can support the combination of at least four signals. Please refer to Figure 2As shown, the signal multiplexing device may include: a first multiplexer, a second multiplexer, a third multiplexer, and an adder. Among them, the signal multiplexing device may further include a plurality of input ports and one output port. Taking the application of the signal multiplexer in an optical transmitter as an example, the signal multiplexing device is coupled between multiple DACs and the driver DVR within the optical transmitter. Each input port of the signal multiplexer can receive the signal output by one DAC, and after combining the signals of multiple DACs into one signal, it is output to one driver DVR through the output port.

[0050] Specifically, both the first multiplexer and the second multiplexer are coupled to the third multiplexer. The first multiplexer can combine the received multiple signals into one first signal, and the second multiplexer can combine the received multiple signals into one second signal. Among them, the number of signals received by the first multiplexer and the second multiplexer is the same to ensure that the third multiplexer can accurately combine the signals output by the first multiplexer and the second multiplexer. The first multiplexer and the second multiplexer can not only combine the received multiple signals into one signal, but also increase the rate of the output signal. Among them, the ratio between the rate of the output signal of the above two multiplexers and the rate of the received signal is the number of signals received by the multiplexer. The third multiplexer is respectively coupled to the first input terminal and the second input terminal of the adder, and is used to output the first signal output by the first multiplexer to the first input terminal of the adder and the second signal output by the second multiplexer to the second input terminal of the adder when the clock signal is at a high level, and output the second signal output by the second multiplexer to the first input terminal of the adder and the first signal output by the first multiplexer to the second input terminal of the adder when the clock signal is at a low level. It can be seen from this that the third multiplexer is a 2:1 multiplexer with two inputs, two outputs, and the signals output by the two output ports differ by a unit time interval (UI). The adder can be a fixed-gain adder, determine the signal compensation value according to the application scenario of the signal multiplexing device, and select a suitable type of adder according to the signal compensation value. The adder can also be an adjustable-gain adder, which respectively adjusts the gains of the two signals received at the input terminal according to the signal compensation requirements of the signal multiplexing device, performs an addition process on the signals after gain adjustment, and outputs them.

[0051] In a possible implementation manner, the first multiplexer and the second multiplexer can receive more than two signals, combine the received multiple signals into one signal and output it, so as to realize combining the received multiple signals into one signal. Among them, the specifications of the first multiplexer and the second multiplexer can be selected according to the application scenario of the signal multiplexing device. For example, see Figure 3As shown, if the signal multiplexing device has 8 input ports and each input port receives a split signal to be combined, then the first multiplexer and the second multiplexer are 4:1 multiplexers. The first multiplexer receives split signals 1 to 4 to be combined, and the second multiplexer receives split signals 5 to 8 to be combined.

[0052] In another possible implementation, both the first multiplexer and the second multiplexer receive two signals, combine the two received signals into one signal and output it, that is, both the first multiplexer and the second multiplexer are 2:1 multiplexers. In practice, when the input ports of the signal multiplexing device are 4, the structure of the signal multiplexing device can be referred to Figure 4 As shown, the first multiplexer receives split signals 1 and 2 to be combined, and the second multiplexer receives split signals 3 and 4 to be combined. When the number of input ports of the signal multiplexing device is greater than 4, that is, the number of signals received by the signal multiplexing device is greater than 4, then the signal multiplexing device may further include multiple other multiplexers. For example, refer to Figure 5 As shown, if the signal multiplexing device has 8 input ports, then in addition to the above three multiplexers, the signal multiplexing device may further include 4 fourth multiplexers. Each fourth multiplexer receives two signals and outputs the two received signals as one signal. The first multiplexer and the second multiplexer respectively combine the signals output by the two fourth multiplexers.

[0053] In practical applications, the first multiplexer and the second multiplexer can use multiplexer chips with the same structure or the same specifications. Among them, the structures of the first multiplexer and the second multiplexer can adopt a circuit structure or a chip with the function of a 2:1 multiplexer commonly used in the industry, or a deformed structure of a Gilbert cell. For example, refer to Figure 6 As shown, it is a schematic structural diagram when the first multiplexer is a 2:1 multiplexer. As Figure 6 As shown, the differential pair receiving two input signals is placed on the lower side. The control ends of the multiple differential pairs on the upper side can be externally connected to a clock signal, and by configuring a clock signal with an appropriate frequency, while combining the two signals into one signal, the bandwidth of the combined signal can be improved. For example, if the transmission speed of the DAC is 16.25 GHz, a clock signal with a frequency of 32.5 GHz can be configured for the first multiplexer receiving two such DACs. Figure 5The first multiplexer shown has a first input terminal Vin1+ and Vin- receiving a first input signal Data1, a second input terminal Vin2+ and Vin2- receiving a second input signal Data2, and an output terminal Vmain+ and Vmain- outputting the combined signal. When the received clock signal is in the high level state, the switching transistors V1, V3, V5, and V7 are turned on, and the switching transistors V2, V4, V6, and V8 are turned off. The turned-on switching transistors V1 and V3 transmit the first input signal Data1 to the output terminal, and the turned-on switching transistors V5 and V7 output the second input signal Data2 to the virtual load Rx. When the received clock signal is in the low level state, the switching transistors V2, V4, V6, and V8 are turned on, and the switching transistors V1, V3, V5, and V7 are turned off. The turned-on switching transistors V2 and V4 output the first input signal Data1 to the virtual load Rx, and the turned-on switching transistors V6 and V8 transmit the second input signal to the output terminal. Through the above first multiplexer structure, the first multiplexer can output the first input signal Data1 during the high level state of the received clock signal and output the second input signal Data2 during the low level state of the received clock signal. Therefore, the output signal has the same frequency as the clock signal, and the first input signal Data1 and the second Data2 are alternately output. Among them, in order to improve the linear response of the signal transmission path of the circuit input signal, a coupling resistor RE can be coupled between the emitters of the two switching transistors receiving the first input signal Data1, and a coupling resistor RE can be coupled between the emitters of the two switching transistors receiving the second input signal Data2. In order to improve the bandwidth of the first multiplexer, an inductor can be connected in series on the branches where the load resistors RL and RX are located.

[0054] It should be noted that the structures of the above first multiplexer and second multiplexer are only examples. In actual use, the first multiplexer and second multiplexer can also adopt other general circuit structures or integrated chips in the industry, and there are no excessive limitations here in this application.

[0055] In order to further improve the quality of the transmitted signal, a continuous time linear equalization (CTLE) can be set on the side of each input port of the signal multiplexing device, and the CTLE can perform signal compensation on the divided signals to be combined. The above CTLE can be installed between an external device and the signal multiplexer, or can be installed between the input port of the signal multiplexer and the first multiplexer and between the input port of the signal multiplexer and the second multiplexer. In addition, since the first multiplexer is a 2:1 multiplexer, it is also beneficial to reduce the signal compensation difficulty of the CTLE and reduce the requirements for the DAC in the optical transmitter.

[0056] The first multiplexer and the second multiplexer combine multiple signals to be merged into two signals. The third multiplexer can perform multiplexing on the output signals of the first multiplexer and the second multiplexer, and generate two multiplexed signals with equal frequencies and a phase difference of 1 UI. Among them, the two signals with a phase difference of 1 UI output by the third multiplexer can form a two-tap FFE with an adder. The implementation method of the FFE function will be described below in combination with embodiments.

[0057] In a possible implementation manner, an existing 2:1 multiplexer structure plus a delay unit can be used to output two multiplexed signals with a delay of 1 UI. That is, the output end of the existing 2:1 multiplexer can be directly coupled to the first input end of the adder, and the output end of the existing 2:1 multiplexer is also coupled to the second input end of the adder through a delay unit, thereby forming two signals with the same frequency and a delay of 1 UI. Among them, the 2:1 multiplexer structure can be the first multiplexer structure shown above Figure 6 or other multiplexer structures in the industry that can implement the 2:1 multiplexing function. There is no further limitation here in this application.

[0058] In another possible implementation manner, a new multiplexer structure can be adopted. For example, the third multiplexer can include a first load circuit, a second load circuit, a first Gilbert cell, and a second Gilbert cell.

[0059] Specifically, the first output terminal of the first Gilbert cell is coupled to the first load circuit, the second output terminal is coupled to the second load circuit, the signal input terminal is coupled to the first multiplexer, the clock input terminal is used to receive the first clock signal, and the first Gilbert cell is configured to output the signal output by the first multiplexer to the first load circuit when the first clock signal is at a high level, and output the signal output by the first multiplexer to the second load circuit when the first clock signal is at a low level; the first output terminal of the second Gilbert cell is coupled to the second load circuit, the second output terminal is coupled to the first load circuit, the signal input terminal is coupled to the second multiplexer, the clock input terminal is used to receive the first clock signal, and the second Gilbert cell is configured to output the signal output by the second multiplexer to the second load circuit when the first clock signal is at a high level, and output the signal output by the second multiplexer to the first load circuit when the first clock signal is at a low level. The first load circuit includes a first resistor, a second resistor, a first inductor, and a second inductor. The second terminal of the first resistor is coupled to the power supply through the first inductor, the second terminal of the second resistor is coupled to the power supply through the second inductor, and the first terminal of the first resistor and the first terminal of the second resistor are coupled to the first output terminal of the first Gilbert cell, the second output terminal of the second Gilbert cell, and the first input terminal of the adder; the second load circuit includes a third resistor, a fourth resistor, a third inductor, and a fourth inductor. The second terminal of the third resistor is coupled to the power supply through the third inductor, the second terminal of the fourth resistor is coupled to the power supply through the fourth inductor, and the first terminal of the third resistor and the first terminal of the fourth resistor are coupled to the second output terminal of the first Gilbert cell, the first output terminal of the second Gilbert cell, and the second input terminal of the adder.

[0060] For ease of understanding, a specific structural example of the third multiplexing is given below.

[0061] See Figure 7 As shown in Figure 7 As shown, the resistor-switching transistors V1 and V2 form a differential pair, the switching transistors V3 and V4 form a differential pair, the switching transistors V5 and V6 form a differential pair, the switching transistors V7 and V8 form a differential pair, the switching transistors V9 and V10 form a differential pair, and the switching transistors V11 and V12 form a differential pair. The resistor RL1 forms the first resistor, the resistor RL2 forms the second resistor, the resistor RL3 forms the third resistor, the resistor RL4 forms the fourth inductor, the inductor L1 forms the first inductor, the inductor L2 forms the second inductor, the inductor L3 forms the third inductor, and the inductor L4 forms the fourth inductor.

[0062] Among them, the bases of switching transistor V1, switching transistor V2, switching transistor V3, and switching transistor V4 are the clock input terminals of the first Gilbert cell; the bases of switching transistor V9 and switching transistor V10 are the signal input terminals of the first Gilbert cell; the collectors of switching transistor V1 and switching transistor V3 are the first output terminals of the first Gilbert cell; the collectors of switching transistor V2 and switching transistor V4 are the second output terminals of the first Gilbert cell. The bases of switching transistor V5, switching transistor V6, switching transistor V7, and switching transistor V8 are the clock input terminals of the second Gilbert cell; the bases of switching transistor V11 and switching transistor V12 are the signal input terminals of the second Gilbert cell; the collectors of switching transistor V5 and switching transistor V7 are the first output terminals of the second Gilbert cell; the collectors of switching transistor V6 and switching transistor V8 are the second output terminals of the second Gilbert cell. The second end of resistor RL1 is coupled to power supply VCC through inductor L1; the second end of resistor RL2 is coupled to power supply VCC through inductor L2; the first ends of resistor RL1 and resistor RL2 form the first output terminal of the third multiplexer. The second end of resistor RL3 is coupled to power supply VCC through inductor L3; the second end of resistor RL4 is coupled to power supply VCC through inductor L4; the first ends of resistor RL3 and resistor RL4 form the second output terminal of the third multiplexer.

[0063] Continue to refer to Figure 7As shown, Vmain+ and Vmain- respectively coupled to the first ends of resistors RL2 and RL1 are the first output ports, and Vpost+ and Vpost- respectively coupled to the first ends of resistors RL4 and RL3 are the second output ports. The first input terminals Vin1+ and Vin- receive the signal Data1 output from the first multiplexer, and the second input terminals Vin2+ and Vin2- receive the signal Data2 output from the second multiplexer. The third multiplexer can perform an "AND" logic operation on the clock signal and the two input signals respectively, that is, control the signal output by the third multiplexer through the state of the clock signal. When the received first clock signal is in the high level state, the switching transistors V1, V3, V5, and V7 are turned on, and the switching transistors V2, V4, V6, and V8 are turned off. The turned-on switching transistors V1 and V3 transmit the signal output from the first multiplexer received by the switching transistors V9 and V10 to the first output port, and the turned-on switching transistors V5 and V7 transmit the signal output from the second multiplexer to the second output port. When the clock signal changes from the high level state to the low level state, the switching transistors V2, V4, V6, and V8 are turned on, and the switching transistors V1, V3, V5, and V7 are turned off. The turned-on switching transistors V2 and V4 transmit the signal output from the first multiplexer to the second output port, and the turned-on switching transistors V6 and V8 transmit the signal output from the second multiplexer to the first output port. Through the above third multiplexer structure, the third multiplexer can output the signal output from the first multiplexer at the first output port during the high level state of the received clock signal, and output the signal output from the second multiplexer during the low level state of the received clock signal. The third multiplexer can also output the signal output from the second multiplexer at the second output port during the high level state of the received clock signal, and output the signal output from the first multiplexer during the low level state of the received clock signal. Therefore, the two paths of data output by the third multiplexer are the same, the signal frequency is equal to the clock signal, and the delay is 1UI for both paths of signals. Among them, in order to improve the linear response degree of the signal transmission path of the circuit input signal, a resistor RE can be coupled between the emitters of the two switching transistors receiving the first signal, and a resistor RE can be coupled between the emitters of the two switching transistors receiving the second signal.

[0064] Combined with the above description, the third multiplexer can implement two paths of signals with the same output frequency and data and a delay of 1UI through the configured clock signal. See Figure 8 As shown, it is a schematic diagram of the basic structure of a two-tap EEF, and C10 and C1 are the coefficients of the two taps of the EEF respectively. Since the data of the two paths of signals output by the third multiplexer are the same, one path of the signal can be used as the signal after the other path of the signal passes through the delay unit. Therefore, the two output ports of the third multiplexer can be used as the two taps of the FFE, and the configuration of the coefficients of the taps is implemented by an analog adder coupled to the third multiplexer in the signal multiplexing device.

[0065] SeeFigure 9 As shown, in order to implement the configuration of the FFE two-tap weights, refer to Figure 9 As shown, the adder provided in the embodiment of the present application may be a fixed-gain analog adder or an adjustable-gain analog adder. As Figure 9 As shown, the analog adder includes an adder ∑ without a gain adjustment function, and gain adjustment devices GM1 and GM2. GM1 is coupled to the first input terminal of the adder ∑ and adjusts the gain of the first path signal output by the third multiplexer. GM2 is coupled to the second input terminal of the adder ∑ and adjusts the gain of the second path signal output by the third multiplexer. The adder ∑ performs an addition process on the two signals whose gains are adjusted by GM1 and GM2 respectively and outputs

[0066] In a possible implementation manner, the adder may include: a first switching transistor, a second switching transistor, a first differential pair coupled to the first switching transistor, a second differential pair coupled to the second switching transistor, a third differential pair coupled to the first output terminal of the first differential pair, a fourth differential pair coupled to the second output terminal of the first differential pair, a fifth differential pair coupled to the first output terminal of the second differential pair, a sixth differential pair coupled to the second output terminal of the second differential pair, a fifth resistor, and a sixth resistor.

[0067] Specifically, the control terminal of the switching transistor in the first differential pair is the first input terminal of the adder; the control terminal of the switching transistor in the second differential pair is the second input terminal of the adder; the first output terminal of the third differential pair is coupled to the first output terminal of the fourth differential pair and the second terminal of the fifth resistor, and the second output terminal of the third differential pair is coupled to the second output terminal of the fourth differential pair and the second terminal of the sixth resistor; the first output terminal of the fifth differential pair is coupled to the first output terminal of the sixth differential pair and the second terminal of the fifth resistor, and the second output terminal of the fifth differential pair is coupled to the second output terminal of the sixth differential pair and the second terminal of the sixth resistor; the control terminals of the switching transistors in the third differential pair and the fourth differential pair receive a first adjustment signal, and adjust the conduction degree of the switching transistors in the third differential pair and the fourth differential pair through the first adjustment signal; the control terminals of the switching transistors in the fifth differential pair and the sixth differential pair receive a second adjustment signal, and adjust the conduction degree of the switching transistors in the fifth differential pair and the sixth differential pair through the second adjustment signal.

[0068] For ease of understanding, a specific structural example of the adder is given below.

[0069] Refer to Figure 10 As shown, it is a schematic structural diagram of an adjustable-gain analog adder. As Figure 10As shown, the switching transistor T1 forms the first switching transistor, the switching transistor T2 forms the second switching transistor, the switching transistors V1 and V2 form the first differential pair, the switching transistors V3 and V4 form the second differential pair, the switching transistors V5 and V6 form the third differential pair, the switching transistors V7 and V8 form the fourth differential pair, the switching transistors V9 and V10 form the fifth differential pair, and the switching transistors V11 and V12 form the sixth differential pair. The resistor R1 forms the fifth resistor, and the resistor R2 forms the sixth resistor.

[0070] Among them, the emitter of the switching transistor V1 is coupled to the switching transistor T1, and the collector of the switching transistor V1 is coupled to the emitters of the switching transistors V5 and V6. The emitter of the switching transistor V2 is coupled to the switching transistor T1, and the collector of the switching transistor V2 is coupled to the emitters of the switching transistors V7 and V8. The emitter of the switching transistor V3 is coupled to the switching transistor T2, and the collector of the switching transistor V3 is coupled to the emitters of the switching transistors V9 and V10. The emitter of the switching transistor V4 is coupled to the switching transistor T2, and the collector of the switching transistor V4 is coupled to the emitters of the switching transistors V11 and V12. The bases of the switching transistors V1 and V2 receive the first path signal output by the third multiplexer, and the bases of the switching transistors V3 and V4 receive the second path signal output by the third multiplexer. In order to improve the signal quality of the adder transmission circuit, a resistor and a capacitor are coupled on the path between the emitters of the switching transistors V1 and V2 and the switching transistor T1, and a resistor and a capacitor are coupled on the path between the emitters of the switching transistors V3 and V4 and the switching transistor T2. The collectors of the switching transistors V5 and V7 are coupled and coupled to the resistor R1, the collectors of the switching transistors V6 and V8 are coupled and coupled to the resistor R2, the collectors of the switching transistors V9 and V11 are coupled and coupled to the resistor R1, and the collectors of the switching transistors V10 and V12 are coupled and coupled to the resistor R2.

[0071] Continue to refer to Figure 10As shown, the first input terminals VIN1P+ and VIN1N receive the first path of signals output by the third multiplexer, and the second input terminals VIN2P and VIN2N receive the second path of signals output by the third multiplexer. When the switching transistors are turned on, the two paths of signals will converge on resistors R1 and R2 and are added and then output through output ports Voutp and Voun. Among them, switching transistors V5, V6, V7, and V8 can receive a first adjustment signal, and the first adjustment signal is the bias voltage of the above-mentioned switching transistors. When the received bias voltage changes, the amplification factor of the switching transistors changes, thereby achieving the effect of adjusting the gain of the received first path of signals. Similarly, switching transistors V9, V10, V11, and V12 can receive a second adjustment signal, and the second adjustment signal is the bias voltage of the above-mentioned switching transistors. When the bias voltage received by the switching transistors changes, the amplification factor of the switching transistors changes, thereby achieving the effect of adjusting the gain of the received second path of signals. After the two paths of signals received by the adder are respectively adjusted in gain by the first adjustment signal and the second adjustment signal, they converge on resistor R1 and resistor R2 and are added, thereby completing the compensation of the signals.

[0072] Combined with the above description, the two output terminals of the above-mentioned third multiplexer can form two taps of the FFE, and the gain adjustment of the above-mentioned adder can complete the configuration of weights for the two taps of the EEF, that is, configure coefficients for the two taps, thereby realizing the FFE signal compensation function of the signal multiplexer.

[0073] It should be noted that Figure 10 The adder structure shown is only an example. In actual applications, the adder can also adopt other analog adder circuit structures and chips with adjustable gain, and there are no excessive restrictions here in this application.

[0074] Combined with the above description, it can be seen that if Figure 6 and Figure 7 the multiplexer structure shown is adopted, multiple multiplexers can be controlled to combine the received signals into one path of signals and output by adjusting the clock signal received by the multiplexer in the adjustment signal multiplexing device. Among them, the clock signal can be provided by a device coupled to the signal multiplexing device, or can be provided by the signal multiplexing device, that is, the signal multiplexing device also includes a clock signal generation circuit.

[0075] In a possible implementation manner, in addition to the above circuits, the signal multiplexing device further includes a frequency divider, a first delay unit, and a second delay unit.

[0076] Among them, referring to Figure 11As shown, the frequency divider is coupled to the first multiplexer and the first delay unit, and is configured to receive the second clock signal, split the second clock signal into a first sub-clock signal and a second sub-clock signal, and output them to the coupled first multiplexer and first delay unit respectively. The frequencies of the first sub-clock signal and the second sub-clock signal are the same, and the ratio between the frequency of the first sub-clock signal and the second clock signal is the ratio between the bandwidth of the first multiplexer and the bandwidth of the third multiplexer. The first delay unit is configured to delay the second sub-clock signal output by the frequency divider so that the phase difference between the first sub-clock signal and the second sub-clock signal is a preset threshold. The second delay unit is configured to delay the second clock signal to obtain a first clock signal and output the first clock signal to the second multiplexer, so as to align the first clock signal with the signal received by the third multiplexer. Among them, the structure of the delay unit can adopt a general circuit structure or chip with phase delay in the industry, and will not be introduced in detail here in this application.

[0077] In an example, if the signal multiplexing device is applied to an optical transmitter, the signal IQ modulator in the optical transmitter performs the function of the above-mentioned first delay unit, that is, the IQ modulator will adjust the two clocks output by the frequency divider into a CLK_I clock signal and a CLK_Q clock signal with a phase difference of a preset threshold. For its specific structure, please refer to Figure 12 as shown.

[0078] In a possible implementation manner, if other multiplexer structures are adopted for the first multiplexer and the second multiplexer in the signal multiplexing device. For example, the first multiplexer and the second multiplexer do not perform multiplexing of multiple signals through a clock signal, but are controlled by a dedicated control signal. To ensure that the phase difference between the signals respectively output by the first multiplexer and the second multiplexer is 1UI to ensure the smooth merging of the signals of the third multiplexer, please refer to Figure 13 as shown, a third delay unit can be provided between the output side of the first multiplexer and the third signal multiplexer. The third delay unit can delay the signal output by the first multiplexer, so that the phase difference between the signal output by the first multiplexer and the signal output by the second multiplexer is 1UI.

[0079] The above is the introduction of the structure of the signal multiplexer. Next, taking the structure of the signal multiplexing device Figure 12 as shown as an example, the signal merging process of the signal multiplexing device will be introduced.

[0080] Taking the example that the first multiplexer and the second multiplexer receive two paths of signals respectively, the first multiplexer receives the signals Data1 and Data1 output after CTLE signal compensation, and the second multiplexer receives the signals Data3 and Data4 output after CTLE signal compensation. If the bandwidth of the signals received by the first multiplexer and the second multiplexer is 16.25 GHz, a clock signal with an external frequency of 65 GHz can be received. The frequency divider performs a frequency division by two on the 65 GHz clock signal to obtain two clock signals with a period of 32.5 GHz each. The IQ modulator modulates the two frequency-divided clock signals into a CLK_I clock signal and a CLK_Q clock signal with a time delay difference of 1 UI, and outputs the above two 32.5 GHz clock signals to the first multiplexer and the second multiplexer respectively. Refer to Figure 14 As shown, the first multiplexer outputs the data of Data1 during the first half cycle (i.e., during the period of outputting high and low levels) of the CLK_I clock signal with a period of 32.5 GHz, and outputs the data of Data2 during the second half cycle (i.e., during the period of outputting low level) of the CLK_I clock signal with a period of 32.5 GHz. The second multiplexer outputs the data of Data3 during the first half cycle (i.e., during the period of outputting high and low levels) of the CLK_Q clock signal with a period of 32.5 GHz, and outputs the data of Data4 during the second half cycle (i.e., during the period of outputting low level) of the CLK_Q clock signal with a period of 32.5 GHz. At this time, the periods of the first path of signal Output1 output by the first multiplexer and the second path of signal Output2 output by the second multiplexer are both 32.5 GHz, thus achieving the effect of combining multiple input signals and improving the signal transmission speed. The second delay unit aligns the 65 GHz clock signal with the above signal data and outputs it to the third multiplexer. The first output terminal main of the third multiplexer outputs the signal of the first path of signal Output1 during the first half cycle of the 65 GHz clock signal, and outputs the signal of the second path Output2 during the second half cycle of the 65 GHz clock signal. The second output terminal post of the third multiplexer outputs the signal of the second path of signal Output2 during the first half cycle of the 65 GHz clock signal, and outputs the signal of the first path Output1 during the second half cycle of the 65 GHz clock signal. At this time, the periods of the two paths of signals output by the two output terminals of the third multiplexer are both 65 GHz and the time delay is 1 UI. The above two paths of signals are respectively subjected to gain adjustment by GM1 and GM2 and adder addition processing to obtain a compensated signal, and then transmitted through a backend coupling device.

[0081] Based on the same inventive concept, an embodiment of the present application further provides an optical transmitter. Refer to Figure 15As shown in the figure, the optical transmitter includes: a digital signal processor (DSP), multiple digital-to-analog converters (DACs), at least one of the aforementioned signal multiplexing devices, a driver (DRV) corresponding to each signal multiplexing device, at least one modulator, and a polarization beam splitter (PBS); each DAC is used to convert a digital signal output by the digital signal processor (DSP) into an analog signal and output it; each signal multiplexing device is coupled to multiple DACs and is used to multiplex the analog signals output by the coupled multiple DACs into one signal and output it; each driver (DRV) is used to receive the signal output by the corresponding signal multiplexing device, perform power amplification, and then output it; each modulator is used to receive the signals output by two drivers (DRVs), adjust the received signals into optical signals, and output them to the polarization beam splitter (PBS) for output.

[0082] Among them, for the structure of the signal multiplexing device, reference can be made to the aforementioned relevant introduction, and no repeated introduction will be made here in this application.

[0083] It should be noted that adopting the above optical transmitter structure can not only improve the signal transmission speed of the optical transmitter by multiplexing the signals output by multiple DACs into one signal through the signal multiplexing device. Since the signal multiplexing device combines the signals output by multiple DACs, the signals output by multiple DACs are coupled to one driver through the signal multiplexing device, which is also beneficial to reducing the volume of the optical transmitter and the cost of the optical transmitter.

[0084] It should be noted that the signal multiplexing device provided in the embodiments of this application can not only be used in an optical transmitter to multiplex the signals output by multiple DACs in the optical transmitter into one signal to improve the signal transmission rate of the optical transmitter. The signal multiplexing device provided in the embodiments of this application can also be applied to other devices that need to improve the signal transmission speed, and no excessive restrictions will be imposed here in this application.

[0085] Those skilled in the art should understand that the embodiments of this application can be provided as a method, a system, or a computer program product. Therefore, this application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0086] This application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices produce a means for implementing the functions specified in one or more of the flows Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0087] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including an instruction means that implements the functions specified in one or more of the flows Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more of the flows Figure 1 one or more flows and / or blocks Figure 1 or a means for implementing the functions specified in one or more of the blocks.

[0089] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. A signal multiplexing device, characterized in that, Comprising: A first multiplexer, a second multiplexer, a third multiplexer, and an adder; The first multiplexer is coupled to the third multiplexer, and the first multiplexer is configured to combine multiple received signals into a first signal and output the first signal to the third multiplexer; The second multiplexer is coupled to the third multiplexer, and the second multiplexer is configured to combine multiple received signals into a second signal and output the second signal to the third multiplexer; The third multiplexer is respectively coupled to the first input terminal and the second input terminal of the adder. The third multiplexer is configured to receive a first clock signal. When the first clock signal is at a high level, the third multiplexer outputs the first signal to the first input terminal and outputs the second signal to the second input terminal. When the first clock signal is at a low level, the third multiplexer outputs the second signal to the first input terminal and outputs the first signal to the second input terminal. The rate of the signal output by the third multiplexer to the adder is twice the rate of the received signal; The adder is configured to perform an addition process on the two signals received at the first input terminal and the second input terminal and output the result.

2. The device according to claim 1, characterized in that, The third multiplexer includes a first load circuit, a second load circuit, a first Gilbert cell, and a second Gilbert cell; A first output terminal of the first Gilbert cell is coupled to the first load circuit, a second output terminal is coupled to the second load circuit, a signal input terminal is coupled to the first multiplexer, and a clock input terminal is configured to receive the first clock signal. The first Gilbert cell is configured to, when the first clock signal is at a high level, output the signal output by the first multiplexer to the first load circuit, and when the first clock signal is at a low level, output the signal output by the first multiplexer to the second load circuit; A first output terminal of the second Gilbert cell is coupled to the second load circuit, a second output terminal is coupled to the first load circuit, a signal input terminal is coupled to the second multiplexer, and a clock input terminal is configured to receive the first clock signal. The second Gilbert cell is configured to, when the first clock signal is at a high level, output the signal output by the second multiplexer to the second load circuit, and when the first clock signal is at a low level, output the signal output by the second multiplexer to the first load circuit.

3. The device according to claim 2, characterized in that, The first load circuit includes a first resistor, a second resistor, a first inductor, and a second inductor. A second end of the first resistor is coupled to a power supply through the first inductor, a second end of the second resistor is coupled to the power supply through the second inductor, and a first end of the first resistor and a first end of the second resistor are coupled to a first output terminal of the first Gilbert cell, a second output terminal of the second Gilbert cell, and a first input terminal of the adder; The second load circuit includes a third resistor, a fourth resistor, a third inductor, and a fourth inductor. The second end of the third resistor is coupled to the power supply through the third inductor, and the second end of the fourth resistor is coupled to the power supply through the fourth inductor. The first ends of the third resistor and the fourth resistor are coupled to the second output end of the first Gilbert cell, the first output end of the second Gilbert cell, and the second input end of the adder.

4. The device according to any one of claims 1 to 3, characterized in that, The signal multiplexing device further includes a plurality of first linear equalizers coupled to the first multiplexer and a plurality of second linear equalizers coupled to the second multiplexer. Each first linear equalizer receives a signal path, compensates the received signal, and outputs it to the first multiplexer; each second linear equalizer receives a signal path, compensates the received signal, and outputs it to the second multiplexer. The signals received by each first linear equalizer and each second linear equalizer are different.

5. The device according to any one of claims 1 to 4, characterized in that, The signal multiplexing device further includes a frequency divider, a first delay unit, and a second delay unit; The frequency divider is coupled to the first multiplexer and the second multiplexer, and is configured to receive a second clock signal, split the second clock signal into a first sub-clock signal and a second sub-clock signal, and output them to the first multiplexer and the first delay unit respectively. The first sub-clock signal and the second sub-clock signal have the same frequency, and the phase difference between the first sub-clock signal and the second sub-clock signal is a preset threshold. The ratio of the frequency of the first sub-clock signal to the second clock signal is the ratio of the bandwidth of the first multiplexer to the bandwidth of the third multiplexer; The first delay unit is configured to perform a delay process on the second sub-clock signal so that the phase difference between the first sub-clock signal and the second sub-clock signal is a preset threshold; The second delay unit is configured to perform a delay process on the second clock signal to obtain the first clock signal and output the first clock signal to the third multiplexer.

6. The device according to any one of claims 1 to 4, characterized in that The signal multiplexing device further includes a third delay unit coupled between the first multiplexer and the third multiplexer. The third delay unit is configured to perform a delay process on the signal output by the first multiplexer so that the phase difference between the signal output by the first multiplexer and the signal output by the second multiplexer is a preset threshold.

7. The device according to any one of claims 1 to 6, characterized in that, The adder is an adjustable gain analog adder, configured to perform gain adjustment on two received signals respectively, perform an addition process on the circuit signals after gain adjustment, and output the result.

8. The device according to any one of claims 1 to 7, characterized in that, The adder includes a first switching transistor, a second switching transistor, a first differential pair coupled to the first switching transistor, a second differential pair coupled to the second switching transistor, a third differential pair coupled to the first output end of the first differential pair, a fourth differential pair coupled to the second output end of the first differential pair, a fifth differential pair coupled to the first output end of the second differential pair, a sixth differential pair coupled to the second output end of the second differential pair, a fifth resistor, and a sixth resistor; The control end of the switching transistor in the first differential pair is the first input end of the adder; The control terminal of the switching transistor in the second differential pair is the second input terminal of the adder; The first output terminal of the third differential pair is coupled to the first output terminal of the fourth differential pair and the second terminal of the fifth resistor, and the second output terminal of the third differential pair is coupled to the second output terminal of the fourth differential pair and the second terminal of the sixth resistor; The first output terminal of the fifth differential pair is coupled to the first output terminal of the sixth differential pair and the second terminal of the fifth resistor, and the second output terminal of the fifth differential pair is coupled to the second output terminal of the sixth differential pair and the second terminal of the sixth resistor; The control terminals of the switching transistors in the third differential pair and the fourth differential pair receive a first adjustment signal, and the conduction degree of the switching transistors in the third differential pair and the fourth differential pair is adjusted by the first adjustment signal; The control terminals of the switching transistors in the fifth differential pair and the sixth differential pair receive a second adjustment signal, and the conduction degree of the switching transistors in the fifth differential pair and the sixth differential pair is adjusted by the second adjustment signal.

9. The device according to any one of claims 1 to 8, characterized in that, The ratio between the rate of the output signal of the first multiplexer and the rate of the received signal is the number of signals received by the first multiplexer, and the ratio between the rate of the output signal of the second multiplexer and the rate of the received signal is the number of signals received by the second multiplexer.

10. An optical transmitter, characterized in that, Comprising a digital signal processor, a plurality of digital-to-analog converters DAC, at least one signal multiplexing device as described in any one of claims 1 to 9, a driver corresponding to each signal multiplexing device, at least one modulator, and a beam combiner; Each DAC is used to convert a path of digital signal output by the digital signal processor into an analog signal and output it; Each signal multiplexing device is coupled to a plurality of DACs, and is used to multiplex the analog signals output by the coupled plurality of DACs into one path of signal and output it; Each driver is used to receive the signal output by the corresponding signal multiplexing device, perform power amplification, and then output it; Each modulator is used to receive the signals output by two drivers, adjust the received signals into optical signals, and output them to the beam combiner for output.

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