System and method for synchronizing B code time and TSN sensitive network time based on FPGA

Abstract

The invention relates to the technical field of time synchronization, in particular to an FPGA-based B code time and TSN sensitive network time synchronization system and method, and the FPGA-based B code time and TSN sensitive network time synchronization system comprises a B code time analysis module, a clock synchronization control module, a thickness calibration module, a parameter configuration module and a jump detection module. According to the system, B code time is used as a standby synchronization source, rapid and stable synchronization is realized in combination with a thickness calibration mode, and precision and reliability are improved by using noise suppression and an intelligent switching strategy. According to the method, the problem of synchronization loss caused by main clock source faults or step jumping can be effectively solved, the stability and applicability of a TSN network system are remarkably enhanced, and the method is suitable for high-precision time-sensitive scenes such as avionics and industrial automation and has important practical value and popularization prospects.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer networks, and particularly relates to a synchronization system and method for B-code time and TSN-sensitive network time based on FPGA. Background Art

[0002] With the continuous development of aviation technology, the data streams generated by devices such as sensors and cameras on aircraft are becoming increasingly large, and the requirements for network bandwidth, communication reliability, real-time performance, and system integration have also increased significantly. Existing communication technologies are gradually difficult to meet the needs of the aviation field. As an emerging network technology, Time-Sensitive Networking (TSN) can provide higher bandwidth and low-latency characteristics to ensure the highly reliable transmission of critical flight information (such as flight attitude, altitude, and other parameters) between systems, thus meeting the needs of avionics equipment for a large amount of data transmission. The TSN network achieves precise time synchronization through the IEEE802.1AS protocol. The core lies in the existence of a master clock in the entire local area network, and other nodes complete time synchronization with reference to this master clock. The node where the master clock is located serves as the master node and interacts with slave nodes through protocol frames to achieve network-wide time synchronization.

[0003] Chinese Patent Application No. CN202311254260.7 provides a time synchronization system, method, computer device, and storage medium. The system includes an IRIG B-code decoder, a time compensation module, a time register, and a TSN network card; if the time synchronization system is connected between an IRIG B-code clock device and a time-sensitive network, the conversion mode is activated. In the conversion mode, the IRIG B-code decoder decodes the first IRIG B-code signal to obtain the first time information and writes it into the time register; the time compensation module determines the first compensation time according to the decoded time; the time register compensates the first time information according to the first compensation time; the TSN network card encapsulates the compensated first time information in the first time synchronization message and sends it to the time-sensitive network, so that the TSN switch and the first terminal device of the substation perform time synchronization according to the compensated first time information. In this way, time synchronization in the time-sensitive network of the substation can be achieved through the IRIG B-code, and the accuracy of time synchronization can be improved.

[0004] However, in practical applications, the time synchronization mechanism of the TSN network still faces many challenges. First, the airborne device network needs to maintain high-precision time synchronization with other systems. Especially when establishing time synchronization between two systems that are far apart, it usually relies on external time-giving clock sources (such as GPS, Beidou, rubidium clocks, etc.). However, when the time-giving clock device fails and cannot output the master clock, the airborne device network will lose the synchronization relationship with other systems, resulting in transmission errors of various sensing parameters and control command signals in the communication data load, and then leading to flight accidents. Second, when synchronizing time with external systems, if there is a clock step jump, it will cause time disorders in the real-time data transmission within the local area network or between the local area network and the external network, resulting in data transmission errors and system control jitters. In addition, when the local TSN network system needs to establish a synchronization relationship with other network systems with different clock sources, traditional methods require replacing the local clock device and redesigning the processor software of the TSN master device, which not only increases the hardware cost but also significantly improves the human input and technical complexity.

[0005] To solve the above problems, a technical solution that can flexibly handle clock source failures, clock jumps, and multi-clock source switching is urgently needed. Summary of the Invention

[0006] The purpose of the present invention is to provide a synchronization system and method for B-code time and TSN-sensitive network time based on FPGA to solve the problems mentioned in the above background technology.

[0007] To achieve the above purpose, the present invention provides the following technical solution: A synchronization system for B-code time and TSN-sensitive network time based on FPGA, including a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module; the B-code time parsing module is used to receive and parse external B-code signals and extract accurate time information; the clock synchronization control module is used to dynamically adjust the master clock of the TSN network system according to the parsed time information; the coarse and fine calibration module is used to selectively integrate the B-code time into the current network time and support fast or smooth synchronization modes; the parameter configuration module is used to flexibly set synchronization parameters through various interfaces; the jump detection module is used to monitor the changes in the clock domain in real time and trigger a switch to the B-code time source in case of abnormalities.

[0008] As a further solution of the present invention, the coarse and fine calibration module includes a frequency calibration unit; the frequency calibration unit is used to gradually adjust the network time according to the deviation between the B-code time and the current network time by using a frequency accumulation algorithm, and the formula is as follows: ; Wherein, represents the new clock frequency, is the current network clock frequency, is the frequency calibration step value, is the calibration attenuation coefficient, is the calibration time interval.

[0009] As a further solution of the present invention, the coarse and fine calibration module further includes a time format conversion unit; the time format conversion unit is used to directly convert the B-code time into the TSN network master clock format in the coarse calibration mode, and the formula is as follows: ; wherein, represents the synchronized time value, is the B-code time, is the local network time, is the time fusion coefficient, and its value range is between 0 and 1.

[0010] As a further solution of the present invention, the parameter configuration module includes a multi-interface adaptation unit; the multi-interface adaptation unit is used to dynamically update the key parameters in the synchronization parameter table through a serial port, a PCIe bus or a network port, and the formula is as follows: ; wherein, represents the updated parameter value, is the default parameter value, is the parameter adjustment weight, is the input parameter change amount.

[0011] As a further solution of the present invention, the jump detection module includes a clock step analysis unit; the clock step analysis unit is used to detect the step change in the clock domain and calculate whether the step amplitude exceeds a preset threshold, and the formula is as follows: ; wherein, represents whether to trigger a step alarm, is the current clock value, is the previous clock value, is the step change threshold.

[0012] As a further solution of the present invention, the clock synchronization control module includes a clock source switching unit; the clock source switching unit is used to automatically switch to the B-code time source when the main clock source fails or a step jump occurs, and the formula is as follows: ; wherein, represents the currently used clock source, is the step alarm flag provided by the jump detection module, is the status flag of the main clock source.

[0013] As a further solution of the present invention, the time smoothing transition unit is used to reduce time jitter through an interpolation algorithm when switching clock sources, and the formula is as follows: ; Wherein, represents the smoothed time value, is the original time value, is the new time value, is the smoothing coefficient, and its value range is between 0 and 1.

[0014] As a further solution of the present invention, the frequency calibration unit further introduces a noise suppression mechanism, and the specific calculation formula is: ; Wherein, represents the filtered frequency value, the original frequency value, is the noise suppression factor, is the noise intensity, which is dynamically estimated by a Kalman filter.

[0015] As a further solution of the present invention, the clock source switching unit further optimizes the switching strategy and introduces a switching cost evaluation model, and the specific calculation formula is: ; Wherein, represents the switching cost, is the time deviation amount, is the frequency deviation amount, is the switching energy consumption, , , are the weight coefficients.

[0016] A synchronization method for B-code time and TSN-sensitive network time based on FPGA is also disclosed, which is characterized by including the following steps: Step S1: Receive an external B-code signal, parse and extract accurate time information; Step S2: Dynamically adjust the master clock frequency and time value of the TSN network system based on the parsed B-code time information; Step S3: Selectively fuse the B-code time with the current network time, and achieve synchronization through a coarse calibration mode or a fine calibration mode, Step S4: Dynamically configure synchronization parameters through a serial port, a PCIe bus or a network port, including a frequency calibration step value, a time fusion coefficient and a step change threshold; Step S5: Real-time monitor the step change in the clock domain. If it is detected that the master clock source fails or the step amplitude exceeds a preset threshold, trigger a switch to the B-code time source; Step S6: When switching the clock source, an interpolation algorithm is adopted to smoothly transition the time value to reduce time jitter.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: Based on the existing TSN network time synchronization, the system introduces the B-code time as a backup synchronization source. When the existing network synchronization time source fails or has a large jump, it can quickly switch to the B-code time to avoid the loss of the synchronization relationship between the local local area network and other system networks. At the same time, the system supports two synchronization modes: coarse calibration and fine calibration, and can select a fast synchronization or a smooth integration into the current network time according to actual needs, thereby reducing the risk of chaos in real-time communication data. In addition, the system also supports flexible configuration, and key parameters can be adjusted through methods such as serial ports, PCIe buses, or network ports, further enhancing the adaptability and compatibility of the system. This innovative design not only improves the reliability and stability of the TSN network in complex environments, but also provides technical support for high-precision time synchronization of larger-scale network systems, effectively solving the problem of synchronization loss caused by the failure or step jump of the master clock source, and significantly improving the reliability of the TSN network system. Secondly, combining the coarse and fine calibration modes takes into account the requirements of fast synchronization and smooth transition, reducing the impact on real-time communication. Thirdly, through flexible parameter configuration and intelligent switching strategies, seamless docking of multiple clock sources is supported, expanding the scope of application of the system. In addition, frequency calibration and noise suppression algorithms are adopted to improve the accuracy and stability of time synchronization. This method is applicable to high-precision time-sensitive scenarios such as avionics and industrial automation, and has important practical value and promotion prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is the system structure block diagram of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0020] A synchronization system for B-code time and TSN sensitive network time based on FPGA, in combination with the attached Figure 1 is described in detail for its implementation process. The system includes a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module. Each module is implemented by FPGA hardware to ensure high-precision time synchronization performance. The following is a complete description of the specific implementation process.

[0021] First, refer to the attachedFigure 1 , which shows the overall structural block diagram of the system. The B-code time parsing module, as the first processing unit of the system, is responsible for receiving the externally input B-code signal and decoding it to extract accurate time information. The B-code signal is usually generated by an external high-precision clock source, and its format includes a second pulse and time-encoding data. The parsing module realizes the capture and decoding of the signal through a hardware logic circuit, and transfers the extracted time information to the subsequent modules. In practical applications, the B-code signal may be affected by noise interference. Therefore, the parsing module is built-in with a digital filter to remove high-frequency noise and improve the signal quality. The parsed B-code time information is stored in a register in a standard format for use by the clock synchronization control module. The parsing module uses a FIR low-pass filter with a cut-off frequency of 1 kHz, and the filter order can be dynamically adjusted (default 64 orders) through a parameter configuration module to suppress the influence of high-frequency noise on the B-code signal.

[0022] The clock synchronization control module is the core part of the system, and its main function is to dynamically adjust the master clock of the TSN network system according to the parsed B-code time. The clock synchronization control module includes a clock source switching unit and a time smooth transition unit. When the master clock source is operating normally, the system preferentially uses the master clock source as the time reference; when the master clock source fails or has a step jump, the clock source switching unit will automatically switch to the B-code time source. The switching logic is implemented through the following formula: ; where, represents the currently used clock source, is the step alarm flag provided by the jump detection module, is the status flag of the master clock source. If the status of the master clock source is abnormal or the step change exceeds the preset threshold, it will switch to the B-code time source. In order to reduce the time jitter that may occur during the switching process, the time smooth transition unit uses an interpolation algorithm to smooth the time value, and the formula is as follows: ; where, represents the smoothed time value, is the original time value, is the new time value, is the smoothing coefficient, and its value range is between 0 and 1. By gradually adjusting the time value, it is ensured that the switching process is stable and does not affect real-time communication. The smoothing coefficient is calibrated through experiments, and users can adjust it as needed through the parameter configuration module. For example, it is set to 0.5 in industrial automation scenarios to accelerate convergence.

[0023] The coarse calibration module is a key component for achieving time synchronization, including a frequency calibration unit and a time format conversion unit. The main task of the frequency calibration unit is to gradually adjust the network time using the frequency accumulation algorithm based on the deviation between the B-code time and the current network time. The specific calculation formula is: ; Where, represents the new clock frequency, is the current network clock frequency, is the frequency calibration step value, is the calibration attenuation coefficient, is the calibration time interval. This formula gradually adjusts the frequency in an exponential decay manner to avoid oscillation phenomena caused by rapid calibration. In addition, the frequency calibration unit also introduces a noise suppression mechanism that dynamically estimates the noise intensity through a Kalman filter and filters the frequency value according to the following formula: ; Where, represents the filtered frequency value, the original frequency value, is the noise suppression factor, is the noise intensity. This mechanism effectively improves the accuracy and stability of frequency calibration, and the state equation of the Kalman filter is , and the observation equation is , where and are the process noise and observation noise respectively. By real-time estimating the noise intensity , dynamically adjusting value, adaptive filtering is achieved.

[0024] The time format conversion unit is responsible for directly converting the B-code time into the TSN network master clock format in the coarse calibration mode. The formula is as follows: ; Where, represents the synchronized time value, is the B-code time, is the local network time, is the time fusion coefficient, and its value range is between 0 and 1. By adjusting value, the coarse calibration or fine calibration mode can be flexibly selected to meet the requirements of different application scenarios.

[0025] The parameter configuration module provides multiple interfaces for dynamically updating the key parameters in the synchronization parameter table. Refer to Appendix Figure 1 , this module includes a multi-interface adaptation unit, supporting parameter configuration through serial ports, PCIe buses, or network ports. The parameter update formula is as follows: ; wherein, represents the updated parameter value, is the default parameter value, is the parameter adjustment weight, is the input parameter change amount. By flexibly configuring the parameters, users can optimize the system performance according to actual needs. For example, in the avionics scenario, the time synchronization requirements in a high-dynamic environment can be met by adjusting the frequency calibration step value and the calibration attenuation coefficient .

[0026] The jump detection module is used to monitor the change of the clock domain in real time and trigger the switch to the B-code time source in case of anomalies. This module includes a clock step analysis unit for detecting the step change of the clock domain and calculating whether the step amplitude exceeds a preset threshold. The step alarm trigger condition is judged by the following formula: ; wherein, indicates whether to trigger the step alarm, is the current clock value, is the previous clock value, is the step change threshold. Once a step change exceeding the threshold is detected, the jump detection module will send an alarm signal to the clock synchronization control module to trigger the clock source switching operation. The step change threshold supports dynamic adjustment according to the network load. For example, when the network delay exceeds 2ms, the threshold is automatically amplified to ; it is restored to under low load to balance sensitivity and false alarm rate. In addition, the clock source switching unit further optimizes the switching strategy by introducing a switching cost evaluation model, and the formula is as follows: ; wherein, represents the switching cost, is the time deviation amount, is the frequency deviation amount, is the switching energy consumption, , , are the weight coefficients. By comprehensively considering the time deviation, frequency deviation and switching energy consumption, the system can intelligently select the optimal switching timing, thereby reducing the impact of switching on network communication.

[0027] In actual application scenarios, the synchronization system of the present invention is widely applicable to high-precision time-sensitive fields such as avionics and industrial automation. For example, in an avionics system, multiple subsystems need to perform real-time data exchange through a TSN network, and the accuracy of time synchronization directly affects the safety of flight control. By introducing the B-code time as a backup synchronization source, the present invention effectively solves the problem of synchronization loss caused by the failure or step jump of the main clock source, and significantly improves the reliability of the system. At the same time, combined with the coarse and fine calibration modes, the system can achieve a balance between fast synchronization and smooth transition, reducing the impact on real-time communication. In addition, through flexible parameter configuration and intelligent switching strategies, the system supports seamless docking of multiple clock sources, expanding the scope of application.

[0028] In summary, the present invention realizes high-precision synchronization of B-code time and TSN-sensitive network time through FPGA hardware, and combines the Figure 1 specific structure and operating principle to describe in detail the functions of each module and their implementation methods. The system design fully considers the requirements of actual application scenarios and has important practical value and promotion prospects.

[0029] Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An FPGA-based synchronization system for B-code time and TSN-sensitive network time, characterized in that, It includes a B-code time parsing module, a clock synchronization control module, a coarse and fine calibration module, a parameter configuration module, and a jump detection module; the B-code time parsing module is used to receive and parse external B-code signals and extract accurate time information; the clock synchronization control module is used to dynamically adjust the master clock of the TSN network system according to the parsed time information; the coarse and fine calibration module is used to selectively integrate the B-code time into the current network time and support fast or smooth synchronization modes; the parameter configuration module is used to flexibly set synchronization parameters through multiple interfaces; the jump detection module is used to monitor the changes in the clock domain in real time and trigger a switch to the B-code time source in case of anomalies.

2. The synchronization system for B-code time and TSN-sensitive network time based on FPGA according to claim 1, wherein: The coarse and fine calibration module includes a frequency calibration unit; the frequency calibration unit is used to gradually adjust the network time according to the deviation between the B-code time and the current network time by using a frequency accumulation algorithm, and the formula is as follows: ； Among them, represents the new clock frequency, is the current network clock frequency, is the frequency calibration step value, is the calibration attenuation coefficient, is the calibration time interval.

3. The synchronization system based on FPGA for B-code time and TSN sensitive network time according to claim 2, characterized in that: The coarse and fine calibration module further includes a time format conversion unit; the time format conversion unit is used to directly convert the B-code time into the TSN network master clock format in the coarse calibration mode, and the formula is as follows: ； Among them, represents the time value after synchronization, is the B-code time, is the local network time, is the time fusion coefficient, and its value range is between 0 and 1.

4. The synchronization system for B-code time and TSN-sensitive network time based on FPGA according to claim 3, characterized in that: The parameter configuration module includes a multi-interface adaptation unit; the multi-interface adaptation unit is used to dynamically update the key parameters in the synchronization parameter table through a serial port, a PCIe bus, or a network port, and the formula is as follows: ； Among them, represents the updated parameter value, is the default parameter value, is the parameter adjustment weight, is the input parameter change amount.

5. The synchronization system based on FPGA for B-code time and TSN-sensitive network time according to claim 1, wherein: The jump detection module includes a clock step analysis unit; the clock step analysis unit is used to detect the step change in the clock domain and calculate whether the step amplitude exceeds a preset threshold, and the formula is as follows: ； Among them, indicates whether a step alarm is triggered, is the current clock value, is the previous clock value, is the step change threshold.

6. The synchronization system for B-code time and TSN-sensitive network time based on FPGA according to claim 1, characterized in that: The clock synchronization control module includes a clock source switching unit; the clock source switching unit is used to automatically switch to the B-code time source when the master clock source fails or there is a step jump, and the formula is as follows: ； Among them, represents the currently used clock source, is the step alarm flag provided by the jump detection module, is the status flag of the main clock source.

7. The synchronization system for B-code time and TSN-sensitive network time based on FPGA according to claim 6, characterized in that: The time smooth transition unit is used to reduce time jitter through an interpolation algorithm when switching the clock source, and the formula is as follows: ； Among them, represents the smoothed time value, is the original time value, is the new time value, is the smoothing coefficient, and its value range is between 0 and 1.

8. The synchronization system for B-code time and TSN-sensitive network time based on FPGA according to claim 2, wherein: The frequency calibration unit further introduces a noise suppression mechanism, and the specific calculation formula is: ； Among them, represents the filtered frequency value, the original frequency value, is the noise suppression factor, is the noise intensity, dynamically estimated by the Kalman filter.

9. The synchronization system based on FPGA for B-code time and TSN-sensitive network time according to claim 6, characterized in that: The clock source switching unit further optimizes the switching strategy and introduces a switching cost evaluation model. The specific calculation formula is as follows: ; Among them, represents the switching cost, is the time deviation amount, is the frequency deviation amount, is the switching energy consumption, , , are the weight coefficients.

10. A synchronization method for B-code time and TSN-sensitive network time based on FPGA, characterized in that, It includes the following steps: Step S1: Receive an external B-code signal, parse and extract accurate time information; Step S2: Based on the parsed B-code time information, dynamically adjust the master clock frequency and time value of the TSN network system; Step S3: Selectively integrate the B-code time with the current network time and achieve synchronization through the coarse calibration mode or the fine calibration mode; Step S4: Dynamically configure synchronization parameters through a serial port, a PCIe bus, or a network port, including the frequency calibration step value, the time fusion coefficient, and the step change threshold; Step S5: Monitor the step change in the clock domain in real time. If it is detected that the master clock source fails or the step amplitude exceeds the preset threshold, trigger a switch to the B-code time source; Step S6: When switching the clock source, use an interpolation algorithm to smoothly transition the time value to reduce time jitter.

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