System and method for memory resource allocation of multi-layer switch firmware combination

Abstract

The present invention discloses a system and method for allocating memory resources of a multi-level switch firmware combination, relating to the field of computer technology. When a server is started, a first hardware resource on a peripheral interconnection link is read. When the first hardware resource includes a switch, the second hardware resource connected to each switch is identified, and the identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. The firmware allocates the first memory resource to the switch and the second hardware resource, and allocates resources to the second hardware resource connected to the switch through the firmware of the switch. The system does not need to read the resource allocation of each peripheral interconnection device in turn, but only needs to read the memory resource allocation set in the firmware of the switch. Therefore, the startup time of the server can be optimized, and the reallocation of memory resources when the server is started can be avoided, thereby ensuring the stability and stability of the memory resource allocation.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a system and method for allocating memory resources of a multi-layer switch firmware combination. Background Art

[0002] Smart NICs (Smart NICs) are widely used in various server architectures in data centers. They offload data processing functions unsuitable for the server's CPU (Central Processing Unit) to programmable hardware chips, reducing CPU consumption. However, because Smart NICs contain numerous internal devices, each of these devices requires memory resources and prioritizes certain memory resources. Some Smart NICs also include switch chips, which connect to other PCI (Peripheral Component Interconnect) devices and thus require memory allocation. Furthermore, server motherboards or PCI device cards also contain similar switch chips, which, along with the PCI devices underneath, also require resources.

[0003] Related technologies reserve resources when the server starts up. However, since a server may involve many switch chips and the switch chip hierarchy cannot be fixed, it is impossible to predict which specific switch chip needs to reserve resources. Therefore, it takes a lot of time to identify and traverse the switch chips of the PCI link to reserve resources, which significantly prolongs the server startup time. Summary of the Invention

[0004] The present invention provides a system and method for allocating memory resources of a multi-layer switch firmware combination, so as to at least solve the problem that the memory resource allocation method in the related art causes a long server startup time.

[0005] The present invention provides a system for allocating memory resources in a combination of multi-layer switch firmware, comprising: at least one processing circuit of a server, the at least one processing circuit being connected to at least one peripheral interconnection link, the at least one processing circuit being used to: execute a read engine, the read engine reading a first hardware resource on the current peripheral interconnection link when the server is started; propagating the read data of the first hardware resource to an identification engine, the identification engine identifying the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifying a second hardware resource connected to each switch; propagating the identification result of the second hardware resource connected to each switch to the firmware of the corresponding switch, the firmware allocating a first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

[0006] The present invention also provides a server comprising the above-mentioned multi-level switch firmware combined memory resource allocation system.

[0007] The present invention also provides a method for allocating memory resources of a multi-layer switch firmware combination, comprising: using at least one processing circuit connected to at least one peripheral interconnection link, wherein the at least one processing circuit is used to: execute a reading engine, the reading engine reads the first hardware resource on the current peripheral interconnection link when the server is started; propagates the read data of the first hardware resource to an identification engine, the identification engine identifies the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifies the second hardware resource connected to each switch; propagates the identification result of the second hardware resource connected to each switch to the firmware of the corresponding switch, and the firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

[0008] The present invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of the method for allocating memory resources of a multi-layer switch firmware combination are implemented.

[0009] The present invention also provides a computer program product, comprising a computer program, which implements the steps of the above-mentioned method for allocating memory resources of a multi-layer switch firmware combination when executed by a processor.

[0010] Through the present invention, the first hardware resource on the peripheral interconnection link can be read when the server is started. When the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, the second hardware resource connected to each switch is identified, and the identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. The firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource, and allocates resources to the second hardware resource connected to it through the firmware of the switch. There is no need for the system to read the resource allocation of each peripheral interconnection device in turn. It is only necessary to read the memory resource allocation set in the firmware of the switch. The memory resource allocation for the switch and the hardware resources connected to the switch is implemented through the firmware, thereby optimizing the startup time of the server and avoiding the reallocation of memory resources when the server starts, thereby ensuring the fixity and stability of the memory resource allocation. Therefore, it can solve the technical problem in the related art that the memory resource allocation method causes a long server startup time. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0012] Figure 1 A schematic diagram of a multi-level switch firmware combined memory resource allocation system provided by an embodiment of the present invention;

[0013] Figure 2 A schematic diagram of a link of a single-level switch provided according to an embodiment of the present invention;

[0014] Figure 3 A schematic diagram of a link of a multi-level switch provided according to an embodiment of the present invention;

[0015] Figure 4 A schematic diagram of a physical connection of a server motherboard according to an embodiment of the present invention;

[0016] Figure 5 A schematic diagram of the structure of a data processor provided according to an embodiment of the present invention;

[0017] Figure 6 A flowchart of a method for allocating memory resources by combining multi-level switch firmware according to an embodiment of the present invention;

[0018] Figure 7 A diagram showing component execution connection relationships of a multi-level switch firmware combined memory resource allocation system during a server startup phase according to an embodiment of the present invention;

[0019] Figure 8 A flowchart of memory resource allocation during the server startup phase according to an embodiment of the present invention;

[0020] Figure 9 A flowchart of reading firmware setting parameters of a switch on a peripheral interconnection link provided according to an embodiment of the present invention;

[0021] Figure 10 A diagram illustrating a component execution connection relationship of a multi-level switch firmware combined memory resource allocation system when a server enters an operating system stage according to an embodiment of the present invention;

[0022] Figure 11 This is a flowchart of memory resource allocation when a server enters the operating system stage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0024] It should be noted that, in the description of the present invention, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. The terms "first," "second," etc., in the present invention are used to distinguish similar objects, and are not used to describe a particular order or precedence.

[0025] An embodiment of the present invention provides a system for allocating memory resources by combining multi-level switch firmware.

[0026] like Figure 1 As shown, the multi-level switch firmware combined memory resource allocation system 10 includes: at least one processing circuit 11 of a server.

[0027] Among them, at least one processing circuit 11 of the server is connected to at least one peripheral interconnection link, and the at least one processing circuit 11 is used to: execute a reading engine, which reads the first hardware resource on the current peripheral interconnection link when the server is started; propagates the read data of the first hardware resource to the recognition engine, which recognizes the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifies the second hardware resource connected to each switch; propagates the identification result of the second hardware resource connected to each switch to the firmware of the corresponding switch, and the firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

[0028] The peripheral interconnection link of the embodiment of the present invention can be a PCI link; the processing circuit 11 is the circuit where the CPU processor is located, which can be controlled by issuing instructions through the BIOS (Basic Input Output System) or the operating system; the first hardware resource can include a peripheral interconnection device (PCI device), a switch, etc., and the switch can be a switch chip; a single-layer switch is connected to other devices without being connected to the switch; a multi-layer switch is a switch connected to at least another switch, which is a hierarchical structure; the second hardware resource can include PCI devices, peripheral interconnection ports (PCI ports), etc. The link connection of a single-layer switch is as follows: Figure 2As shown, the link connections of the multi-level switches are as follows Figure 3 shown.

[0029] As server functions continue to grow, the number of devices that need to be connected is increasing, such as multiple smart network cards, high-performance graphics cards, large-capacity storage devices, etc. However, due to the limited number of root ports of the server CPU's peripheral interconnection link, it is unable to accommodate more peripheral interconnection devices. Therefore, switches need to be introduced to expand the number of peripheral interconnection interfaces. The peripheral interconnection interfaces also need to be physically connected to the interconnection devices. In short, the server motherboard directly links multiple peripheral interconnection links, as well as multiple device links such as peripheral interconnection devices, switches, and peripheral interconnection ports linked on the links. The physical links of the server motherboard are as follows: Figure 4 As shown, these hardware resources all require reserved memory resources, so it takes too much time to allocate resources when the server starts, resulting in extended server startup time and low startup efficiency.

[0030] Therefore, the embodiment of the present invention can read the first hardware resource on the peripheral interconnection link when the server starts up. When the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, it identifies the second hardware resource connected to each switch, and propagates the identification result of the second hardware resource connected to each switch to the firmware FW of the corresponding switch. The firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource, and allocates resources to the second hardware resource connected to it through the firmware of the switch. The server does not need to read the resource allocation of each peripheral interconnection device in turn, but only needs to read the memory resource allocation set in the firmware of the switch. The memory resource allocation for the switch and the hardware resources connected to the switch is implemented through the firmware, thereby optimizing the startup time of the server and avoiding the reallocation of memory resources when the server starts up, thereby ensuring the fixity and stability of the memory resource allocation.

[0031] In addition, it should be noted that, in the embodiment of the present invention, the processing circuit 11 is controlled by BIOS during the startup phase of the server.

[0032] In an embodiment of the present invention, the firmware is used to: if the second hardware resource includes a peripheral interconnect device, allocate the first memory resource to the peripheral interconnect device according to the target setting of the firmware; if the second hardware resource includes a peripheral interconnect port, allocate the first memory resource to the peripheral interconnect port when the peripheral interconnect port needs to support a hot plug function.

[0033] Among them, the target setting is the memory resource allocation pre-set for the peripheral interconnection device in the switch firmware; the hot plug function is the Hotplug function, which allows the device to be connected or removed at any time while the server is running.

[0034] It can be understood that, when the second hardware resource includes a peripheral interconnection device, the embodiment of the present invention can allocate the first memory resource to the peripheral interconnection device according to the target setting of the firmware; when the second hardware resource includes a peripheral interconnection port and the peripheral interconnection port needs to support the hot plug function, the first memory resource is allocated to the peripheral interconnection port. Since the hot plug function allows the device to be connected or removed at any time when the server is running, the memory resource demand will change. Therefore, when the peripheral interconnection port needs to support the hot plug function, the embodiment of the present invention can allocate the first memory resource to the peripheral interconnection port, so that the memory resources can be dynamically allocated and managed according to the actual situation of the device, and resource conflicts with other devices can be avoided.

[0035] In an embodiment of the present invention, the allocation engine is configured to: when a peripheral interconnection port is connected to a current peripheral interconnection link, if the peripheral interconnection port is a target port, allocate the first memory resource to the peripheral interconnection port.

[0036] The target type is a specific type of PCI port, such as a connection port of a graphics card, a network card, or a storage controller. These ports have specific and immediate requirements for memory resources.

[0037] It can be understood that, in an embodiment of the present invention, when a target port is connected to the current peripheral interconnection link, the first memory resource is allocated to the peripheral interconnection port to avoid resource conflicts between other devices and the device connected to the port, thereby ensuring that the device connected to the target port can operate normally and stably.

[0038] Specifically, during the PCI enumeration phase, the BIOS continues to determine whether the current PCI link and the absence of a Switch chip are specific PCI ports (i.e., target ports). If it is a specific PCI port, 32-bit memory resources will be reserved. If it is not a specific PCI port and a PCI Switch chip exists, the BIOS will no longer enable the Hotplug function for the upstream and downstream ports of the Switch chip. The PCI device resource allocation for the upstream and downstream ports of the Switch chip is based on the settings in the Switch firmware FW. The BIOS only reads the actual memory resource size required by the upstream and downstream ports of the Switch chip and the PCI devices.

[0039] In an embodiment of the present invention, the at least one processing circuit 11 is configured to: if the first hardware resource includes a peripheral interconnect device, propagate the read data to the allocation engine, and the allocation engine allocates the first memory resource to the peripheral interconnect device.

[0040] It is understandable that, in an embodiment of the present invention, when the first hardware resource includes a peripheral interconnect device, the read data is propagated to the allocation engine, and the allocation engine allocates the first memory resource to the peripheral interconnect device, and normally allocates 32-bit resources to the peripheral interconnect device.

[0041] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a read engine, the read engine reads the identifier of the peripheral interconnect device; propagate the identifier of the peripheral interconnect device to an identification engine, the identification engine identifies whether the peripheral interconnect device is a data processor based on the identifier; and when the peripheral interconnect device is a data processor, the allocation engine allocates the first memory resource according to the resource size of the data processor.

[0042] The identifier is used to identify the type of the peripheral interconnection device, and the identifier can be DID (Device ID) and VID (Vendor ID).

[0043] Because a DPU (Data Processing Unit) typically has specific memory resource requirements, embodiments of the present invention can read the identifier of a peripheral interconnect device and use the identifier to identify whether the peripheral interconnect device is a DPU, so as to adopt different memory allocation strategies for the peripheral interconnect device. If the peripheral interconnect device is not a DPU, memory resources are allocated normally to it. If it is a DPU device, memory resources are allocated to the peripheral interconnect device based on the resource size of the DPU to ensure the normal operation of the DPU device.

[0044] It should be noted that DPU is a dedicated processor that provides data center infrastructure virtualization services such as network, storage, security, and management around data processing. It is a computing architecture composed of CPUs based on ARM / X86 architectures and dedicated hardware acceleration engines such as ASIC (Application Specific Integrated Circuit) / NP (Network Processor) / FPGA (Field Programmable Gate Array). It forms an entity that provides virtualization functions and requires sufficient resources to support complex service operations. Therefore, resources need to be reserved. The structure of DPU is as follows: Figure 5 As shown, DPU products have been widely used in various architecture servers in data centers (often in the form of smart network cards), including but not limited to X86 architecture and ARM architecture. However, no matter what architecture server, when using the smart network card, it is necessary to reserve resources for the smart network card in advance. This is because the smart network card contains many devices, such as network port devices, virtual network cards, storage devices SSD and other physical or virtual devices. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized. Therefore, it is necessary to reserve resources for the DPU in advance to ensure that various devices can obtain the required memory resources and operate normally.

[0045] Among them, whether it is a data processor is judged based on the identification, specifically, the DID and VID of the peripheral interconnection device can be identified. If the DID and VID exist in the pre-set data processor identification information list, the peripheral interconnection device is judged to be a data processor, otherwise it is not a data processor.

[0046] Specifically, when the server starts, the BIOS reads the DID and VID of each PCI device during the PCI enumeration phase of the DXE (Driver Execution Environment) phase to confirm whether the current device is a DPU device. If not, 32-bit memory resources are allocated normally. If it is a DPU device, 32-bit resources are reserved based on the known 32-bit resource size of the DPU. At the same time, the PCI link physically connected to the current DPU accumulates the MMIO (Memory-Mapped I / O) 32-bit resources reserved by the DPU when counting the 32-bit resources required by other PCI devices. At the same time, the BIOS enables the hot-plug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0047] For example, the server's CPU has multiple PCI links, among which PCI link A is connected to a DPU device and several other common PCI devices (including PCI device A and PCI device B). PCI link A has a PCI link bridge for connecting the CPU and the devices on PCI link A. Based on the existing 32-bit memory resource size of the DPU device, for example, 200MB of MIMO32 resources are reserved for it. At the same time, the 32-bit memory resources required by PCI device A and PCI device B on PCI link A are also counted. For example, PCI device A requires 30MB and PCI device B requires 15MB. Therefore, the total 32-bit memory resources required by PCI link A are 200+30+15=245MB.

[0048] In the embodiment of the present invention, the firmware sets a hot-swap function for the upstream and downstream ports of the switch to which the first memory resource has been allocated.

[0049] It can be understood that the firmware of the embodiment of the present invention sets a hot-swap function for the upstream and downstream ports of the switch to which the first memory resource has been allocated. By enabling the hot-swap function, the required memory resources are automatically allocated to the device when it is inserted, and these resources are automatically recovered when the device is unplugged, thereby realizing dynamic management of resources, improving resource utilization, and avoiding waste of resources.

[0050] For example, suppose a server has a switch chip (named Switch X) that is connected to multiple PCI devices, some of which need to support hot-swap functionality, including:

[0051] Downstream port 1 of Switch X is connected to a hot-swappable high-speed network interface card (NIC) device A, while downstream port 2 is connected to a standard storage device (non-hot-swappable). Switch X's upstream port connects to the upper-level PCI link, ultimately leading to the CPU. Device A requires 32MB of memory for packet caching and processing during normal operation.

[0052] The SwitchX FW reserves 32MB of memory in its memory resource allocation table for downlink port 1, where device A resides. This ensures stable memory resource support for device A during hot-swapping, whether it's being inserted or removed, preventing device malfunctions due to memory allocation issues.

[0053] At the same time, Switch X's firewall enables the Hotplug function for the PCI configuration space on downstream port 1. When device A is plugged into downstream port 1 on Switch X, the Hotplug function is triggered, and Switch X allocates the previously reserved 32MB of memory resources to device A according to pre-configured rules in the firewall. Switch X also reports device A's access information, including device type and required resources, to the system for appropriate configuration and management. When device A is unplugged, the Hotplug function on downstream port 1 notifies Switch X to reclaim the 32MB of memory allocated to device A and mark it as available for use by other devices.

[0054] In addition to the downstream ports, Switch X's firewall also enables the Hotplug function in the PCI configuration space of the upstream ports. When device A is inserted or removed, in addition to Switch X's own resource management, the Hotplug function on the upstream port transmits the hotplug event to the upper-level PCI link. Upon receiving this event, the upper-level link adjusts based on the overall system resource situation. For example, if the insertion of device A causes system memory resources to become scarce, the upper-level link may notify other devices to adjust resource usage appropriately or request more memory resources from the upper-level system to ensure stable operation of the entire system.

[0055] In the embodiment of the present invention, at least one processing circuit 11 is configured to start an allocation engine, where the allocation engine is a switch to which the first memory resource has been allocated, and a peripheral interconnection link to which the switch is located is configured with a hot-swap function.

[0056] It is understandable that the embodiment of the present invention can set a hot-swap function for the peripheral interconnection link of the switch to which the first memory resource has been allocated to achieve dynamic allocation and recycling of resources, improve the utilization rate of memory resources, and avoid waste of memory resources.

[0057] In addition, it should be noted that the hot-swap function of the peripheral interconnection link can only be set by the BIOS. Since the BIOS has the highest authority and priority in initializing and configuring hardware during the system startup process, only the BIOS can enable the hot-swap function of the PCI link bridge. This ensures that the hot-swap function is correctly initialized when the system starts and works in coordination with other parts of the system to avoid compatibility issues or system failures.

[0058] In the embodiment of the present invention, at least one processing circuit 11 is configured to execute a startup engine when the identification engine polls all peripheral interconnection links, the first hardware resource, and the second hardware resource, and the startup engine starts the operating system of the server.

[0059] It is understandable that, in the embodiment of the present invention, when the identification engine polls all peripheral interconnection links, the first hardware resources and the second hardware resources, it executes the startup engine, starts the operating system of the server, and enters the next stage of memory resource allocation.

[0060] In summary, the process of allocating the first memory resource when the server is started, ie, in the startup phase, in the embodiment of the present invention is as follows.

[0061] 1. When the server starts, the BIOS reads the DID and VID of each PCI device during the PCI enumeration phase of the DXE phase to confirm whether the current device is a DPU device. If not, 32-bit memory resources are allocated normally. If it is a DPU device, 32-bit resources are reserved based on the known 32-bit resource size of the DPU. At the same time, the PCI link physically connected to the current DPU accumulates the MMIO 32-bit resources reserved by the DPU when counting the 32-bit resources required by other PCI devices. At the same time, the BIOS enables the hot-plug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0062] 2. During the PCI enumeration phase, the BIOS continues to determine whether the current PCI link and the absence of a switch chip are specific PCI ports. If so, 32-bit memory resources will be reserved. If not and a PCI switch chip is present, the BIOS will no longer enable the Hotplug function for the upstream and downstream ports of the switch chip. The PCI device resource allocation for the upstream and downstream ports of the switch chip is based on the settings in the switch firmware. The BIOS only reads the actual memory resource size required by the upstream and downstream ports of the switch chip and the PCI devices. At the same time, the BIOS will enable the Hotplug function in the PCI configuration space of the PCI link of the switch chip scanned during the PCI enumeration phase of DXE, because the PCI link bridge can only be enabled by the BIOS.

[0063] 3. The switch chip's firmware reserves memory resources for the PCI ports that need to support hot-swap functionality. At the same time, enable the Hotplug function in the PCI configuration space of the upstream and downstream ports of the switch chip where the memory resources are reserved. All switch chips in the server should reserve resources and enable the Hotplug function in this way.

[0064] 4. According to steps 1 and 2, all PCI link bridges and the switch chips and their devices under the corresponding PCI link bridges are polled in sequence. After polling all the PCI links and switch chips of the CPU, continue to boot and enter the operating system.

[0065] The embodiments of the present invention can flexibly adapt to the memory resource requirements of different types of peripheral interconnection devices, switches, and peripheral interconnection ports, avoiding insufficient memory resource allocation for devices that may cause the devices to be unable to be used normally, while improving the utilization rate of memory resources, avoiding waste of memory resources, and thereby improving the overall performance and stability of the server.

[0066] For example, assume that a server currently has two CPUs, CPU1 and CPU2. Each CPU is connected to multiple PCI links, each of which is connected to different devices and switch chips. Device A (a non-DPU) and device B (a DPU) are connected to PCI link 1 of CPU1. Port A exists, and the downstream port of switch chip 1 on link 1 is connected to devices C and D. The firmware setting specifies that device C requires 16 MB of memory and device D requires 8 MB of memory. Device C supports hot swapping. Perform the following steps:

[0067] 1. The server boots up, and the BIOS enters the PCI enumeration (DXE) phase. The BIOS reads the DID and VID of device A, confirms it's not a DPU, and allocates 32-bit memory resources to it as normal. It then reads the DID and VID of device B, confirms it's a DPU, and, assuming it requires 32MB of 32-bit memory, reserves it. Simultaneously, when Link 1 calculates the resource requirements of other devices, it adds the 32MB reserved by Device B. The BIOS also enables the Hotplug feature in the PCI configuration space of the bridge that physically connects Device B.

[0068] 2. If link 1 does not have a switch chip and has PCI port A, the BIOS reserves 32 bits of memory for port A. If link 1 does have switch chip 1, the BIOS does not enable the Hotplug function for Switch 1's upstream and downstream ports. Instead, it reads Switch 1's firmware to obtain the actual memory resource requirements for its upstream and downstream ports and the connected PCI devices. For example, if Switch 0's downstream ports are connected to devices C and D, the firmware specifies that device C requires 16MB of memory and device D requires 8MB of memory. The BIOS records this information and also enables the Hotplug function in the PCI configuration space of the PCI link where Switch 1 is located.

[0069] 3. Switch1's FW reserves memory resources for its PCI ports that need to support hot plugging. Assume that device C, connected to downstream port 1 of Switch1, supports hot plugging. The FW reserves 16MB of memory for it and enables the hot plug function in the PCI configuration space of downstream port 1 and upstream port. All switch chips in the server, such as Switch1 and Switch2, follow this method.

[0070] 4. Check all PCI link bridges, switch chips, and their devices on CPUs 1 and 2. For example, check PCI link 2 on CPU 1 and repeat the above steps for device identification, resource reservation, and hot-swap function settings. After completing the polling of all CPU PCI links and switch chips, the server continues booting and enters the operating system.

[0071] In an embodiment of the present invention, at least one processing circuit 11 is used to: after the server enters the operating system, execute a reading engine, the reading engine reads the memory allocation function of the server; and an allocation engine reallocates the first memory resource of the server according to the memory allocation function.

[0072] The memory allocation function is used to determine whether resources need to be reallocated. The memory allocation function can be identified through the Grub parameter of the operating system, which is PCI=realloc.

[0073] Since resource requirements of a server may change when it enters the operating system, the embodiment of the present invention reads the memory allocation function of the server after the server enters the operating system to determine whether the first memory resource needs to be reallocated.

[0074] In addition, it should be noted that, in the embodiment of the present invention, the processing circuit when the server enters the operating system stage may be the operating system, that is, all operations in the operating system stage are executed by the BIOS.

[0075] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a reading engine before reallocating the first memory resources of the server according to the memory allocation function, wherein the reading engine reads the reallocation requirements of the server; and an allocation engine reallocates the first memory resources of the server according to the reallocation requirements and the memory allocation function.

[0076] It is understandable that the embodiment of the present invention can determine whether the first memory resource of the server needs to be reallocated based on the reallocation requirement and the memory allocation function.

[0077] In an embodiment of the present invention, if the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

[0078] It is understandable that the embodiment of the present invention deletes the memory allocation function when no reallocation request from the server is read, so that memory resources are not reallocated when the server enters the operating system, and the allocation parameters of the first memory resource in the server startup phase are retained.

[0079] Specifically, when the server enters the operating system, the Grub interface of the operating system adds the PCI=realloc parameter to the Grub parameters by default. If the system does not need to reallocate the memory resources allocated by the BIOS at this time, this parameter will be removed from the Grub file; if the memory resources allocated by the BIOS need to be reallocated at this time, this parameter will be retained, and the operating system will reallocate all PCI resources of the server.

[0080] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a scanning engine, the scanning engine scans all peripheral interconnection links of the server; propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, and if the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are recognized, the hot plug function is enabled, and the first memory resource allocated to the current peripheral interconnection link during the server startup phase is reserved.

[0081] It can be understood that the embodiment of the present invention can execute a scanning engine, propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, and when it recognizes the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link, turns on the hot plug function, indicating that the device may change dynamically, then retains the first memory resource allocated by the current peripheral interconnection link during the server startup phase to ensure that the device can work normally when it is connected or removed, and reasonably allocates memory resources.

[0082] In an embodiment of the present invention, the identification engine is used to: if the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are identified, turn off the hot plug function, and allocate the engine to reallocate the first memory resource of the server according to the memory allocation function.

[0083] It can be understood that when the embodiment of the present invention identifies that the hot-swap function of the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, or the switch connected to the current peripheral interconnection link is turned off, the first memory resource that has been allocated when the server is started or the device to which the first memory resource cannot be allocated is reallocated to achieve flexible allocation of memory resources to adapt to new memory resource allocation requirements.

[0084] In the embodiment of the present invention, the identification engine is configured to stop allocating the first memory resource of the server if it is identified that the current peripheral interconnection link is idle, or the switch connected to the current peripheral interconnection link is idle.

[0085] It can be understood that, in the embodiment of the present invention, when the current peripheral interconnection link space or the switch connected to the current peripheral interconnection link is idle, the first memory resources of the server are stopped from being allocated, and these resources are reserved for other more needed tasks or processes, thereby improving the overall utilization of memory resources and enabling the server to run more efficiently.

[0086] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a scanning engine, the scanning engine scans the current peripheral interconnection link level; propagate the scanning data of the scanning engine to the recognition engine, the recognition engine recognizes the scanning data, if the current peripheral interconnection link level is N, then the number of reallocations of the first memory resource is N+1; the allocation engine allocates the first memory resource according to the number of reallocations.

[0087] Since the server's peripheral interconnection links may have a multi-layer structure, such as Figure 4As shown, the embodiment of the present invention can scan the current peripheral interconnection link level. If a data switch is physically connected during the scanning process, the scanning is continued until all data switches of all levels are scanned and the final number of levels is counted. If the number of levels is N, the number of times resources are reallocated is counted as N + 1. After the scanning of the levels is completed, resources are reallocated for the scanned levels. The statistical number of levels and the number of reallocations can provide a basis for subsequent resource reallocation to ensure the accuracy of resource reallocation.

[0088] In an embodiment of the present invention, at least one processing circuit 11 is used to: execute a reading engine, the reading engine reads the second memory resources of the server; propagate the remaining resources of the second memory resources to the recognition engine, the recognition engine identifies whether the remaining resources are less than the resource threshold; propagate the recognition result of the recognition engine to the allocation engine, and the allocation engine stops the allocation of the first memory resources of the hardware resources of the current level or the next level when the remaining resources are less than the resource threshold.

[0089] The resource threshold may be set according to specific circumstances, such as 4G.

[0090] It can be understood that the embodiment of the present invention can identify the second memory resource to optimize the allocation of the first memory resource. When the remaining resources of the second memory resource are less than the resource threshold, it indicates that the current memory resources are insufficient, and the allocation of the first memory resource of the hardware resources of the current level or the next level is stopped to improve the rationality and effectiveness of the memory resource allocation.

[0091] In an embodiment of the present invention, the allocation engine is used to: if any firmware of the multi-level switch does not support the hot-swap function, reallocate the first memory resource of the peripheral interconnection link where the firmware that does not support the hot-swap function is located; if all firmware of the multi-level switch supports the hot-swap function, retain the allocation parameters of the first memory resource in the server startup phase.

[0092] It can be understood that, in the embodiment of the present invention, if any firmware of the multi-level switch does not support the hot-swap function, the first memory resource of the peripheral interconnection link where the firmware that does not support the hot-swap function is located is reallocated, so that the memory resource is better adapted to the link that does not support hot-swap, avoiding problems caused by the mismatch between the hot-swap-related resource allocation and the actual hardware capabilities, and making the memory resource allocation more reasonable, releasing part of the memory resources originally reserved for the hot-swap function and using them for other places that are more needed, thereby improving the overall utilization efficiency of the memory resources; when all the firmware of the multi-level switch supports the hot-swap function, the allocation parameters of the first memory resource in the server startup phase are retained to more flexibly adapt to the dynamic changes of the device, and can avoid system performance fluctuations or configuration errors that may be caused by frequent adjustments to memory allocation, thereby maintaining the overall performance and stability of the server.

[0093] Specifically, the embodiments of the present invention can perform detailed resource reallocation based on the device conditions and hot-swap function status of each layer, thereby improving the rationality and effectiveness of resource allocation and avoiding resource conflicts and uneven resource allocation among devices at multiple layers. Specifically:

[0094] The purpose of resource allocation is to provide memory resources for connected peripheral interconnection devices to support their operation. Therefore, if there is no peripheral interconnection device under the peripheral interconnection link of the current level, it is meaningless to allocate memory resources to the peripheral interconnection link, which will cause resource waste. Therefore, no resource allocation is performed on the bridge of the current level, or the hot plug function of the data switch is turned off, indicating that there will be no device insertion or removal operation of the current data switch. The first memory resources reserved in the startup phase will not be used due to the connection or removal of the device. Therefore, the reserved first memory resources are released for subsequent allocation to other devices to improve resource utilization.

[0095] If there are peripheral interconnection devices under the peripheral interconnection link of the current level, resources will be allocated to the peripheral interconnection devices to ensure the normal operation of these devices. If the hot plug function of the data switch bridge is enabled, it indicates that devices may be connected or removed. Therefore, resources will not be allocated to the peripheral interconnection devices. The resources set at the server startup stage will be used to avoid device failure or data loss caused by reallocation of resources.

[0096] If there are peripheral interconnection devices and devices at the next level under the peripheral interconnection link of the current level, resources are allocated to the peripheral interconnection devices to ensure normal operation of the devices. It is also determined whether there are peripheral interconnection devices on the peripheral interconnection link of the next level to further determine whether resources need to be allocated to the devices at the next level, thereby achieving reasonable resource allocation for the entire hierarchical structure.

[0097] If the peripheral interconnection link of the next level is not connected to a peripheral interconnection device and the hot plug function is turned off, it means that no new device will be connected or removed, so there is no need to allocate resources for the bridge to avoid resource waste. If the peripheral interconnection link of the next level has peripheral interconnection devices, in order to ensure the normal operation of these devices, memory resources need to be allocated to them to meet the operation requirements of the devices. Or if the hot plug function of the next level is turned on, it indicates that there may be a device insertion or removal operation, so there is no need to reallocate the first memory resources.

[0098] After allocating and judging resources for peripheral interconnection links and devices at all levels, when the resource reallocation of the N+1 layer is completed, it indicates that the resource allocation work of the entire server system has been completed. Ending resource allocation can allow the system to enter a stable operating state, avoid unnecessary resource allocation operations, and improve system efficiency and stability.

[0099] Specifically, the specific operations of the embodiment of the present invention after the server enters the operating system are as follows:

[0100] 1. When the server enters the operating system, the operating system's Grub interface adds the PCI=realloc parameter to the Grub parameters by default. If the system does not need to reallocate the memory resources allocated by the BIOS, remove this parameter from the Grub file. If the system needs to reallocate the memory resources allocated by the BIOS, retain this parameter. The operating system will reallocate all PCI resources of the server. When the system driver scans the PCI bridge and the Switch chip under the PCI bridge and the PCI configuration space of the downstream port of the Switch chip, the Hotplug function is turned on. The resources reserved for this device during BIOS startup are retained. If the Hotplug function of the PCI configuration space of the PCI bridge, the Switch chip under the PCI bridge, and the downstream port of the Switch chip is disabled, the operating system will reallocate the resources that the BIOS has allocated during the DXE phase or the devices to which 32-bit memory resources cannot be allocated. If there are no devices on the PCI bridge or Switch chip and the downstream port of the Switch chip in the PCI link and the Hotplug function is disabled, there is no need to allocate 32-bit memory resources. In this way, the PCI devices under the system can normally obtain 32-bit memory resources and meet the conditions for use under special requirements.

[0101] 2. When reallocating resources under the operating system, it is necessary to scan the PCI bridge device of each PCI link. Here, only one PCI link is used as an example to illustrate.

[0102] First, scan the current PCI link layer. If a Switch physical connection appears during the scanning process, continue scanning until all layers of the Switch chip are scanned and the final number of layers is counted. If the number of layers is N, the number of times the resources are reallocated is counted as N+1. After the scanning is completed, the system reallocates resources for the scanned layers. If there is no PCI terminal device under the bridge of the first layer, the bridge will not be allocated resources or the Hotplug function is not enabled, the reserved resources will be released. If there is a PCI terminal device under the bridge of the first layer, the terminal device will be allocated resources. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not reallocate resources to this PCI device. Resource allocation can be used according to the resource size set when the BIOS is started; if there is a PCI terminal device under the first-level bridge and a lower-level bridge device, resources need to be allocated to the PCI terminal device and it is determined whether there is a PCI terminal device on the next-level bridge. If there is no terminal device on the next-level bridge and the Hotplug function of the PCI configuration space of the next-level bridge is turned off, no resources need to be allocated to this bridge. If there is a PCI terminal device under the next-level bridge, resources are allocated to the next-level bridge or the Hotplug function of the lower-level bridge is enabled. There is no need for the system to reallocate resources for this switch. It can be used according to the memory resources allocated when the BIOS is started. N+1 layers of resource allocation are performed in this way until 32-bit resource allocation is completed.

[0103] When all PCI device resource allocations for the server are completed, if the 4G memory resources meet the needs of all current PCI devices, there is no problem. If the 4G memory resources are insufficient, 32-bit memory resources will be allocated to the PCI devices identified at the current level. If there are no memory resources to allocate, no resources will be allocated to the remaining PCI devices at the current level or the Switch bridge chips and PCI devices at the next level. If the Switch chip FW of any node in the FW of the multi-level Switch chips of the PCI link does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If the FW of each Switch chip level in the FW of the multi-level Switch chips of the PCI link supports the Hotplug function, resources will be reserved according to the resource size allocated by the BIOS when the server is started, and no resource reallocation will be performed.

[0104] For example, suppose a server has a CPU connected to two PCI links (Link A and Link B). Link A consists of a PCI bridge, connected to a switch chip (Switch A). Switch A's downstream ports are connected to three PCI end devices (Device A1, Device A2, and Device A3). Link B consists of a PCI bridge, connected to two switch chips (Switch B1 and Switch B2). Switch B1's downstream port is connected to Device C1, and Switch C2's downstream port is connected to Devices D1 and D3.

[0105] When the server boots, the BIOS enumerates PCI devices and allocates resources during the DXE phase. 32-bit memory resources are allocated to devices on Link A and Link B, and the Hotplug feature is enabled for some devices and bridges. For example, 512MB of resources are reserved for device A1, 256MB for device A2, and 128MB for device A3; 384MB for device B1, 256MB for device B2, and 192MB for device B3. Hotplug is also enabled for the PCI bridge on Link A and the upstream and downstream ports of Switch A. Hotplug is also enabled for the PCI bridge on Link B and the upstream and downstream ports of Switch B1 and Switch B2.

[0106] When the server boots into the operating system, the PCI=realloc parameter is added to the Grub interface by default. If you want the system to reallocate the memory resources allocated by the BIOS, retain this parameter.

[0107] The system driver scans the PCI bridge of link A and finds that the Hotplug function of the PCI configuration space of Switch A and its downstream ports is enabled. Therefore, the resources reserved for devices A1, A2, and A3 during BIOS startup are retained and not reallocated. If, during the scanning process, it is found that the Hotplug function of the PCI configuration space of a downstream port of Switch B2 is disabled, the operating system will reallocate the resources on link B that the BIOS has already allocated during the DXE phase or the devices to which 32-bit memory resources cannot be allocated.

[0108] The system scans the layers of link B and finds two layers of switch chips (Switch B1 and Switch B2). Therefore, the number of layers N = 2, and the number of resource reallocations is counted as N + 1 = 3 times.

[0109] First allocation (first layer: PCI bridge): Link B's PCI bridge has two lower-level bridge devices, Switch B1 and Switch B2, so no resources are allocated to the PCI bridge.

[0110] Second allocation (second layer: Switch B1 and Switch B2): Switch B1 has PCI terminal device C1 under it, and resources are allocated to device C1. Because Switch B1's Hotplug function is enabled, the operating system does not reallocate Switch B1's resources and uses them according to the resource size allocated during BIOS startup.

[0111] Third allocation (third layer: no more lower-level bridges): Since it has reached the last layer and there are no more lower-level bridges, resource allocation is completed for devices B2 and B3.

[0112] Assume that the total 32-bit memory resources required by all PCI devices exceed 4GB. When allocating resources for Link B, after allocating resources for devices C1 and D1, insufficient memory resources remain for device D2. Therefore, no resources are allocated to device D3. Assume that the FW on Switch B1 supports Hotplug, but the FW on Switch B2 does not. The system layer will reallocate resources for Link B. If both the FWs on Switch B1 and Switch B2 support Hotplug, resources are reserved based on the BIOS allocation at server startup, and no resource reallocation is performed.

[0113] In general, because smart network card devices require 32-bit memory addresses and the server's 32-bit memory address resources are limited with a maximum capacity of 4GB, it is necessary to reserve resources for the smart network card in advance. At the same time, because the CPU's PCI link has a limited number of root ports and cannot accommodate more PCI devices, a switch chip is introduced to expand the number of PCI interfaces. However, the expanded PCI interface also requires physical connection to a PCI device, which also requires resource reservation. Therefore, the present invention reserves resources by identifying the PCI interface or a fixed PCI interface with no connected devices during server startup through the BIOS. At the same time, the Hotplug function of the switch chip and the PCI link bridge where the switch chip is located must be enabled. For unused switch chips that do not require a special fixed PCI interface, there is no need to reserve resources or set up Hotplug settings. Simply enable or disable the Hotplug function of the switch chip and the PCI link bridge where the switch chip is located.

[0114] When the server starts, the operating system will also allocate resources to all devices on the server. Resource allocation includes both reserved resources and currently identified device resource allocation. If there are too many devices when the current device starts, some device resources will not be effectively allocated. That is, 4G 32-bit resources cannot meet the total device demand exceeding the 4G limit, which will cause some devices to be unusable. If the PCI link devices of the current server are all directly connected to the PCI end bridge port of the CPU, there is no need to worry about insufficient 4G resources. However, if the PCI link passes through multiple levels of Switch chips or multiple PCI root bridges connect multiple PCI Switches, insufficient Switch resource reservation will occur, which will cause the devices under the system to not work properly, especially DPUs and devices that need to support hot-swap functions. In order to solve the problem that DPU devices or hot-swappable devices cannot be used in the system due to excessive resource reservation, the present invention implements the problem of reallocating resources in the system by adding the pci=realloc parameter to the Grub file when the system is started. At the same time, if the Hotplug function of the Switch bridge and the Rootport of the PCI link where it is located is enabled, no memory resources are reallocated. If the Hotplug function of the Switch bridge and the Rootport of the PCI link where it is located is disabled, all memory resources are reallocated to ensure the rational use of memory resources. In this way, when the server starts and enters the operating system, the system will reallocate the MMIO32 memory resources of the entire PCI link of the server according to the disablement status of the Hotplug function attribute of the PCI link and the Grub parameter setting.

[0115] However, when there are too many switch chips in the PCI link, the BIOS will spend too much time allocating resources when the server starts. In this case, in order to optimize the server startup time and ensure that the resource allocation of each switch chip is fixed, the present invention sets the resources and hotplug function of the switch chip in the FW of the switch chip. During startup, the BIOS only needs to read the resource size allocated by the switch chip and does not need to reserve resources and set the hotplug function for the switch chip and the downstream PCI port again. However, the hotplug function of the PCI link needs to be enabled in the BIOS startup setting.

[0116] According to the multi-layer switch firmware combined memory resource allocation system 10 proposed in an embodiment of the present invention, the first hardware resource on the peripheral interconnection link can be read when the server is started. When the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, the second hardware resource connected to each switch is identified, and the identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. Based on the identification result of the second hardware resource, the firmware allocates the first memory resource to the switch and the second hardware resource, and allocates resources for the second hardware resource connected to it through the firmware of the data switch. There is no need for the system to read the resource allocation of each peripheral interconnection device in turn, and it is only necessary to read the memory resource allocation set in the firmware of the switch. The memory resource allocation for the switch and the hardware resources connected to the switch is implemented through the firmware, thereby optimizing the startup time of the server and avoiding the reallocation of memory resources when the server starts, thereby ensuring the stability and stability of the memory resource allocation.

[0117] An embodiment of the present invention further provides a server comprising the above-mentioned multi-level switch firmware combined with memory resource allocation system.

[0118] An embodiment of the present invention also provides a method for allocating memory resources by combining firmware of a multi-level switch.

[0119] like Figure 6 As shown, the method for allocating memory resources by combining multi-level switch firmware includes the following steps:

[0120] In step S101, at least one processing circuit connected to at least one peripheral interconnect link is used, wherein the at least one processing circuit is used to: execute a read engine, the read engine reading a first hardware resource on the current peripheral interconnect link when the server is started;

[0121] It can be understood that the embodiment of the present invention can use at least one processing circuit connected to at least one peripheral interconnection link, and the at least one processing circuit is used to execute a read engine. The read engine reads the first hardware resource on the current peripheral interconnection link when the server starts, so as to subsequently allocate memory resources.

[0122] In step S102, the read data of the first hardware resource is propagated to the recognition engine, which recognizes the read data and, if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, recognizes the second hardware resource connected to each switch.

[0123] It can be understood that the embodiment of the present invention can propagate the read data of the first hardware resource to the recognition engine, and the recognition engine recognizes the read data. If the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, the second hardware resource connected to each switch is recognized to achieve reasonable memory resource allocation when a switch exists in the peripheral interconnection link.

[0124] In step S103, the identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch, and the firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

[0125] It can be understood that the embodiment of the present invention can identify the second hardware resource connected to each switch, and propagate the identification result of the second hardware resource connected to each switch to the firmware of the corresponding switch. The firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource, and allocates resources for the second hardware resource connected to it through the firmware of the data switch. There is no need for the system to read the resource allocation of each peripheral interconnection device in turn, but only needs to read the memory resource allocation set in the firmware of the switch. The memory resource allocation for the switch and the hardware resources connected to the switch is implemented through the firmware, thereby optimizing the startup time of the server and avoiding the reallocation of memory resources when the server starts, thereby ensuring the fixity and stability of the memory resource allocation.

[0126] It should be noted that the description of the features in the embodiment corresponding to the method of multi-level switch firmware combined memory resource allocation can be found in the relevant description of the embodiment corresponding to the system of multi-level switch firmware combined memory resource allocation, which will not be repeated here.

[0127] According to the method for allocating memory resources of a multi-layer switch firmware combination proposed in an embodiment of the present invention, the first hardware resource on the peripheral interconnection link can be read when the server is started. When the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, the second hardware resource connected to each switch is identified, and the identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch. The firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource, and allocates resources to the second hardware resource connected to it through the firmware of the data switch. The server does not need to read the resource allocation of each peripheral interconnection device in turn, but only needs to read the memory resource allocation set in the switch firmware. The memory resource allocation for the switch and the hardware resources connected to the switch is implemented through the firmware, thereby optimizing the startup time of the server and avoiding the reallocation of memory resources when the server starts, thereby ensuring the stability and stability of the memory resource allocation.

[0128] The following describes a process of memory resource allocation in a multi-layer switch firmware combination according to an embodiment of the present invention through a specific embodiment. The BIOS or operating system controls the processing circuit, and the processing circuit performs specific operations, including:

[0129] 1. Server startup phase.

[0130] During the server startup phase, the execution connection relationship between the various components of the multi-level switch firmware combination memory resource allocation system is as follows: Figure 7 As shown, the BIOS controls the processing circuit during the server startup phase, which is equivalent to the BIOS executing the memory resource allocation operation during the server startup phase, specifically: executing the reading engine to read the first hardware resource (including peripheral interconnection devices, single-layer switches, multi-layer switches, etc.), the second hardware resource connected to the switch (including peripheral interconnection ports, peripheral interconnection devices, etc.), and the identifier of the peripheral interconnection device; the recognition engine receives the data read by the reading engine, generates a corresponding recognition result, and transmits the recognition result to the allocation engine and the firmware; the allocation engine allocates the first memory resource to the peripheral interconnection device, the peripheral interconnection port, etc. according to the recognition result of the first hardware resource and sets the hot-swap function, and the firmware allocates the first memory resource to the corresponding switch and the second hardware resource connected to the switch according to the recognition result of the switch in the first hardware resource and sets the hot-swap function; after the first memory resource allocation is completed, the startup engine is executed, and the startup engine starts the server's operating system.

[0131] The following combination Figure 7 The execution connection relationship diagram between the various components in the startup phase is used to describe the specific execution process of memory resource allocation in the server startup phase. The process is as follows Figure 8 As shown, including:

[0132] 1. When the server starts, the BIOS reads the DID and VID of each PCI device during the PCI enumeration phase of the DXE phase to confirm whether the current device is a DPU device. If not, 32-bit memory resources are normally allocated. If it is a DPU device, 32-bit resources are reserved based on the known 32-bit resource size of the DPU. At the same time, the PCI link physically connected to the current DPU accumulates the MMIO 32-bit resources reserved by the DPU when counting the 32-bit resources required by other PCI devices. At the same time, the BIOS enables the hot-plug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0133] 2. During the PCI enumeration phase, the BIOS continues to determine whether the current PCI link and the absence of a Switch chip are specific PCI ports. If so, 32-bit memory resources will be reserved. If not and a PCI Switch chip exists, the BIOS will no longer enable the Hotplug function for the upstream and downstream ports of the Switch chip. The PCI device resource allocation for the upstream and downstream ports of the Switch chip will be based on the settings in the Switch FW. The BIOS only reads the actual memory resource size required by the upstream and downstream ports of the Switch chip and the PCI devices. At the same time, the BIOS will enable the Hotplug function in the PCI configuration space of the PCI link of the Switch chip scanned during the PCI enumeration phase of DXE, because the PCI link bridge can only be enabled by the BIOS.

[0134] After the BIOS determines that a Switch chip exists in the PCI link, the process of reading the FW firmware parameter settings of the Switch chip is as follows: Figure 9 As shown in the figure, the BIOS reads the actual memory resource size required by the upstream and downstream ports and PCI devices of the switch chip. At the same time, the BIOS enables the Hotplug function in the PCI configuration space of the PCI link of the switch chip scanned during the PCI enumeration phase of the DXE. The switch chip's firmware reserves the memory resource size for the PCI ports on the switch that need to support hot plugging. At the same time, the Hotplug function is enabled in the PCI configuration space of the upstream and downstream ports of the switch chip for reserved memory resources. All switch chips in the server use this method to reserve resources and enable the Hotplug function.

[0135] 3. According to steps 1 and 2, all PCI links and the switch chips and their devices under the corresponding PCI links are polled in sequence. After polling all the PCI links and switch chips of the CPU, continue to boot and enter the operating system.

[0136] 2. The server enters the operating system stage.

[0137] The server enters the operating system stage. The execution connection relationship between the various components of the multi-level switch firmware combination memory resource allocation system is as follows: Figure 10As shown, the operating system control processing circuit of the server is equivalent to the server entering the operating system stage and the operating system performs the reallocation of the first memory resources, specifically: the execution reading engine reads the memory allocation function of the server and reads whether there is a memory resource reallocation demand; the allocation engine reads the result according to the memory resource reallocation demand transmitted by the reading engine, executes the deletion operation of the memory allocation function (that is, does not reallocate memory resources) or reallocates the first memory resource; after identifying the reallocation first memory resource instruction, executes the scanning engine, the scanning engine is used for the hierarchical structure of the peripheral interconnection link, hardware resources, hot plug function settings, etc., and transmits the scan data to the recognition engine; the recognition engine is used to identify the scan data and transmit it to the allocation engine; the allocation engine reallocates the first memory resource.

[0138] The following combination Figure 10 The execution connection relationship diagram between the various components in the startup phase is used to describe the specific execution process of memory resource allocation when the server enters the operating system phase. The process is as follows Figure 11 As shown, including:

[0139] 1. When the server enters the operating system, the operating system's Grub interface adds the PCI=realloc parameter to the Grub parameters by default. If the system does not need to reallocate the memory resources allocated by the BIOS, remove this parameter from the Grub file. If the system needs to reallocate the memory resources allocated by the BIOS, retain this parameter. The operating system will reallocate all PCI resources of the server. When the system driver scans the PCI bridge and the Switch chip under the PCI bridge and the PCI configuration space of the downstream port of the Switch chip, the Hotplug function is turned on. This device reserves resources during BIOS startup. If the Hotplug function is disabled for the PCI configuration space of the PCI bridge, the switch chip under the PCI bridge, and the downstream ports of the switch chip, the operating system will reallocate the resources already allocated by the BIOS during the DXE phase or the devices to which 32-bit memory resources cannot be allocated. If there are no devices on the PCI bridge or the switch chip and the downstream ports of the switch chip in the PCI link and the Hotplug function is disabled, no 32-bit memory resources need to be allocated. This ensures that PCI devices in the system can normally obtain 32-bit memory resources and meet the conditions for use under special requirements.

[0140] 2. When reallocating resources under the operating system, the PCI bridge device of each PCI link needs to be scanned. Here, only one PCI link is used as an example. First, the current PCI link layer is scanned. If a physical switch connection is found during the scanning process, the scanning continues until all layers of switch chips are scanned. The final number of layers is counted. If the number of layers is N, the number of resource reallocations is counted as N+1. After the scanning of the layers is completed, the system reallocates resources to the scanned layers. If there is no PCI terminal device under the bridge of the first layer, no resources are allocated to this bridge. If the Hotplug function is not enabled, the reserved resources are released.

[0141] If there is a PCI terminal device under the first-level bridge, resources will be allocated to this terminal device. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not allocate resources to this PCI device and will use the resources according to the size set during BIOS startup.

[0142] If there is a PCI terminal device under the first-level bridge and a lower-level bridge device, resources need to be allocated to the PCI terminal device and it is determined whether there is a PCI terminal device on the next-level bridge. If there is no terminal device on the next-level bridge and the Hotplug function of the PCI configuration space of the next-level bridge is disabled, then no resources need to be allocated to this bridge. If there is a PCI terminal device under the next-level bridge, resources are allocated to the next-level bridge or the Hotplug function of the next-level bridge is enabled. There is no need for the system to reallocate resources for this switch. The memory resources allocated during BIOS startup can be used. This N+1 layer resource allocation is repeated until 32-bit resource allocation is completed.

[0143] When all PCI device resource allocations for the server are completed, if the 4G memory resources meet the needs of all current PCI devices, there is no problem. If the 4G memory resources are insufficient, 32-bit memory resources will be allocated to the PCI devices identified at the current level. If there are no memory resources to allocate, no resources will be allocated to the remaining PCI devices at the current level or the Switch bridge chips and PCI devices at the next level. If the Switch chip FW of any node in the FW of the multi-level Switch chips of the PCI link does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If the FW of each Switch chip level in the FW of the multi-level Switch chips of the PCI link supports the Hotplug function, resources will be reserved according to the resource size allocated by the BIOS when the server is started, and no resource reallocation will be performed.

[0144] In summary, the multi-level switch firmware combined memory resource allocation method of the present invention utilizes BIOS to determine whether the switch chip of the PCI link exists when the server starts. If not, the PCI device of the PCI link is directly determined, especially the DPU or a specific PCI device is actively identified, and the Hotplug function is set to be enabled in the PCI configuration space of the bridge of the PCI link where the DPU and the specific device are located. For normally identified PCI devices, resources are allocated in a normal mode and the Hotplug function of the PCI link is disabled. However, resources are reserved for specific ports of the PCI link and the Hotplug function of the PCI link is enabled. No resources are allocated to other PCI links and the Hotplug function of the corresponding PCI links is disabled. When a PCI link switch chip exists, the downstream port of the switch chip is determined to determine whether resources need to be reserved to support the hot plug function in the system and no PCI device exists, or whether a PCI device exists on the downstream port.

[0145] When the above two situations occur, the Hotplug function of the upstream and downstream ports of the Switch chip and the PCI configuration space of the PCI link bridge will be enabled. If there is no special requirement, the Hotplug function of the Switch chip will be disabled to facilitate resource reallocation under the system. In this way, the PCI devices of other PCI link bridges will be trained in turn until all are completed and started to enter the operating system interface.

[0146] Since the above operations are performed by the BIOS, they affect the server startup time and cannot be guaranteed to be accurate when there are too many switch chips. Therefore, if a PCI switch chip is present, the BIOS will directly read the switch chip firmware to read and allocate the memory resource size of each upstream and downstream port. Because the upstream and downstream ports of the switch chip firmware have been set to Hotplug enabled and are managed by the switch chip firmware, the BIOS does not need to set the Hotplug function of the upstream and downstream ports of the switch chip. The BIOS only needs to enable the Hotplug function of the PCI link bridge where the switch chip is located. This method is convenient and fast, and improves resource allocation efficiency.

[0147] After the server enters the operating system, if the system does not need to reallocate memory resources, remove the PCI=realloc parameter. If necessary, use the default setting and set the PCI=realloc parameter in the Grub parameters. The operating system will then reallocate memory resources. Even if the BIOS has already allocated memory resources, such as 32-bit memory resources, the system will still reallocate memory resources. Because memory resources are limited and the location information of the DPU and specific PCI devices cannot be fixed, according to the parameter function, PCI devices identified later may have no resources to allocate because memory resources have already been allocated. However, PCI links with the Hotplug function enabled do not require memory resource reallocation.

[0148] At the same time, the system will scan the Switch level. If there are N-level Switch chips, the Switch chip will be reallocated N+1 times, and the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located must enable the Hotplug function. If the Hotplug function of any node in the entire link is not turned on, resources will be reallocated. If all are turned on, the memory resources allocated when BIIOS is started will be used for allocation. When reallocating memory resources, the level of the Switch scanned is N, the number of scans is N+1, and 32-bit memory resources are allocated to PCI devices starting from N+1. When the N+1 memory resource allocation is completed, resources are allocated to the PCI devices of the N-level until all devices in the PCI link bridge have completed resource allocation. If there is insufficient 32-bit memory resources, the memory resources will be allocated. The memory resource allocation of the Switch chip and PCI devices at the subsequent level is abandoned; therefore, the BIOS enables the Hotplug function of the PCI link where the DPU and specific PCI devices are located, and the Hotplug function of the upstream and downstream ports of the PCI link Switch chip and the PCI link bridge by default to avoid the system reallocation causing the DPU and specific PCI devices to be unable to be used normally. If the Hotplug function of the DPU and specific PCI devices is disabled and the 32-bit memory resources of the DPU device are exhausted, the resources of the DPU and specific PCI devices will be released and unable to meet the memory resource requests during normal use, resulting in the DPU being unable to be displayed or the DPU or specific PCI device functions being unable to be used normally. The above settings can ensure that the DPU and specific PCI devices can be used normally at any time, without worrying about resource problems causing the DPU to be unusable.

[0149] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0150] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned multi-layer switch firmware combined memory resource allocation method embodiments when running.

[0151] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0152] An embodiment of the present invention further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned multi-level switch firmware combined memory resource allocation method embodiments are implemented.

[0153] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present invention.

[0154] The above is a detailed introduction to a memory resource allocation method provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A system for allocating memory resources by combining multi-level switch firmware, characterized in that: include: At least one processing circuit of the server, the at least one processing circuit being connected to at least one peripheral interconnect link, the at least one processing circuit being configured to: executing a reading engine, wherein the reading engine reads a first hardware resource on a current peripheral interconnection link when the server is started; Propagating the read data of the first hardware resource to an identification engine, the identification engine identifying the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifying a second hardware resource connected to each switch; The identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch, and the firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

2. The system for allocating memory resources by combining multi-level switch firmware according to claim 1, characterized in that: The firmware is used to: If the second hardware resource includes a peripheral interconnect device, allocating a first memory resource to the peripheral interconnect device according to the target setting of the firmware; If the second hardware resource includes a peripheral interconnection port, then when the peripheral interconnection port needs to support a hot plug function, the first memory resource is allocated to the peripheral interconnection port.

3. The system for allocating memory resources by combining multi-level switch firmware according to claim 1, characterized in that: The at least one processing circuit is configured to: If the first hardware resource includes a peripheral interconnect device, the read data is propagated to an allocation engine, and the allocation engine allocates a first memory resource to the peripheral interconnect device.

4. The system for allocating memory resources by combining multi-level switch firmware according to claim 3, characterized in that: The at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads an identification of the peripheral interconnection device; Propagating the identification of the peripheral interconnect device to an identification engine, wherein the identification engine identifies whether the peripheral interconnect device is a data processor based on the identification; When the peripheral interconnect device is a data processor, the allocation engine allocates the first memory resource according to the resource size of the data processor.

5. The system for allocating memory resources by combining multi-level switch firmware according to claim 3, characterized in that: The allocation engine is used to: When the current peripheral interconnection link is connected to a peripheral interconnection port, if the peripheral interconnection port is a target port, a first memory resource is allocated to the peripheral interconnection port.

6. The system for allocating memory resources by combining multi-layer switch firmware according to any one of claims 1 to 5, characterized in that: The firmware sets a hot-swap function for the upstream and downstream ports of the switch to which the first memory resource has been allocated.

7. The system for allocating memory resources by combining multi-layer switch firmware according to any one of claims 1 to 5, characterized in that: The at least one processing circuit is configured to: An allocation engine is started, where the allocation engine is a switch to which the first memory resource has been allocated, and a hot-swap function is set on a peripheral interconnection link.

8. The system for allocating memory resources by combining multi-level switch firmware according to claim 1, characterized in that: The at least one processing circuit is configured to: When the identification engine polls all peripheral interconnection links, the first hardware resource, and the second hardware resource, a startup engine is executed, and the startup engine starts the operating system of the server.

9. The system for allocating memory resources by combining multi-level switch firmware according to claim 8, characterized in that: The at least one processing circuit is configured to: After the server enters the operating system, the reading engine is executed, and the reading engine reads the memory allocation function of the server; An allocation engine reallocates the first memory resource of the server according to the memory allocation function.

10. The system for allocating memory resources by combining multi-level switch firmware according to claim 8, characterized in that: The at least one processing circuit is configured to: Before reallocating the first memory resource of the server according to the memory allocation function, executing the reading engine, wherein the reading engine reads the reallocation requirement of the server; An allocation engine reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

11. The system for allocating memory resources by combining multi-layer switch firmware according to claim 9, characterized in that: If the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

12. The system for allocating memory resources by combining multi-level switch firmware according to claim 9, characterized in that: The at least one processing circuit is configured to: executing a scanning engine, wherein the scanning engine scans all peripheral interconnection links of the server; The scanning data of the scanning engine is propagated to the recognition engine. The recognition engine recognizes the scanning data. If the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are recognized, the hot plug function is enabled, and the first memory resource allocated to the current peripheral interconnection link during the server startup phase is reserved.

13. The system for allocating memory resources by combining multi-layer switch firmware according to claim 12, characterized in that: The recognition engine is used to: If the current peripheral interconnection link, the first hardware resource connected to the current peripheral interconnection link, and the switch connected to the current peripheral interconnection link are identified, the hot plug function is turned off, and the allocation engine reallocates the first memory resource of the server according to the memory allocation function.

14. The system for allocating memory resources by combining multi-layer switch firmware according to claim 12, wherein: The recognition engine is used to: If it is identified that the current peripheral interconnection link is idle, or the switch connected to the current peripheral interconnection link is idle, allocating the first memory resource of the server is stopped.

15. The system for allocating memory resources by combining multi-layer switch firmware according to any one of claims 9 to 14, characterized in that: The at least one processing circuit is configured to: executing a scanning engine, wherein the scanning engine scans a current peripheral interconnection link level; Propagating the scan data of the scan engine to the recognition engine, the recognition engine recognizing the scan data, and if the current peripheral interconnection link level is N, the number of times the first memory resource is reallocated is N+1; The allocation engine performs a first memory resource allocation according to the reallocation number.

16. The system for memory resource allocation based on multi-layer switch firmware combination according to claim 15, characterized in that: The at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads a second memory resource of the server; propagating the remaining resource of the second memory resource to the recognition engine, the recognition engine identifying whether the remaining resource is less than a resource threshold; The recognition result of the recognition engine is propagated to the allocation engine, and the allocation engine stops allocating the first memory resource of the hardware resource of the current level or the next level when the remaining resource is less than the resource threshold.

17. The system for allocating memory resources by combining multi-layer switch firmware according to claim 16, wherein: The allocation engine is used to: If any firmware of the multi-level switch does not support the hot-swap function, reallocate the first memory resource of the peripheral interconnection link where the firmware that does not support the hot-swap function is located; If all firmwares of the multi-layer switch support the hot-swap function, the allocation parameter of the first memory resource in the server startup phase is retained.

18. A server, characterized in that: A system comprising multi-level switch firmware combined memory resource allocation according to any one of claims 1 to 17.

19. A method for allocating memory resources in a multi-layer switch firmware combination, characterized in that: include: At least one processing circuit connected using at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: executing a reading engine, wherein the reading engine reads a first hardware resource on a current peripheral interconnection link when the server is started; Propagating the read data of the first hardware resource to an identification engine, the identification engine identifying the read data, and if the first hardware resource includes at least one of a single-layer switch and a multi-layer switch, identifying a second hardware resource connected to each switch; The identification result of the second hardware resource connected to each switch is propagated to the firmware of the corresponding switch, and the firmware allocates the first memory resource to the switch and the second hardware resource based on the identification result of the second hardware resource.

20. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for allocating memory resources of a multi-layer switch firmware combination are implemented as claimed in claim 19.

21. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for allocating memory resources of a multi-layer switch firmware combination are implemented as claimed in claim 19.

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