Laminated structure for printed circuit board and printed circuit board
Through the stacking design of signal plane and power plane and buried capacity processing, the problem of high transmission loss of printed circuit boards is solved, significant optimization of transmission loss and improvement of signal integrity is achieved, and product design is simplified.
Patent Information
- Application Number
- CN202510376642.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-27
- Publication Date
- 2025-07-01
AI Technical Summary
The prior art is not effective in reducing the transmission loss of printed circuit boards. Conventional solutions such as increasing the copper thickness of the power layer and the copper strips on the back mount have process difficulties and welding offset risks. The vertical power supply scheme is insufficiently mature and the problems of heat dissipation and power supply dynamic performance are prominent.
The signal plane and power plane stacking design is adopted. The signal vias and isolation ground holes do not extend to the power plane. The power vias and reflow ground holes run through the entire stacked structure. Combined with the buried capacity processing, it reduces the need for underlying welding, enhances current conduction capability and reduces the number of signal layers.
Significantly reduce transmission loss by 30%, improve signal integrity and reliability, simplify product design and layout difficulty, and optimize electromagnetic compatibility and heat dissipation performance of the power plane layer.
Smart Images
Figure CN120239169A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure generally relate to the technical field of electronic devices, and more particularly, to a stacked structure for a printed circuit board and a printed circuit board. Background Art
[0002] As the power consumption of chips continues to increase, the maximum continuous current required by the chips continues to increase, which leads to an increase in the transmission loss between the voltage regulator and the chips. How to optimize the transmission loss has become a direction for improving product competitiveness and cost optimization.
[0003] To reduce the transmission loss, a conventional solution is to optimize the trace and increase the copper thickness of the power plane. However, limited by the size of the voltage regulator and the requirements of high-speed trace fan-out, this solution has little benefit in optimizing the transmission loss. Another solution is to add copper bars on the back of the printed circuit board through surface mount technology to reduce the transmission loss. However, there is a risk of welding offset during the welding of the copper bars, and the chip backplane needs to be correspondingly hollowed out or heightened and customized to accommodate the copper bars, which increases the process difficulty. In addition, vertical power supply is also an effective means to solve the transmission loss. By mounting the power module on the back of the chip, the conduction distance can be shortened. However, the maturity of this solution is insufficient, and the heat dissipation and power supply dynamic performance problems will become bottlenecks. Summary of the Invention
[0004] In a first aspect of the present disclosure, a stacked structure for a printed circuit board is provided. The stacked structure includes: a signal plane portion, including a signal isolation ground layer and a signal layer for transmitting signals, the signal layer being stacked with the signal isolation ground layer; a power plane portion, stacked with the signal plane portion through a connection layer, and including a pair of power return ground layers and a plurality of power layers disposed between the pair of power return ground layers; signal vias and signal isolation ground vias, the signal vias and the signal isolation ground vias extending from the surface of the signal plane portion away from the power plane portion into the signal plane portion and not extending into the power plane portion; and a plurality of power vias and a plurality of power return ground vias, at least one of the power vias and at least one of the power return ground vias extending from the surface of the signal plane portion away from the power plane portion, passing through the signal plane portion, the connection layer and the power plane portion, and extending to the surface of the power plane portion away from the signal plane portion.
[0005] In a second aspect of the present disclosure, a printed circuit board is provided, including the stacked structure according to the first aspect of the present disclosure.
[0006] It should be understood that the content described in this content part is not intended to define the key features or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS
[0007] In conjunction with the accompanying drawings and with reference to the following detailed description, the above and other features, advantages, and aspects of the embodiments of the present disclosure will become more apparent. In the drawings, the same or similar reference numerals denote the same or similar elements, where:
[0008] Figure 1 FIG. shows a schematic cross-sectional view of a stacked structure for a printed circuit board according to an embodiment of the present disclosure;
[0009] Figure 2A FIG. shows a top view of the stacked structure as viewed from the side of the signal plane portion;
[0010] Figure 2B FIG. shows a top view of the stacked structure as viewed from the side of the power plane portion;
[0011] Figure 3A and Figure 3B FIG. shows an exemplary arrangement of the signal plane portion of the stacked structure; and
[0012] Figure 4 FIG. shows a schematic cross-sectional view of a stacked structure employing buried capacitance processing according to an embodiment of the present disclosure;
[0013] DESCRIPTION OF REFERENCE NUMERALS:
[0014] 100 Stacked structure;
[0015] 110 Signal plane portion;
[0016] 111 Signal isolation ground layer;
[0017] 112 Signal layer;
[0018] 120 Power plane portion;
[0019] 121 Power return ground layer;
[0020] 122 Power layer;
[0021] 130 Connection layer;
[0022] 140 Dielectric layer;
[0023] 150 Power return ground via;
[0024] 151 Signal isolation ground via;
[0025] 160 Power via;
[0026] 161 signal vias;
[0027] 170 capacitors. Detailed implementation manners
[0028] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not used to limit the protection scope of the present disclosure.
[0029] It should be noted that the titles of any sections / subsections provided herein are not restrictive. Various embodiments are described throughout this document, and any type of embodiment can be included under any section / subsection. In addition, the embodiments described in any section / subsection can be combined with any other embodiments described in the same section / subsection and / or different section / subsections in any manner.
[0030] In the description of the embodiments of the present disclosure, the term "including" and its like should be understood as an open inclusion, that is, "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The term "some embodiments" should be understood as "at least some embodiments". There may also be other explicit and implicit definitions hereinafter. The terms "first", "second", etc. may refer to different or the same objects. There may also be other explicit and implicit definitions hereinafter.
[0031] As mentioned above, as the power consumption of the chip continues to increase, the maximum continuous current required by the chip continues to increase, which leads to an increase in the transmission loss between the voltage regulator and the chip. How to optimize the transmission loss has become a direction for improving product competitiveness and cost optimization. To reduce the transmission loss, a conventional solution is to optimize the traces and increase the copper thickness of the power layer. However, limited by the size of the voltage regulator and the requirements of high-speed trace fan-out, the benefits of this solution in optimizing the transmission loss are minimal. Another solution is to add copper bars on the back of the printed circuit board through surface mount technology to reduce the transmission loss. However, there is a risk of welding offset during the welding of the copper bars, and the chip backplane needs to be correspondingly hollowed out or heightened and customized to accommodate the copper bars, which increases the process difficulty. In addition, vertical power supply is also an effective means to solve the transmission loss. By mounting the power module on the back of the chip, the conduction distance can be shortened. However, the maturity of this solution is insufficient, and the heat dissipation and power supply dynamic performance issues will become bottlenecks.
[0032] To solve or at least partially solve the above problems or other potential problems of the printed circuit board in the traditional solution, embodiments of the present disclosure provide a stacking scheme for a printed circuit board. In this scheme, by laminating the signal plane part and the power plane part, at least one power via and at least one power return ground via of the signal plane part and the power plane part penetrate the entire laminated structure, while the signal vias and signal isolation ground vias of the signal plane part do not extend into the power plane part, so that a part of the copper foil of the power plane is complete, enhancing the current conduction ability. Further, since the bottom layer of the signal plane part is connected to the connection layer, the bottom layer changes from an outer layer to an inner layer, so that the bottom layer can be set as a high-speed signal layer. In this way, the number of high-speed signal layers in the signal plane part can be further reduced, thereby realizing a layer reduction design and significantly reducing the difficulty of product design layout. Further, by performing buried capacitance treatment on the power plane layer, the need for soldering on the bottom layer of the printed circuit board is reduced, while the signal integrity and reliability are improved. The following will be combined with Figures 1 to 4 to describe the embodiments of the present disclosure.
[0033] Figure 1 FIG. shows a schematic cross-sectional view of a stacked structure 100 for a printed circuit board according to some embodiments of the present disclosure. As Figure 1 shown, the stacked structure 100 described herein generally includes a signal plane part 110, a power plane part 120, a connection layer 130, signal vias 161, signal isolation ground vias 151, a plurality of power vias 160, and a plurality of power return ground vias 150.
[0034] In some embodiments, as Figure 1 shown, the signal plane part 110 includes a plurality of signal isolation ground layers 111 and a plurality of signal layers 112 for transmitting signals. The plurality of signal layers 112 and the plurality of signal isolation ground layers 111 are stacked. In some embodiments, the plurality of signal layers 112 and the plurality of signal isolation ground layers 111 are alternately arranged, and each signal layer 112 is separated from the adjacent signal isolation ground layer 111 by a dielectric layer 140. In other embodiments, two or more signal isolation ground layers 111 may be provided between adjacent signal layers 112 to ensure signal isolation performance.
[0035] Alternatively, in some embodiments, the signal plane part 110 may include a single signal isolation ground layer 111 or a single signal layer 112, and the scope of the present disclosure is not limited in this regard.
[0036] As Figure 1As shown, the power plane portion 120 includes a pair of power return ground layers 121 and a plurality of power layers 122 disposed between the pair of power return ground layers 121. The plurality of power layers 122 are spaced apart from the pair of power return ground layers 121 by a dielectric layer 140. Adjacent power layers 122 are also spaced apart from each other by the dielectric layer 140.
[0037] As Figure 1 shown, a connection layer 130 is disposed between the power plane portion 120 and the signal plane portion 110 to join the two together such that the power plane portion 120 and the signal plane portion 110 are stacked on top of each other. The stacked structure 100 is an asymmetric stacked structure. When the stacked structure 100 is placed in the orientation shown in Figure 1 , the signal plane portion 110 is located above the power plane portion 120. It should be understood that when the stacked structure 100 is placed in other orientations, the power plane portion 120 and the signal plane portion 110 may have other relative positional relationships.
[0038] In some embodiments, as Figure 1 shown, a single power via 160 and a single power return ground via 150 extend from the surface of the signal plane portion 110 remote from the power plane portion 120, through the signal plane portion 110, the connection layer 130, and the power plane portion 120, to the surface of the power plane portion 120 remote from the signal plane portion 110. Figure 1 Only a single power via 160 and a single power return ground via 150 are shown as examples to illustrate the principles of the present disclosure. It should be understood that other power vias 160 and power return ground vias 150 may also have a similar arrangement, i.e., extending from the surface of the signal plane portion 110 remote from the power plane portion 120 to the surface of the power plane portion 120 remote from the signal plane portion 110. As Figure 2A and Figure 2B shown, in the signal plane portion 110 and the power plane portion 120, a plurality of power vias 160 and a plurality of power return ground vias 150 are arranged in an array.
[0039] Alternatively or additionally, in some embodiments, one or more of the plurality of power vias 160 and the plurality of power return ground vias 150 may extend from the surface of the signal plane portion 110 remote from the power plane portion 120 into the power plane portion 120 without extending to the surface of the power plane portion 120 remote from the signal plane portion 110.
[0040] As Figures 1 to 2B shown, signal vias 161 and signal isolation ground vias 151 extend from the surface of the signal plane portion 110 remote from the power plane portion 120 into the signal plane portion 110 and do not extend into the power plane portion 120. Figure 1Only a single signal via 161 and a single signal isolation ground via 151 are shown as examples to illustrate the principle of the present disclosure. It should be understood that other signal vias 161 and signal isolation ground vias 151 may also have a similar arrangement, that is, extending from the surface of the signal plane portion 110 away from the power plane portion 120 into the signal plane portion 110 and not extending into the power plane portion 120. As Figure 2B shown, only a plurality of power vias 160 and a plurality of power return ground vias 150 are arranged in an array on the surface of the power plane portion 120 away from the signal plane portion 110, while the signal via 161 and the signal isolation ground via 151 do not extend to the surface of the power plane portion 120 away from the signal plane portion 110. With this arrangement, a part of the copper foil of the power plane portion 120 can be made complete, thereby enhancing the current conduction ability.
[0041] In some embodiments, as Figure 2A and Figure 2B shown, the signal via 161 and the signal isolation ground via 151 are respectively plural. Each power via 160 is adjacent to at least one power return ground via 150, and each signal via 161 is adjacent to at least one signal isolation ground via 151. In this way, electromagnetic interference can be reduced, and signal integrity and electromagnetic compatibility can be improved.
[0042] In some embodiments, the signal plane portion 110 is formed in the first lamination process, the power plane portion 120 is formed in the second lamination process, and the signal plane portion 110 and the power plane portion 120 are stacked together through the connection layer 130 in the third lamination process. The signal via 161 and the signal isolation ground via 151 are formed in the signal plane portion 110 after the first lamination process and before the third lamination process, and the plurality of power vias 160 and the plurality of power return ground vias 150 are formed in the signal plane portion 110 and the power plane portion 120 after the third lamination process. By laminating the signal plane portion 110 and the power plane portion 120 separately and then laminating them together for the second time, the manufacturing accuracy and reliability of the multi-layer stack structure can be effectively improved, and the processing difficulty can be reduced.
[0043] In some embodiments, as Figure 1 shown, there are plural signal layers 112, and one of the plural signal layers 112 in the signal plane portion 110 is in contact with the connection layer 130. Alternatively, in some other embodiments, one of the plural signal isolation ground layers 111 in the signal plane portion 110 may be in contact with the connection layer 130.
[0044] In some embodiments, as Figure 1As shown, there are multiple signal vias 161 and multiple signal isolation ground vias 151. At least one of the multiple signal vias 161 and at least one of the multiple signal isolation ground vias 151 extend from the surface of the signal plane portion 110 away from the power plane portion 120 to the signal layer 112 in the multiple signal layers 112 that contacts the connection layer 130.
[0045] In some embodiments, the signal layer 112 adjacent to the connection layer 110 in the multiple signal layers 112 is a high-speed signal layer. High-speed signal lines usually need to be located in the inner layer of the signal plane portion 110, and its number of layers determines the number of layers of the multi-layer stack structure. By connecting the bottom layer of the signal plane portion 110 to the connection layer 130, the bottom layer changes from the outer layer to the inner layer. Therefore, the bottom layer can be set as a high-speed signal layer. Thus, the number of high-speed signal layers in the signal plane portion 110 can be further reduced, thereby achieving a layer reduction design and significantly reducing the difficulty of product design layout.
[0046] The following will further describe the layer reduction design of the signal plane portion 110 in conjunction with Figure 3A and 3B drawings. Figure 3A FIG. is an example structure of the signal plane portion 110. As Figure 3A shown, the signal plane portion 110 includes an L1 signal layer, an L2 isolation ground layer, an L3 signal layer, an L4 isolation ground layer, an L5 signal layer, an L6 isolation ground layer, and an L7 signal layer. Since high-speed signal lines usually need to be arranged in the inner layer, the L3 signal layer and the L5 signal layer can be arranged as high-speed signal layers. The high-speed signal layers are two layers, and the entire signal plane portion 110 is a 7-layer structure. Figure 3B FIG. is another example structure of the signal plane portion 110. Combining Figure 1 and Figure 3B shown, after laminating the signal plane portion 110 and the power plane portion 120, the L7 signal layer at the bottom layer of the signal plane portion 110 contacts the connection layer 130, and the L7 signal layer at the bottom layer changes from the outer layer to the inner layer. Therefore, the L7 signal layer can be arranged as a high-speed signal layer. When two high-speed signal layers also need to be arranged, the L3 signal layer and the L7 signal layer can be arranged as high-speed signal layers, so that the L5 signal layer and the L6 isolation ground layer of the signal plane portion 110 can be omitted, thereby achieving a layer reduction design of reducing two layers.
[0047] In some embodiments, as Figure 4As shown, the power plane portion 120 further includes at least one capacitor 170, and at least one capacitor 170 is coupled between at least one of the paired power return ground layers 121 and an adjacent power layer 122. For example, the capacitor 170 is coupled between the power return ground layer 121 at the bottom layer of the power plane portion 120 and the adjacent power layer 122. One electrode of the capacitor 170 is connected to the power return ground layer 121, and the other electrode is connected to the power layer 122 adjacent to the power return ground layer 121. By performing the buried capacitor treatment on the power plane layer, the requirement for soldering on the bottom layer of the printed circuit board is reduced, while the signal integrity and reliability are improved.
[0048] In some embodiments, as Figure 1 shown, the power plane portion 120 may be a four-layer structure, including two power layers 122 and two power return ground layers 121. As Figure 1 shown, one power return ground layer 121 is adjacent to the connection layer 130, and the other power return ground layer 121 is disposed on a side of the power plane portion 120 away from the connection layer 130. With this arrangement, the power return ground layer 121 at the bottom layer of the power plane portion 120 can isolate the electromagnetic interference of the power layer 122 to the outside, and the power return ground layer 121 at the top layer of the power plane portion 120 can isolate the interlayer crosstalk of the power layer 122 to the signal plane portion 110. In other embodiments, more power layers 122 may be provided between the two power return ground layers 121.
[0049] In some embodiments, considering power loss, production cycle, and cost comprehensively, the two power layers 122 in the power plane portion 120 may adopt a thick copper design, for example, including 5 oz (ounce) of copper foil.
[0050] Compared with the conventional stack structure, the stack structure for the printed circuit board provided by the embodiments of the present disclosure can significantly optimize the transmission loss, for example, reduce it by 30%. For example, for a core voltage of 1V, the transmission loss of the stack structure of the embodiments of the present disclosure can be optimized by 30 - 40 w.
[0051] The embodiments of the present disclosure are also reflected in the following examples.
[0052] Example 1. A stack structure for a printed circuit board, including:
[0053] A signal plane portion, including a signal isolation ground layer and a signal layer for transmitting signals, and the signal layer is stacked with the signal isolation ground layer;
[0054] A power plane portion, stacked with the signal plane portion through a connection layer, and including paired power return ground layers and a plurality of power layers disposed between the paired power return ground layers;
[0055] Signal vias and signal isolation ground vias, the signal vias and the signal isolation ground vias extend from the surface of the signal plane portion away from the power plane portion into the signal plane portion and do not extend into the power plane portion; and
[0056] A plurality of power vias and a plurality of power return ground vias, at least one of the power vias and at least one of the power return ground vias extend from the surface of the signal plane portion away from the power plane portion, through the signal plane portion, the connection layer and the power plane portion, to the surface of the power plane portion away from the signal plane portion.
[0057] Example 2. The stacked structure according to Example 1, wherein the signal vias and the signal isolation ground vias are respectively plural, each power via is disposed adjacent to at least one of the power return ground vias, and each signal via is disposed adjacent to at least one of the signal isolation ground vias.
[0058] Example 3. The stacked structure according to Example 1, wherein the signal plane portion is formed in a first lamination process, the power plane portion is formed in a second lamination process, and the signal plane portion and the power plane portion are stacked together through the connection layer in a third lamination process, and
[0059] wherein the signal vias and the signal isolation ground vias are formed in the signal plane portion after the first lamination process and before the third lamination process, and the plurality of power vias and the plurality of power return ground vias are formed in the signal plane portion and the power plane portion after the third lamination process.
[0060] Example 4. The stacked structure according to Example 1, wherein there are plural signal layers, and one of the plural signal layers is in contact with the connection layer.
[0061] Example 5. The stacked structure according to Example 4, wherein the signal vias and the signal isolation ground vias are respectively plural, and at least one of the plural signal vias and at least one of the plural signal isolation ground vias extend from the surface of the signal plane portion away from the power plane portion to the signal layer in contact with the connection layer among the plural signal layers.
[0062] Example 6. The stacked structure according to Example 5, wherein the signal layer adjacent to the connection layer among the plural signal layers is a high-speed signal layer.
[0063] Example 7. The stacked structure according to Example 1, wherein the power plane portion further includes at least one capacitor, and the at least one capacitor is coupled between at least one of the paired power return ground layers and an adjacent power layer.
[0064] Example 8. The stacked structure according to Example 1, wherein the power layer includes a 5 oz copper foil.
[0065] Example 9. The stacked structure according to Example 1, wherein the power plane portion includes two power layers.
[0066] Example 10. A printed circuit board comprising the stacked structure according to any one of Examples 1-9.
[0067] The various implementations of the present disclosure have been described above. The above description is exemplary, not exhaustive, and is not limited to the disclosed implementations. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described implementations. The choice of terms used herein is intended to best explain the principles of the implementations, practical applications, or improvements to technologies in the market, or to enable other ordinary skilled persons in the art to understand the various implementation manners disclosed herein.
Claims
1. A laminate structure (100) for a printed circuit board, comprising: The signal plane part (110) comprises a signal isolation layer (111) and a signal layer (112) for transmitting signals, wherein the signal layer (112) and the signal isolation layer (111) are stacked; A power plane portion (120) is overlapped with the signal plane portion (110) via a connection layer (130), and comprises a pair of power return ground layers (121) and a plurality of power layers (122) arranged between the pair of power return ground layers (121); A signal via (161) and a signal isolation ground hole (151), wherein the signal via (161) and the signal isolation ground hole (151) extend from a surface of the signal plane portion (110) away from the power plane portion (120) into the signal plane portion (110) and do not extend into the power plane portion (120); as well as A plurality of power vias (160) and a plurality of power return ground holes (150), at least one of the power vias (160) and at least one of the power return ground holes (150) extending from a surface of the signal plane portion (110) away from the power plane portion (120), through the signal plane portion (110), the connection layer (130) and the power plane portion (120), to a surface of the power plane portion (120) away from the signal plane portion (110).
2. The stacked structure (100) according to claim 1, wherein the signal via (161) and the signal isolation ground hole (151) are respectively multiple, each of the power via (160) is arranged adjacent to at least one of the power return ground holes (150), and each of the signal via (161) is arranged adjacent to at least one of the signal isolation ground holes (151).
3. The laminate structure (100) according to claim 1, wherein the signal plane portion (110) is formed in a first lamination process, the power plane portion (120) is formed in a second lamination process, and the signal plane portion (110) and the power plane portion (120) are stacked together through the connection layer (130) in a third lamination process, and The signal via (161) and the signal isolation ground hole (151) are formed in the signal plane part (110) after the first pressing process and before the third pressing process, and the plurality of power vias (160) and the plurality of power return ground holes (150) are formed in the signal plane part (110) and the power plane part (120) after the third pressing process.
4. The stacked structure (100) according to claim 1, wherein there are a plurality of signal layers (112), and one signal layer (112) among the plurality of signal layers (112) is in contact with the connection layer (130).
5. The stacked structure (100) according to claim 4, wherein the signal via (161) and the signal isolation ground hole (151) are respectively multiple, and at least one signal via (161) among the multiple signal vias (161) and at least one signal isolation ground hole (151) among the multiple signal isolation ground holes (151) extend from the surface of the signal plane part (110) away from the power plane part (120) to the signal layer (112) among the multiple signal layers (112) that is in contact with the connection layer (130).
6. The stacked structure (100) according to claim 5, wherein the signal layer (112) adjacent to the connection layer (110) among the plurality of signal layers (112) is a high-speed signal layer.
7. The stacked structure (100) according to claim 1, wherein the power plane portion (120) further comprises at least one capacitor (170), and the at least one capacitor (170) is coupled between at least one power return layer (121) in the pair of power return layers (121) and an adjacent power layer (122).
8. The laminate structure (100) of claim 1, wherein the power layer (122) comprises 5 oz copper foil.
9. The stacked structure (100) according to claim 1, wherein the power plane portion (120) comprises two power layers (122).
10. A printed circuit board comprising the laminate structure (100) according to any one of claims 1 to 9.