Multilayer printed circuit board for interconnecting pins and semiconductor dies and corresponding interconnecting method

Abstract

The invention relates to a multilayer printed circuit board for interconnecting pins and semiconductor dies and a corresponding interconnecting method. There is provided a multilayer printed circuit board for interconnecting a pin and a semiconductor die, including: a multilayer substrate including a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each of the substrate layers being composed of an insulating material; pin holders embedded in the multilayer substrate, one end of each pin holder being exposed from the top surface of the top substrate layer for inserting a pin in the pin holder; die contacts embedded in the multilayer substrate, one end of each die contact being exposed from a bottom surface of the bottom substrate layer for electrical coupling with a contact of a semiconductor die; and first interconnection structures embedded in the multilayer substrate, each first interconnection structure being connected between a respective pin holder and a respective die contact for electrically coupling the two.

Description

Technical Field

[0001] The present disclosure relates to power module packaging, and more particularly, to a multi-layer printed circuit board and a corresponding interconnection method for interconnecting pins and semiconductor dies during power module packaging. Background Art

[0002] Pins are a common interconnection method for connecting semiconductor dies (especially semiconductor dies applied to power modules in vehicles) to a main circuit board (usually a printed circuit board), and they play a very important interconnection role in the final product. However, pins and pin holders are one of the most vulnerable components in the final product. Different from wiring, pins and pin holders are very easy to be damaged because they not only have to withstand the force of being pressed / inserted during the interconnection process, but also face various situations that may occur during the soldering process. The soldering process of pins and pin holders is relatively complex, so various defects often occur, including for example solder splash, pin tilt deformation, holder deformation, holder failure, and so on.

[0003] In short, pins and pin holders are important and critical components for interconnecting semiconductor dies, and any defect or failure of them will have an adverse impact on the final product. Therefore, there is an urgent need to propose an interconnection technical solution that can avoid defects and failures of pins and pin holders.

[0004] For this reason, the present application proposes a multi-layer printed circuit board for interconnecting pins and semiconductor dies and a corresponding interconnection method that can solve the above problems. Summary of the Invention

[0005] One object of the present disclosure is to provide an improved multi-layer printed circuit board for interconnecting pins and semiconductor dies and a corresponding interconnection method.

[0006] According to one aspect of the present disclosure, there is provided a multi-layer printed circuit board for interconnecting pins and semiconductor dies, including: a multi-layer substrate including a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each substrate layer being composed of an insulating material; pin holders embedded in the multi-layer substrate, one end of each pin holder being exposed from the top surface of the top substrate layer for inserting pins into the pin holders; die contacts embedded in the multi-layer substrate, one end of each die contact being exposed from the bottom surface of the bottom substrate layer for electrically coupling with a contact of a semiconductor die; and a first interconnection structure embedded in the multi-layer substrate, each first interconnection structure being connected between a corresponding pin holder and a corresponding die contact for electrically coupling the two.

[0007] According to one or more embodiments of the present disclosure, each pin holder includes: a tubular cavity extending in a direction perpendicular to the multi-layer substrate and adapted to receive one end of a pin therein; and a first flange provided at one end of the tubular cavity and protruding laterally with respect to the tubular cavity, the first flange being disposed above the top surface of the top substrate layer.

[0008] According to one or more embodiments of the present disclosure, the multi-layer printed circuit board further includes: auxiliary connectors embedded in the multi-layer substrate and extending in a direction perpendicular to the multi-layer substrate, one end of each auxiliary connector being electrically coupled to a corresponding pin holder and the other end being electrically connected to a corresponding die contact, wherein each auxiliary connector includes: a columnar body extending in a direction perpendicular to the multi-layer substrate; and a second flange provided at one end of the columnar body and protruding laterally with respect to the columnar body.

[0009] According to one or more embodiments of the present disclosure, the multi-layer printed circuit board further includes: flange interconnects, each flange interconnect being connected between the second flange of a corresponding auxiliary connector and a corresponding pin holder for electrically coupling the two.

[0010] According to one or more embodiments of the present disclosure, wherein the auxiliary connector includes a first auxiliary connector, the second flange of the first auxiliary connector and the flange interconnect connected thereto being disposed between the top substrate layer and an adjacent core substrate layer; and wherein the flange interconnect connected to the second flange of the first auxiliary connector is further connected to the tubular cavity of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the first auxiliary connector.

[0011] According to one or more embodiments of the present disclosure, wherein the second flange of the first auxiliary connector and the corresponding flange interconnect connected thereto are integrally formed of the same layer of metal.

[0012] According to one or more embodiments of the present disclosure, wherein the auxiliary connector includes a second auxiliary connector, the second flange of the second auxiliary connector and the flange interconnect connected thereto being disposed above the top surface of the top substrate layer; and wherein the flange interconnect connected to the second flange of the second auxiliary connector is further connected to the first flange of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector.

[0013] According to one or more embodiments of the present disclosure, wherein the second flange of the second auxiliary connector, the corresponding flange interconnect, and the first flange of the corresponding pin holder connected to each other are integrally formed of the same layer of metal.

[0014] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: a second interconnect structure embedded in the multilayer substrate, each second interconnect structure being connected between at least two die contacts for electrically coupling the at least two die contacts.

[0015] According to one or more embodiments of the present disclosure, at least a portion of the first interconnect structure, the second interconnect structure, and / or the die contacts is formed by a thick copper embedding process.

[0016] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: buried spacers, each buried spacer extending from the bottom surface of the top substrate layer through the one or more core substrate layers and the bottom substrate layer, and extending beyond the bottom surface of the bottom substrate layer by a first length, wherein the first length depends on the thickness of the semiconductor die.

[0017] According to one or more embodiments of the present disclosure, wherein the first length is equal to the sum of the thickness of the semiconductor die and the thickness of a die attachment layer for attaching the semiconductor die to the multilayer printed circuit board.

[0018] According to one or more embodiments of the present disclosure, the multilayer printed circuit board further includes: a negative temperature coefficient contact embedded in the multilayer substrate, the negative temperature coefficient contact being exposed from an opening provided at a central portion of the bottom substrate layer for coupling to a negative temperature coefficient sensor.

[0019] According to one or more embodiments of the present disclosure, wherein the die contacts include thick copper contacts and / or thin copper contacts; and wherein the die contacts serve as one or more of the following: gate-substrate contacts, source-substrate contacts, gate pad contacts, and / or source pad contacts.

[0020] According to another aspect of the present disclosure, there is provided a pin including: a rod-shaped body, a first end of the rod-shaped body being pointed and adapted to be inserted into a pin holder, a second end of the rod-shaped body including an elastic portion and being adapted to be inserted into a through hole; and a stop portion provided at a position on the rod-shaped body at a certain distance from the first end and protruding laterally with respect to the rod-shaped body, wherein the pin is adapted to be mounted in a pin holder in the multilayer printed circuit board as described above, and wherein when the first end of the pin is inserted into the pin holder, the stop portion abuts above a first flange of the pin holder.

[0021] According to yet another aspect of the present disclosure, there is provided a power module, comprising: a carrier substrate; a semiconductor die attached to the carrier substrate; a multilayer printed circuit board as described above, attached to the semiconductor die and electrically coupled to the semiconductor die through die contacts of the multilayer printed circuit board; a housing encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board; and pins inserted into pin holders in the multilayer printed circuit board and exposed from one side of the housing.

[0022] According to still another aspect of the present disclosure, there is provided a method for interconnecting pins and a semiconductor die, comprising the steps of: attaching a semiconductor die to a carrier substrate; attaching a multilayer printed circuit board as described above to the semiconductor die; inserting pins into pin holders in the multilayer printed circuit board; and encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board with an insulating material to form a housing.

[0023] According to still yet another aspect of the present disclosure, there is provided a method for interconnecting pins and a semiconductor die, comprising the steps of: attaching a multilayer printed circuit board as described above to the semiconductor die; attaching a semiconductor die to a carrier substrate; inserting pins into pin holders in the multilayer printed circuit board; and encapsulating the carrier substrate, the semiconductor die and the multilayer printed circuit board with an insulating material to form a housing.

[0024] According to one or more embodiments of the present disclosure, attaching the multilayer printed circuit board to the semiconductor die includes the following steps: coating an attachment material on contacts of the semiconductor die; placing the multilayer printed circuit board on the semiconductor die such that contacts of the bottom substrate layer of the multilayer printed circuit board are in contact with the contacts of the semiconductor die via the attachment material; and performing a sintering, soldering and / or curing process to cure the attachment material.

[0025] Other features and advantages of the present disclosure will become clearer from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. Description of the Drawings

[0026] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the specification, are used to explain the principles of the present disclosure.

[0027] Referring to the accompanying drawings, the present disclosure can be more clearly understood from the following detailed description, wherein:

[0028] Figure 1A A cross-sectional view of a multilayer printed circuit board 100 for interconnecting pins and a semiconductor die according to an embodiment of the present disclosure is schematically shown;

[0029] Figure 1B And Figure 1C schematically show Figure 1A a top view and a bottom view of the multi - layer printed circuit board 100 shown in

[0030] Figure 2A schematically show a front view of the pin 10 according to one or more embodiments of the present disclosure, Figure 2B show a side view of the pin 10;

[0031] Figure 3 show a schematic dimensional comparison between the conventional pin 20 and the pin 10 according to an embodiment of the present disclosure;

[0032] Figure 4 show an exemplary flowchart of a method 300 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure;

[0033] Figures 5A to 5E schematically show the Figure 4 schematic cross - sectional view of a device corresponding to some steps of the method shown;

[0034] Figure 6 show an exemplary flowchart of another method 300' for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure

[0035] Figure 7A show a schematic three - dimensional modeling model of a power module according to an embodiment of the present disclosure;

[0036] Figure 7B show Figure 7A a perspective view of some components in the multi - layer printed circuit board for interconnecting pins and semiconductor dies in the power module of

[0037] Figure 7C show Figure 7A a bottom view of the multi - layer printed circuit board for interconnecting pins and semiconductor dies in the power module of

[0038] Note that in the embodiments described below, sometimes the same reference numerals are used commonly between different drawings to denote the same part or parts having the same function, and their repeated description is omitted. In some cases, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0039] For ease of understanding, the positions, dimensions, ranges, etc. of the various structures shown in the drawings and the like sometimes do not represent the actual positions, dimensions, ranges, etc. Therefore, the present disclosure is not limited to the positions, dimensions, ranges, etc. disclosed in the drawings and the like. Detailed Embodiments

[0040] In applications in the automotive field, a pin interconnection process is often used when interconnecting a power module including a semiconductor die and a main circuit board (such as a printed circuit board). For example, first, the semiconductor die is attached to a carrier substrate, and a pin holder is mounted on the carrier substrate. Subsequently, pins are inserted into the pin holder on the carrier substrate and soldered by means such as reflow soldering. Finally, the semiconductor die and the carrier substrate are encapsulated with an insulating material such as epoxy resin to obtain a power module with pins, and the pins are used for further attachment to the main circuit board. However, various defects often exist in the pins and pin holders in the power module obtained through such a manufacturing process, such as poor soldering resulting in poor contact between the pins and the pin holders, damage or excessive inclination of the pin holders, solder overflow, and so on. These defects can lead to a decline in product performance or even render the product unusable, and thus need to be urgently solved.

[0041] To this end, the inventors of the present application have proposed a new technical solution for interconnecting pins and semiconductor dies, that is, using a dedicated multi-layer printed circuit board to interconnect the pins and the semiconductor die. Specifically, the multi-layer printed circuit board proposed in the present disclosure for interconnecting pins and semiconductor dies includes pin holders embedded therein and contacts for coupling to the semiconductor die. When it is necessary to interconnect the pins and the semiconductor die, first, the multi-layer printed circuit board is attached to the semiconductor die through its contacts, and then the pins are inserted into the pin holders in the multi-layer printed circuit board, thereby realizing the interconnection of the semiconductor die and the pins. In addition, other interconnection structures may be provided in the multi-layer printed circuit board proposed in the present disclosure for interconnecting pins and semiconductor dies, such that the multi-layer printed circuit board can provide other interconnection functions for the semiconductor die.

[0042] The following will refer to the drawings to describe in detail more specific embodiments of the new technical solution of the present disclosure for interconnecting pins and semiconductor dies. It should be noted that: unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present disclosure.

[0043] The following description of at least one exemplary embodiment is merely illustrative and is in no way a limitation on the present disclosure, its application, or its use. That is, the structures and methods herein are shown in an exemplary manner to illustrate different embodiments of the structures and methods in the present disclosure. However, those skilled in the art will understand that they are merely illustrative ways that can be used to implement the present disclosure, rather than exhaustive ways. In addition, the drawings do not have to be drawn to scale, and some features may be enlarged to show details of specific components.

[0044] Technologies, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered as part of the authorization specification.

[0045] In all examples shown and discussed herein, any specific values should be construed as merely exemplary, rather than as limitations. Thus, other examples of the exemplary embodiments may have different values.

[0046] Figure 1A A cross-sectional view of a multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure is schematically shown.

[0047] As Figure 1A described, the multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include a multilayer substrate 102, which is composed of a bottom substrate layer 104, one or more core substrate layers 106, and a top substrate layer 108 stacked in sequence. Each substrate layer includes an insulating material, which may include any material suitable for forming an insulating substrate layer of a printed circuit board, such as polyimide or epoxy resin, etc. In addition, the materials of the respective substrate layers of the multilayer substrate 102 may be the same or different from each other.

[0048] In a preferred embodiment, the hardness and mechanical strength of the bottom substrate layer 104 and the top substrate layer 108 may be superior to those of the core substrate layer 106, thereby providing better mechanical support for the entire multilayer printed circuit board 100.

[0049] Those skilled in the art will understand that although Figure 1A three core substrate layers 106 and the shapes, sizes, and thicknesses of the respective substrate layers are schematically shown, this is not intended to constitute any limitation. The multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include any number of core substrate layers, and the shapes, sizes, thicknesses, and materials of the respective substrate layers may be set arbitrarily according to needs.

[0050] Figure 1B and Figure 1Care schematically shown respectively Figure 1A a top view and a bottom view of the multi-layer printed circuit board 100 shown in Figure 1B in which details of the top substrate layer 108 are shown in more detail, while Figure 1C details of the bottom substrate layer 104 are shown in more detail. Figure 1A The cross-sectional view of Figure 1B and Figure 1C is taken along line A-A in

[0051] With reference to Figures 1A to 1C , the multi-layer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may further include: pin holders 110 embedded in the multi-layer substrate 102. One end of each pin holder 110 may be exposed from the top surface of the top substrate layer 108 for plugging pins into the pin holders. The multi-layer printed circuit board 100 according to an embodiment of the present disclosure may further include: die contacts 120 embedded in the multi-layer substrate 102, and first interconnect structures 130 embedded in the multi-layer substrate 102. As shown in Figure 1C , one end of each die contact 120 may be exposed from the bottom surface of the bottom substrate layer 104 for electrically coupling to the contacts of the semiconductor die. Each first interconnect structure 130 may be connected between the corresponding pin holder 110 and the corresponding die contact 120 for electrically coupling the two.

[0052] The multi-layer printed circuit board 100 according to an embodiment of the present disclosure embeds pin holders 110 for plugging pins and die contacts 120 for coupling semiconductor dies in its multi-layer substrate 102, and further interconnects the pin holders 110 and the die contacts 120 through the first interconnect structures 130. When using the multi-layer printed circuit board 100 according to the present disclosure to interconnect pins and semiconductor dies, by attaching the multi-layer printed circuit board 100 and the semiconductor die together through planar contact, and then inserting the pins into the pin holders 110 in the multi-layer printed circuit board 100, the interconnection of the pins and the semiconductor die can be achieved. Such an interconnection scheme can achieve many beneficial technical effects. On the one hand, compared with the prior art in which the pin holders are fixed above the carrier substrate, the scheme of the present disclosure embeds the pin holders 110 in the multi-layer substrate 102, making the pin holders 110 more stable and less likely to tilt, thus avoiding the problem of pin holder damage that may occur during the process of plugging pins. On the other hand, the multi-layer printed circuit board 100 and the semiconductor die are interconnected by planar contact, which can also improve the interconnection effect.

[0053] In one or more embodiments in accordance with the present disclosure, the pin retainer 110 may be electrically coupled to the corresponding die contact 120 via one or more first interconnect structures 130. For example, as Figure 1A shown, the leftmost pin retainer 110 in the figure is electrically coupled to the die contact 120 via one first interconnect structure 130, while another adjacent pin retainer 110 is electrically coupled to the die contact 120 via two first interconnect structures 130 respectively disposed between different core substrate layers.

[0054] In one or more embodiments in accordance with the present disclosure, the first interconnect structure 130 and the die contact 120 may be formed by various processes known in the art for manufacturing conductive components in printed circuit boards. For example, it may be formed by thin copper layers disposed between respective substrate layers, or may be formed by thick copper blocks embedded in the substrate layers through a thick copper embedding (also known as copper block embedding, Cu In-lay) process.

[0055] In one or more embodiments in accordance with the present disclosure, the die contact 120 may include a thick copper contact and / or a thin copper contact. The thick copper contact may be used as a source contact that needs to conduct a relatively large current, for example, while the thin copper contact may be used as a gate contact that only needs to conduct a relatively small current, for example. In a preferred embodiment, the die contact 120 may be used as one or more of the following: a gate-substrate contact, a source-substrate contact, a gate pad contact, and / or a source pad contact, etc.

[0056] Those skilled in the art will understand that although Figures 1A to 1C shows the number, distribution, shape, and size of the pin retainer 110, the die contact 120, and the corresponding first interconnect structure 130, this is not intended to constitute any limitation. The multi-layer printed circuit board 100 according to the embodiments of the present disclosure may include any number, any distribution, any shape, and any size of pin retainers 110, die contacts 120, and / or first interconnect structures 130. In addition, the die contact 120 and the first interconnect structure 130 according to the embodiments of the present disclosure are not limited to being formed of copper, but may include any material suitable for forming conductive contacts.

[0057] Continuing to refer to Figure 1A and Figure 1B , in one or more embodiments in accordance with the present disclosure, each pin retainer 110 may include a tubular cavity 112 and a first flange 114. The tubular cavity 112 may extend in a direction perpendicular to the multi-layer substrate 102 and is adapted to receive one end of the pin 10 therein. The first flange 114 may be disposed at one end of the tubular cavity 112 and protrude laterally with respect to the tubular cavity 112. As Figure 1AAs described in [reference], the first flange 114 is disposed above the top surface of the top substrate layer 108 and serves as one end of the pin holder 110 exposed from the top surface of the top substrate layer 108. To be adapted to insert the pin 10 into the pin holder, the inner diameter of the tubular cavity 112 of the pin holder 110 matches the diameter of the insertion end of the pin 10, and the first flange 114 can be formed as an annular ring having an inner diameter consistent with the inner diameter of the tubular cavity 112 and an outer diameter greater than the inner diameter, as Figure 1B clearly shown in

[0058] In an embodiment according to the present disclosure, by providing the first flange 114 at one end of the tubular cavity 112 of the pin holder 110, the pin holder 110 can be more firmly supported in the multilayer substrate 102 by means of the interaction between the first flange 114 and the top substrate layer 108.

[0059] Figure 2A A front view of the pin 10 according to one or more embodiments of the present disclosure is schematically shown, and the pin 10 is adapted to the pin holder 110 in the multilayer printed circuit board 100 according to an embodiment of the present disclosure. Figure 2B A side view of the pin 10 is shown.

[0060] As Figure 2A and Figure 2B shown, the pin 10 according to an embodiment of the present disclosure may include an elongated rod-shaped body 12. The first end of the rod-shaped body 12 is pointed and adapted to be inserted into the pin holder 110, and its second end includes an elastic portion 16 and is adapted to be snapped into a through hole, such as a through hole provided in the total circuit board (such as a printed circuit board) to which the pin is to be connected. The pin 10 may further include a stop portion 14, which is disposed at a position on the rod-shaped body 12 at a distance L1 from the first end and protrudes laterally with respect to the rod-shaped body 12. The distance L1 of the stop portion 14 from the first end of the rod-shaped body 12 may depend on the height of the pin holder. In a preferred embodiment, the distance L1 of the stop portion 14 from the first end of the rod-shaped body 12 may be the same as or slightly less than the height of the pin holder. In a preferred embodiment, the stop portion 14 may include two semi-cylindrical protrusions relatively disposed on opposite sides of the rod-shaped body 12, and the radius W1 of such semi-cylindrical protrusions may depend on the size of the flange of the pin holder, for example, may be equal to or slightly less than the width W0 of the annular flange of the pin holder (as Figure 1B shown in

[0061] In an embodiment according to the present disclosure, when the first end of the pin 10 is inserted into the pin holder 110, the stop portion 14 of the pin 10 can abut above the first flange 114 of the pin holder 110. On the one hand, the mutual abutment of the stop portion 14 of the pin 10 and the first flange 114 of the pin holder 110 can provide more mechanical support for the pin 10 (which will be discussed in more detail later), making the insertion of the pin 10 more secure. On the other hand, the stop portion 14 of the pin 10 can also prevent the pin 10 from being inserted too deeply into the pin holder, ensuring that the insertion depth of the pin 10 is appropriate.

[0062] Figure 3 A schematic dimensional comparison between a conventional pin 20 and a pin 10 according to an embodiment of the present disclosure is shown.

[0063] As described above, in the existing pin interconnection technology, the pin holder is disposed on the carrier substrate. However, in the embodiment of the present application, the pin holder is disposed in a multilayer printed circuit board attached above the semiconductor die. Therefore, on the premise that the overall thickness of the power module remains unchanged, the presence of the multilayer printed circuit board according to the embodiment of the present disclosure enables the height of the pin holder to be higher, while the pins can be shorter, and these changes can also improve the effect of pin interconnection.

[0064] As Figure 3 shown, the height H1 of the pin 10 according to an embodiment of the present disclosure can be less than the height H0 of the conventional pin 20. In a preferred embodiment, the height H1 of the pin 10 according to an embodiment of the present disclosure can be approximately 1.3 mm less than the height H0 of the conventional pin 20. This is because the thickness of the bottom substrate layer of the multilayer printed circuit board can be approximately 1 mm, and the total thickness of the semiconductor die and the die attachment layer for attaching the semiconductor die to the multilayer printed circuit board can be approximately 0.3 mm. Therefore, the height H1 of the pin 10 according to the embodiment of the present disclosure can be reduced by approximately 1 mm + 0.3 mm = 1.3 mm relative to the conventional pin.

[0065] Continue to refer to Figure 3, also schematically shows a conventional pin holder 22 plugged into the conventional pin 20 and a pin holder 110 according to an embodiment of the present disclosure plugged into the pin 10 according to an embodiment of the present disclosure. Among them, the height of the pin holder 22 is D0, and the height of the pin holder 110 is D1. When the pin 10 is plugged into the pin holder 110, if a lateral force F1 is applied to the top end of the pin 10, a corresponding force f1 will be applied to the part of the pin 10 plugged into the pin holder 110. It is desirable that this force f1 be as small as possible to avoid damage to the pin. The force f1 applied to the part of the pin 10 plugged into the pin holder 110 satisfies the formula: F1*(H1 - D1) = f1*D1, where H1 is the height of the pin 10 and D1 is the height of the pin holder 110. From this formula, it can be seen that the smaller the height of the pin and the larger the height of the pin holder, when a lateral force is applied to the top end of the pin, the corresponding force f1 applied to the part of the pin plugged into the pin holder is smaller. For example, the height H0 of the conventional pin 20 is 14.8 mm, and the height D0 of the corresponding pin holder 22 is 2.8 mm. Then the force f0 applied to the plugged part of the pin 20 is f0 = F0*(H0 - D0) / D0 = F0*(14.8 - 2.8) / 2.8 ≈ 4.29F0. In contrast, the height H1 of the pin 10 according to the present disclosure is 13.5 mm, and the height D0 of the corresponding pin holder 110 is 4.5 mm. Based on the above formula, the force f1 applied to the plugged part of the pin 10 is f1 = F1*(13.5 - 4.5) / 4.5 ≈ 2.22F1, which is reduced by about 51.7% compared to the conventional pin.

[0066] Back to Figures 1A to 1C , the multilayer printed circuit board 100 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may further include auxiliary connectors 140A / 140B embedded in the multilayer substrate 102 and extending in a direction perpendicular to the multilayer substrate 102. One end of each auxiliary connector is electrically coupled to the corresponding pin holder 110, and the other end is electrically connected to the corresponding die contact 120.

[0067] In one or more embodiments according to the present disclosure, as Figure 1A shown, each auxiliary connector 140A / 140B may include a columnar body 144 and a second flange 142 provided at one end of the columnar body 144. The columnar body 144 may extend in a direction perpendicular to the multilayer substrate 102 to connect to the die contact 120. The second flange 142 projects laterally with respect to the columnar body 144.

[0068] As Figure 1A and Figure 1BAs shown, the multi-layer printed circuit board 100 according to an embodiment of the present disclosure may further include flange interconnects 146, and each flange interconnect 146 may be connected between the second flange 142 of the corresponding auxiliary connector 140A / 140B and the corresponding pin holder 110, thereby electrically coupling the corresponding auxiliary connector 140A / 140B to the corresponding pin holder 110.

[0069] In one or more embodiments according to the present disclosure, the auxiliary connector may include a first auxiliary connector 140A, and the second flange 142 of the first auxiliary connector 140A and the flange interconnect 146 connected thereto are disposed between the top substrate layer 108 and the adjacent core substrate layer 106. The flange interconnect 146 connected to the second flange 142 of the first auxiliary connector 140A may also be connected to the tubular cavity 112 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the first auxiliary connector 140A.

[0070] Since the flange interconnect 146 connected to the second flange 142 of the first auxiliary connector 140A is disposed below the top substrate layer 108, Figure 1B the flange interconnect cannot be seen in the top view of the top substrate layer 108 shown originally. However, for clearly showing its shape, the flange interconnect 146 in the perspective state is shown by a dashed line in the Figure 1B top view.

[0071] In a preferred embodiment, the second flange 142 of the first auxiliary connector 140A and the corresponding flange interconnect 146 connected to each other may be integrally formed by the same layer of metal.

[0072] In one or more embodiments according to the present disclosure, the auxiliary connector may include a second auxiliary connector 140B, and the second flange 142 of the second auxiliary connector 140B and the flange interconnect 146 connected thereto are disposed on the top surface of the top substrate layer 108. The flange interconnect 146 connected to the second flange 142 of the second auxiliary connector 140B may also be connected to the first flange 114 of the corresponding pin holder 110, thereby electrically coupling the corresponding pin holder 110 to the second auxiliary connector 140B.

[0073] In a preferred embodiment, the second flange 142 of the second auxiliary connector 140B, the corresponding flange interconnect 146, and the first flange 114 of the corresponding pin holder 110 connected to each other are integrally formed by the same layer of metal.

[0074] In one or more embodiments according to the present disclosure, the first flange of a pin holder may be respectively connected to the second flanges of a plurality of auxiliary connectors through a plurality of flange interconnects. AsFigure 1B As described in , the first flange 114' of the pin holder is respectively connected to the second flanges 142' of the two auxiliary connectors 140B' through two flange interconnects 146' extending in opposite directions, so that the pin holder can be electrically connected to at least two auxiliary connection connectors 140B' and thus electrically coupled to at least two die contacts.

[0075] Those skilled in the art will understand that although Figures 1A to 1C the first auxiliary connector 140A and the second auxiliary connector 140B are shown in , this is not intended to impose any limitation. The multilayer printed circuit board 100 according to an embodiment of the present disclosure may include only the first auxiliary connector 140A, may include only the second auxiliary connector 140B, or may include both the first auxiliary connector 140A and the second auxiliary connector 140B.

[0076] In one or more embodiments according to the present disclosure, the pin holder 110 can be electrically coupled to the die contact through the first interconnect structure and can also be electrically coupled to the die contact via the flange interconnect and the auxiliary connector. This provides great flexibility for the interconnect design of the multilayer printed circuit board, enabling various different interconnect structures to be flexibly arranged in the multilayer printed circuit board according to application requirements, making full use of the area and space, and reducing hardware consumption.

[0077] Continuing to refer to Figure 1A and Figure 1B , in one or more embodiments according to the present disclosure, the multilayer printed circuit board 100 may further include a second interconnect structure 150 embedded in the multilayer substrate 102. Each second interconnect structure 150 can be connected between at least two die contacts 120 for electrically coupling these die contacts together. The second interconnect structure 150 can be formed by various processes known in the art for manufacturing conductive components in printed circuit boards. For example, it can be formed by a thin copper layer disposed between the respective substrate layers, or can be formed by a thick copper block embedded in the substrate layer through a thick copper embedding (also known as copper block embedding, CuIn - lay) process.

[0078] In a preferred embodiment, at least a part of the first interconnect structure 130, the second interconnect structure 150, and / or the die contacts 120 according to an embodiment of the present disclosure is formed by a thick copper embedding process.

[0079] In the multilayer printed circuit board 100 according to an embodiment of the present disclosure, in addition to the connection structures (such as the first interconnect structure 130, the auxiliary connectors 140A / 140B, the flange connectors 146, etc.) for connecting the pin holders 110 and the die contacts 120, an interconnect structure (such as the second interconnect structure 150) for realizing the connection between the respective die contacts 120 may also be included. The second interconnect structure 150 enables pinless interconnection of the respective contacts of the semiconductor die to be attached through the multilayer printed circuit board 100, which provides an additional possible connection method between the respective contacts of the semiconductor die, thereby bringing more possibilities to the design of the entire power module.

[0080] Those skilled in the art will understand that although Figures 1A to 1C the number, distribution, shape, and size of the auxiliary connectors 140A / 140B, the flange interconnects 146, and the second interconnect structure 150, etc. are shown, this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to an embodiment of the present disclosure may include any number, any distribution, any shape, and any size of the auxiliary connectors 140A / 140B, the flange interconnects 146, and / or the second interconnect structure 150, etc. In addition, the flange interconnects 146 and the second interconnect structure 150 according to an embodiment of the present disclosure are not limited to being made of copper, but may include any material suitable for forming conductive components.

[0081] Continuing to refer to Figures 1A to 1C , the multilayer printed circuit board 100 according to an embodiment of the present disclosure may also optionally include buried spacers 160, which are disposed at idle positions in the multilayer substrate 102 where no other conductive components are provided, and are made of an insulating material having a certain mechanical strength for enhancing the mechanical support for the multilayer printed circuit board 100. As Figure 1A shown, each buried spacer 160 extends from the bottom surface of the top substrate layer 108 through the core substrate layer 106 and the bottom substrate layer 104, and extends beyond the bottom surface of the bottom substrate layer 104 by a first length, which may depend on the thickness of the semiconductor die to which the multilayer printed circuit board 100 is to be attached.

[0082] In a preferred embodiment, when the multilayer printed circuit board 100 is attached to the semiconductor die, one end of the buried spacer 160 extending beyond the bottom substrate layer 104 abuts against a support structure for supporting the semiconductor die to enhance the mechanical support for the multilayer printed circuit board 100. Therefore, the first length of the buried spacer 160 extending beyond the bottom substrate layer 104 may be equal to or slightly greater than the sum of the thickness of the semiconductor die and the thickness of the die attachment layer, where the die attachment layer refers to the material layer for attaching the semiconductor die to the multilayer printed circuit board.

[0083] Continue to refer to Figures 1A to 1C According to an embodiment of the present disclosure, the multilayer printed circuit board 100 may further optionally include a negative temperature coefficient (NTC) contact 170 embedded in the multilayer substrate 102. The negative temperature coefficient contact 170 may be exposed from an opening 180 provided at the central portion of the bottom substrate layer 104 for coupling to a negative temperature coefficient sensor. A temperature sensor may be provided in the opening 180 for detecting the temperature of the power module.

[0084] Those skilled in the art will understand that although Figures 1A to 1C the number, distribution, shape, and size of the buried spacers 160 and the negative temperature coefficient contacts 170, etc. are shown, this is not intended to constitute any limitation. The multilayer printed circuit board 100 according to an embodiment of the present disclosure may include any number, any distribution, any shape, and any size of buried spacers 160 and negative temperature coefficient contacts 170, etc.

[0085] Those skilled in the art will understand that although Figures 1A to 1C the multilayer printed circuit board 100 shown in Figures 1A to 1C includes various different components, this is only for showing various different components as comprehensively as possible in the same set of drawings, and is not intended to constitute any limitation. The multilayer printed circuit board 100 according to an embodiment of the present disclosure may only include Figures 1A to 1C a part of the various components shown in

[0086] Moreover, those skilled in the art will also understand that although Figure 1A the multilayer printed circuit board 100 shown in Figure 1A includes various different components in the same cross-sectional view, this is only for showing various different components as comprehensively as possible in the same drawing, and is not intended to constitute any limitation. The various different components of the multilayer printed circuit board 100 according to an embodiment of the present disclosure may not appear in the same cross-sectional view, so the cross-sectional view of the multilayer printed circuit board 100 may only include

[0087] Next, a method for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure will be described in conjunction with Figure 4 and Figures 5A to 5E Among them, Figure 4 shows an exemplary flowchart of a method for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure, and Figures 5A to 5E schematically shows in conjunction with Figure 4Schematic cross-sectional view of an apparatus corresponding to some steps of the method shown. Those skilled in the art will understand that the method for interconnecting pins and semiconductor dies described in connection with Figure 4 and Figures 5A to 5E is performed using a multi-layer printed circuit board according to an embodiment of the present disclosure for interconnection, and thus the corresponding description of the multi-layer printed circuit board also applies herein.

[0088] As Figure 4 shown, a method 300 for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include step S310, step S320, step S330, and step S340.

[0089] At step S310, as Figure 5A shown, a semiconductor die 200 is attached to a carrier substrate 30. In an embodiment according to the present disclosure, the carrier substrate 30 may be a ceramic substrate covered with copper, such as a direct bond copper (DBC) ceramic substrate or an active metal brazing (AMB) ceramic substrate, etc., or any other type of carrier substrate.

[0090] In one or more embodiments according to the present disclosure, the semiconductor die 200 may include a plurality of contacts 202 and 204. In a preferred embodiment, the smaller area contact 204 may include a gate contact, and the larger area contact 202 may include a source contact.

[0091] Those skilled in the art will understand that although the number, distribution, shape, and size of the contacts of the semiconductor die 200 are schematically shown in FIG. 2, this is not intended to constitute any limitation. The semiconductor die 200 according to an embodiment of the present disclosure may include contacts of any number, any distribution, any shape, and any size.

[0092] At step S320, a multi-layer printed circuit board 100 according to an embodiment of the present disclosure is attached to the semiconductor die 200.

[0093] In one or more embodiments according to the present disclosure, attaching the multi-layer printed circuit board 100 to the semiconductor die 200 may be achieved through steps S322, S324, and S326 described below.

[0094] At step S322, as Figure 5B shown, an attachment material 206 is coated on the contacts 202 and 204 of the semiconductor die 200. The attachment material 206 may include, for example, sintering material, solder, gel, etc.

[0095] At step S324, as Figure 5CAs shown in [FIGURE], a multilayer printed circuit board 100 is placed on a semiconductor die 200 such that the contacts 120 exposed from the bottom substrate layer 104 of the multilayer printed circuit board 100 are in contact with the contacts 202 and 204 of the semiconductor die 200 via an attachment material 206.

[0096] In a preferred embodiment, a negative temperature coefficient contact 170 may be coupled to a negative temperature coefficient sensor 208.

[0097] In a preferred embodiment, one end of the buried spacer 160 of the multilayer printed circuit board 100 that protrudes from the bottom substrate layer 104 abuts against the carrier substrate 30 below the semiconductor die 200, thereby providing better mechanical support for the multilayer printed circuit board 100.

[0098] At step S326, a sintering, soldering, and / or curing process is performed to cure the attachment material 206, thereby fixedly attaching the multilayer printed circuit board 100 and the semiconductor die 200 together. In a preferred embodiment, as Figure 5C shown, a sintering tool 40 may be used to press the printed circuit board 200 against the semiconductor die 200, thereby enhancing the strength of the attachment.

[0099] Continuing to refer to Figure 4 , at step S330, the pins 10 are inserted into the pin holders 110 of the multilayer printed circuit 100, as Figure 5D shown.

[0100] At step S340, as Figure 5E shown, the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100 are encapsulated or potted with epoxy resin to form a housing 50, thereby obtaining a packaged power module.

[0101] Figure 4 The execution order of steps S310 and S320 of the method 300 for interconnecting pins and a semiconductor die shown in [FIGURE] can be interchanged. Figure 6 [FIGURE] shows another method 300' for interconnecting pins and a semiconductor die according to an embodiment of the present disclosure, which is a variant embodiment of the method 300 for interconnecting pins and a semiconductor die shown in [FIGURE]. Compared with Figure 4 the method 300 in [FIGURE], the main difference of the method 300' shown in Figure 4 [FIGURE] is that step S320 is performed first and then step S310. Except for the difference in the execution order of the steps, the content described above regarding Figure 6 the method 300 in [FIGURE] can be applied to the corresponding features of the method 300' shown in Figure 4 [FIGURE]. Figure 6 shown.

[0102] As Figure 6 shown, the method 300' for interconnecting pins and semiconductor dies according to an embodiment of the present disclosure may include step S320, step S310, step S330, and step S340.

[0103] At step S320, a multilayer printed circuit board 100 according to an embodiment of the present disclosure is attached to the semiconductor die 200.

[0104] At step S310, the semiconductor die 200 is attached to the carrier substrate 30.

[0105] At step S330, the pins 10 are inserted into the pin holders 110 of the multilayer printed circuit 100.

[0106] At step S340, the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100 are encapsulated or potted with epoxy resin to form a housing 50, thereby obtaining a packaged power module.

[0107] Figure 5E Schematically shows a power module according to one or more embodiments of the present disclosure, which can be manufactured, for example, by Figure 4 the method 300 for interconnecting pins and semiconductor dies shown, or by Figure 6 the method 300' for interconnecting pins and semiconductor dies shown.

[0108] As Figure 5E shown, the power module may include: a carrier substrate 30; a semiconductor die 200 disposed on the carrier substrate 30; a multilayer printed circuit board 100 according to one or more embodiments of the present disclosure, disposed on the semiconductor die 200 and electrically coupled to the semiconductor die 200 through its die contacts; a housing 40 encapsulating the carrier substrate 30, the semiconductor die 200, and the multilayer printed circuit board 100; and pins 10 inserted into the pin holders in the multilayer printed circuit board 100 and exposed from one side of the housing 50.

[0109] Figure 7A Shows a schematic three-dimensional modeling model of a power module according to an embodiment of the present disclosure. Refer to Figure 7A , shows the packaged power module, where the pins 10 are exposed from one side of the housing 50 for further coupling to a main circuit board.

[0110] Figure 7B Shows Figure 7A a perspective view of some components in the multilayer printed circuit board for interconnecting pins and semiconductor dies in the power module of Figure 7B, showing pin 10, pin holder 110, auxiliary connector 140, and flange interconnect 146, and also showing gate contact 120a and source contact 120b that serve as die contacts.

[0111] Figure 7C Shows Figure 7A The bottom perspective view of the multilayer printed circuit board for interconnecting pins and semiconductor dies in the power module of. As Figure 7C shown, the multilayer printed circuit board according to an embodiment of the present disclosure includes source-substrate contact 120c, gate-substrate contact 120d, source pad contact 120e, and gate pad contact 120f that are exposed from the bottom substrate layer and serve as die contacts, and negative temperature coefficient contact 170 that is exposed from the openings of the bottom substrate layer.

[0112] Those skilled in the art will understand that the above Figures 7A to 7C shown modeling models are only for the convenience of those skilled in the art to better understand the technical concept of the present invention and are not intended to constitute any limitation.

[0113] In the specification and claims, words such as "front", "rear", "top", "bottom", "above", "below", etc., if any, are used for descriptive purposes and not necessarily for describing invariant relative positions. It should be understood that such words are interchangeable under appropriate circumstances, so that the embodiments of the present disclosure described herein, for example, can operate in other orientations different from those shown or otherwise described herein.

[0114] As used herein, the word "exemplary" means "serving as an example, instance, or illustration", rather than as a "model" to be precisely replicated. Any implementation described herein exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Moreover, the present disclosure is not limited by any theory expressed or implied in the above technical field, background art, summary of the invention, or detailed description.

[0115] As used herein, the word "substantially" means including any minor variations caused by design or manufacturing defects, tolerances of devices or components, environmental impacts, and / or other factors. The word "substantially" also allows for differences from the perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in actual implementations.

[0116] Additionally, the foregoing description may have referred to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element / node / feature is directly connected (or directly communicates) to another element / node / feature electrically, mechanically, logically, or otherwise. Similarly, unless otherwise expressly stated, "coupled" means that one element / node / feature can be connected to another element / node / feature either directly or indirectly mechanically, electrically, logically, or otherwise to allow interaction, even if the two features may not be directly connected. That is, "coupled" is intended to encompass both direct and indirect connections of elements or other features, including connections using one or more intermediate elements.

[0117] Additionally, solely for purposes of reference, terms such as "first", "second", etc. may also be used herein and are thus not intended to be limiting. For example, unless the context clearly indicates otherwise, the words "first", "second", and other such numerical words referring to a structure or element do not imply an order or sequence.

[0118] It should also be understood that when the term "comprising / including" is used herein, it specifies the presence of the stated features, wholes, steps, operations, units, and / or components, but does not preclude the presence or addition of one or more other features, wholes, steps, operations, units, and / or components and / or combinations thereof.

[0119] In the present disclosure, the term "provide" is used broadly to encompass all ways of obtaining an object, and thus "providing an object" includes, but is not limited to, "purchasing", "preparing / manufacturing", "arranging / setting", "installing / assembling", and / or "ordering" the object, etc.

[0120] Those skilled in the art should recognize that the boundaries between the above operations are merely illustrative. Multiple operations can be combined into a single operation, a single operation can be distributed over additional operations, and operations can be performed at least partially overlapping in time. Moreover, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be varied in various other embodiments. However, other modifications, variations, and substitutions are also possible. Accordingly, the specification and drawings should be regarded as illustrative rather than restrictive.

[0121] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art should understand that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The embodiments disclosed herein can be combined arbitrarily without departing from the spirit and scope of the present disclosure. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A multi-layer printed circuit board for interconnecting pins and semiconductor dies, characterized in that, Comprising: A multi-layer substrate including a bottom substrate layer, one or more core substrate layers, and a top substrate layer stacked in sequence, each substrate layer being made of an insulating material; Pin holders embedded in the multi-layer substrate, one end of each pin holder being exposed from the top surface of the top substrate layer for inserting pins into the pin holders; Die contacts embedded in the multi-layer substrate, one end of each die contact being exposed from the bottom surface of the bottom substrate layer for electrically coupling to the contacts of a semiconductor die; And A first interconnect structure embedded in the multi-layer substrate, each first interconnect structure connecting between a corresponding pin holder and a corresponding die contact for electrically coupling the two.

2. The multilayer printed circuit board according to claim 1, wherein Each pin holder includes: A tubular cavity extending in a direction perpendicular to the multi-layer substrate and adapted to receive one end of a pin therein; and A first flange provided at one end of the tubular cavity and protruding laterally with respect to the tubular cavity, the first flange being disposed above the top surface of the top substrate layer.

3. The multilayer printed circuit board according to claim 2, wherein, Further comprising: Auxiliary connectors embedded in the multi-layer substrate and extending in a direction perpendicular to the multi-layer substrate, one end of each auxiliary connector being electrically coupled to a corresponding pin holder and the other end being electrically connected to a corresponding die contact, Wherein each auxiliary connector includes: A columnar body extending in a direction perpendicular to the multi-layer substrate; and A second flange provided at one end of the columnar body and protruding laterally with respect to the columnar body.

4. The multilayer printed circuit board according to claim 3, wherein Further comprising: Flange interconnects, each flange interconnect connecting between the second flange of a corresponding auxiliary connector and a corresponding pin holder for electrically coupling the two.

5. The multi-layer printed circuit board according to claim 4, wherein Among them, The auxiliary connector includes a first auxiliary connector, the second flange of the first auxiliary connector and the flange interconnect connected thereto being disposed between the top substrate layer and an adjacent core substrate layer; and Wherein the flange interconnect connected to the second flange of the first auxiliary connector is also connected to the tubular cavity of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the first auxiliary connector.

6. The multi-layer printed circuit board according to claim 5, wherein Among them, The second flange of the first auxiliary connector and the corresponding flange interconnect connected thereto are integrally formed by the same layer of metal.

7. The multilayer printed circuit board according to claim 4, Characterized in that Wherein the auxiliary connector includes a second auxiliary connector, the second flange of the second auxiliary connector and the flange interconnect connected thereto being disposed above the top surface of the top substrate layer; and Wherein the flange interconnect connected to the second flange of the second auxiliary connector is also connected to the first flange of the corresponding pin holder, thereby electrically coupling the corresponding pin holder to the second auxiliary connector.

8. The multi-layer printed circuit board according to claim 7, wherein Among them, The second flange of the second auxiliary connector, the corresponding flange interconnect, and the first flange of the corresponding pin holder connected thereto are integrally formed by the same layer of metal.

9. The multilayer printed circuit board according to claim 1, wherein, Further comprising: A second interconnect structure, embedded in the multilayer substrate, with each second interconnect structure connected between at least two die contacts for electrically coupling the at least two die contacts.

10. The multilayer printed circuit board according to claim 9, wherein Among them, At least a portion of the first interconnect structure, the second interconnect structure, and / or the die contacts are formed by a thick copper embedding process.

11. The multilayer printed circuit board according to claim 1, wherein Further comprising: A buried spacer, with each buried spacer extending from the bottom surface of the top substrate layer through the one or more core substrate layers and the bottom substrate layer, and extending beyond the bottom surface of the bottom substrate layer by a first length, wherein the first length depends on the thickness of the semiconductor die.

12. The multilayer printed circuit board according to claim 11, wherein Among them, The first length is equal to the sum of the thickness of the semiconductor die and the thickness of the die attach layer for attaching the semiconductor die to the multilayer printed circuit board.

13. The multilayer printed circuit board according to claim 1, characterized in that, Further comprising: A negative temperature coefficient contact, embedded in the multilayer substrate, with the negative temperature coefficient contact exposed from an opening provided at the central portion of the bottom substrate layer for coupling to a negative temperature coefficient sensor.

14. The multilayer printed circuit board according to any one of claims 1 to 13, wherein Among them, The die contacts include thick copper contacts and / or thin copper contacts; and wherein the die contacts serve as one or more of the following: gate-substrate contacts, source-substrate contacts, gate pad contacts, and / or source pad contacts.

15. A pin, characterized in that, Comprising: A rod-shaped body, with the first end of the rod-shaped body being pointed and adapted to be inserted into a pin holder, and the second end of the rod-shaped body including an elastic portion and adapted to be inserted into a through hole; And A stop portion, provided at a position on the rod-shaped body at a certain distance from the first end and protruding laterally with respect to the rod-shaped body, wherein the pin is adapted to be mounted in a pin holder in the multilayer printed circuit board according to any one of claims 2 to 14, and wherein when the first end of the pin is inserted into the pin holder, the stop portion abuts above a first flange of the pin holder.

16. A power module, characterized in that, Comprising: A carrier substrate; A semiconductor die, attached to the carrier substrate; The multilayer printed circuit board according to any one of claims 1 to 14, attached to the semiconductor die and electrically coupled to the semiconductor die through die contacts of the multilayer printed circuit board; A housing, encapsulating the carrier substrate, the semiconductor die, and the multilayer printed circuit board; And Pins, inserted into pin holders in the multilayer printed circuit board and exposed from one side of the housing.

17. A method for interconnecting pins and a semiconductor die, characterized in that, Comprising the following steps: Attaching a semiconductor die to a carrier substrate; Attaching the multilayer printed circuit board according to any one of claims 1 to 14 to the semiconductor die; Inserting pins into pin holders in the multilayer printed circuit board; And Encapsulating the carrier substrate, the semiconductor die, and the multilayer printed circuit board with an insulating material to form a housing.

18. The method according to claim 17, wherein Attaching the multi-layer printed circuit board to the semiconductor die includes the following steps: Coating an attachment material on the contacts of the semiconductor die; Placing the multi-layer printed circuit board on the semiconductor die such that the contacts of the bottom substrate layer of the multi-layer printed circuit board are in contact with the contacts of the semiconductor die via the attachment material; and Performing a sintering, soldering, and / or curing process to cure the attachment material.

19. A method for interconnecting pins and a semiconductor die, characterized in that, Includes the following steps: Attaching the multi-layer printed circuit board according to any one of claims 1 to 14 to the semiconductor die; Attaching the semiconductor die to a carrier substrate; Inserting pins into pin holders in the multi-layer printed circuit board; And Encapsulating the carrier substrate, the semiconductor die, and the multi-layer printed circuit board with an insulating material to form a housing.

20. The method according to claim 19, characterized in that Attaching the multi-layer printed circuit board to the semiconductor die includes the following steps: Coating an attachment material on the contacts of the semiconductor die; Placing the multi-layer printed circuit board on the semiconductor die such that the contacts of the bottom substrate layer of the multi-layer printed circuit board are in contact with the contacts of the semiconductor die via the attachment material; and Performing a sintering, soldering, and / or curing process to cure the attachment material.

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