Semiconductor device and preparation method thereof, and storage system

Abstract

The invention discloses a semiconductor device, a preparation method thereof and a storage system. The semiconductor device includes: an isolation structure; the grid assemblies and the isolation structures are alternately distributed in the first direction, each grid assembly comprises two grid structures oppositely arranged in the first direction, the isolation structures and the grid structures extend in the second direction, and the extension length of the grid structures is larger than that of the isolation structures; wherein in the second direction, the gate assembly comprises a first sub-portion close to the end portion of the isolation structure and a second sub-portion away from the end portion, in the third direction, the depth of the first sub-portion is smaller than that of the second sub-portion, and the first direction, the second direction and the third direction intersect in pairs.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of semiconductor technology, and particularly to semiconductor devices, their manufacturing methods, and storage systems. Background Art

[0002] A memory is a memory device used to store information in modern information technology. Its main function is to store programs and various data, and can quickly and automatically complete the access of programs or data during the operation of a computer. Taking a dynamic random access memory (DRAM) as an example, a DRAM usually includes multiple memory cells, and each memory cell includes a transistor and a capacitor.

[0003] Currently, how to further improve the yield of semiconductor devices such as DRAMs is one of the technical problems that those skilled in the art urgently need to solve. Summary of the Invention

[0004] The semiconductor device, its manufacturing method, and storage system provided by the embodiments of the present application can solve or partially solve the above-mentioned deficiencies in the prior art or other deficiencies in the prior art.

[0005] According to the semiconductor device provided in the first aspect of the present application, it includes:

[0006] An isolation structure; and

[0007] A gate assembly, which is alternately distributed with the isolation structure along a first direction. The gate assembly includes two gate structures oppositely arranged along the first direction. The isolation structure and the gate structure both extend along a second direction, and the extension length of the gate structure is greater than the extension length of the isolation structure;

[0008] Wherein, in the second direction, the gate assembly includes a first sub - part near the end of the isolation structure and a second sub - part far from the end. In a third direction, the depth of the first sub - part is less than the depth of the second sub - part. The first direction, the second direction, and the third direction intersect pairwise.

[0009] According to the manufacturing method of the semiconductor device provided in the second aspect of the present application, it includes:

[0010] Forming gate trenches and isolation structures that are alternately distributed along a first direction; and

[0011] Forming a gate assembly in the gate trenches. The gate assembly includes two gate structures oppositely arranged along the first direction. The gate structure and the isolation structure both extend along a second direction, and the extension length of the gate structure is greater than the extension length of the isolation structure;

[0012] Wherein, in the second direction, the gate assembly includes a first sub - portion near the end of the isolation structure and a second sub - portion far from the end. In the third direction, the depth of the first sub - portion is less than the depth of the second sub - portion, and the first direction, the second direction, and the third direction intersect pairwise.

[0013] According to the storage system provided in the third aspect of the present application, the storage system includes a controller and the semiconductor device described above. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0014] In the semiconductor device provided by the embodiment of the present application, the depth of the first sub - portion of the gate assembly is less than the depth of the second sub - portion. The first sub - portion is close to the end of the isolation structure, and the second sub - portion is far from the isolation structure. Therefore, compared with the case where the depths of the first sub - portion and the second sub - portion are the same, when the depth of the first sub - portion is less than the depth of the second sub - portion, the characteristic dimension of the bottom surface of the first sub - portion, that is, the width along the first direction, is larger. Thus, the punching process can easily separate the two gate structures at the first sub - portion, thereby avoiding the problem of leakage due to the failure to completely separate the two gate structures.

[0015] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the detailed description of the non - restrictive embodiments with reference to the following drawings, other features, objectives, and advantages of the present application will become more obvious. The drawings are used to better understand the solution and do not constitute a limitation to the present application. In the drawings:

[0017] Figure 1 is a top - view schematic diagram of a semiconductor device according to an embodiment of the present application;

[0018] Figure 2 is Figure 1 one of the cross - sectional schematic diagrams at A - A;

[0019] Figure 3 is Figure 1 another cross - sectional schematic diagram at A - A;

[0020] Figures 4 to 18 is a process schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0021] Figure 19 is a flow schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application; and

[0022] Figure 20 It is a block diagram of a system with semiconductor devices according to an embodiment of the present application.

[0023] Reference numerals:

[0024] 100, isolation structure; 101, third trench; 110, isolation conductive layer;

[0025] 120, first isolation layer; 121, filling insulating layer; 122, isolation dielectric layer;

[0026] 200, gate assembly; 201, first sub - part; 202, second sub - part;

[0027] 203, gate trench; 204, second gap; 210, gate structure;

[0028] 211, gate insulating layer; 212, gate conductive layer; 213, initial gate layer;

[0029] 220, gate isolation layer; 300, insulating part; 301, second trench; 302, groove;

[0030] 303, first part; 304, second part; 310, first insulating layer;

[0031] 320, second insulating layer; 321, first gap; 400, semiconductor layer;

[0032] 410, initial semiconductor pillar; 500, mask layer; 600, third dielectric layer;

[0033] 700, system; 701, memory system; 702, semiconductor device;

[0034] 703, memory controller; 704, host. Detailed implementation manners

[0035] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0036] It should be noted that in this specification, the expressions such as first, second, third, etc. are only used to separate one feature from another feature region and do not represent any limitation on the features, especially do not represent any order of precedence.

[0037] In the accompanying drawings, for ease of illustration, the thickness, dimensions, and shape of the components have been slightly adjusted. The drawings are provided only by way of example and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms of approximation and not of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0038] It should also be understood that expressions such as "comprises", "comprising", "has", "including", and / or "including having" are open-ended and not closed-ended expressions in this specification, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence of one or more other features, elements, components, and / or combinations thereof. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just individual elements in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0039] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0040] It should be noted that, without conflict, the embodiments and features in the embodiments of this application may be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recited order and may be executed in any order or executed in parallel. The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0041] In addition, in this application, the term "layer" refers to a portion of a material that includes a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope less than the scope of the structure below or above. In addition, the layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers. In addition, when using "connected" or "coupled" in this application, it may indicate direct or indirect contact between the corresponding components, unless there is a clear other limitation or can be deduced from the context.

[0042] With the rapid development of memory technology, the storage cell size of DRAM is getting smaller and smaller, and its array architecture has changed from 8F2 Developed to 6F 2 , and then from 6F 2 Developed to 4F 2 . The architecture of the memory has evolved from planar array transistors to recess gate array transistors, then from recess gate array transistors to buried saddle Fin array transistors, and then from buried saddle Fin array transistors to vertical gate transistors.

[0043] DRAM generally includes multiple memory cells. Each memory cell includes a transistor and a capacitor. Adjacent transistors are separated by an isolation structure. Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0. Whether it is a planar transistor, a recess gate array transistor, a buried transistor, or a vertical gate transistor, they all include a gate structure, a source electrode, a drain electrode, and a channel. The drain electrode of the transistor is electrically connected to the bit line (BL), the source electrode of the transistor is electrically connected to one electrode plate of the capacitor, and the other electrode plate of the capacitor can be grounded or connected to a reference voltage. The gate structure of the transistor is electrically connected to the word line (WL). The word line is used to apply a voltage to control the on or off of the transistor, and the bit line is used to perform read or write operations on the capacitor when the transistor is on.

[0044] Taking the vertical gate transistor as an example, vertical gate transistors are divided into single-gate transistors, double-gate transistors, triple-gate transistors, and all-around gate transistors. The MSG transistor (mirror single gate transistor) is a type of single-gate transistor. An isolation structure is provided between two adjacent MSG transistors in a semiconductor device. The gate structure of the MSG transistor is located on the side of its channel away from the isolation structure, and the gate structures of two adjacent MSG transistors are mirror-symmetrically distributed with respect to the isolation structure. As Figure 1 and Figure 2 shown, the embodiments of the present application provide a method for manufacturing the above-mentioned semiconductor device. The manufacturing method includes: forming long trenches and short trenches that are alternately distributed along a first direction (x direction), and both the long trenches and the short trenches extend along a second direction (y direction); forming an isolation structure 100 in the short trenches; depositing a thin gate insulating layer 211 on the inner wall of the long trenches; forming an initial gate layer 213 on the surface of the gate insulating layer 211; using a punching process (punch) to remove the bottom of the initial gate layer 213 to divide the initial gate layer 213 into two gate conductive layers; filling the remaining space in the long trenches with an insulating material.

[0045] However, due to the limitations of the etching process, whether it is a long trench or a short trench, the critical dimension (CD) gradually decreases along the third direction (z-direction), i.e., the etching depth direction, and the bottom surface of the trench is an arc surface rather than a plane. During the process of etching the long trench, due to the loading effect, the etching depth in the area of the long trench near the end of the short trench is relatively shallow, and the critical dimension of the long trench in this area, that is, the width of the long trench along the first direction (x-direction), is smaller than that in other areas. This results in that after the gate insulating layer 211 is formed on the inner wall of the long trench, the thickness of the bottom of the gate insulating layer 211 in this area is thinner, while the thickness of the bottom in other areas is thicker. Therefore, the bottom surface of the gate insulating layer 211 in this area is still arc-shaped, while the bottom surface in other areas is flat. Although the height of the bottom surface of the initial gate layer 213 is basically the same in each area after the initial gate layer 213 is formed on the surface of the gate insulating layer 211 subsequently, it is difficult to completely separate the part of the initial gate layer 213 in this area by the punching process, which further leads to a leakage problem between the two gate conductive layers.

[0046] To solve the above problems, as Figure 19 shown, the embodiment of the present application provides another preparation method 1000 of a semiconductor device, and the preparation method includes:

[0047] S100: Form gate trenches 203 and isolation structures 100 that are alternately distributed along the first direction (see Figure 13 );

[0048] S200: Form a gate assembly 200 in the gate trenches 203. The gate assembly 200 includes two gate structures 210 that are oppositely arranged along the first direction (x-direction). The gate structures 210 and the isolation structures 100 both extend along the second direction (y-direction), and the extension length of the gate structures 210 is greater than the extension length of the isolation structures 100 (see Figure 18 ).

[0049] Wherein, in the second direction (y-direction), the gate assembly 200 includes a first sub-part 201 near the end of the isolation structure 100 and a second sub-part 202 far from the end. In the third direction (z-direction), the depth of the first sub-part 201 is less than the depth of the second sub-part 202. The first direction, the second direction, and the third direction intersect pairwise. As an example, the first direction, the second direction, and the third direction are perpendicular to each other pairwise. The first direction may be the x-direction in the drawing, the second direction may be the y-direction in the drawing, and the third direction may be the z-direction in the drawing.

[0050] As described above, due to the limitations of the etching process, the feature size of the trench gradually decreases along the third direction (z direction), so that the feature size of the gate assembly 200 formed in the trench also gradually decreases along the third direction (z direction). And since the depth of the first sub - part 201 of the gate assembly 200 in the embodiment of the present application is less than the depth of the second sub - part 202, the first sub - part 201 is close to the end of the isolation structure 100, and the second sub - part 202 is far from the isolation structure 100. Therefore, compared with the case where the depths of the first sub - part 201 and the second sub - part 202 are the same, when the depth of the first sub - part 201 is less than the depth of the second sub - part 202, the feature size of the bottom surface of the first sub - part 201, that is, the width along the first direction (x direction), is larger. Thus, the punching process can easily separate the two gate structures 210 at the first sub - part 201, thereby avoiding the problem of leakage caused by the failure to completely separate the two gate structures 210.

[0051] The following specifically introduces each step in the method for manufacturing a semiconductor device in the embodiment of the present application.

[0052] Step S100

[0053] In step S100, gate trenches 203 and isolation structures 100 that are alternately distributed along the first direction (x direction) are formed in the semiconductor layer 400. The gate trenches 203 and the isolation structures 100 both extend along the second direction (y direction), and the extension length of the gate trenches 203 is greater than the extension length of the isolation structures 100.

[0054] As an example, step S100 may include: forming insulating parts 300 and isolation structures 100 that are alternately distributed along the first direction (x direction). Specifically, as Figure 4 shown, from the first surface of the semiconductor layer 400, second trenches 301 and third trenches 101 that are alternately distributed along the first direction (x direction) are formed in the semiconductor layer 400. The second trenches 301 and the third trenches 101 both extend along the second direction (y direction), and the extension length of the second trenches 301 is greater than the extension length of the third trenches 101; as Figure 8 shown, isolation structures 100 are formed in the third trenches 101; as Figure 10 shown, insulating parts 300 are formed in the second trenches 301. The insulating parts 300 include a first part 303 close to the end of the isolation structure 100 and a second part 304 far from the end; next, a part of the first part 303 and a part of the second part 304 of the insulating parts 300 are removed. Specifically, as Figure 11As shown, a groove 302 can be formed by first removing a part of the second part 304 of the insulating portion 300. For example, a patterned mask layer 500 can be formed on one side of the insulating portion 300 and the isolation structure 100, and the mask layer 500 has an opening corresponding to the second part 304. Through the opening, 40 nm to 70 nm of the second part 304 is removed along the third direction (z direction); the mask layer 500 is removed; then, as Figure 12 shown, a part of the first part 303 and the remaining part of the second part 304 are removed synchronously, so that the removal depth of the first part 303 along the third direction (z direction) is less than the removal depth of the second part 304 along the third direction (z direction). Thus, a space for removing a part of the first part 303 and the second part 304 forms a gate trench 203. At this time, the bottom surface of the gate trench 203 is the top surface of the remaining insulating portion 300, and the height of the first part 303 of the remaining insulating portion 300 along the third direction (z direction) is greater than the height of its second part 304 along the third direction (z direction). And as known from the above, due to the limitation of the etching process, the feature size of the second trench 301 gradually decreases along the third direction (z direction). Thus, compared with the case where the heights of the first part 303 and the second part 304 are the same, the fact that the height of the first part 303 is higher than the height of the second part 304 can make the feature size of the bottom surface of the gate trench 203, that is, the width along the first direction (x direction), larger, so that the gate conductive layer 212 here can be easily separated by the punching process subsequently.

[0055] In some embodiments, the insulating portion 300 may include a first insulating layer 310 and a second insulating layer 320. Thus, during the process of removing a part of the insulating portion 300, as Figure 10 shown, a patterned mask layer 500 can be formed on one side of the insulating portion 300 and the isolation structure 100, and the mask layer 500 has an opening corresponding to the second part 304; as Figure 11 shown, through the opening, a part of the first insulating layer 310 in the second part 304 is removed along the third direction to form a groove 302; the mask layer 500 is removed; as Figure 12 shown, a part of the first insulating layer 310 in the first part 303 and the remaining second part 304 are removed synchronously; as Figure 13 shown, then a part of the second insulating layer 320 in the first part 303 and the second part 304 is removed synchronously, so that the exposed surfaces of the first insulating layer 310 and the second insulating layer 320 are flush at the same position.

[0056] As an example, in the case where the insulating portion 300 includes a first insulating layer 310 and a second insulating layer 320, the insulating portion 300 can be formed in the second trench 301 in the following manner: as Figure 8As shown, a second insulating layer 320 is formed on the inner wall of the second groove 301, and the second insulating layer 320 surrounds to form a first gap 321; as Figure 9 shown, a first insulating layer 310 is formed in the first gap 321. Among them, the materials of the first insulating layer 310 and the second insulating layer 320 may but are not limited to include silicon oxide, silicon oxynitride or silicon nitride, and the materials of the first insulating layer 310 and the second insulating layer 320 may be the same or different. If the materials of the first insulating layer 310 and the second insulating layer 320 are the same, then there is no obvious interface between the first insulating layer 310 and the second insulating layer 320. Among them, the first insulating layer 310 and the second insulating layer 320 can be formed in the second groove 301 by a thin film deposition process, and the thin film deposition process may but is not limited to a physical vapor deposition (Physical Vapor Deposition, abbreviated as PVD) process, a chemical vapor deposition (Chemical Vapor Deposition, abbreviated as CVD) process, an atomic layer deposition (Atomic Layer Deposition, abbreviated as ALD) process or a combination of any several of the above processes. In addition, since the first insulating layer 310 and the second insulating layer 320 will cover the first surface of the semiconductor layer 400 during the actual deposition process of the first insulating layer 310 and the second insulating layer 320, after the deposition process is completed, a chemical mechanical polishing (Chemical Mechanical Polishing, CMP) process can be used to remove the portions of the first insulating layer 310 and the second insulating layer 320 covering the first surface.

[0057] In addition, to improve the isolation effect of the isolation structure 100 and reduce the electrical interference between two adjacent transistors, the isolation structure 100 can be formed in the following manner: the second trench 301 and the third trench 101 are filled with a sacrificial material; the sacrificial material in the third trench 101 is removed; a second isolation material is deposited in the third trench 101 to form a second isolation layer (not shown) having an air gap; the sacrificial material in the second trench 301 is removed. Specifically, the second isolation material can be deposited in the third trench 101 at two different deposition rates. In other words, a part of the second isolation layer can be formed on the inner wall of the third trench 101 at a first deposition rate, and at the same time, another part of the second isolation layer can be formed at the opening of the third trench 101 at a second deposition rate greater than the first deposition rate. Since the second deposition rate is greater than the first deposition rate, when these two parts are deposited simultaneously, the second isolation material at the opening of the third trench 101 will quickly seal the opening. However, due to the slower first deposition rate, there is still some space in the third trench 101 that is not filled with the second isolation material after sealing, thereby forming an air gap. Since the air gap has a low dielectric constant, and its dielectric constant is close to that of a vacuum, the presence of the air gap can reduce the overall dielectric constant of the second isolation layer, thereby reducing the parasitic capacitance and thus reducing the electrical interference between two adjacent transistors. During the formation of the air gap, the size and position of the air gap can be adjusted by controlling the first deposition rate and the second deposition rate. The larger the ratio between the second deposition rate and the first deposition rate, the larger the air gap formed in the second isolation layer, and the better the effect of reducing the parasitic capacitance. For example, the range of the ratio α between the second deposition rate and the first deposition rate can be 1 ≤ α ≤ 3. As an example, the range of the ratio α can be 1.5 ≤ α ≤ 2. In addition, those skilled in the art should understand that without departing from the technical solution claimed in the present application, the structure, composition, and generation process of the second isolation layer having an air gap can be changed to obtain the various results and advantages described in this specification.

[0058] It should be noted that in addition to improving the isolation effect through the air gap, the isolation structure 100 can also improve the isolation effect by providing an isolation conductive layer 110, and subsequently improve the coupling effect between two adjacent transistors by grounding or connecting a negative voltage to the isolation conductive layer 110.

[0059] When the isolation structure 100 includes the isolation conductive layer 110, the isolation structure 100 can be formed in the following manner: the second trench 301 and the third trench 101 are filled with a sacrificial material; the sacrificial material in the third trench 101 is removed; as Figure 5 shown, an isolation dielectric layer 122 is formed on the inner wall of the third trench 101; an isolation conductive layer 110 is formed in the gap surrounded by the isolation dielectric layer 122; as Figure 6As shown, a part of the isolation conductive layer 110 is removed to expose part of the sidewalls of the gap; as Figure 7 and Figure 8 shown, a filling insulating material is formed in the remaining space of the gap to form a filling insulating layer 121, and the sacrificial material in the second trench 301 is removed.

[0060] It should be noted that when the width of the second trench 301 in the first direction (x direction) is greater than the width of the third trench 101 in the first direction (x direction), the second insulating layer 320 and the filling insulating layer 121 can be formed synchronously. For example, after removing a part of the isolation conductive layer 110 during the process of forming the isolation structure 100, the sacrificial material in the second trench 301 can be removed first, and then insulating materials can be deposited in the second trench 301 and the third trench 101 simultaneously. Since the width of the second trench 301 in the first direction (x direction) is greater than the width of the third trench 101 in the first direction (x direction), when a relatively thin layer of insulating material covers the inner wall of the second trench 301, the remaining space in the third trench 101 has been filled with insulating material. At this time, as Figure 7 shown, the insulating material covering the inner wall of the second trench 301 constitutes the second insulating layer 320, and the insulating material filled in the third trench 101 constitutes the filling insulating layer 121.

[0061] Figure 1 FIG. shows a top view schematic diagram of a semiconductor device in an embodiment of the present application; Figure 14 FIG. shows Figure 13 a cross-sectional schematic diagram in a plane parallel to the first direction (x direction) and the second direction (y direction) along the center line of the gate trench 203 in FIG.

[0062] As Figure 1 and Figure 14As shown, in order to divide the semiconductor layer 400 into a plurality of initial semiconductor pillars 410, before forming the insulating portion 300 and the isolation structure 100, the manufacturing method further includes: forming a plurality of first trenches (not shown) spaced apart along the second direction (y direction) in the semiconductor layer 400 from the first surface of the semiconductor layer 400, the first trenches extending along the first direction (x direction); forming a third dielectric layer 600 in the first trenches. Thus, after the second trench 301 and the third trench 101 are formed subsequently, the second trench 301 and the third trench 101 intersect the first trenches respectively, dividing a part of the semiconductor layer 400 into a plurality of initial semiconductor pillars 410. At this time, the third dielectric layer 600 covers two sidewalls of the initial semiconductor pillar 410 oppositely arranged along the second direction (y direction). Subsequently, semiconductor pillars can be formed based on the initial semiconductor pillars 410, and the semiconductor pillars include a channel and a source electrode and a drain electrode respectively located on both sides of the channel along the third direction (z direction). For example, a source electrode can be formed based on one end of the initial semiconductor pillar 410 away from the second surface of the semiconductor layer 400; the semiconductor layer 400 is thinned from the second surface of the semiconductor layer 400 to expose one end of the initial semiconductor pillar 410 away from the first surface; a drain electrode is formed based on one end of the initial semiconductor pillar 410 away from the first surface. Among them, the source electrode and the drain electrode can be formed by doping the ends of the initial semiconductor pillar 410.

[0063] Step S200

[0064] In step S200, a gate assembly 200 is formed in the gate trench 203. The gate assembly 200 includes two gate structures 210 oppositely arranged along the first direction (x direction) and a gate isolation layer 220 located between the two gate structures 210. Among them, the gate structure 210 includes a gate insulating layer 211 and a gate conductive layer 212, and the gate conductive layer 212 is located on the side of the gate insulating layer 211 facing the gate isolation layer 220 along the first direction. The material of the gate insulating layer 211 can include but is not limited to silicon oxide, silicon oxynitride or silicon nitride, and the material of the gate conductive layer 212 can include but is not limited to polysilicon, tungsten, aluminum, titanium, copper, cobalt, tungsten nitride or a combination of any of the above.

[0065] As an example, step S200 may include: as Figure 15 shown, a gate insulating layer 211 is formed on the sidewall of the gate trench 203 extending along the third direction (z direction), and the gate insulating layer 211 and the remaining insulating portion 300 enclose and form a second gap 204; as Figure 16 shown, an initial gate layer 213 is formed on the inner wall of the second gap 204; as Figure 17 shown, the part of the initial gate layer 213 in contact with the insulating portion 300 is removed to divide the initial gate layer 213 into two gate conductive layers 212; as Figure 18As shown, a gate isolation layer 220 is formed in the remaining space of the gate trench 203. Among them, the material of the gate insulating layer 211 can include, but is not limited to, silicon oxide, silicon oxynitride, or silicon nitride. When the material of the gate insulating layer 211 is silicon oxide, the gate insulating layer 211 can be formed by oxidizing the semiconductor layer 400, or can be directly deposited with silicon oxide in the gate trench 203 through a thin film deposition process.

[0066] According to the above, the height of the first part 303 of the remaining insulating portion 300 of the gate trench 203 along the third direction (z direction) is greater than the height of its second part 304 along the third direction (z direction). Thus, in the region of the end of the gate trench 203 close to the isolation structure 100, compared with the case where the heights of the first part 303 and the second part 304 are the same, the height of the first part 303 is higher than the height of the second part 304, so that the characteristic dimension of the bottom surface of the gate trench 203, that is, the width along the first direction, is larger. Therefore, after the initial gate layer 213 is formed in the gate trench 203, the part of the initial gate layer 213 close to the end of the isolation structure 100 can be easily separated by a punching process. Thus, not only the punching process window of the initial gate layer 213 is increased, but also the process window for leading out the connection contacts of the gate conductive layer 212 and the isolation conductive layer 110 from the back surface of the semiconductor layer 400 is increased.

[0067] In order to improve the adhesion between the gate conductive layer 212 and the gate insulating layer 211, before forming the gate conductive layer 212 on the inner wall of the first gap 321, a gate adhesion layer can also be formed on the side wall of the first gap 321 extending along the third direction. Among them, the material of the gate adhesion layer includes at least one of titanium nitride, tantalum nitride, and tungsten carbide.

[0068] In addition, the preparation method can also include: forming a bit line extending along the first direction on the side of the drain far from the source. Specifically, a conductive layer can be formed on the side of the drain far from the source; forming a plurality of fourth trenches (not shown) penetrating the conductive layer, the fourth trenches extending along the first direction and corresponding to the first trenches one by one, to divide the conductive layer into a plurality of bit lines, and the bit lines are connected to a plurality of drains distributed along the first direction. Among them, the material of the bit line can include, but is not limited to, at least one of tungsten, titanium nitride, copper, and silver. Additionally, the preparation method can also include: forming a capacitor connected to the source on the side of the source far from the drain.

[0069] As Figure 1 and Figure 18As shown in the figure, an embodiment of the present application further provides a semiconductor device. The semiconductor device includes isolation structures 100 and gate assemblies 200 that are alternately distributed along a first direction (x direction). The gate assemblies 200 include two gate structures 210 that are oppositely arranged along the first direction (x direction). The isolation structures 100 and the gate structures 210 both extend along a second direction (y direction), and the extension length of the gate structures 210 is greater than the extension length of the isolation structures 100. Among them, in the second direction (y direction), the gate assembly 200 includes a first sub - part 201 near the end of the isolation structure 100 and a second sub - part 202 far from the end. In the third direction (z direction), the depth of the first sub - part 201 is less than the depth of the second sub - part 202. The first direction, the second direction, and the third direction intersect pairwise.

[0070] In some embodiments, the semiconductor device further includes an insulating part 300 located on one side of the gate assembly 200 along the third direction (z direction). The insulating part 300 extends along the second direction (y direction). In the first direction (x direction), the size of the insulating part 300 close to the gate assembly 200 is greater than its size far from the gate assembly 200. In other words, the insulating part 300 is located below the gate assembly 200. Among them, the insulating part 300 includes a first part 303 and a second part 304 distributed along the second direction (y direction). The first part 303 is connected to the first sub - part 201, and the second part 304 is connected to the second sub - part 202. In the third direction, the depth of the first part 303 is greater than the depth of the second part 304. As an example, as Figure 14 shown, the difference h between the depth of the first part 303 and the depth of the second part 304 is 40 nm to 70 nm. For example, h can be 45 nm, 50 nm, 55 nm, or 60 nm.

[0071] In some embodiments, along the third direction (z direction), the surface of the second sub - part 202 close to the second part 304 is located between the surface of the first sub - part 201 close to the first part 303 and the surface of the first part 303 far from the first sub - part 201. In other words, the position of the surface of the first sub - part 201 close to the first part 303 is higher than the position of the surface of the second sub - part 202 close to the second part 304. Among them, the height difference in the third direction between the surface of the first sub - part 201 close to the first part 303 and the surface of the second sub - part 202 close to the second part 304 is 40 nm to 70 nm.

[0072] In some embodiments, the sum of the depths of the first sub - part 201 and the first part 303 in the third direction is less than the sum of the depths of the second sub - part 202 and the second part 304 in the third direction.

[0073] In some embodiments, the insulating portion 300 may be formed of one insulating material or multiple insulating materials. For example, the insulating portion 300 may include a first insulating layer 310 and a second insulating layer 320. The first insulating layer 310 extends in the second direction, and the second insulating layer 320 covers the sidewalls of the first insulating layer 310 extending in three directions and the surface of the first insulating layer 310 facing away from the gate assembly 200. Among them, the materials of the first insulating layer 310 and the second insulating layer 320 may but are not limited to include silicon oxide, silicon oxynitride, or silicon nitride. If the materials of the first insulating layer 310 and the second insulating layer 320 are the same, there is no obvious interface between the first insulating layer 310 and the second insulating layer 320. In other words, the insulating portion 300 is a structure formed by depositing one insulating material. If the materials of the first insulating layer 310 and the second insulating layer 320 are different, then the insulating portion 300 is formed of multiple materials.

[0074] In some embodiments, the gate assembly 200 includes two gate structures 210 disposed opposite to each other along the first direction (x direction) and a gate isolation layer 220 located between the two gate structures 210. Among them, the gate structure 210 includes a gate insulating layer 211 and a gate conductive layer 212. The gate insulating layer 211 extends in the second direction (y direction), and the gate conductive layer 212 is located on the side of the gate insulating layer 211 facing the gate isolation layer 220 along the first direction (x direction). Among them, the materials of the gate insulating layer 211 and the gate isolation layer 220 may be the same or different, and this application does not make a limitation in this regard. In addition, in order to improve the adhesion between the gate conductive layer 212 and the gate insulating layer 211, a gate adhesion layer may also be provided between the gate insulating layer 211 and the gate conductive layer 212.

[0075] In addition, the isolation structure 100 in the embodiments of the present application may have various structural forms:

[0076] Form 1. The isolation structure 100 may include an isolation conductive layer 110 and a first isolation layer 120. The isolation conductive layer 110 extends along the second direction (y direction), and the first isolation layer 120 surrounds the isolation conductive layer 110. Thus, subsequently, by grounding the isolation conductive layer 110 or connecting it to a negative voltage, the coupling effect between two adjacent transistors can be improved, thereby reducing the electrical interference between two adjacent transistors. Among them, the first isolation layer 120 may be formed of one isolation material or may be formed of multiple isolation materials. For example, the first isolation layer 120 includes a filling insulating layer 121 and an isolation dielectric layer 122. The filling insulating layer 121 is located on one side of the isolation conductive layer 110 along the third direction (z direction). In the first direction (x direction), the size of the isolation conductive layer 110 close to the filling insulating layer 121 is larger than its size away from the filling insulating layer 121. In other words, the isolation conductive layer 110 is located below the filling insulating layer 121, and the isolation dielectric layer 122 covers the side wall of the isolation conductive layer 110 extending along the first direction and the surface of the isolation conductive layer 110 facing away from the filling insulating layer 121.

[0077] Form 2. The isolation structure 100 includes a second isolation layer (not shown) extending along the second direction, and the second isolation layer has an air gap. Since the air gap has a low dielectric constant, and its dielectric constant is close to that of a vacuum, the presence of the air gap can reduce the overall dielectric constant of the second isolation layer, thereby reducing the parasitic capacitance and further reducing the electrical interference between two adjacent transistors.

[0078] In addition, the embodiment of the present application further provides a storage system, which includes a controller and the above semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0079] Figure 20 The block diagram of a system with a semiconductor device according to an embodiment of the present application is shown. The system 700 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle-mounted computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a storage device therein. As Figure 20 shown, the system 700 may include a host 704 and a memory system 701. The memory system 701 has one or more semiconductor devices 702 and a memory controller 703. The host 704 may be a processor of the electronic device. For example, a central processing unit (CPU), or may be a system-on-chip 700 (SoC), for example, an application processor (AP). The host 704 may be configured to send data to or receive data from the semiconductor device 702.

[0080] The semiconductor device 702 can be any semiconductor device disclosed in the present application, such as Figure 18 the semiconductor device shown. According to some embodiments, the memory controller 703 is coupled to the semiconductor device 702 and the host 704, and is configured to control the semiconductor device 702. The memory controller 703 can manage the data stored in the semiconductor device 702 and communicate with the host 704.

[0081] In some embodiments, the memory controller 703 is designed to operate in a low-duty-cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 703 is designed to operate in a high-duty-cycle environment, such as a Solid State Drive (SSD) or an Embedded Multimedia Card (eMMC), which are used as data storage devices for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays. The memory controller 703 can be configured to control the operations of the semiconductor device 702, such as read, erase, and program operations. The memory controller 703 can also be configured to manage various functions related to the data stored in or to be stored in the semiconductor device 702, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 703 is further configured to process an Error Correction Code (ECC) related to the data read from or written to the semiconductor device 702. Any other appropriate functions can also be performed by the memory controller 703, for example, formatting the semiconductor device 702. The memory controller 703 can communicate with an external device (e.g., the host 704) according to a specific communication protocol. For example, the memory controller 703 can communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a High-Speed PCI (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a FireWire protocol, etc.

[0082] It should be understood that the various forms of the processes shown above can be used, with steps reordered, added, or deleted. As an example, the steps recited in the disclosure of the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions disclosed in the present application can be achieved, and this is not limited herein.

[0083] The above specific embodiments do not constitute a limitation on the protection scope of this application. Those skilled in the art should understand that various modifications, combinations, sub - combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims

1. A semiconductor device, characterized in that, Including: Isolation structure; And A gate assembly, alternately distributed with the isolation structure along a first direction, the gate assembly includes two gate structures oppositely arranged along the first direction, both the isolation structure and the gate structure extend along a second direction, and the extension length of the gate structure is greater than that of the isolation structure; Wherein, in the second direction, the gate assembly includes a first sub - portion near the end of the isolation structure and a second sub - portion far from the end, in a third direction, the depth of the first sub - portion is less than that of the second sub - portion, and the first direction, the second direction and the third direction intersect pairwise.

2. The semiconductor device according to claim 1, wherein, The semiconductor device further includes: An insulating portion, located on one side of the gate assembly along the third direction and extending along the second direction, in the first direction, the size of the insulating portion close to the gate assembly is greater than its size far from the gate assembly; Wherein, the insulating portion includes a first portion and a second portion distributed along the second direction, the first portion is connected to the first sub - portion, the second portion is connected to the second sub - portion, and in the third direction, the depth of the first portion is greater than that of the second portion.

3. The semiconductor device according to claim 2, wherein, The difference between the depth of the first portion and the depth of the second portion is 40nm - 70nm.

4. The semiconductor device according to claim 2, wherein, Along the third direction, the surface of the second sub - portion close to the second portion is located between the surface of the first sub - portion close to the first portion and the surface of the first portion far from the first sub - portion, and the height difference between the surface of the first sub - portion close to the first portion and the surface of the second sub - portion close to the second portion in the third direction is 40nm - 70nm.

5. The semiconductor device according to claim 2, wherein, The sum of the depths of the first sub - portion and the first portion in the third direction is less than the sum of the depths of the second sub - portion and the second portion in the third direction.

6. The semiconductor device according to claim 2, wherein, The insulating portion includes: A first insulating layer, extending along the second direction; and A second insulating layer, covering the side wall of the first insulating layer extending along the third direction and the surface of the first insulating layer facing away from the gate assembly.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The gate assembly further includes a gate isolation layer located between the two gate structures; Wherein, the gate structure includes: A gate insulating layer, extending along the second direction; and A gate conductive layer, located on the side of the gate insulating layer facing the gate isolation layer along the first direction.

8. The semiconductor device according to claim 7, wherein, The gate structure may further include: A gate adhesion layer, located between the gate insulating layer and the gate conductive layer.

9. The semiconductor device according to any one of claims 1 to 6, wherein, The isolation structure includes: An isolation conductive layer, extending along the second direction; and A first isolation layer, surrounding the isolation conductive layer.

10. The semiconductor device according to claim 9, wherein, The first isolation layer includes: A filling insulating layer, located on one side of the isolation conductive layer along the third direction, in the first direction, the size of the isolation conductive layer close to the filling insulating layer is greater than its size far from the filling insulating layer; and An isolation dielectric layer, covering the side wall of the isolation conductive layer extending along the first direction and the surface of the isolation conductive layer facing away from the filling insulating layer.

11. The semiconductor device according to any one of claims 1 to 6, wherein, The isolation structure includes: A second isolation layer extending along the second direction and having an air gap.

12. The semiconductor device according to any one of claims 1 to 6, wherein, A plurality of semiconductor pillars are further disposed between the isolation structure and the gate assembly, spaced apart along the second direction.

13. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming gate trenches and isolation structures alternately distributed along a first direction; And Forming a gate assembly in the gate trenches, the gate assembly including two gate structures oppositely disposed along the first direction, the gate structures and the isolation structures both extending along the second direction, and the extension length of the gate structures being greater than the extension length of the isolation structures; Wherein, in the second direction, the gate assembly includes a first sub - portion near the end of the isolation structure and a second sub - portion away from the end, and in the third direction, the depth of the first sub - portion is less than the depth of the second sub - portion, and the first direction, the second direction, and the third direction intersect pairwise.

14. The method for manufacturing a semiconductor device according to claim 13, wherein, Forming gate trenches and isolation structures alternately distributed along a first direction includes: Forming insulating portions and the isolation structures alternately distributed along the first direction, the insulating portions including a first part near the end of the isolation structure and a second part away from the end; and Removing part of the first part and part of the second part to form the gate trenches; Wherein, the removal depth of the first part along the third direction is less than the removal depth of the second part along the third direction.

15. The method for manufacturing a semiconductor device according to claim 14, wherein, Removing part of the first part and part of the second part includes: Removing part of the second part to form a groove; and Simultaneously removing part of the first part and the remaining part of the second part to form the gate trenches.

16. The method for manufacturing a semiconductor device according to claim 15, wherein, Removing part of the second part to form a groove includes: Forming a patterned mask layer on one side of the insulating portion and the isolation structure, the mask layer having an opening corresponding to the second part; Removing a part of the second part through the opening; and Removing the mask layer.

17. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein, Before forming the insulating portions and the isolation structures alternately distributed along the first direction, the preparation method further includes: Forming a plurality of first trenches spaced apart along the second direction on a first side of the semiconductor layer, the first trenches extending along the first direction; and Forming a third dielectric layer in the first trenches.

18. The method for manufacturing a semiconductor device according to claim 17, wherein, Forming insulating portions and the isolation structures alternately distributed along the first direction includes: Forming second trenches and third trenches alternately distributed along the first direction on a first side of the semiconductor layer, the second trenches and the third trenches both extending along the second direction, and the extension length of the second trenches being greater than the extension length of the third trenches; Forming the insulating portions in the second trenches; and Forming the isolation structures in the third trenches.

19. The method for manufacturing a semiconductor device according to claim 18, wherein, Forming insulating portions in the second trenches includes: Forming a second insulating layer on the inner wall of the second trenches, the second insulating layer surrounding to form a first gap; and Forming a first insulating layer in the first gap; Wherein, the insulating portions include the first insulating layer and the second insulating layer.

20. The method for manufacturing a semiconductor device according to any one of claims 14 to 16, wherein, Forming a gate assembly in the gate trenches includes: A gate insulating layer is formed on a sidewall of the gate trench extending in the third direction, and the gate insulating layer and the remaining insulating portion enclose a second gap; An initial gate layer is formed on an inner wall of the second gap; A portion of the initial gate layer in contact with the insulating portion is removed to divide the initial gate layer into two gate conductive layers; and A gate isolation layer is formed in a remaining space of the gate trench; Wherein, the gate structure includes the gate conductive layer and the gate insulating layer.

21. The method for manufacturing a semiconductor device according to claim 20, wherein, Before forming the gate conductive layer on the inner wall of the first gap, the manufacturing method further includes: Forming a gate adhesion layer on a sidewall of the first gap extending in the third direction.

22. A storage system, characterized in that, The storage system includes a controller and the semiconductor device according to any one of claims 1 to 12, the controller is coupled to the semiconductor device and is configured to control the semiconductor device to store data.

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