Three-dimensional memory and electronic equipment

Abstract

The embodiment of the invention provides a three-dimensional memory and electronic equipment, the three-dimensional memory comprises a first chip and a second chip which are arranged along a third direction, the first chip comprises a memory array area and a non-memory array area, and the second chip comprises a peripheral control area; the projection of the peripheral control area in the third direction covers the non-storage array area; the non-memory array area of the first chip comprises a plurality of resistor structures, and the first end and the second end of each resistor structure are coupled to the second chip.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and in particular, to a three-dimensional memory and an electronic device. Background Art

[0002] A wafer on wafer (WoW) structure refers to integrating all the devices in a memory onto two chips, namely a memory array chip and a logic chip. In the WoW structure, a delay unit is generally located in the peripheral circuit area of the logic chip. However, arranging a resistor in the delay unit in the logic chip requires an additional resistor structure area, resulting in a waste of the memory area. Summary of the Invention

[0003] Embodiments of the present disclosure provide a three-dimensional memory and an electronic device.

[0004] In a first aspect, embodiments of the present disclosure provide a three-dimensional memory. The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a memory array area and a non-memory array area, and the second chip includes a peripheral control area. A projection of the peripheral control area along the third direction covers the non-memory array area.

[0005] The non-memory array area of the first chip includes a plurality of resistor structures. A first end and a second end of each resistor structure are both coupled to the second chip.

[0006] In some embodiments, the peripheral control area in the second chip includes a plurality of inverters, and the plurality of resistor structures correspond to the plurality of inverters one by one.

[0007] The first end of the resistor structure is coupled to the first end of the corresponding inverter, the second end of the resistor structure is coupled to the second end of the corresponding inverter, and the resistor structure and the inverter together form a delay unit.

[0008] In some embodiments, a surface of the first chip close to the second chip includes a plurality of first bonding pairs, and a surface of the second chip close to the first chip includes a plurality of second bonding pairs. The plurality of resistor structures correspond to the plurality of first bonding pairs one by one, and the plurality of resistor structures correspond to the plurality of second bonding pairs one by one.

[0009] The first end of the resistor structure is sequentially coupled to the first end of the corresponding inverter via a first bonding structure in the corresponding first bonding pair and a third bonding structure in the corresponding second bonding pair.

[0010] The second end of the resistor structure is coupled to the second end of the corresponding inverter via the second bonding structure in the corresponding first bonding pair and the fourth bonding structure in the corresponding second bonding pair in sequence.

[0011] In some embodiments, the resistor structure includes N + 2 first metal structures and N second metal structures. The first metal structures extend along a second direction, and the second metal structures extend along a first direction; N is an integer greater than 0, and the first direction and the second direction intersect.

[0012] A plurality of the first metal structures are located on a first wiring layer of the first chip, and a plurality of the second metal structures are located on a second wiring layer of the first chip; the first wiring layer of the first chip and the second wiring layer of the first chip are arranged in sequence along the third direction.

[0013] Wherein, the first end of the first one of the first metal structures forms the first end of the resistor structure, the second end of the i-th first metal structure is electrically connected to the first end of the i-th second metal structure, the second end of the i-th second metal structure is electrically connected to the first end of the (i + 1)-th first metal structure, and the second end of the last one of the first metal structures forms the second end of the resistor structure; i is an integer greater than 0 and less than or equal to N.

[0014] In some embodiments, the first metal structures have two types, which are respectively referred to as first sub-metal structures and second sub-metal structures.

[0015] The first sub-metal structures and the second sub-metal structures are fabricated using a double patterning technique DPT.

[0016] In some embodiments, both the first sub-metal structures and the second sub-metal structures extend along the second direction, and each first sub-metal structure and each second sub-metal structure are arranged alternately along the first direction.

[0017] In some embodiments, for each of the first sub-metal structures, it is electrically connected to two adjacent second metal structures respectively through two first contact structures.

[0018] For each of the second sub-metal structures, it is electrically connected to two adjacent second metal structures respectively through two second contact structures.

[0019] Wherein, along the first direction, the first contact structures and the second contact structures are arranged alternately in sequence; along the second direction, two first contact structures are arranged, or two second contact structures are arranged.

[0020] In some embodiments, the storage array region includes a plurality of storage cells, and each storage cell includes a capacitor and a transistor;

[0021] The first wiring layer of the first chip is further configured to form a landing contact structure for the capacitor in the storage cell.

[0022] In some embodiments, the three-dimensional memory is a dynamic random access memory (DRAM).

[0023] In a second aspect, an embodiment of the present disclosure provides an electronic device, which includes the three-dimensional memory according to any one of the first aspect.

[0024] An embodiment of the present disclosure provides a three-dimensional memory and a memory. The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a storage array region and a non-storage array region, and the second chip includes a peripheral control region. The projection of the peripheral control region along the third direction covers the non-storage array region. The non-storage array region of the first chip includes a plurality of resistor structures, and the first end and the second end of each resistor structure are both coupled to the second chip. In this way, by fabricating a plurality of resistor structures in the non-storage array region of the first chip and coupling each resistor structure to the second chip, the area can be saved. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of the composition structure of a chip structure Figure 1 ;

[0026] Figure 2 Schematic diagram of the composition structure of a chip structure Figure 2 ;

[0027] Figure 3 Schematic diagram of the composition structure of a delay unit;

[0028] Figure 4 Schematic diagram of the composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 1 ;

[0029] Figure 5 Schematic diagram of the composition structure of a three-dimensional memory provided by an embodiment of the present disclosure Figure 2 ;

[0030] Figure 6 Schematic diagram of the composition structure of a resistor structure provided by an embodiment of the present disclosure Figure 1 ;

[0031] Figure 7 Schematic diagram of a double patterning technology (DPT) process provided by an embodiment of the present disclosure;

[0032] Figure 8Schematic diagram of the composition structure of a resistor structure provided by an embodiment of the present disclosure Figure 2 ;

[0033] Figure 9 Schematic diagram of the composition structure of another type of resistor structure provided by an embodiment of the present disclosure;

[0034] Figure 10 Schematic diagram of the composition structure of an electronic device provided by an embodiment of the present disclosure. Detailed implementation manners

[0035] Next, the technical solutions in the embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present disclosure. It can be understood that the specific embodiments described herein are only used to explain the related applications, rather than limiting the present disclosure. In addition, it should be noted that for the convenience of description, only parts related to the related applications are shown in the drawings.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

[0037] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it can be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0038] It should be noted that the terms "first / second / third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that "first / second / third" can be interchanged with a specific order or sequence when allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0039] See Figure 1 , which shows a schematic diagram of the composition structure of a chip structure Figure 1 . As Figure 1As shown, the chip structure is specifically a one - wafer structure 10. The one - wafer structure 10 includes a cell array area 111 and a peripheral area 112. The cell array area 111 is distributed on both sides of the peripheral area 112. In the one - wafer structure 10, the cell array area 111 includes not only memory cells (memory cell, cell), but also devices such as sense amplifiers (sense amplifier, SA), sub - wordline drivers (sub wordline driver, SWD), and input / output amplifier drivers (IOSA DRV).

[0040] Furthermore, the devices integrated on one chip can be separately fabricated on two chips. Refer to Figure 2 , which shows a schematic composition structure of a chip structure Figure 2 . As Figure 2 shown, the chip structure is specifically a WoW 20. The WoW structure 20 includes two chips. One is a cell - array wafer, which can also be called an AG1 chip 21, and the other is a logic wafer, which can also be called an AG2 chip 22. The AG1 chip 21 and the AG2 chip 22 can be connected together through a bonding technology.

[0041] It should be noted that the AG1 chip 21 includes a cell - array area 211 and an intermediate area 212. The cell - array area 211 is distributed on both sides of the intermediate area 212. The cell - array area 211 only includes memory cells. There are no devices in the intermediate area 212, which is a blank area. It is a complementary - metal - oxide - semiconductor - free zone (CMOS free zone), and the intermediate area 212 can also be called a non - cell - array area. Since the intermediate area 212 is empty, devices such as capacitor structures and resistor structures can be fabricated in the intermediate area 212, and no specific limitations are made in this regard.

[0042] It should also be noted that the AG2 chip 22 includes a redistribution area 221 and a peripheral circuit area 222, and the redistribution area 221 is located on both sides of the peripheral circuit area 222. The memory array area 211 of the AG1 chip 21 only includes memory cells, and the other devices such as SA, SWD, and IOSA DRV included in the memory array area 111 of the single-chip structure 10 are placed in the redistribution area 221 of the AG2 chip 22; the composition structures of the peripheral circuit area 222 of the AG2 chip 22 and the peripheral circuit area 112 of the single-chip structure 10 are the same.

[0043] It should also be noted that after changing the single-chip structure 10 to the WoW structure 20, the original memory array area in the AG1 chip 21 (i.e., the memory array area 111 of the single-chip structure 10) now only includes memory cells, and the metal wirings at the positions where devices such as SA and SWD were made in the original single-chip structure 10 need to be re-routed and connected to the devices such as SA and SWD on the AG2 chip 22; and in the AG2 chip 22, the original memory array area now only includes devices such as SA and SWD and no memory cells, so the corresponding metal wirings also need to be re-routed. These metal wirings in the AG1 chip 21 and the AG2 chip 22 that need to be re-routed are called the redistribution area 221.

[0044] See Figure 3 , which shows a schematic diagram of the composition structure of a delay unit. As Figure 3 shown, the delay unit 30 includes an invertor 31, an invertor 32, and a resistor 33 ( Figure 3 the label 33 is not marked in

[0045] It should be noted that the delay unit 30 is located in the chip of the single-chip structure and is integrated in the peripheral circuit area of the single-chip structure.

[0046] In the WoW structure, the delay unit is generally located in the peripheral circuit area of the AG2 chip, and many CMOS devices have been integrated in the AG2 chip. Placing the resistor in the delay unit in the AG2 chip requires an additional resistor structure area, thus requiring a lot of memory area and causing waste of the memory area.

[0047] Based on this, embodiments of the present disclosure provide a three-dimensional memory, which includes a first chip and a second chip arranged along a third direction. The first chip includes a storage array region and a non-storage array region, and the second chip includes a peripheral control region; the projection of the peripheral control region along the third direction covers the non-storage array region; the non-storage array region of the first chip includes a plurality of resistance structures, and the first end and the second end of each resistance structure are coupled to the second chip. In this way, by fabricating the resistance structures in the logic chip of the WoW structure in the non-storage array region of the first chip and coupling each resistance structure to the second chip, the area can be saved.

[0048] The following will describe each embodiment of the present disclosure in detail with reference to the drawings.

[0049] In one embodiment of the present disclosure, refer to Figure 4 , which shows a schematic composition structure of a three-dimensional memory provided by an embodiment of the present disclosure. Figure 1 As Figure 4 shown, the three-dimensional memory 40 includes a first chip 41 and a second chip 42 arranged along a third direction. The first chip 41 includes a storage array region 411 and a non-storage array region 412, and the second chip 42 includes a peripheral control region 421; the projection of the peripheral control region 421 along the third direction covers the non-storage array region 412;

[0050] The non-storage array region 412 of the first chip 41 includes a plurality of resistance structures 50, and the first end and the second end of each resistance structure 50 are coupled to the second chip 42.

[0051] In the embodiments of the present disclosure, the three-dimensional memory 40 relates to the field of semiconductor integrated circuits, particularly to three-dimensional (3D) chip layout design. Specifically, a metal wire is fabricated by a double pattern technology (DPT) process to form a resistance structure, which can be applied to a circuit that requires a delayed signal in the WoW structure, but no specific limitation is made thereto.

[0052] It should be noted that a semiconductor chip may include a top surface on the front side and a bottom surface on the back side opposite to the front side; when ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the semiconductor chip is defined as the third direction.

[0053] It should also be noted that the first chip 41 can also be referred to as a memory array chip, and the second chip 42 can also be referred to as a logic chip. The first chip 41 and the second chip 42 form a WoW structure. The non-memory array area 412 in the original first chip 41 was empty, so the resistor structure in the original peripheral control area 421 located in the second chip 42 can be arranged in the non-memory array area 412 of the first chip 41, thus eliminating the need for an additional area to fabricate the resistor structure.

[0054] It should also be noted that, as Figure 4 shown, the second chip 42 may further include a memory array area 422, and the memory array area 422 is located on both sides of the peripheral control area 421. Additionally, the non-memory array area 412 is located in the middle area of the first chip 41, and the memory array area 411 is located on both sides of the non-memory array area 412.

[0055] It should also be noted that the peripheral control area 421 can also be referred to as the peripheral circuit area. Here, the projection of the peripheral control area 421 in the third direction covers the non-memory array area 412. That is to say, the projection of the resistor structure 50 in the third direction is located within the projection of the peripheral control area 421 in the third direction, and its projection will not exceed the non-memory array area 412 and will not extend to the memory array area 411. The memory array area 411 includes a memory cell array, and the memory cell array includes a plurality of memory cells arranged in rows and columns.

[0056] As Figure 4 shown, a plurality of resistor structures 50 are fabricated in the non-memory array area 412 of the first chip 41, and each resistor structure 50 is coupled to the second chip 42, thus eliminating the need for an additional area to fabricate the resistor structure and saving area.

[0057] In some embodiments, referring to Figure 5 , which shows a schematic structural composition of a three-dimensional memory provided by an embodiment of the present disclosure Figure 2 . As Figure 5 shown, the peripheral control area in the second chip 42 includes a plurality of inverters 60, and the plurality of resistor structures 50 correspond to the plurality of inverters 60 one by one;

[0058] The first end of the resistor structure 50 is coupled to the first end of the corresponding inverter 60, the second end of the resistor structure 50 is coupled to the second end of the corresponding inverter 60, and the resistor structure 50 and the inverter 60 together form a delay unit.

[0059] Here, the first end of the resistor structure 50 is represented by C, the second end of the resistor structure 50 is represented by D; the first end of the inverter 60 is represented by E, and the second end of the inverter 60 is represented by F.

[0060] It should be noted that there are multiple inverters 60 in the peripheral control area of the second chip 42, and each inverter 60 needs to be coupled to a corresponding resistor structure 50 located in the non-memory array area of the first chip 41 to form a corresponding plurality of delay units for delaying signal operations.

[0061] Furthermore, in some embodiments, as Figure 5 shown, the surface of the first chip 41 close to the second chip 42 includes a plurality of first bonding pairs 71, and the surface of the second chip 42 close to the first chip 41 includes a plurality of second bonding pairs 72; the plurality of resistor structures 50 correspond to the plurality of first bonding pairs 71 one by one, and the plurality of resistor structures 50 correspond to the plurality of second bonding pairs 72 one by one;

[0062] The first end of the resistor structure 50 is sequentially coupled to the first end of the corresponding inverter 60 through the first bonding structure 711 in the corresponding first bonding pair 71 and the third bonding structure 721 in the corresponding second bonding pair 72;

[0063] The second end of the resistor structure 50 is sequentially coupled to the second end of the corresponding inverter 60 through the second bonding structure 712 in the corresponding first bonding pair 71 and the fourth bonding structure 722 in the corresponding second bonding pair 72.

[0064] Specifically, as Figure 5 shown, the first end of the resistor structure 50 is first coupled to the second wiring layer M1, and then sequentially coupled to the third wiring layer M2 and the fourth wiring layer M3 through the M1 layer, and then coupled to the first bonding structure 711 through the M3 layer; the second end of the resistor structure 50 is first coupled to the M1 layer, and then sequentially coupled to the M2 layer and the M3 layer through the M1 layer, and then coupled to the second bonding structure 712 through the M3 layer.

[0065] It should be noted that the first bonding structure 711 can be bonded to the third bonding structure 721 through a hybrid bonding structure (Hybrid Bonding PAD), or can be bonded to the third bonding structure 721 through other bonding technologies, such as conductive bumps, etc., and no specific limitation is made thereto. Similarly, the second bonding structure 712 can be bonded to the fourth bonding structure 722 through a hybrid bonding structure, or can be bonded to the fourth bonding structure 722 through other bonding technologies, and no specific limitation is made thereto either.

[0066] It should also be noted that, as Figure 5As shown, the memory array region in the first chip 41 can also be bonded to the memory array region in the second chip 42 through the M1 layer, M2 layer, M3 layer, and the hybrid bonding structure. Here, the memory array region in the first chip 41 only includes memory cells, and the memory array region in the second chip 42 includes devices such as a row decoder (X-Decoder, XDEC), a bit line sense amplifier (Bit Line Sense Amplifier, BLSA), and SWD, but does not include memory cells. Specifically, the memory cells in the memory array region of the first chip 41 are bonded to the BLSA or X-DEC devices in the memory array region of the second chip 42. Additionally, Figure 5 Only the specific connection relationship between the memory array regions of the first chip 41 and the second chip 42 on one side is shown, and the memory array regions on the other side are not shown. Please refer to Figure 5 for understanding.

[0067] It should also be noted that in the memory array region, the bit line (Bit Line, BL) or the word line (Word Line, WL) can be connected out through a contact structure.

[0068] In some embodiments, as Figure 5 shown, the resistive structure 50 may include N + 2 first metal structures 51 and N second metal structures 52. The first metal structures 51 extend along the second direction, and the second metal structures 52 extend along the first direction; N is an integer greater than 0, and the first direction and the second direction intersect.

[0069] Based on Figure 5 the resistive structure 50 shown in Figure 6 , which shows the compositional structure schematic of a resistive structure provided by an embodiment of the present disclosure Figure 1 . As Figure 5 and Figure 6 shown, a plurality of first metal structures 51 are located on the first wiring layer of the first chip 41, and a plurality of second metal structures 52 are located on the second wiring layer of the first chip 41; the first wiring layer and the second wiring layer of the first chip 41 are arranged in sequence along the third direction;

[0070] wherein, the first end of the first first metal structure 51 forms the first end of the resistive structure 50, the second end of the i-th first metal structure 51 is electrically connected to the first end of the i-th second metal structure 52, the second end of the i-th second metal structure 52 is electrically connected to the first end of the (i + 1)-th first metal structure 51, and the second end of the last first metal structure 51 forms the second end of the resistive structure 50; i is an integer greater than 0 and less than or equal to N.

[0071] Here, the first wiring layer is denoted as M0, and the second wiring layer is denoted as M1.

[0072] It should be noted that a first direction and a second direction are defined on the top surface of the semiconductor chip. That is to say, a third direction is perpendicular to the plane where the first direction and the second direction are located. In addition, the first direction and the second direction intersect. The first direction and the second direction can be perpendicular to each other or intersect at other angles, and no specific limitation is made thereto. Exemplarily, taking the first direction and the second direction being perpendicular to each other as an example, the specific implementation of the embodiments of the present disclosure will be described in detail.

[0073] It should also be noted that the number of the first metal structures 51 and the second metal structures 52 differs by 2, and does not include Figure 6 the 2 metal structures at both ends of the M1 layer, because they are essentially metal structures obtained by the contact between the first bonding structure 711 and the first end of the resistance structure 50, and the second bonding structure 712 and the second end of the resistance structure 50. Therefore, they are not regarded as the second metal structures 52.

[0074] It should also be noted that each first metal structure 51 located in the M0 layer is electrically connected to the corresponding second metal structure 52 located in the M1 layer. Figure 5 For simplicity of drawing, only the first end of the first metal structure 51 of the first one and the second end of the first metal structure 51 of the last one in the resistance structure 50 are shown to be electrically connected to the M1 layer, and the connection relationship between the remaining first metal structures 51 and the M1 layer is not shown.

[0075] As Figure 5 shown, the first metal structures 51 and the second metal structures 52 in the resistance structure 50 are arranged in an S shape. Such an S-shaped setting can increase the resistance value within a metal wire of a limited length. It can be understood that, under the same thickness and cross-sectional area, the longer the wire, the greater its resistance value. Therefore, considering the space limitation of the layout, the resistance structure 50 is generally set in an S shape, but no specific limitation is made thereto, and different shapes can be set according to the required resistance value. In addition, the number of metal structures included in the resistance structure 50 corresponding to each inverter 60 is not limited, and the length, number, series or parallel connection of the metal structures can be selected according to the specific required resistance value.

[0076] In some embodiments, as Figure 6 shown, the first metal structure 51 has two types, which are respectively called the first sub-metal structure 511 and the second sub-metal structure 512 ( Figure 6 only 1 label 511 and 512 are marked in

[0077] and the remaining first sub-metal structures and second sub-metal structures are not marked with labels);

[0078] It should be noted that the resistor structure 50 is fabricated using the metal patterning of the double patterning technique DPT. The DPT process is a technique known in the industry, also known as double exposure or two exposures, which divides the data of the same graphic layer into two or two photomasks for imaging respectively. That is to say, two photomasks are set for the same layer of metal. During lithography, the two photomasks take turns, and each photomask only has about half of the metal trace information. Exemplarily, as Figure 6 shown, the first sub-metal structure 511 is the first layer of photomask, and the second sub-metal structure 512 is the second layer of photomask. Using the metal patterning of DPT can obtain metal lines with finer resistance values, and a resistor structure 50 can be formed by using the same pattern and two ports.

[0079] Refer to Figure 7 , which shows a schematic diagram of a double patterning technique DPT process provided by an embodiment of the present disclosure. As Figure 7 shown, Wa and Wb respectively represent the widths of the metal lines in region A and region B, and R A and R B respectively represent the resistance values of the metal lines in region A and region B. Assuming Wa = 2 × Wb, then R B = 2R A , that is to say, if the resistance value of each metal line in region A is 5Ω, then the resistance value of each metal line in region B is 10Ω. Then, if a resistance value of 100Ω is to be obtained, 20 metal lines are required in region A and 10 metal lines are required in region B. The total line width of the metal lines required in region A is 4 times that of the metal lines required in region B. Therefore, using the DPT process to fabricate the first metal structure 51 located in the M0 layer can make finer metal lines and use a smaller area for obtaining metal lines with the same resistance value.

[0080] In some embodiments, refer to Figure 8 , which shows a schematic composition structure of a resistor structure provided by an embodiment of the present disclosure Figure 2 , specifically a top view schematic diagram of the resistor structure 50. As Figure 8 shown, both the first sub-metal structure 511 and the second sub-metal structure 512 extend along the second direction ( Figure 8 only one label 511 and 512 are marked in , and the remaining first sub-metal structures and second sub-metal structures are not marked with labels), and each first sub-metal structure 511 and each second sub-metal structure 512 are arranged alternately along the first direction.

[0081] Exemplarily, as Figure 6 and Figure 8As shown, the first first metal structure 51 is the first sub-metal structure 511, and its first end forms the first end of the resistance structure 50; the last first metal structure 51 is the first sub-metal structure 511, and its second end forms the second end of the resistance structure 50.

[0082] In some embodiments, as Figure 6 and Figure 8 shown, the resistance structure 50 may further include a plurality of first contact structures 53 and a plurality of second contact structures 54.

[0083] For each first sub-metal structure 511, it is electrically connected to two adjacent second metal structures 52 through two first contact structures 53 respectively;

[0084] For each second sub-metal structure 512, it is electrically connected to two adjacent second metal structures 52 through two second contact structures 54 respectively;

[0085] Wherein, along the first direction, the first contact structures 53 and the second contact structures 54 are arranged alternately in sequence; along the second direction, two first contact structures 53 are arranged, or two second contact structures 54 are arranged.

[0086] Exemplarily, as Figure 6 shown, the second first metal structure 51 is the second sub-metal structure 512, and the third first metal structure 51 is the first sub-metal structure 511. Among them, the second sub-metal structure 512 is electrically connected to the first and second second metal structures 52 through two second contact structures 54 respectively, and the first sub-metal structure 511 is electrically connected to the second and third second metal structures 52 through two first contact structures 53 respectively.

[0087] It should be noted that for the resistance structure 50, the conductive columns of the first contact structure 53 and the second contact structure 54 can also provide part of the resistance value, but no specific limitation is made thereto.

[0088] In some embodiments, the M0 layer is prepared using tungsten (W), and the M1 layer, M2 layer, and M3 layer are prepared using copper (Cu).

[0089] It should be noted that the sheet resistance of W is much larger than that of Cu. Preparing the first metal structure on the M0 layer results in a larger resistance value compared to preparing the first metal structure on other metal wiring layers. Among them, the sheet resistance refers to the resistance value per unit thickness and per unit area of the conductive material.

[0090] In some embodiments, the memory array region 411 of the first chip 41 includes a plurality of memory cells, and each memory cell includes a capacitor and a transistor;

[0091] The first wiring layer of the first chip 41 is also used to form a landing contact structure for the capacitor in the memory cell.

[0092] That is to say, the M0 layer of the first chip 41 and the landing contact structure (CapLanding Pad) of the capacitor in the memory array area 411 are the same layer.

[0093] It should be noted that in the memory array area 411, the landing contact structure of the capacitor is used as an electrical connection structure to connect the source or drain of the transistor (Metal Oxide Semiconductor field effect transistor, MOS transistor) in the memory cell to the lower plate of the capacitor. That is to say, in the memory array area 411, the landing contact structure of the capacitor in the M0 layer is used to connect the MOS transistor and the capacitor, and the source and drain electrodes of the MOS transistor are also formed in the M0 layer. In addition, the shape of the landing contact structure of the capacitor can be in the shape of a "work" character, but no specific limitation is made thereto.

[0094] In some embodiments, the 3D memory is a dynamic random access memory DRAM.

[0095] In summary, the embodiments of the present disclosure provide a resistance structure 50. The two ends of the resistance structure 50 have a first end and a second end. The first end and the second end of the resistance structure 50 are respectively connected to the first bonding structure 711 and the second bonding structure 712 in the first bonding pair 71. The inverter 60 in the delay unit in the peripheral control area 421 of the second chip 42 also has a first end and a second end. The first end and the second end of the inverter 60 are respectively connected to the third bonding structure 721 and the fourth bonding structure 722 in the second bonding pair 72. Then, the third bonding structure 721 is connected to the first bonding structure 711 through a hybrid bonding structure, and the fourth bonding structure 722 is connected to the second bonding structure 712 through a hybrid bonding structure. In this way, the two ends of the resistance structure 50 can be connected to the delay unit.

[0096] See Figure 9 , which shows a schematic diagram of the composition structure of another type of resistance structure provided by the embodiments of the present disclosure. Figure 9 In (a) of [], it is an active resistor (Active-R). The active resistor refers to a resistor made of doped semiconductor. Exemplarily, it is a high-concentration N-type doping (N+); Figure 9 In (b) of [], it is a transistor turn-on resistor (TR turn-on R); Figure 9 In (c) of [], it is a polysilicon resistor (Poly-R). The polysilicon resistor refers to a resistor made of a semiconductor using a polysilicon (Poly) layer as the gate of the MOS transistor.

[0097] It should be noted that in Figure 9In this case, Node-A and Node-B respectively represent the two ports of the resistor structure.

[0098] It should also be noted that, compared with the active resistor, the resistor structure 50 in the present disclosure is easy to obtain intermediate resistance values; compared with the transistor turn-on resistance, the power supply (VDD) connected to the resistor structure 50 changes less; compared with the polysilicon resistor, the resistor structure 50 does not require additional processes. Additionally, in the WoW structure, no additional area is required, and the resistor structure 50 is made in the blank area in the middle of the memory array chip, which can save area.

[0099] In another embodiment of the present disclosure, refer to Figure 10 , which shows a schematic diagram of the composition structure of an electronic device provided by an embodiment of the present disclosure. As Figure 10 shown, the electronic device 80 includes the three-dimensional memory 40 described in any one of the foregoing embodiments.

[0100] In the embodiment of the present disclosure, for the electronic device 80, since it includes the three-dimensional memory 40 described in the foregoing embodiment, area can be saved.

[0101] For the details not disclosed in the embodiments of the present disclosure, reference may be made to the description of the foregoing embodiments for understanding.

[0102] The above is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

[0103] It should be noted that in the present disclosure, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one..." does not exclude the presence of additional identical elements in the process, method, article or device including such element.

[0104] The serial numbers of the above embodiments of the present disclosure are only for description and do not represent the superiority or inferiority of the embodiments.

[0105] The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0106] The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0107] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0108] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that, The three-dimensional memory includes a first chip and a second chip arranged along a third direction. The first chip includes a memory array region and a non-memory array region, and the second chip includes a peripheral control region; a projection of the peripheral control region along the third direction covers the non-memory array region; The non-memory array region of the first chip includes a plurality of resistance structures, and a first end and a second end of each resistance structure are coupled to the second chip.

2. The three-dimensional memory according to claim 1, wherein The peripheral control region in the second chip includes a plurality of inverters, and the plurality of resistance structures correspond to the plurality of inverters one by one; The first end of the resistance structure is coupled to the first end of the corresponding inverter, the second end of the resistance structure is coupled to the second end of the corresponding inverter, and the resistance structure and the inverter together form a delay unit.

3. The three-dimensional memory according to claim 2, wherein A surface of the first chip close to the second chip includes a plurality of first bonding pairs, and a surface of the second chip close to the first chip includes a plurality of second bonding pairs; the plurality of resistance structures correspond to the plurality of first bonding pairs one by one, and the plurality of resistance structures correspond to the plurality of second bonding pairs one by one; The first end of the resistance structure is coupled to the first end of the corresponding inverter via a first bonding structure in the corresponding first bonding pair and a third bonding structure in the corresponding second bonding pair in sequence; The second end of the resistance structure is coupled to the second end of the corresponding inverter via a second bonding structure in the corresponding first bonding pair and a fourth bonding structure in the corresponding second bonding pair in sequence.

4. The three-dimensional memory according to claim 2, wherein The resistance structure includes N + 2 first metal structures and N second metal structures. The first metal structures extend along a second direction, and the second metal structures extend along a first direction; N is an integer greater than 0, and the first direction and the second direction intersect; The plurality of first metal structures are located on a first wiring layer of the first chip, and the plurality of second metal structures are located on a second wiring layer of the first chip; the first wiring layer and the second wiring layer of the first chip are arranged in sequence along the third direction; Wherein, the first end of the first one of the first metal structures forms the first end of the resistance structure, the second end of the i-th first metal structure is electrically connected to the first end of the i-th second metal structure, the second end of the i-th second metal structure is electrically connected to the first end of the (i + 1)-th first metal structure, and the second end of the last one of the first metal structures forms the second end of the resistance structure; i is an integer greater than 0 and less than or equal to N.

5. The three-dimensional memory according to claim 4, wherein The first metal structures have two types, respectively called a first sub-metal structure and a second sub-metal structure; The first sub-metal structure and the second sub-metal structure are fabricated using a double patterning technique DPT.

6. The three-dimensional memory according to claim 5, wherein Both the first sub-metal structure and the second sub-metal structure extend along the second direction, and each of the first sub-metal structures and each of the second sub-metal structures are arranged alternately along the first direction.

7. The three-dimensional memory according to claim 5, wherein For each of the first sub-metal structures, it is electrically connected to two adjacent second metal structures through two first contact structures respectively; For each of the second sub-metal structures, it is electrically connected to two adjacent second metal structures through two second contact structures respectively; Wherein, along the first direction, the first contact structures and the second contact structures are arranged alternately in sequence; along the second direction, two first contact structures are arranged, or two second contact structures are arranged.

8. The three-dimensional memory according to claim 4, wherein The memory array region includes a plurality of memory cells, and each of the memory cells includes a capacitor and a transistor; The first wiring layer of the first chip is further used to form a landing contact structure of the capacitor in the memory cell.

9. The three-dimensional memory according to any one of claims 1-8, characterized in that, The three-dimensional memory is a dynamic random access memory DRAM.

10. An electronic device, characterized in that, The electronic device includes the three-dimensional memory according to any one of claims 1-9.

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