Semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device. The semiconductor device comprises a first chip and a second chip which are bonded with each other. The first chip comprises a first storage array and a second storage array which are adjacent, the first storage array is provided with a first bit line and a second bit line, and the second storage array is provided with a first complementary bit line and a second complementary bit line. The first chip further comprises a conductive interconnection structure, the conductive interconnection structure is located between the storage array and the second chip, the conductive interconnection structure at least comprises a first conductive part, the first conductive part is electrically connected with the first bit line, and the first conductive part is coupled with the first sensing amplifier; the second complementary conductive part is electrically connected with the second complementary bit line, and the second complementary conductive part is coupled with the second sense amplifier; wherein a first coupling capacitance is generated between the first conductive part and the second complementary conductive part. The embodiment of the invention is beneficial to improving the stability of the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technologies, and particularly to a semiconductor device. Background Art

[0002] A memory cell in a Dynamic Random Access Memory (DRAM) generally includes a capacitor and a transistor. The transistor has a gate, a first end, and a second end, and is electrically connected to a word line and a bit line structure. The storage and reading of data information are achieved through the cooperation of the word line and the bit line structure. Specifically, the gate of the transistor is connected to the word line, the first end of the transistor is connected to the bit line structure, the second end of the transistor is connected to the capacitor, and the word line controls the opening of the channel region of the transistor, so as to read the data information stored in the capacitor through the bit line structure, or write the data information into the capacitor through the bit line structure for storage.

[0003] To save chip area, a memory chip including a memory array and a logic chip having a logic circuit including a sense amplifier array and a word line driver are respectively fabricated on two different wafers, and the two different wafers are hybridly bonded using a Hybrid Bonding process. According to this method, the memory array and the logic circuit can be fabricated through separate processes. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor device, which is at least beneficial to improving the sensing and amplifying ability of a sense amplifier and enhancing the stability of the semiconductor device.

[0005] In some embodiments of the present disclosure, on the one hand, a semiconductor device is provided, including: a first chip and a second chip bonded to each other along a preset direction; the first chip includes a plurality of memory arrays arranged along a first direction, the plurality of memory arrays include adjacent first and second memory arrays, the first memory array includes a plurality of bit lines arranged at intervals along a second direction, the second memory array includes a plurality of complementary bit lines arranged at intervals along the second direction, wherein the plurality of bit lines include adjacent first and second bit lines, and the plurality of complementary bit lines include adjacent first and second complementary bit lines; the second chip includes a sense amplifier array corresponding to the memory arrays one by one, the sense amplifier array includes a plurality of sense amplifiers, the plurality of sense amplifiers include a first sense amplifier and a second sense amplifier, wherein the first sense amplifier is coupled to the first bit line and the first complementary bit line, and the second sense amplifier is coupled to the second bit line and the second complementary bit line; the first chip further includes: a conductive interconnect structure located between the memory array and the second chip, the conductive interconnect structure at least includes: a first conductive part, the first conductive part is electrically connected to the first bit line and is coupled to the first sense amplifier; a second complementary conductive part, the second complementary conductive part is electrically connected to the second complementary bit line and is coupled to the second sense amplifier; wherein, a first coupling capacitance is generated between the first conductive part and the second complementary conductive part.

[0006] In some examples, the first conductive part and the second complementary conductive part are disposed on the same layer.

[0007] In some examples, along the preset direction, the first conductive part is directly opposite to the first memory array, and the second complementary conductive part is directly opposite to the second memory array; wherein, along the first direction, at least a part of the first conductive part is directly opposite to the second complementary conductive part.

[0008] In some examples, the conductive interconnect structure further includes: a first common conductive part, the first common conductive part is located on a side of the first conductive part facing the second chip, and the same first common conductive part extends to a side of the second complementary conductive part facing the second chip; wherein, a first capacitance is generated between the first common conductive part and the first conductive part, a second capacitance is generated between the first common conductive part and the second complementary conductive part, and the first capacitance and the second capacitance are connected in series to form the first coupling capacitance.

[0009] In some examples, the conductive interconnect structure further includes: a redistribution layer including a plurality of wire portions that are in the same layer and are discrete from each other; a first conductive plug layer including a plurality of first conductive plugs that are in the same layer and are discrete from each other, wherein the first bit line and the second complementary bit line are respectively electrically connected to corresponding wire portions via corresponding first conductive plugs; and a second conductive plug layer including a plurality of second conductive plugs that are in the same layer and are discrete from each other, wherein one wire portion is electrically connected to the first conductive portion via a corresponding second conductive plug, and another wire portion is electrically connected to the second complementary conductive portion via a corresponding second conductive plug.

[0010] In some examples, one first conductive plug and one second conductive plug are both disposed at an edge of the first memory array adjacent to the second memory array; another first conductive plug and another second conductive plug are both disposed at an edge of the second memory array adjacent to the first memory array.

[0011] In some examples, the conductive interconnect structure further includes: a second conductive portion electrically connected to the second bit line, the second conductive portion facing the second memory array and being coupled to the second sense amplifier; and a first complementary conductive portion electrically connected to the first complementary bit line, the first complementary conductive portion facing the first memory array and being coupled to the first sense amplifier; wherein the second conductive portion and the first complementary conductive portion are disposed in the same layer, and in a first direction, at least a part of the second conductive portion faces the first complementary conductive portion, and a second coupling capacitance is generated between the second conductive portion and the first complementary conductive portion.

[0012] In some examples, the conductive interconnect structure further includes: a second common conductive portion located on a side of the second conductive portion facing the second chip, and the same second common conductive portion extends to a side of the first complementary conductive portion facing the second chip; wherein a third capacitance is generated between the second common conductive portion and the second conductive portion, a fourth capacitance is generated between the second common conductive portion and the first complementary conductive portion, and the third capacitance and the fourth capacitance are connected in series to form the second coupling capacitance.

[0013] In some examples, the first conductive portion, the second conductive portion, the first complementary conductive portion, and the second complementary conductive portion are disposed in the same layer; the first complementary conductive portion is located on a side of the first conductive portion along a second direction, and the second complementary conductive portion is located on a side of the second conductive portion along the second direction.

[0014] In some examples, along the preset direction, the first sense amplifier faces the first memory array; along the preset direction, the second sense amplifier faces the second memory array.

[0015] In some examples, along the preset direction, both the first conductive part and the second complementary conductive part face the first memory array, and along the second direction, the first conductive part and the second complementary conductive part face each other at least partially.

[0016] In some examples, the conductive interconnect structure further includes: a plurality of conductive plugs, the first bit line is in electrical contact with the first conductive part via the corresponding conductive plug, and the second bit line is in electrical contact with the second complementary conductive part via the corresponding conductive plug.

[0017] In some examples, the conductive interconnect structure further includes: a first conductive shielding part, the first conductive shielding part is arranged on the same layer as the first conductive part and is located on the side of the first conductive part away from the second complementary conductive part; a second conductive shielding part, the second conductive shielding part is arranged on the same layer as the first conductive shielding part and is located on the side of the second complementary conductive part away from the first conductive part.

[0018] In some examples, the conductive interconnect structure further includes: a second conductive part, the second conductive part is electrically connected to the second bit line and is coupled to the second sense amplifier; a first complementary conductive part, the first complementary conductive part is electrically connected to the first complementary bit line and is coupled to the first sense amplifier; wherein, a second coupling capacitance is generated between the second conductive part and the first complementary conductive part; the second conductive part and the first complementary conductive part are on the same layer, and along the second direction, the second conductive part and the first complementary conductive part face each other at least partially, and a second coupling capacitance is generated between the second conductive part and the first complementary conductive part.

[0019] In some examples, both the second conductive part and the first complementary conductive part face the first memory array; the first conductive part and the second conductive part are in different layers from each other.

[0020] In some examples, the conductive interconnect structure further includes: an intermediate conductive shielding part, the intermediate conductive shielding part is located between the first conductive part and the second conductive part and extends along the second direction.

[0021] In some examples, along the second direction, the arrangement direction of the first complementary bit line to the second complementary bit line is the same as that of the first bit line to the second bit line; or, along the second direction, the arrangement direction of the first complementary bit line to the second complementary bit line is opposite to that of the first bit line to the second bit line.

[0022] In some examples, the capacitance value of the first coupling capacitor satisfies: C = (80% - 120%) × C0, where C is the capacitance value of the first coupling capacitor, and C0 is the parasitic capacitance value between the first bit line and the second bit line.

[0023] In some examples, the bit line, the complementary bit line, the first conductive part, and the second complementary conductive part all extend along the first direction.

[0024] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0025] A semiconductor device with excellent structural performance provided by the embodiments of the present disclosure. The semiconductor device includes a stacked first chip and a second chip. The first chip includes a plurality of memory arrays, each memory array includes a plurality of bit lines, and the plurality of bit lines include adjacent first bit lines and second bit lines. The second chip includes a sense amplifier coupled to the bit lines and complementary bit lines of the memory array. The semiconductor device further includes a conductive interconnect structure located between the memory array and the second chip. The conductive interconnect structure includes a first conductive part and a second complementary conductive part. The first conductive part is electrically connected to the first bit line and is electrically connected to the first sense amplifier. The second complementary conductive part is electrically connected to the second complementary bit line and is electrically connected to the second sense amplifier. By additionally providing the first conductive part and the second complementary conductive part, the first bit line and the second complementary bit line are redistributed at positions different from the bit line layer, so that a first coupling capacitor is generated between the first conductive part and the second complementary conductive part. During the sensing and amplification by the second sense amplifier, the parasitic capacitance between the first bit line and the second bit line is in the same direction as the first coupling capacitor, that is, the influence trend of the first coupling capacitor on the voltage of the second complementary conductive part is the same as the influence trend of the parasitic capacitance on the voltage of the second bit line. Furthermore, during the sensing and amplification by the second sense amplifier, there is a large voltage difference between the second bit line and the second complementary bit line, thus ensuring that the second sense amplifier has excellent amplification ability, and further improving the stability of the semiconductor device. Description of the Drawings

[0026] One or more embodiments are illustrated by way of example in the accompanying drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, unless otherwise stated, and the figures in the drawings do not constitute a scale limitation; To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the accompanying drawings required for use in the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0027] Figure 1 It is a schematic diagram of the architecture of a semiconductor device;

[0028] Figure 2 It is a schematic three-dimensional structure diagram of a semiconductor device provided by some embodiments of the present disclosure;

[0029] Figure 3 It is Figure 2 a schematic diagram of the architecture of the semiconductor device shown in

[0030] Figure 4 It is Figure 2 a schematic three-dimensional structure diagram including a first storage array and a second storage array in

[0031] Figure 5 It is Figure 4 a schematic top view structure diagram including bit lines, first conductive plugs, rewiring layers, and second conductive plugs in

[0032] Figure 6 It is Figure 5 a schematic top view structure diagram showing second conductive plugs, first conductive parts, second conductive parts, first complementary conductive parts, second complementary conductive parts, first common conductive parts, and second common conductive parts based on

[0033] Figure 7 It is Figure 2 a schematic partial cross-sectional structure diagram including a first bit line, a second complementary bit line, a first conductive plug, a wire part, a second conductive plug, a first conductive part, a second complementary conductive part, and a first common conductive part in

[0034] Figure 8 It is Figure 2 a schematic partial cross-sectional structure diagram including a second bit line, a first complementary bit line, a first conductive plug, a wire part, a second conductive plug, a second conductive part, a first complementary conductive part, and a second common conductive part in

[0035] Figure 9 It is a schematic diagram of the architecture of a semiconductor device provided by other embodiments of the present disclosure;

[0036] Figure 10 A partial three-dimensional structure diagram of a semiconductor device provided in some other embodiments of the present disclosure;

[0037] Figure 11 Another partial three-dimensional structure diagram of a semiconductor device provided in some other embodiments of the present disclosure;

[0038] Figure 12 is Figure 11 A partial cross-sectional structure diagram cut along the second direction X in Detailed implementation manners

[0039] Figure 1 is an architecture diagram of a semiconductor device. Referring to Figure 1 , the semiconductor device includes a memory chip and a logic chip bonded to each other. Among them, the memory chip includes a plurality of memory arrays 11 arranged in sequence, Figure 1 Three memory arrays 11 are schematically shown in . Among them, the memory array 11 in the middle position includes a plurality of bit lines. Taking 8 bit lines as an example, they are respectively labeled as BL<0>, BL<1>, BL<2>, BL<3>, BL<4>, BL<5>, BL<6>, BL<7>. The memory arrays 11 on the opposite sides of the memory array 11 each include 8 complementary bit lines, and the 8 complementary bit lines are respectively labeled as BLB<0>, BLB<1>, BBL<2>, BLB<3>, BLB<4>, BLB<5>, BLB<6>, BLB<7>.

[0040] The logic chip includes a plurality of sense amplifiers SA (SA, Sense Amplifier). Each sense amplifier SA is respectively coupled to the corresponding bit line and complementary bit line. Figure 1 In , SA represents a sense amplifier, Figure 1 The coupling relationship between each sense amplifier and the corresponding bit line and complementary bit line is schematically shown in .

[0041] It should be noted that the complementary bit lines are also bit lines. Here, it is only for distinguishing the bit lines in different memory arrays. For example, the memory array in the middle position is defined as the first memory array, and the memory arrays on the opposite sides of the first memory array are respectively defined as the second memory array and the third memory array. For the reference of the bit lines in the second memory array, the bit lines in the first memory array are the complementary bit lines. Specifically, if the bit line for which the signal needs to be amplified is in the first memory array, then the bit lines in the first memory array are called bit lines, and the bit lines in the second memory array adjacent to the first memory array are used as references, and the bit lines in the second memory array are called complementary bit lines. The bit lines in the third memory array adjacent to the first memory array are also used as references, and the bit lines in the third memory array are also called complementary bit lines. If the bit line for which the signal needs to be amplified is in the second memory array, then similarly, the bit lines in the second memory array are called bit lines, and the bit lines in the first memory array adjacent to the second memory array are called complementary bit lines.

[0042] It should also be noted that in the embodiments of the present disclosure, regarding the bit lines and the complementary bit lines, it is only for distinguishing the bit lines in adjacent memory arrays. The above explanations also apply to the subsequent descriptions of "bit lines" and "complementary bit lines".

[0043] Continue to refer to Figure 1 , during the process of the semiconductor device performing a data read operation, the sense amplifier SA is used to read the voltages of the bit line and the corresponding complementary bit line, and amplify the voltage difference between the bit line and the complementary bit line, so as to achieve the purpose of reading the signal on the bit line. However, there is a parasitic capacitance in the semiconductor device. The existence of this parasitic capacitance reduces the voltage difference between the bit line and the complementary bit line, thereby causing characteristic mismatch of the sense amplifier SA, affecting the overall amplification ability of the sense amplifier SA, and further affecting the read and write performance of the semiconductor device, resulting in poor stability of the semiconductor device.

[0044] Analysis reveals that the above-mentioned parasitic capacitance mainly refers to the parasitic capacitance C0 existing between adjacent bit lines. It can be understood that there is also the parasitic capacitance C0 between adjacent complementary bit lines. Figure 1 The parasitic capacitance C0 between adjacent bit lines is shown in Figure 1 , and the parasitic capacitance between adjacent complementary bit lines is not shown. Taking the bit line BL<2> and the bit line BLB<3> as an example, the signal on the bit line BL<2> is the signal that the sense amplifier SA needs to amplify. The sense amplifier SA needs to amplify the voltage difference between the bit line BL<2> and the complementary bit line BLB<2> to achieve the purpose of amplifying the signal on the bit line BL<2>. Since there is a parasitic capacitance C0 between the bit line BL<3> and the bit line BL<2>, this parasitic capacitance C0 constitutes a charge and discharge path for the bit line BL<2>, and this parasitic capacitance C0 will affect the voltage on the bit line BL<2>, resulting in the weakening of the amplification ability of the sense amplifier SA for the bit line BL<2>.

[0045] Further analysis reveals that if there is a coupling capacitance between the designed bit line BL<3> and the corresponding complementary bit line BLB<2>, the influence of the voltage change of the coupling capacitance on the complementary bit line BLB<2> can cancel out the influence of the voltage change of the parasitic capacitance C0 on the bit line BL<2>. This can compensate for the voltage influence brought by the parasitic capacitance C0 on the bit line BL<2>, resulting in a larger voltage difference between the bit line BL<2> and the complementary bit line BLB<2>, improving the amplification ability of the sense amplifier SA for the bit line BL<2>, and further improving the read and write performance of the semiconductor device.

[0046] Embodiments of the present disclosure provide a semiconductor device that redistributes at least the positions of the first bit line and the second complementary bit line using a conductive interconnect structure, redistributing the first bit line to the first conductive portion and the second complementary bit line to the second complementary conductive portion, and there is a first coupling capacitance between the first conductive portion and the second complementary conductive portion. This first coupling capacitance can compensate for the voltage influence brought by the above parasitic capacitance on the second bit line, increasing the voltage difference between the second bit line and the corresponding complementary bit line, improving the overall amplification ability of the sense amplifier, and further improving the stability of the read and write performance of the semiconductor device.

[0047] The following will elaborate on the embodiments of the present disclosure in conjunction with the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present disclosure, many technical details are presented to help readers better understand the embodiments. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the embodiments of the present disclosure can still be implemented.

[0048] Figure 2 Is a three-dimensional structural schematic diagram of a semiconductor device provided for some embodiments of the present disclosure, Figure 3 Is Figure 2 An architecture diagram of the semiconductor device shown in Figure 4 Is Figure 2 A three-dimensional structural schematic diagram of the one including the first storage array and the second storage array in Figure 5 Is Figure 4 A top view structural schematic diagram of the one including the bit line, the first conductive plug, the rewiring layer, and the second conductive plug in Figure 6 Is Figure 5 A top view structural schematic diagram showing the second conductive plug, the first conductive portion, the second conductive portion, the first complementary conductive portion, the second complementary conductive portion, the first common conductive portion, and the second common conductive portion on the basis of Figure 7 Is Figure 2A partial cross-sectional structure schematic diagram of a first bit line, a second complementary bit line, a first conductive plug, a wire portion, a second conductive plug, a first conductive portion, a second complementary conductive portion, and a first common conductive portion. Figure 8 is Figure 2 A partial cross-sectional structure schematic diagram of a second bit line, a first complementary bit line, a first conductive plug, a wire portion, a second conductive plug, a second conductive portion, a first complementary conductive portion, and a second common conductive portion.

[0049] Referring Figures 2 to 8 , the semiconductor device includes a first chip 101 and a second chip 102 bonded to each other along a preset direction Z. The first chip 101 includes a plurality of memory arrays arranged along a first direction Y. The plurality of memory arrays include adjacent first memory array 11A and second memory array 11B. The first memory array 11A includes a plurality of bit lines arranged at intervals along a second direction X. The second memory array 11B includes a plurality of complementary bit lines arranged at intervals along the second direction X. Among them, the plurality of bit lines include adjacent first bit line and second bit line. The plurality of complementary bit lines include adjacent first complementary bit line and second complementary bit line.

[0050] Each memory array includes a plurality of memory cells, and the memory cells can be DRAM memory cells.

[0051] 8 bit lines of the memory array are schematically shown in the drawings. The bit lines arranged in sequence along the second direction X are sequentially labeled as BL<0>, BL<1>, BL<2>, BL<3>, BL<4>, BL<5>, BL<6>, BL<7>. The plurality of complementary bit lines are correspondingly labeled as BLB<0>, BLB<1>, BLB<2>, BLB<3>, BLB<4>, BLB<5>, BLB<6>, BLB<7>. Among them, if one of two adjacent bit lines is the first bit line, the other bit line is the second bit line. For the convenience of description and explanation, hereinafter, the bit line BL<2> and the bit line BL<3> will be used as examples of the first bit line BL<2> and the second bit line BL<3> respectively for illustration. It can be understood that the bit lines BL<0> and BL<1> are also the first bit line BL<0> and the second bit line BL<1> respectively, the bit lines BL<4> and BL<5> are also the first bit line BL<4> and the second bit line BL<5> respectively, and the bit lines BL<6> and BL<7> are also the first bit line BL<6> and the second bit line BL<7> respectively. It can be understood that the embodiments of the present disclosure only use 8 bit lines as examples, and the actual number of bit lines included in each memory array can be greater than 8.

[0052] The plurality of storage arrays may further include a third storage array 11C, and the third storage array 11C and the second storage array 11B are respectively located on opposite sides of the first storage array 11A. Among them, the third storage array 11C also includes a plurality of complementary bit lines arranged at intervals along the second direction X, and the plurality of bit lines are respectively labeled as BLB<0>, BLB<1>, BLB<2>, BLB<3>, BLB<4>, BLB<5>, BLB<6>, BLB<7>.

[0053] The first complementary bit line BLB<0> corresponding to the first bit line BL<0> in the first storage array 11A is located in the third storage array 11C, and the second complementary bit line BLB<1> corresponding to the second bit line BL<1> in the first storage array 11A is located in the third storage array 11C. The first complementary bit line BLB<4> corresponding to the first bit line BL<4> in the first storage array 11A is located in the third storage array 11C, and the second complementary bit line BLB<5> corresponding to the second bit line BL<5> in the first storage array 11A is located in the third storage array 11C. The first complementary bit line BLB<2> corresponding to the first bit line BL<2> in the first storage array 11A is located in the second storage array 11B, and the second complementary bit line BLB<3> corresponding to the second bit line BL<3> in the first storage array 11A is located in the second storage array 11B. The first complementary bit line BLB<6> corresponding to the first bit line BL<6> in the first storage array 11A is located in the second storage array 11B, and the second complementary bit line BLB<7> corresponding to the second bit line BL<7> in the first storage array 11A is located in the second storage array 11B.

[0054] In some examples, as Figure 3 shown, along the second direction X, the arrangement direction of the first bit line to the second bit line may also be opposite to the arrangement direction of the first complementary bit line to the second complementary bit line. For example, the arrangement direction of the first bit line BL<2> to the second bit line BL<3> is the positive direction of the second direction X, and the arrangement direction of the first complementary bit line BLB<2> to the second complementary bit line BLB<3> is the negative direction of the second direction X.

[0055] It can be understood that in other examples, along the second direction X, the arrangement direction of the first bit line to the second bit line may be the same as the arrangement direction of the first complementary bit line to the second complementary bit line. For example, the arrangement direction of the first bit line BL<2> to the second bit line BL<3> is the positive direction of the second direction X, and the arrangement direction of the first complementary bit line BLB<2> to the second complementary bit line BLB<3> is also the positive direction of the second direction X.

[0056] The second chip 102 includes a logic circuit, which includes but is not limited to a sense amplifier array, a word line driver, a read / write conversion circuit, etc. The second chip 102 includes a sense amplifier array corresponding one-to-one to the memory array. The sense amplifier array includes a plurality of sense amplifiers, and the plurality of sense amplifiers includes a first sense amplifier SA1 and a second sense amplifier SA2. Among them, the first sense amplifier SA1 is coupled to the first bit line BL<2> and the first complementary bit line BLB<2>, and the second sense amplifier SA2 is coupled to the second bit line BL<3> and the second complementary bit line BLB<3>.

[0057] The first chip 101 further includes a conductive interconnect structure (not labeled). The conductive interconnect structure is located between the memory array and the second chip 102. The conductive interconnect structure at least includes: a first conductive portion 1211, the first conductive portion 1211 is electrically connected to the first bit line BL<2>, and the first conductive portion 1211 is coupled to the first sense amplifier SA1; a second complementary conductive portion 1212, the second complementary conductive portion 1212 is electrically connected to the second complementary bit line BLB<3>, and the second complementary conductive portion 1212 is coupled to the second sense amplifier SA2; wherein, a first coupling capacitor C1 is generated between the first conductive portion 1211 and the second complementary conductive portion 1212.

[0058] Specifically, the first bit line is coupled to the first sense amplifier SA1 via the first conductive portion 1211, and the second complementary bit line is coupled to the second sense amplifier SA2 via the second complementary conductive portion 1212.

[0059] Since the first bit line BL<2> is adjacent to the second bit line BL<3>, there is a parasitic capacitance C0 between these two bit lines. When the second bit line BL<3> is the bit line to be amplified, this parasitic capacitance C0 will affect the amplification ability of amplifying the voltage difference between the second bit line BL<3> and the second complementary bit line BLB<3>. That is to say, the second bit line BL<3> will be affected by the parasitic capacitance C0. By additionally providing the first conductive portion 1211 and the second complementary conductive portion 1212, a first coupling capacitance C1 is generated between the first bit line BL<2> and the second complementary bit line BLB<3>. The existence of this first coupling capacitance C1 causes the voltage of the second complementary bit line BLB<3> to also change. And during the amplification of the second bit line BL<3> and the second complementary bit line BLB<3> by the second sense amplifier SA2, the influence trend of the parasitic capacitance C0 on the voltage of the second bit line BL<3> is the same as the influence trend of the first coupling capacitance C1 on the voltage of the second complementary bit line BLB<3>. This can compensate for the influence of the existence of the parasitic capacitance C0 on the voltage loss of the second bit line BL<3>, that is, it can compensate for the voltage difference loss between the second bit line BL<3> and the second complementary bit line BLB<3> caused by the parasitic capacitance, so that the voltage difference between the second bit line BL<3> and the second complementary bit line BLB<3> is larger during the amplification of the second bit line BL<3> by the second sense amplifier SA2, thereby ensuring the amplification ability of the second sense amplifier SA2 for the second bit line BL<3> and improving the read and write performance of the semiconductor device.

[0060] Similarly, the conductive interconnect structure may further include: a second conductive portion 1213, the second conductive portion 1213 is electrically connected to the second bit line BL<3>, and the second conductive portion 1213 is coupled to the second sense amplifier SA2; a first complementary conductive portion 1214, the first complementary conductive portion 1214 is electrically connected to the first complementary bit line BLB<2>, and the first complementary conductive portion 1214 is coupled to the first sense amplifier SA1; wherein, a second coupling capacitance C2 is generated between the second conductive portion 1213 and the first complementary conductive portion 1214.

[0061] Specifically, the second bit line is coupled to the second sense amplifier SA2 via the second conductive portion 1213, and the first complementary bit line is coupled to the first sense amplifier SA1 via the first complementary conductive portion 1214.

[0062] Since the first bit line BL<2> is adjacent to the second bit line BL<3>, there is a parasitic capacitance C0 between these two bit lines. When the first bit line BL<2> is the bit line to be amplified, this parasitic capacitance C0 will affect the amplification ability of amplifying the voltage difference between the first bit line BL<2> and the first complementary bit line BLB<2>. That is to say, the first bit line BL<2> will be affected by the parasitic capacitance C0. By additionally providing a second conductive portion and a first complementary conductive portion, a second coupling capacitance C2 is generated between the second bit line BL<3> and the first complementary bit line BLB<2>. The existence of this second coupling capacitance C2 causes the voltage of the first complementary bit line BLB<2> to also change. And during the period when the first sense amplifier SA1 amplifies the first bit line BL<2> and the first complementary bit line BLB<2>, the influence trend of the parasitic capacitance C0 on the voltage of the first bit line BL<2> is the same as the influence trend of the second coupling capacitance C2 on the voltage of the first complementary bit line BLB<2>. This can compensate for the influence of the existence of the parasitic capacitance C0 on the voltage loss of the first bit line BL<2>, that is, it can compensate for the lost voltage difference between the first bit line BL<2> and the first complementary bit line BLB<2> caused by the parasitic capacitance C0, making the voltage difference between the first bit line BL<2> and the first complementary bit line BLB<2> larger during the period when the first sense amplifier SA1 amplifies the first bit line BL<2>, thereby ensuring the amplification ability of the first sense amplifier SA1 for the first bit line BL<2> and improving the read and write performance of the semiconductor device.

[0063] Taking the first memory array 11A and the second memory array 11B as examples, for the sake of more clearly showing the corresponding relationship between the first bit line, the second bit line, the first complementary bit line, the second complementary bit line, the first conductive portion, the first complementary conductive portion, the second conductive portion one, and the second complementary conductive portion, in Figure 4 and Figure 6 there is the following identification corresponding relationship: For the first bit line BL<2> and the second bit line BL<3>, the corresponding first conductive portion 1211 and second conductive portion 1213 are respectively identified as bl<2> and bl<3>. For the first complementary bit line BLB<2> and the second complementary bit line BLB<3>, the corresponding first complementary conductive portion 1214 and second complementary conductive portion 1212 are respectively identified as blb<2> and blb<3>. For the first bit line BL<6> and the second bit line BL<7>, the corresponding first conductive portion 1211 and second conductive portion 1213 are respectively identified as bl<6> and bl<7>. For the first complementary bit line BLB<6> and the second complementary bit line BLB<7>, the corresponding first complementary conductive portion 1214 and second complementary conductive portion 1212 are respectively identified as blb<6> and blb<7>.

[0064] Among them, the bit line and the complementary bit line both extend along the first direction Y. In some examples, the first conductive portion 1211 and the second complementary conductive portion 1212 also both extend along the first direction Y, and the second conductive portion 1212 and the first complementary conductive portion 1214 also both extend along the first direction Y.

[0065] In some examples, the first conductive portion 1211 and the second complementary conductive portion 1212 are arranged on the same layer. Specifically, along the preset direction Z, the heights of the first conductive portion 1211 and the second complementary conductive portion 1212 in the semiconductor device can be the same, and the thickness of the first conductive portion 1211 can be the same as the thickness of the second complementary conductive portion 1212.

[0066] In some examples, the material of the first conductive portion 1211 can also be the same as the material of the second complementary conductive portion 1212. For example, the material of the first conductive portion 1211 can be at least one of polysilicon, copper, aluminum, or tungsten. It can be understood that the embodiments of the present disclosure do not limit the materials of the first conductive portion 1211 and the second complementary conductive portion 1212. In some other examples, the materials of the first conductive portion 1211 and the second complementary conductive portion 1212 can also be different.

[0067] In some examples, the second conductive portion 1213 and the first complementary conductive portion 1214 can also be arranged on the same layer. Specifically, along the preset direction Z, the heights of the second conductive portion 1213 and the first complementary conductive portion 1214 in the semiconductor device can be the same, and the thickness of the second conductive portion 1213 can be the same as the thickness of the first complementary conductive portion 1214.

[0068] The material of the second conductive portion 1213 can also be the same as the material of the first complementary conductive portion 1214. For example, the material of the second conductive portion 1213 can be at least one of polysilicon, copper, aluminum, or tungsten. It can be understood that the embodiments of the present disclosure do not limit the materials of the second conductive portion 1213 and the first complementary conductive portion 1214. In some other examples, the materials of the second conductive portion 1213 and the first complementary conductive portion 1214 can also be different.

[0069] In some examples, the first conductive portion 1211, the second conductive portion 1213, the first complementary conductive portion 1214, and the second complementary conductive portion 1212 are all arranged on the same layer. The first complementary conductive portion 1214 can be located on one side of the first conductive portion 1211 along the second direction X, and the second complementary conductive portion 1212 can be located on one side of the second conductive portion 1213 along the second direction X.

[0070] In the preset direction Z, the first conductive part 1211 faces the first storage array 11A, and the second complementary conductive part 1212 faces the second storage array 11B; wherein, in the first direction Y, the first conductive part 1211 and the second complementary conductive part 1212 face each other at least partially.

[0071] The second complementary conductive part 1212 may be located in the extending direction of the first conductive part 1211. For example, in the second direction X, the width of the first conductive part 1211 may be the same as the width of the second complementary conductive part 1212.

[0072] In addition, in the second direction X, the width of the first conductive part 1211 may be greater than the width of the first bit line BL<2>, and the width of the second complementary conductive part 1212 may be greater than the width of the second complementary bit line BLB<2>.

[0073] In some examples, when the parasitic capacitance C0 is relatively small, in the first direction Y, the first conductive part 1211 and the second complementary conductive part 1212 face each other at least partially, and the capacitance formed between the facing first conductive part 1211 and the second complementary conductive part 1212 can be used as the first coupling capacitance C1.

[0074] It can be understood that since the area of the region where the first conductive part 1211 and the second complementary conductive part 1212 face each other in the first direction Y is relatively small, in order to increase the magnitude of the first coupling capacitance C1, the conductive interconnection structure may further include: a first common conductive part 1224, the first common conductive part 1224 is located on the side of the first conductive part 1211 facing the second chip 102, and the same first common conductive part 1224 extends to the side of the second complementary conductive part 1212 facing the second chip 102; wherein, a first capacitance C11 is generated between the first common conductive part 1224 and the first conductive part 1211, a second capacitance C12 is generated between the first common conductive part 1224 and the second complementary conductive part 1212, and the first capacitance C11 and the second capacitance C12 are connected in series to form the first coupling capacitance C1.

[0075] In a specific example, the capacitance value of the first coupling capacitance C1 satisfies: C = (80% - 120%) × C0, where C is the capacitance value of the first coupling capacitance C1, and C0 is the parasitic capacitance value between the first bit line and the second bit line. According to the parasitic capacitance value between the first bit line and the second bit line and the corresponding capacitance value of the first coupling capacitance C1, the relative positional relationship between the first conductive part 1211, the second complementary conductive part 1212, and the first common conductive part 1224 can be reasonably designed so that the capacitance value of the first coupling capacitance C1 meets the requirements.

[0076] In the preset direction Z, the second conductive part 1213 can be opposite to the second storage array 11B, and the first complementary conductive part 1214 can be opposite to the first storage array 11A. In a specific example, the second conductive part 1213 and the first complementary conductive part 1214 are arranged on the same layer. In the first direction, the second conductive part 1213 and the first complementary conductive part 1214 are at least partially opposite to each other, and a second coupling capacitor C2 is generated between the second conductive part 1213 and the first complementary conductive part 1214.

[0077] The conductive interconnection structure may further include: a second common conductive part 1225, which is located on the side of the second conductive part 1213 facing the second chip 102 (refer to Figure 2 ), and the same second common conductive part 1225 extends to the side of the first complementary conductive part 1214 facing the second chip 102; wherein, a third capacitor C21 is generated between the second common conductive part 1225 and the second conductive part 1213, a fourth capacitor C22 is generated between the second common conductive part 1225 and the first complementary conductive part 1214, and the third capacitor C21 and the fourth capacitor C22 are connected in series to form the second coupling capacitor C2.

[0078] Similarly, the capacitance value of the second coupling capacitor C2 satisfies: C = (80% - 120%) × C0, where C is the capacitance value of the second coupling capacitor, and C0 is the parasitic capacitance value between the first bit line and the second bit line. According to the parasitic capacitance value between the first bit line and the second bit line and the capacitance value of the corresponding second coupling capacitor C2, the relative positional relationship between the second conductive part 1213, the first complementary conductive part 1214, and the second common conductive part 1225 can be reasonably designed so that the capacitance value of the second coupling capacitor C2 meets the requirements.

[0079] The conductive interconnection structure further includes: a redistribution layer, which includes a plurality of wire parts 1222 that are on the same layer and are separated from each other; a first conductive plug layer, which includes a plurality of first conductive plugs 1221 that are on the same layer and are separated from each other. The first bit line BL<2> and the second complementary bit line BLB<3> are respectively electrically connected to the corresponding wire parts 1222 through the corresponding first conductive plugs 1221; a second conductive plug layer, which includes a plurality of second conductive plugs 1223 that are on the same layer and are separated from each other. One of the wire parts 1222 is electrically connected to the first conductive part 1211 through the corresponding second conductive plug 1223, and the other wire part 1222 is electrically connected to the second complementary conductive part 1212 through the corresponding second conductive plug 1223.

[0080] The first bit line BL<2> is electrically connected to the first conductive portion 1211 through the corresponding first conductive plug 1221, wire portion 1222, and second conductive plug 1223 in sequence; the second complementary bit line BLB<3> is electrically connected to the second complementary conductive portion 1212 through the corresponding first conductive plug 1221, wire portion 1222, and second conductive plug 1223 in sequence.

[0081] Similarly, the second bit line BL<3> and the first complementary bit line BLB<2> are electrically connected to the corresponding wire portion 1222 through the corresponding first conductive plug 1221 respectively; one wire portion 1222 is electrically connected to the second conductive portion 1213 through the corresponding second conductive plug 1223 to realize the electrical connection between the second bit line BL<3> and the second conductive portion 1213, and the other wire portion 1222 is electrically connected to the first complementary conductive portion 1214 through the corresponding second conductive plug 1223 to realize the electrical connection between the first complementary bit line BLB<2> and the first complementary conductive portion 1214.

[0082] Through the redistribution layer, the first conductive plug layer, and the second conductive plug layer, the first bit line BL<2> and the second complementary bit line BLB<3> are respectively redistributed to the positions where the first conductive portion 1211 (i.e., bl<2>) and the second complementary conductive portion 1212 (i.e., blb<3>) are located, so that the second bit line BL<3> and the first complementary bit line BLB<2> are respectively redistributed to the positions where the second conductive portion 1213 (i.e., bl<3>) and the first complementary conductive portion 1214 (i.e., blb<2>) are located.

[0083] Wherein, the material of the wire portion 1222 can be polysilicon, copper, aluminum, tungsten, etc.

[0084] In some examples, a first conductive plug 1221 and a second conductive plug 1223 are both arranged at the edge of the first memory array 11A adjacent to the second memory array 11B; another first conductive plug 1221 and another second conductive plug 1223 are both arranged at the edge of the second memory array 11B adjacent to the first memory array 11A. In this way, it is beneficial to shorten the length of the wire portion 1222, and further beneficial to reduce the parasitic capacitance between adjacent wire portions 1222.

[0085] In the preset direction Z, the first sense amplifier SA1 can be directly opposite to the first memory array 11A; in the preset direction Z, the second sense amplifier SA2 can be directly opposite to the second memory array 11B.

[0086] Some other embodiments of the present disclosure also provide a semiconductor device. The semiconductor device provided in this embodiment is substantially the same as the foregoing embodiment, and the main difference is that in the foregoing embodiment, the first conductive portion and the second complementary conductive portion are respectively opposite to the first storage array and the second storage array. In the following embodiment, both the first conductive portion and the second complementary conductive portion are opposite to the first storage array. The semiconductor device provided in some other embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in order to avoid repetition and redundancy, and without contradiction, the corresponding descriptions in the foregoing embodiments also apply to the following embodiments. The same or similar content as the foregoing embodiments will not be repeated below, and the content that is different from the foregoing embodiments will be described in detail below.

[0087] Figure 9 is a schematic diagram of an architecture of a semiconductor device provided in some other embodiments of the present disclosure, Figure 10 is a schematic diagram of a partial three-dimensional structure of a semiconductor device provided in some other embodiments of the present disclosure, Figure 11 is another schematic diagram of a partial three-dimensional structure of a semiconductor device provided in some other embodiments of the present disclosure, Figure 12 is Figure 11 a schematic diagram of a partial cross-sectional structure cut along the second direction X in

[0088] Referring to Figures 9 to 12 , the semiconductor device includes a first chip and a second chip bonded to each other along a preset direction Z; the first chip includes a plurality of storage arrays arranged along a first direction Y, the plurality of storage arrays include adjacent first storage array 11A and second storage array 11B, the first storage array 11A includes a plurality of bit lines arranged at intervals along a second direction X, the second storage array 11B includes a plurality of complementary bit lines arranged at intervals along the second direction X, wherein, the plurality of bit lines include adjacent first bit line and second bit line, the plurality of complementary bit lines include adjacent first complementary bit line and second complementary bit line; the second chip includes a sense amplifier array corresponding to the storage array one by one, the sense amplifier array includes a plurality of sense amplifiers, the plurality of sense amplifiers include a first sense amplifier SA1 and a second sense amplifier SA2, wherein, the first sense amplifier SA1 is coupled to the first bit line and the first complementary bit line, the second sense amplifier SA2 is coupled to the second bit line and the second complementary bit line; the first chip further includes: a conductive interconnect structure, the conductive interconnect structure is located between the storage array and the second chip, the conductive interconnect structure at least includes: a first conductive portion 2211, the first conductive portion 2211 is electrically connected to the first bit line, and the first conductive portion 2211 is coupled to the first sense amplifier SA1; a second complementary conductive portion 2212, the second complementary conductive portion 2212 is electrically connected to the second complementary bit line 2212, and the second complementary conductive portion 2212 is coupled to the second sense amplifier SA2; wherein, a first coupling capacitor C1 is generated between the first conductive portion 2211 and the second complementary conductive portion 2212.

[0089] Taking the first bit line and the second bit line as the first bit line BL<0> and the second bit line BL<1> respectively, the corresponding first complementary bit line and second complementary bit line are the first complementary bit line BLB<0> and the second complementary bit line BLB<1> respectively. Among them, the first conductive part 2211 is labeled as bl<0>, indicating that the first conductive part 2211 is electrically connected to the first bit line BL<0> correspondingly; the second complementary conductive part 2212 is labeled as blb<1>, indicating that the second complementary conductive part 2212 is electrically connected to the second complementary bit line BLB<1> correspondingly. Similarly, the conductive interconnection structure may further include a second conductive part 2213 and a first complementary conductive part 2214. The second conductive part 2213 in the semiconductor device is labeled as bl<1>, indicating that the second conductive part 2213 is electrically connected to the second bit line BL<1> correspondingly, and the first complementary conductive part 2214 in the semiconductor device is labeled as blb<0>, indicating that the first complementary conductive part 2214 is electrically connected to the first complementary bit line BLB<1> correspondingly.

[0090] In addition, for the bit lines BL<4> and BL<5>, the first bit line BL<4> and the second bit line BL<5> are defined. For the first bit line BL<0> and the second bit line BL<1>, along the preset direction Z, the corresponding first sense amplifier SA1 and second sense amplifier SA2 can both face the first storage array 11A; for the first bit line BL<4> and the second bit line BL<5>, along the preset direction Z, the corresponding first sense amplifier SA1 and second sense amplifier SA2 can both face the second storage array 11B. By reasonably setting the positions of the corresponding first sense amplifier SA1 and second sense amplifier SA2, the distribution density of the sense amplifiers can be reduced, the signal interference problem caused by different sense amplifiers can be reduced, which is beneficial to further improving the amplification ability of the sense amplifiers.

[0091] The first conductive part 2211 and the second complementary conductive part 2212 are arranged on the same layer, and along the preset direction Z, both the first conductive part 2211 and the second complementary conductive part 2212 face the first storage array 11A, and along the second direction X, at least part of the first conductive part 2211 faces the second complementary conductive part 2212, and both the first conductive part 2211 and the second complementary conductive part 2212 extend along the first direction Y.

[0092] The first conductive part 2211 and the second complementary conductive part 2212 adopt a side-to-side facing manner, which is beneficial to increasing the facing area, thereby increasing the capacitance value of the first coupling capacitor C1. Without additionally setting a facing first common conductive part, the capacitance value of the first coupling capacitor C1 formed between the first conductive part 2211 and the second complementary conductive part 2212 can meet the requirements.

[0093] Among them, both the first conductive part 2211 and the second complementary conductive part 2212 extend along the first direction Y.

[0094] In some examples, along the first direction Y, the length of the first conductive part 2211 is the same as that of the second complementary conductive part 2212, and along the second direction X, the first conductive part 2211 and the second complementary conductive part 2212 are completely opposite to each other.

[0095] In other examples, along the first direction Y, the length of the first conductive part 2211 may also be different from that of the second complementary conductive part 2212, and along the second direction X, the first conductive part 2211 and the second complementary conductive part 2212 may also be partially opposite to each other, as long as a first coupling capacitance C1 is ensured between them.

[0096] The conductive interconnect structure further includes: a plurality of conductive plugs 2221. The first bit line BL<0> is in electrical contact with the first conductive part 2211 via the corresponding conductive plug 2221, and the second complementary bit line BLB<1> is in electrical contact with the second complementary conductive part 2212 via the corresponding conductive plug 2221.

[0097] The conductive interconnect structure may further include: a first conductive shielding part 301, which is disposed on the same layer as the first conductive part 2211 and is located on the side of the first conductive part 2211 away from the second complementary conductive part 2212; a second conductive shielding part 302, which is disposed on the same layer as the first conductive shielding part 301 and is located on the side of the second complementary conductive part 2212 away from the first conductive part 2211.

[0098] Among them, the first conductive shielding part 301, the second conductive shielding part 302, the first conductive part 2211, and the second complementary conductive part 2212 may all be disposed on the same layer. These four parts may be obtained by patterning the same conductive layer, and the materials of the four may be the same.

[0099] The first conductive shielding part 301 and the second conductive shielding part 302 can play a role in anti-interference and reduce the interference caused by other conductive structures on the same layer to the first coupling capacitance C1.

[0100] The conductive interconnect structure may further include: a second conductive portion 2213, the second conductive portion 2213 is electrically connected to the second bit line BL<1>, and the second conductive portion 2213 is coupled to the second sense amplifier SA2; a first complementary conductive portion 2214, the first complementary conductive portion 2214 is electrically connected to the first complementary bit line BLB<0>, and the first complementary conductive portion 2214 is coupled to the first sense amplifier SA1; wherein, a second coupling capacitor C2 is generated between the second conductive portion 2213 and the first complementary conductive portion 2214; the second conductive portion 2213 and the first complementary conductive portion 2214 are in the same layer, and in the second direction X, the second conductive portion 2213 and the first complementary conductive portion 2214 are at least partially facing each other.

[0101] The conductive interconnect structure may further include: a third conductive shielding portion 303, the third conductive shielding portion 303 is located on a side of the second conductive portion 2213 away from the first complementary conductive portion 2214, and is also located on a side of the first complementary conductive portion 2214 away from the second conductive portion 2213. The third conductive shielding portion 303, the second conductive portion 2213, and the first complementary conductive portion 2214 may be in the same layer.

[0102] Regarding the function of the third conductive shielding portion 303, reference may be made to the description of the functions of the first conductive shielding portion 301 and the second conductive shielding portion 302 above, and details will not be elaborated here.

[0103] In some examples, in the preset direction Z, the second conductive portion 2213 and the first complementary conductive portion 2214 may also both face the first memory array 11A, and the first conductive portion 2211 and the second conductive portion 2213 are in different layers from each other. For example, the second conductive portion 2213 is located on a side of the first conductive portion 2211 facing the first memory array 11A, or the second conductive portion 2213 is located on a side of the first conductive portion 2211 away from the first memory array 11A.

[0104] When both the first conductive portion 2211 and the second conductive portion 2213 face the first memory array 1A, the conductive interconnect structure may further include an intermediate conductive shielding portion 304, and the intermediate conductive shielding portion 304 is located between the first conductive portion 2211 and the second conductive portion 2213. Wherein, the intermediate conductive shielding portion 304 extends in the second direction X, and there may be a plurality of intermediate conductive shielding portions 304 that are spaced apart and in the same layer between the first conductive portion 2211 and the second conductive portion 2213.

[0105] The material of the intermediate conductive shielding portion 304 may include polysilicon, copper, aluminum, or tungsten, etc. The functions of the intermediate conductive shielding portion 304 include: further reducing the interference of the parasitic capacitance between the first conductive portion and the second conductive portion, and reducing the interference of the parasitic capacitance between the first complementary conductive portion and the second complementary conductive portion.

[0106] Among them, each memory array further includes a plurality of word lines. Correspondingly, each intermediate conductive shielding portion 304 can be connected to a corresponding word line.

[0107] It can be understood that in some other examples, along the preset direction Z, the second conductive portion 2213 and the first complementary conductive portion 2214 can also be directly opposite to the second memory array 11B. Among them, the first conductive portion 2211, the second conductive portion 2213, the first complementary conductive portion 2214, and the second complementary conductive portion 2212 can be arranged in the same layer, and along the second direction X, the first conductive portion 2211 and the second complementary conductive portion 2212 are at least partially directly opposite, and the second conductive portion 2213 and the first complementary conductive portion 2214 are at least partially directly opposite.

[0108] In the above technical solution, by additionally providing the first conductive portion, the second conductive portion, the first complementary conductive portion, and the second complementary conductive portion, the first bit line, the second bit line, the first complementary bit line, and the second complementary bit line are redistributed at positions different from the bit lines, so that a second coupling capacitor is generated between the first complementary conductive portion and the second conductive portion. During the sensing and amplifying period of the sense amplifier, the parasitic capacitance between the first bit line and the second bit line is in the same direction as the second coupling capacitor, that is, the influence trend of the second coupling capacitor on the voltage of the first complementary conductive portion is the same as the influence trend of the parasitic capacitance on the voltage of the first bit line. Furthermore, during the sensing and amplifying period of the sense amplifier, there is a large voltage difference between the first bit line and the first complementary bit line, thereby ensuring that the sense amplifier has excellent amplification ability.

[0109] Similarly, a first coupling capacitor is generated between the first conductive portion and the second complementary conductive portion. During the sensing and amplifying period of the sense amplifier, the parasitic capacitance between the first bit line and the second bit line is in the same direction as the first coupling capacitor, that is, the influence trend of the first coupling capacitor on the voltage of the second complementary conductive portion is the same as the influence trend of the parasitic capacitance on the voltage of the second bit line. Furthermore, during the sensing and amplifying period of the sense amplifier, there is a large voltage difference between the second bit line and the second complementary bit line, thereby ensuring that the sense amplifier has excellent amplification ability.

[0110] Those of ordinary skill in the art can understand that the above embodiments are specific examples for implementing the present disclosure. In actual applications, various changes can be made in form and details without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the protection scope of the embodiments of the present disclosure should be determined by the scope defined by the claims.

Claims

1. A semiconductor device, characterized in that, Including: A first chip and a second chip bonded to each other along a preset direction; The first chip includes a plurality of memory arrays arranged along a first direction, the plurality of memory arrays including adjacent first and second memory arrays, the first memory array including a plurality of bit lines spaced apart along a second direction, the second memory array including a plurality of complementary bit lines spaced apart along the second direction, wherein the plurality of bit lines include adjacent first and second bit lines, and the plurality of complementary bit lines include adjacent first and second complementary bit lines; The second chip includes a sense amplifier array corresponding one-to-one to the memory arrays, the sense amplifier array including a plurality of sense amplifiers, the plurality of sense amplifiers including first and second sense amplifiers, wherein the first sense amplifier is coupled to the first bit line and the first complementary bit line, and the second sense amplifier is coupled to the second bit line and the second complementary bit line; The first chip further includes: a conductive interconnect structure located between the memory arrays and the second chip, the conductive interconnect structure at least including: A first conductive portion electrically connected to the first bit line and coupled to the first sense amplifier; A second complementary conductive portion electrically connected to the second complementary bit line and coupled to the second sense amplifier; Wherein, a first coupling capacitance is generated between the first conductive portion and the second complementary conductive portion.

2. The semiconductor device according to claim 1, wherein The first conductive portion and the second complementary conductive portion are provided on the same layer.

3. The semiconductor device according to claim 2, wherein, In the preset direction, the first conductive portion faces the first memory array, and the second complementary conductive portion faces the second memory array; wherein, in the first direction, the first conductive portion and the second complementary conductive portion are at least partially facing each other.

4. The semiconductor device according to claim 3, characterized in that, The conductive interconnect structure further includes: A first common conductive portion located on a side of the first conductive portion facing the second chip, and the same first common conductive portion extends to a side of the second complementary conductive portion facing the second chip; Wherein, a first capacitance is generated between the first common conductive portion and the first conductive portion, a second capacitance is generated between the first common conductive portion and the second complementary conductive portion, and the first capacitance and the second capacitance are connected in series to form the first coupling capacitance.

5. The semiconductor device according to claim 3, characterized in that, The conductive interconnect structure further includes: A redistribution layer including a plurality of wire portions that are on the same layer and separated from each other; A first conductive plug layer including a plurality of first conductive plugs that are on the same layer and separated from each other, and the first bit line and the second complementary bit line are respectively electrically connected to the corresponding wire portions via the corresponding first conductive plugs; A second conductive plug layer, the second conductive plug layer including a plurality of second conductive plugs that are in the same layer and are discrete from each other, wherein one of the wire portions is electrically connected to the first conductive portion via the corresponding second conductive plug, and the other wire portion is electrically connected to the second complementary conductive portion via the corresponding second conductive plug.

6. The semiconductor device according to claim 5, characterized in that, One of the first conductive plugs and one of the second conductive plugs are both disposed at an edge of the first memory array adjacent to the second memory array; the other first conductive plug and the other second conductive plug are both disposed at an edge of the second memory array adjacent to the first memory array.

7. The semiconductor device according to claim 3, wherein The conductive interconnect structure further includes: A second conductive portion, the second conductive portion being electrically connected to the second bit line, the second conductive portion facing the second memory array, and the second conductive portion being coupled to the second sense amplifier; A first complementary conductive portion, the first complementary conductive portion being electrically connected to the first complementary bit line, the first complementary conductive portion facing the first memory array, and the first complementary conductive portion being coupled to the first sense amplifier; Wherein, the second conductive portion and the first complementary conductive portion are disposed in the same layer, and in the first direction, at least a part of the second conductive portion faces the first complementary conductive portion, and a second coupling capacitance is generated between the second conductive portion and the first complementary conductive portion.

8. The semiconductor device according to claim 7, wherein, The conductive interconnect structure further includes: A second common conductive portion, the second common conductive portion being located on a side of the second conductive portion facing the second chip, and the same second common conductive portion extending to a side of the first complementary conductive portion facing the second chip; Wherein, a third capacitance is generated between the second common conductive portion and the second conductive portion, a fourth capacitance is generated between the second common conductive portion and the first complementary conductive portion, and the third capacitance and the fourth capacitance are connected in series to form the second coupling capacitance.

9. The semiconductor device according to claim 8, wherein, The first conductive portion, the second conductive portion, the first complementary conductive portion, and the second complementary conductive portion are disposed in the same layer; the first complementary conductive portion is located on a side of the first conductive portion along the second direction, and the second complementary conductive portion is located on a side of the second conductive portion along the second direction.

10. The semiconductor device according to claim 7, wherein, In the preset direction, the first sense amplifier faces the first memory array; in the preset direction, the second sense amplifier faces the second memory array.

11. The semiconductor device according to claim 2, wherein, In the preset direction, both the first conductive portion and the second complementary conductive portion face the first memory array, and in the second direction, at least a part of the first conductive portion faces the second complementary conductive portion.

12. The semiconductor device according to claim 11, wherein, The conductive interconnect structure further includes: A plurality of conductive plugs, the first bit line is in electrical contact with the first conductive portion via the corresponding conductive plug, and the second bit line is in electrical contact with the second complementary conductive portion via the corresponding conductive plug.

13. The semiconductor device according to claim 11, wherein The conductive interconnect structure further includes: A first conductive shielding portion, the first conductive shielding portion being disposed in the same layer as the first conductive portion and being located on a side of the first conductive portion away from the second complementary conductive portion; A second conductive shielding portion, the second conductive shielding portion is disposed in the same layer as the first conductive shielding portion, and is located on a side of the second complementary conductive portion away from the first conductive portion.

14. The semiconductor device according to claim 11, wherein, The conductive interconnect structure further includes: A second conductive portion, the second conductive portion is electrically connected to the second bit line, and the second conductive portion is coupled to the second sense amplifier; A first complementary conductive portion, the first complementary conductive portion is electrically connected to the first complementary bit line, and the first complementary conductive portion is coupled to the first sense amplifier; Wherein, a second coupling capacitance is generated between the second conductive portion and the first complementary conductive portion; The second conductive portion and the first complementary conductive portion are in the same layer, and in the second direction, at least a part of the second conductive portion and the first complementary conductive portion are directly opposite to each other, and a second coupling capacitance is generated between the first conductive portion and the second complementary conductive portion.

15. The semiconductor device according to claim 14, wherein, Both the second conductive portion and the first complementary conductive portion are directly opposite to the first memory array; the first conductive portion and the second conductive portion are in different layers from each other.

16. The semiconductor device according to claim 14, wherein The conductive interconnect structure further includes: An intermediate conductive shielding portion, the intermediate conductive shielding portion is located between the first conductive portion and the second conductive portion, and the intermediate conductive shielding portion extends along the second direction.

17. The semiconductor device according to claim 1, wherein In the second direction, the arrangement direction of the first complementary bit line to the second complementary bit line is the same as the arrangement direction of the first bit line to the second bit line; or, in the second direction, the arrangement direction of the first complementary bit line to the second complementary bit line is opposite to the arrangement direction of the first bit line to the second bit line.

18. The semiconductor device according to claim 1, characterized in that, The capacitance value of the first coupling capacitance satisfies: C = (80% - 120%) × C0, where C is the capacitance value of the first coupling capacitance, and C0 is the parasitic capacitance value between the first bit line and the second bit line.

19. The semiconductor device according to claim 1, wherein The bit line, the complementary bit line, the first conductive portion, and the second complementary conductive portion all extend along the first direction.

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