Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: forming a stack including a first region and a second region by sequentially forming a first stack, a recessed target layer, and a second stack over a lower structure; forming a sacrificial isolation layer in the first region; forming a plurality of vertical openings in the first region; forming a plurality of pad isolation openings in the second region; removing the first stack and the second stack from the first region and the second region through the vertical opening and the pad isolation opening; and forming a preliminary level layer in each of the first region and the second region by recessing the recessing target layer of the stack.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0197651, filed on December 29, 2023, which is incorporated herein by reference in its entirety. Technical field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device including three - dimensional memory cells and a method of manufacturing the semiconductor device. Background art

[0004] Recently, in order to meet the requirements of large capacity and miniaturization of memory devices, a three - dimensional (3D) memory device including a plurality of memory cells stacked three - dimensionally has been proposed. 3D memory devices are generally new and need further improvement. Summary of the invention

[0005] Embodiments of the present disclosure relate to a 3D semiconductor device (hereinafter simply referred to as a semiconductor device) including highly integrated memory cells and a method of manufacturing the semiconductor device.

[0006] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a stack including a first region and a second region by sequentially forming a first stack, a target recessed layer, and a second stack over a lower structure; forming a sacrificial isolation layer in the first region; forming a plurality of vertical openings in the first region; forming a plurality of pad isolation openings in the second region; removing the first stack and the second stack from the first region and the second region through the vertical openings and the pad isolation openings; and forming a preliminary horizontal layer in each of the first region and the second region by recessing the target recessed layer of the stack.

[0007] According to another embodiment of the present disclosure, a semiconductor device includes: a lower structure; a vertical stack including horizontal wires vertically stacked from the lower structure; a stepped stack horizontally extending from the vertical stack and including edge portions of the horizontal wires; a linear pad isolation gap formed on two sidewall surfaces of the stepped stack; and a hole - shaped pad isolation gap penetrating the stepped stack and vertically extending in a direction of stacking the horizontal wires.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a substrate including a connection region and a memory cell region; vertical bit lines extending in a first direction perpendicular to the top surface of the substrate and spaced apart from each other in the memory cell region; horizontal layers stacked above the substrate and spaced apart from each other, extending in a second direction intersecting the first direction, and electrically connected to the vertical bit lines; word lines overlapping the horizontal layers and extending in a third direction, and providing stepped pad regions in the connection region; and data storage elements electrically connected to the horizontal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1A is a schematic perspective view showing a memory cell according to an embodiment of the present disclosure.

[0010] Figure 1B is Figure 1A a schematic cross-sectional view of the memory cell shown in

[0011] Figure 1C is a plan view showing Figure 1A the switching element shown in

[0012] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present disclosure.

[0013] Figure 2A and Figure 2B is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 3A is a cross-sectional view taken along Figure 2A and Figure 2B the line A-A' shown in

[0015] Figure 3B is a cross-sectional view taken along Figure 2A and Figure 2B the line B-B' shown in

[0016] Figure 3C is a cross-sectional view taken along Figure 2A and Figure 2B the line C-C' shown in

[0017] Figures 4A to 22C shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0018] Figures 23A to 23F is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0019] Figures 24A to 24C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0020] Figures 25 to 27 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. Detailed Description

[0021] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the disclosure, like reference numerals refer to like components in the various figures and embodiments.

[0022] The drawings are not necessarily to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or on a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer is present between the first layer and the second layer or between the first layer and the substrate.

[0023] The following embodiments of the present disclosure described below relate to three-dimensional memory cells (hereinafter also simply referred to as memory cells). By vertically stacking the memory cells, the parasitic capacitance of the memory cells is reduced while the density of the memory cells is increased.

[0024] Figure 1A is a schematic perspective view showing a memory cell according to an embodiment of the present disclosure. Figure 1B is Figure 1A a schematic cross-sectional view of the memory cell shown in Figure 1C is Figure 1A a plan view of the switching element shown in

[0025] Referring to Figures 1A to 1C , the memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP arranged adjacent to each other in the horizontal direction.

[0026] The first wire BL may be linear and may be oriented in a first direction D1. The first direction D1 may be a vertical direction. The first wire BL may be, for example, a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include, for example, a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include, for example, polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first wire BL may include, for example, polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0027] The switching element TR can be spaced apart from the wire BL in the second direction D2. In the data writing operation and data reading operation performed on the data storage element CAP, the switching element TR can control the supply of voltage (or current) to the data storage element CAP. The switching element TR can include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL can include a horizontal wire. The second wire DWL can be a horizontal word line. The horizontal layer HL can include an active layer. The switching element TR can be, for example, a transistor, and in this case, when the switching element TR is a transistor, the second wire DWL can be used as a gate electrode. The switching element TR can also be referred to as a cell transistor, an access element, or a selection element. The second wire DWL can be referred to as a horizontal gate electrode or a horizontal word line.

[0028] The horizontal layer HL can extend in a second direction D2 that intersects the first direction D1. The second wire DWL can extend in a third direction D3 that intersects the first direction D1 and the second direction D2. The first direction D1 can be a vertical direction, the second direction D2 can be a first horizontal direction, and the third direction D3 can be a second horizontal direction. The horizontal layer HL can extend in the first horizontal direction (i.e., the second direction D2), while the second wire DWL can extend in the second horizontal direction (i.e., the third direction D3). The horizontal layer HL and the second wire DWL can intersect each other. The horizontal layer HL and the second wire DWL can be perpendicular to each other.

[0029] The horizontal layer HL can be horizontally oriented from the first wire BL in the second direction D2. Thus, the first end of the horizontal layer HL can be in contact with the first wire BL. The second wire DWL can have a dual structure. For example, the second wire DWL can include an upper horizontal line G1 and a lower horizontal line G2 that face each other, with the horizontal layer HL therebetween. The interlayer dielectric layer GD can be formed on the top surface and the bottom surface of the horizontal layer HL. The upper horizontal line G1 can be disposed above the horizontal layer HL, and the lower horizontal line G2 can be disposed below the horizontal layer HL. The upper horizontal line G1 and the lower horizontal line G2 can have the same structure. The second wire DWL can include a pair of upper horizontal line G1 and lower horizontal line G2. In the second wire DWL, the same driving voltage can be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 can form a pair coupled to a single memory cell MC. According to another embodiment of the present disclosure, different driving voltages can be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the horizontal lines between the upper horizontal line G1 and the lower horizontal line G2 can be used as a back gate or a shielding gate.

[0030] The horizontal layer HL may include semiconductor materials. For example, the horizontal layer HL may include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present disclosure, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). According to another embodiment of the present disclosure, the horizontal layer HL may include a conductive metal oxide. According to another embodiment of the present disclosure, the horizontal layer HL may include a two-dimensional material. For example, the two-dimensional material may include MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

[0031] The top surface and the bottom surface of the horizontal layer HL may have flat surfaces. The top surface and the bottom surface of the horizontal layer HL may be parallel to each other in the second direction D2.

[0032] The horizontal layer HL may include a channel CH, a first doped region SR located between the channel CH and the first wire BL, and a second doped region DR located between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH may be formed of the oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin body layer.

[0033] In each of the upper horizontal line G1 and the lower horizontal line G2, the width in the second direction D2, for example, the width of the overlapping portion overlapping with the horizontal layer HL, may be greater than the width of the portion not overlapping with the horizontal layer HL. Due to this difference in width, the second wire DWL may have a notched sidewall. Return reference Figure 1C , the second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may refer to the portion overlapping with the channel CH of the horizontal layer HL, while the channel non-overlapping portion NOL may refer to the portion not overlapping with the horizontal layer HL. The channel overlapping portion WLP may have a cross shape or a diamond shape.

[0034] Viewed from a top view, the horizontal layer HL may have a cross shape or a diamond shape. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL may have a curved shape or a circular shape.

[0035] The channel CH and the channel overlapping portion WLP of the second wire DWL may overlap with each other. The channel CH may have a cross shape or a diamond shape. The size of the channel overlapping portion WLP of the second wire DWL may be larger than the size of the channel CH. The channel overlapping portion WLP of the second wire DWL may completely overlap with the channel CH.

[0036] The first doped region SR and the second doped region DR may be doped with impurities of the same conduction type. The first doped region SR and the second doped region DR may be doped with N-type conductive impurities or P-type conductive impurities. The first doped region SR and the second doped region DR may include at least one impurity selected from the following: arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first wire BL, and the second doped region DR may be coupled to the data storage element CAP. The first doped region SR and the second doped region DR may be referred to as the first source / drain region and the second source / drain region.

[0037] The second wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked in sequence. The second wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second wire DWL may include a stack of a low work function material and a high work function material.

[0038] The interlayer dielectric layer GD may be disposed between the horizontal layer HL and the second wire DWL. The interlayer dielectric layer GD may be referred to as a gate dielectric layer. The interlayer dielectric layer GD may be referred to as a horizontal layer side dielectric layer. The interlayer dielectric layer GD may include, for example, silicon oxide, silicon nitride, metal oxide, metal nitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD may include, for example, SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD may be formed by thermal oxidation of a semiconductor material.

[0039] The data storage element CAP may include a storage element such as a capacitor. The data storage element CAP may be horizontally disposed from the switching element TR in the second direction D2. The data storage element CAP may include a first electrode SN that horizontally extends from the horizontal layer HL in the second direction D2. The data storage element CAP may further include a second electrode PN disposed above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN may be horizontally disposed in the second direction D2. The first electrode SN may include an internal space and a plurality of outer surfaces, and the internal space of the first electrode SN may include a plurality of inner surfaces. The outer surfaces of the first electrode SN may include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN may vertically extend in the first direction D1, and the horizontal outer surfaces of the first electrode SN may horizontally extend in the second direction D2 or the third direction D3. The internal space of the first electrode SN may be a three-dimensional space. The dielectric layer DE may conformally cover the inner and outer surfaces of the first electrode SN. The second electrode PN may be disposed in the internal space of the first electrode SN above the dielectric layer DE. Some of the outer surfaces of the first electrode SN may be electrically connected to the second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP may be coupled to the common plate PL.

[0040] The data storage element CAP may be a three-dimensional structure. The first electrode SN may have a three-dimensional structure. The first electrode SN having a three-dimensional structure may have a horizontally oriented three-dimensional structure in the second direction D2. For example, the first electrode SN may have a cylindrical shape, which may include a cylindrical inner surface and a cylindrical outer surface. The portion of the cylindrical outer surface of the first electrode SN oriented in the third direction D3 may be electrically connected to the second doped region DR of the horizontal layer HL via the second contact node SNC. The dielectric layer DE and the second electrode PN may be disposed above the cylindrical inner surface of the first electrode SN. The dielectric layer DE and the second electrode PN may also be disposed above the horizontally oriented outer surfaces of the first electrode SN.

[0041] According to another embodiment of the present disclosure, the first electrode SN may have a columnar or column-cylindrical shape. Column-cylindrical shape means a structure in which the first electrode includes a columnar first portion and a cylindrical second portion, which are combined (i.e., combined). Column-cylindrical electrodes are known in the art, and thus, no more detailed description thereof is required.

[0042] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a titanium nitride / silicon germanium / tungsten nitride stack (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, the silicon germanium may be a gap-filling material filling the interior of the first electrode SN, the titanium nitride (TiN) may be used as the second electrode PN of the capacitor CAP, and the tungsten nitride may be a low-resistance material.

[0043] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include, for example, silicon oxide, silicon nitride, a high-k material, or a combination thereof. The high-k material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0044] The dielectric layer DE can be formed of a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconia (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on zirconia (ZrO2). The ZAZ stack can have a structure in which zirconia (ZrO2), alumina (Al2O3), and zirconia (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack can be referred to as zirconia (ZrO2)-based layers. According to another embodiment of the present disclosure, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnia (HfO2). The dielectric layer DE can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can have a structure in which alumina (Al2O3) is stacked on hafnia (HfO2). The HAH stack can have a structure in which hafnia (HfO2), alumina (Al2O3), and hafnia (HfO2) are sequentially stacked. The HA stack and the HAH stack can be referred to as hafnia (HfO2)-based layers. In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al2O3) can have a larger bandgap energy than zirconia (ZrO2) and hafnia (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconia (ZrO2) and hafnia (HfO2). Accordingly, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap energy than the high-k material. The dielectric layer DE can include, for example, silicon dioxide (SiO2) instead of alumina (Al2O3) as the high-bandgap material. Since the dielectric layer DE includes the high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present disclosure, the dielectric layer DE can include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O2 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacked structures, alumina (Al2O3) can be thinner than zirconia (ZrO2) and hafnia (HfO2).

[0045] According to another embodiment of the present disclosure, the dielectric layer DE can include a high-k material and a high-bandgap material, and can have a laminated structure in which a plurality of high-k materials and a plurality of high-bandgap materials are stacked, or a hybrid structure in which the high-k material and the high-bandgap material are mixed with each other.

[0046] According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0047] According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0048] According to another embodiment of the present disclosure, the dielectric layer DE may include a perovskite dielectric material. The perovskite dielectric material may include SrTiO3, (Ba,Sr)TiO3, BaTiO3, PbTiO3, PZT, PLZT, or PbTiO3.

[0049] According to another embodiment of the present disclosure, an interface control layer (not shown) may be further formed between the first electrode SN and the dielectric layer DE to reduce leakage current. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0050] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor.

[0051] The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material. For example, the storage unit MC may include a thyristor, the first wire BL may be a cathode wire, and the data storage element CAP may be replaced with an anode wire. Thus, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode coupled in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state with a large current flowing or a low conductance state with a small current flowing or no current flowing. The storage unit MC according to this embodiment of the present disclosure may have a "1" state and a "0" state respectively according to the high conductance state and the low conductance state of the thyristor.

[0052] Return reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first wire BL. The first contact node BLC may be electrically connected to the first wire BL and the horizontal layer HL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The second contact node SNC may be electrically connected to the horizontal layer HL and the first electrode SN. The first contact node BLC and the second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. According to another embodiment of the present disclosure, the first contact node BLC and the second contact node SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0053] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present disclosure. Figure 1D The memory cell MC1 may be similar to Figures 1A to 1C the memory cell MC. Hereinafter, the detailed description of the constituent elements that also appear in Figures 1A to 1C will be omitted.

[0054] The memory cell MC1 may include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The horizontal layer HL may include a first doped region SR, a second doped region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0055] The memory cell MC1 may further include a first contact node BLC between the first wire BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP.

[0056] The second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be horizontally arranged in the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first wire BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The first work function electrode G11 may be arranged between the second work function electrode G12 and the third work function electrode G13. The horizontal layer HL may have a thickness thinner than that of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0057] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of different work function materials. The first work function electrode G11 may have a higher work function than the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include low work function materials. The second work function electrode G12 and the third work function electrode G13 may have work functions lower than the mid-gap work function of silicon. For example, the high work function material may have a work function higher than about 4.5 eV, while the low work function material may have a work function lower than about 4.5 eV. In an embodiment, the first work function electrode G11 may include a metal-based material, while the second work function electrode G12 and the third work function electrode G13 may include semiconductor materials.

[0058] The second work function electrode G12 and the third work function electrode G13 may include polysilicon doped with an N-type dopant. The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0059] According to an embodiment of the present disclosure, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may be horizontally arranged in the second direction D2 in the order of the second work function electrode G12 - the first work function electrode G11 - the third work function electrode G13. For example, the first work function electrode G11 may include a metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0060] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a PMP (polysilicon-metal-polysilicon) structure, in which polysilicon, metal, and polysilicon are horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may be doped polysilicon doped with an N-type dopant. The N-type dopant may include phosphorus or arsenic.

[0061] A first barrier layer G12L may be provided between the first work function electrode G11 and the second work function electrode G12. A second barrier layer G13L may be provided between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the top surface, the bottom surface, and the side surface adjacent to the third work function electrode G13 of the first work function electrode G11.

[0062] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13. Therefore, the second wire DWL may have a low resistance. The first work function electrodes G11 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The second work function electrodes G12 and the third work function electrodes G13 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, and a horizontal layer HL is interposed therebetween. The overlapping area between the first work function electrode G11 and the horizontal layer HL may be larger than the overlapping areas between the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrode G13 may have an independent structure overlapping with the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlapping portion WLP and a channel non-overlapping portion NOL, and the second work function electrode G12 and the third work function electrode G13 may become a part of the channel overlapping portion WLP. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 may be in direct contact with each other.

[0063] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a triple work function electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13, which extend in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0064] As Figure 1C shown, each second wire DWL may include a channel overlapping portion WLP and a channel non-overlapping portion NOL. The channel overlapping portion WLP may have a cross shape or a diamond shape. The channel overlapping portion WLP may completely overlap the channel CH. The second wire DWL extending in the third direction D3 may have a notch-shaped sidewall surface formed by the channel overlapping portion WLP and the channel non-overlapping portion NOL. From a top view perspective, the notch-shaped sidewall surface may be provided by a protruding portion formed by the channel overlapping portion WLP and a recessed portion formed by the channel non-overlapping portion NOL. The channel overlapping portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, and the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0065] In the second direction D2, the high work function first work function electrode G11 may be disposed at the center of the second wire DWL, while the low work function second work function electrode G12 and third work function electrode G13 may be disposed at both ends of the second wire DWL, thereby reducing leakage current, such as gate-induced drain leakage (GIDL).

[0066] Since the high work function first work function electrode G11 is disposed at the center of the second wire DWL, the threshold voltage of the switching element TR can be increased. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field can be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field can be formed between the data storage element CAP and the second wire DWL.

[0067] As described above, the memory cell MC1 may include a second wire DWL having a triple work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap with the channel CH. The second work function electrode G12 may be disposed adjacent to the first wire BL and the first doped region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, thereby improving the leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, thereby improving the leakage current. Due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR may be increased. In addition, due to the high work function of the first work function electrode G11, the height of the memory cell MC1 may be reduced, which is advantageous for integration.

[0068] Figure 2A and Figure 2B is a schematic plan view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3A is along Figure 2A and Figure 2B the sectional view taken along the line A-A' shown in Figure 3B is along Figure 2A and Figure 2B the sectional view taken along the line B-B' shown in Figure 3C is along Figure 2A and Figure 2B the sectional view taken along the line C-C' shown in Figure 2A is a plan view at the level of the second wire Figure 2B is a plan view at the level of the horizontal layer. Figures 3A to 3C shows a memory cell array MCA1.

[0069] Refer to Figure 2A , Figure 2B , Figure 3A , Figure 3B and Figure 3C , the semiconductor device 100 may include a plurality of memory cell arrays MCA1, MCA2, MCA3, and MCA4. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of memory cells MC. For a detailed description of each memory cell MC, reference may be made to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0070] The semiconductor device 100 may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked in a first direction D1, and the row array of memory cells MC may include a plurality of memory cells MC arranged horizontally in a second direction D2 and a third direction D3. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a column array of memory cells MC.

[0071] The semiconductor device 100 may include a plurality of sub-memory cell arrays. For example, the semiconductor device 100 may include first to fourth sub-memory cell arrays. The first sub-memory cell array may include a row array of memory cells MC arranged adjacent to each other in a second direction D2, and the first sub-memory cell array may have a mirror type structure in which adjacent memory cells MC share a first wire BL. The second sub-memory cell array may include two memory cells MC arranged adjacent to each other in a second direction D2, and the second sub-memory cell array may have a mirror type structure in which adjacent memory cells MC share a second electrode PN of a data storage element CAP. In the third sub-memory cell array, the memory cells MC may be vertically stacked in a first direction D1. The fourth sub-memory cell array may include a plurality of memory cells MC arranged horizontally in a third direction D3. By combining the first sub-memory cell array and the second sub-memory cell array, the data storage element CAP, the switching element TR, the first wire BL, and the switching element TR may be alternately arranged in the second direction D2 in the mentioned order.

[0072] An inter-cell dielectric layer IL may be disposed between the memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include, for example, silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer. A top dielectric layer TIL may be disposed above the uppermost inter-cell dielectric layer IL.

[0073] Cell isolation layers ISOA and ISOB may be disposed between the memory cells MC arranged adjacent to each other in a third direction D3 (see Figure 2A)。The unit isolation layers ISOA and ISOB may be referred to as vertical inter-unit dielectric layers. The unit isolation layers ISOA and ISOB may include, for example, silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The unit isolation layers ISOA and ISOB may include a first unit isolation layer ISOA and a second unit isolation layer ISOB. The first unit isolation layer ISOA and the second unit isolation layer ISOB may vertically extend in a first direction D1. The first unit isolation layer ISOA and the second unit isolation layer ISOB may have a column structure that vertically extends in the first direction D1. The first unit isolation layer ISOA and the second unit isolation layer ISOB may be alternately arranged in a second direction D2. The first unit isolation layer ISOA may be disposed between the data storage elements CAP in a third direction D3. The second unit isolation layer ISOB may be disposed between the first wires BL in the third direction D3. The second wire DWL may be disposed between the first unit isolation layer ISOA and the second unit isolation layer ISOB in the second direction D2.

[0074] The memory cell arrays MCA1, MCA2, MCA3, and MCA4 may be disposed on the lower structure LS.

[0075] Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of second wires DWL vertically stacked in the first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of horizontal layers HL vertically stacked in the first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of data storage elements CAP vertically stacked in the first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of first wires BL vertically extending in the first direction D1.

[0076] As Figure 1C shown, each second wire DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap with the channel CH. The second wire DWL extending in the third direction D3 may include a plurality of channel overlap portions WLP. Since the channel overlap portions WLP and the channel non-overlap portions NOL are alternately repeated in the third direction D3, the second wire DWL may have a notched sidewall.

[0077] A plurality of first passivation layers BF1 may be disposed between the lowermost second wire DWL in the second wire DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include, for example, silicon oxide. The first wire BL, the second wire DWL, and the data storage element CAP may be electrically disconnected from the lower structure LS through the first to third passivation layers BF1, BF2, and BF3. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The lowermost inter-level dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0078] The first wire BL may vertically extend in a first direction D1 from an upper portion of the lower structure LS. The horizontal layer HL may extend in a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction. The third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0079] Viewed from a top view, the horizontal layer HL may have a cross shape or a rhombus shape. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL may have a curved shape or a circular shape. As Figure 1B shown, the horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP.

[0080] The inter-level dielectric layer GD may be formed on the first surface (or top surface) and the second surface (or bottom surface) of the horizontal layer HL, respectively.

[0081] The horizontal layer spacer HLS may be formed on the sidewall of the horizontal layer HL. The horizontal layer spacer HLS may include a dielectric material. The horizontal layer spacer HLS may include, for example, silicon oxide. The horizontal layer spacer HLS may directly contact the unit isolation layers ISOA and ISOB. The horizontal layers HL disposed adjacent to each other in the third direction D3 may be separated from each other by the horizontal layer spacer HLS.

[0082] The first covering layer BC can be disposed between the second wire DWL and the first wire BL. The second covering layer CC can be disposed between the second wire DWL and the first electrode SN of the data storage element. The first covering layer BC can be disposed between the upper horizontal line G1 and the first wire BL. In addition, the first covering layer BC can be disposed between the lower horizontal line G2 and the first wire BL. The second covering layer CC can be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP. In addition, the second covering layer CC can also be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. A memory cell MC can include a pair of first covering layers BC and a pair of second covering layers CC.

[0083] The first covering layer BC and the second covering layer CC can include a dielectric material. The first covering layer BC and the second covering layer CC can include, for example, silicon oxide, silicon nitride, silicon oxynitride, an air gap, or a combination thereof. The first covering layer BC can include, for example, silicon oxide, while the second covering layer CC can include a stack of silicon oxide and silicon nitride.

[0084] The memory cell MC can further include a first contact node BLC and a second contact node SNC. The first contact node BLC can surround the outer wall of the first wire BL. The second contact node SNC can be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC can include a metal-based material or a semiconductor material. The second contact node SNC can include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC can include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC can include doped polysilicon. The first doped region SR and the second doped region DR can include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0085] The horizontal layer HL of the switching element TR horizontally disposed in the third direction D3 can share a second wire DWL. The horizontal layer HL of the switching element TR horizontally disposed in the third direction D3 can be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 can share a first wire BL. The horizontal layer HL of the switching element TR horizontally disposed in the third direction D3 can share a second wire DWL.

[0086] The first unit isolation layer ISOA can be disposed between the first electrodes SN of the data storage elements CAP in the third direction D3. The first electrodes SN can be separated from each other by the first unit isolation layer ISOA. The second electrode PN of the data storage element CAP can be coupled to the common plate PL.

[0087] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit portion.

[0088] For example, the lower structure LS may include a structure in which a peripheral circuit portion, a metal interconnect structure, and a bonding pad structure are stacked in the mentioned order. The memory cell arrays MCA1, MCA2, MCA3, and MCA4 and the peripheral circuit portion of the lower structure LS may be connected together by wafer bonding.

[0089] The peripheral circuit portion of the lower structure LS may be disposed at a level lower than the memory cell arrays MCA1, MCA2, MCA3, and MCA4. This may be referred to as a COP (Cell over PERI) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell arrays MCA1, MCA2, MCA3, and MCA4. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0090] For example, the peripheral circuit portion may include a sub-word line driver and a sense amplifier. The first wire BL may be coupled to the sense amplifier, and the second wire DWL may be coupled to the sub-word line driver.

[0091] According to another embodiment of the present disclosure, the peripheral circuit portion may be disposed at a level higher than the memory cell arrays MCA1, MCA2, MCA3, and MCA4. This may be referred to as a POC (PERI over Cell) structure.

[0092] According to another embodiment of the present disclosure, the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND, a ferroelectric RAM (FeRAM), a spin transfer torque RAM (STTRAM), a phase change RAM (PCRAM), or a resistive RAM (ReRAM).

[0093] According to another embodiment of the present disclosure, each memory cell MC may be replaced with Figure 1D the memory cell MC1 shown in.

[0094] The semiconductor device 100 may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a memory cell region where memory cells MC are formed, and the second region R2 and the third region R3 may be connection regions. The second region R2 and the third region R3 may be regions forming edge portions of a second wire DWL of the memory cell MC. Memory cells MC of memory cell arrays MCA1, MCA2, MCA3, and MCA4 may be disposed in the first region R1. Edge portions of the second wire DWL of the memory cell arrays MCA1 and MCA3 may be disposed in the second region R2. Edge portions of the second wire DWL of the memory cell arrays MCA2 and MCA4 may be disposed in the third region R3. A plurality of third cell isolation layers ISOC may be formed between the first region R1 and the second region R2. A plurality of third cell isolation layers ISOC may be formed between the first region R1 and the third region R3. The third cell isolation layer ISOC may be formed of the same material as that of the first cell isolation layer ISOA and the second cell isolation layer ISOB.

[0095] The edge portion of the second wire DWL may include a stepped structure. Hereinafter, the structure including the edge portion of the second wire DWL may be simply referred to as "stepped stack WLE". The stepped stack WLE may be disposed in the second region R2 and the third region R3.

[0096] A first pad isolation gap WSL1 and a second pad isolation gap WSL2 may be formed in the second region R2 and the third region R3.

[0097] The second pad isolation gap WSL2 may be disposed between the first pad isolation gaps WSL1. The length of the second pad isolation gap WSL2 in the second direction D2 may be greater than the length in the third direction D3. The second pad isolation gap WSL2 may extend in the second direction D2. The second pad isolation gap WSL2 may include a dielectric material. The first pad isolation gap WSL1 may be referred to as a linear pad isolation gap, and the second pad isolation gap WSL2 may be referred to as a hole-shaped pad isolation gap or a column-shaped pad isolation gap. The first pad isolation gap WSL1 may be formed on two side surfaces of the stepped stack WLE. The second pad isolation gap WSL2 may penetrate the stepped stack WLE.

[0098] The first pad isolation gap WSL1 and the second pad isolation gap WSL2 may include the same material. For example, the first pad isolation gap WSL1 and the second pad isolation gap WSL2 may include, for example, silicon oxide, silicon nitride, silicon carbon oxide, or a combination thereof.

[0099] The stepped stacked WLE can be supported by a first pad isolation slit WSL1 and a second pad isolation slit WSL2. The first pad isolation slit WSL1 and the second pad isolation slit WSL2 can be referred to as "support slits". The second pad isolation slit WSL2 can be referred to as a "columnar isolation slit". The second pad isolation slit WSL2 can suppress the bending of the stepped stacked WLE. Therefore, the second pad isolation slit WSL2 can increase the structural strength of the stepped stacked WLE.

[0100] The first pad isolation slit WSL1 can be disposed between the memory cell arrays MCA1 and MCA3 in the second region R2. The stepped stacked WLEs of the memory cell arrays MCA1 and MCA3 can be spaced apart from each other by the first pad isolation slit WSL1. The first pad isolation slit WSL1 can be disposed between the memory cell arrays MCA2 and MCA4 in the third region R3. The stepped stacked WLEs of the memory cell arrays MCA2 and MCA4 can be spaced apart from each other by the first pad isolation slit WSL1.

[0101] Return reference Figures 3A to 3C , the memory cell array MCA1 can include a vertical stack WLS extending from the first region R1 to the second region R2. The portion of the vertical stack WLS disposed in the second region R2 can simply be referred to as the stepped stacked WLE. The other memory cell arrays MCA2, MCA3, and MCA4 can also include a vertical stack WLS and a stepped stacked WLE.

[0102] The vertical stack WLS can include a plurality of second conductive wires DWL and inter-cell dielectric layers IL stacked in a first direction D1. Each second conductive wire DWL of the vertical stack WLS can have a dual structure including an upper horizontal line G1 and a lower horizontal line G2. The vertical stack WLS can further include a horizontal layer HL, an interlayer dielectric layer GD, and a horizontal layer spacer HLS. The horizontal layer spacer HLS can be disposed horizontally between the horizontal layers HL. The interlayer dielectric layer GD can be disposed on the top surface and the bottom surface of the horizontal layer HL, respectively.

[0103] The stepped stacked WLE may include a plurality of second wires DWL and inter-cell dielectric layers IL stacked in a first direction D1. Each second wire DWL of the stepped stacked WLE may have a dual structure including an upper horizontal line G1 and a lower horizontal line G2. The stepped stacked WLE may further include a pad portion GP between the upper horizontal line G1 and the lower horizontal line G2. The pad portion GP may electrically connect the upper horizontal line G1 and the lower horizontal line G2 to each other. The upper horizontal line G1, the lower horizontal line G2, and the pad portion GP may include the same material. For example, the upper horizontal line G1, the lower horizontal line G2, and the pad portion GP may include a metal-based material. The stepped stacked WLE may include a plurality of steps (or step terraces) whose lengths gradually decrease in the stacking direction (i.e., the first direction D1). The length of the pad portion GP may gradually decrease in the stacking direction (i.e., the first direction D1). The horizontal length of the pad portion GP in a third direction D3 may be different at each level. For example, the horizontal length of the lowermost pad portion GP may be the largest, while the horizontal length of the uppermost pad portion GP may be the smallest.

[0104] The second wires DWL of the stepped stacked WLE may be respectively coupled to contact plugs CT.

[0105] As described above, the memory cell array MCA1 of the semiconductor device 100 may include: a vertically stacked WLS above a lower structure LS, the vertically stacked WLS including second wires DWL that are alternately vertically stacked starting from the upper part of the lower structure LS, with a first pad isolation gap WSL1 therebetween; a stepped stacked WLE extending from the second wires DWL; and a second pad isolation gap WSL2 that extends vertically in the direction in which the second wires DWL are stacked while passing through the stepped stacked WLE.

[0106] According to the above embodiments of the present disclosure, the second pad isolation gap WSL2 may prevent bridging between the second wires DWL in the second region R2. In addition, the second pad isolation gap WSL2 may serve as a wet barrier when forming the pad portion GP, thereby further preventing bridging between the vertically stacked second wires DWL. Specifically, when the second pad isolation gap WSL2 includes silicon oxycarbide, it may serve as a wet barrier when forming the pad portion GP, and thus may further prevent bridging between the vertically stacked second wires DWL.

[0107] Figures 4A to 22C A method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0108] Figure 4A is a plan view at the level of the fourth layer 14 showing a method for forming a stack SB and sacrificial isolation openings 15A, 15B, and 15C, Figure 4B is along Figure 4AA plan view taken along line A-A' shown in [the figure]. Figure 4C is a cross-sectional view taken along Figure 4A line A1-A1' shown in [the figure].

[0109] Referring to Figures 4A to 4C , a stack SB can be formed over a lower structure 11. The lower structure 11 can be a material suitable for semiconductor processing, including at least one of a conductive material, a dielectric material, and a semiconductor material. A plurality of materials can be formed over the lower structure 11. The lower structure 11 can include a semiconductor substrate. The lower structure 11 can include a silicon-containing material. The lower structure 11 can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination of the above materials, or multiple layers of the above materials. The lower structure 11 can also include other semiconductor materials such as germanium. The lower structure 11 can include a III / V semiconductor substrate, such as a compound semiconductor substrate such as gallium arsenide (GaAs). The lower structure 11 can include, for example, a silicon-on-insulator (SOI) substrate.

[0110] The stack SB can include a plurality of sub-stacks stacked alternately. Each sub-stack can include a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14 stacked in the mentioned order. The first layer 12A and the third layer 12B can be formed of the same material and can include silicon germanium or single-crystalline silicon germanium. The second layer 13 and the fourth layer 14 can be formed of the same material and can include single-crystalline silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 can be formed by an epitaxial growth process. The lowermost first layer 12A can be used as a seed layer during the epitaxial growth process. The first layer 12A can be thinner than the second layer 13, and the fourth layer 14 can be thicker than the second layer 13.

[0111] According to this embodiment of the present disclosure, the stack SB can include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, a third stack SB3, and a fourth stack SB4. The stack SB can include the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, the third stack SB3, the fourth layer 14, and the fourth stack SB4 stacked in the mentioned order. The stack SB can also include a fifth stack SB5 located at the uppermost layer. Each of the first stack SB1, the second stack SB2, the third stack SB3, and the fourth stack SB4 can include a three-layer stack of the first layer 12A / second layer 13 / third layer 12B. For example, when the first layer 12A and the third layer 12B include silicon germanium layers and the second layer 13 includes a single-crystalline silicon layer, the first stack SB1, the second stack SB2, the third stack SB3, and the fourth stack SB4 can include a stack of first silicon germanium / single-crystalline silicon / second silicon germanium (SiGe / Si / SiGe). The fifth stack SB5 can also include the second layer 13 over the three-layer stack of the first layer 12A / second layer 13 / third layer 12B.

[0112] The second layer 13 may include a first single-crystalline silicon layer, and the fourth layer 14 may include a second single-crystalline silicon layer. The second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer. For example, the second single-crystalline silicon layer may be disposed between the first stack SB1 and the second stack SB2. Each of the first stack SB1 to the fourth stack SB4 may include a stack of a first silicon-germanium layer / a first single-crystalline silicon layer / a second silicon-germanium layer, and the second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer.

[0113] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as "sacrificial layers", and the fourth layer 14 may be referred to as a "recess target layer". The stack SB may be referred to as a "vertical stack". The stack SB may be formed by alternating a plurality of sacrificial layers and recess target layers. The sacrificial layers may include the first to fourth stacks SB1 to SB4, and each of the first to fourth stacks SB1 to SB4 may include a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. The recess target layer may include the fourth layer 14. Each sacrificial layer may include a three-layer stack of a first silicon-germanium layer / a first single-crystalline silicon layer / a second silicon-germanium layer, and each recess target layer may include a single layer of the second single-crystalline silicon layer, and the second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer.

[0114] Referring to FIGS. 2 to Figure 3C as described above, when the memory cells MC are vertically stacked, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, the third stack SB3, the fourth layer 14, and the fourth stack SB4 may be alternately stacked several times in the mentioned order.

[0115] The stack SB may include a first region R1, a second region R2, and a third region R3. The first region R1 may be an area where memory cells are to be formed, while the second region R2 and the third region R3 may be areas where pad portions are to be formed. The first region R1 may be disposed between the second region R2 and the third region R3.

[0116] Subsequently, portions of the stack SB can be etched to form a plurality of sacrificial isolation openings 15A, 15B, and 15C. The sacrificial isolation openings 15A and 15B can be initial openings for cell isolation and can include a first sacrificial isolation opening 15A and a second sacrificial isolation opening 15B. The first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B can be formed in the first region R1. When forming the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B, a third sacrificial isolation opening 15C can be formed at the boundary portion between the first region R1 and the second region R2 and at the boundary portion between the first region R1 and the third region R3. The size of the first sacrificial isolation opening 15A can be larger than that of the second sacrificial isolation opening 15B. The third sacrificial isolation opening 15C can be larger than the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B. A portion of the third sacrificial isolation opening 15C can be larger than the second sacrificial isolation opening 15B and smaller than the first sacrificial isolation opening 15A. From a top view perspective, the first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can have a rectangular shape. According to another embodiment of the present disclosure, the first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can have a circular shape or an oval shape.

[0117] According to another embodiment of the present disclosure, the sacrificial isolation openings 15A, 15B, and 15C can be referred to as sacrificial isolation trenches.

[0118] The first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can extend vertically in the first direction D1. In the first region R1, the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B can be alternately arranged in the second direction D2. A plurality of first sacrificial isolation openings 15A can be arranged in the third direction D3. A plurality of second sacrificial isolation openings 15B can be arranged in the third direction D3. The first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can penetrate the stack SB in the first direction D1.

[0119] After forming the sacrificial isolation openings 15A, 15B, and 15C, the exposed portions of the lower structure 11 below the sacrificial isolation openings 15A, 15B, and 15C can be etched. Accordingly, the bottom surfaces of the sacrificial isolation openings 15A, 15B, and 15C can extend into the lower structure 11. The bottom surfaces of the sacrificial isolation openings 15A, 15B, and 15C can include a U-shaped profile. Due to the sacrificial isolation openings 15A, 15B, and 15C, the fourth layer 14 can have a mesh pattern.

[0120] Figure 5A is a plan view at the level of the fourth layer 14 showing a method for forming the sacrificial isolation layers 16A, 16B, and 16C,Figure 5B is a cross-sectional view taken along Figure 5A the line A1 - A1’ shown in Figure 5C is a cross-sectional view taken along Figure 5A the line B - B’ shown in

[0121] Referring to Figures 5A to 5C , sacrificial isolation layers 16A, 16B, and 16C can be formed to fill sacrificial isolation openings 15A, 15B, and 15C. The sacrificial isolation layers 16A, 16B, and 16C can include a first sacrificial isolation layer 16A, a second sacrificial isolation layer 16B, and a third sacrificial isolation layer 16C. The first sacrificial isolation layer 16A can fill the first sacrificial isolation opening 15A, the second sacrificial isolation layer 16B can fill the second sacrificial isolation opening 15B, and the third sacrificial isolation layer 16C can fill the third sacrificial isolation opening 15C.

[0122] The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include the same material. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can be formed of a dielectric material. For example, the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. Forming the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include forming a sacrificial isolation material over the stack SB to fill the sacrificial isolation openings 15A, 15B, and 15C, and planarizing the sacrificial isolation material to expose the topmost layer of the stack SB. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can have different sizes or different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A can be greater than that of the second sacrificial isolation layer 16B. The lengths of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B in the third direction D3 can be the same, and the lengths in the second direction D2 can be different. The length of the first sacrificial isolation layer 16A in the second direction D2 can be greater than the length of the second sacrificial isolation layer 16B. The size (or volume) of the third sacrificial isolation layer 16C can be greater than those of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B.

[0123] The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can extend vertically in the first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B can be alternately arranged in the second direction D2 in the first region R1. A plurality of first sacrificial isolation layers 16A can be arranged in the third direction D3. A plurality of second sacrificial isolation layers 16B can be arranged in the third direction D3. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can penetrate the stack SB in the first direction D1.

[0124] Each of the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C may include a stack of a sacrificial liner layer and a sacrificial gap-fill layer. The sacrificial liner layer and the sacrificial gap-fill layer may include, for example, silicon oxide, silicon nitride, silicon oxynitride, amorphous carbon, or a combination thereof. The sacrificial liner layer may be used as a barrier layer to prevent loss of the sacrificial gap-fill layer during subsequent recess processes of the fourth layer 14.

[0125] After forming the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C, a stepped structure ST may be formed in each of the second region R2 and the third region R3 by etching the stack SB.

[0126] To form Figure 5CThe stepped structure ST shown can form multiple thinning mask layers and perform multiple thinning etches. The thinning mask layer may include a photoresist pattern, and the thinning etch may be a process of etching the stack SB from the topmost stack order. For example, a first etching process including a first thinning mask layer and a first thinning etch, a second etching process including a second thinning mask layer and a second thinning etch, a third etching process including a third thinning mask layer and a third thinning etch, and a fourth etching process including a fourth thinning mask layer and a fourth thinning etch may be sequentially performed. The first etching process may include etching the fifth stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4. In the second etching process, the second thinning mask layer may be formed by thinning the first thinning mask layer, and the second thinning etch may include etching the fifth stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4, and etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SB4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3. In the third etching process, the third thinning mask layer may be formed by thinning the second thinning mask layer, and the third thinning etch may include: etching the stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4; etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SB4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3; etching the first layer 12A of the third stack SB3, the fourth layer 14 between the third stack SB3 and the second stack SB2, and the third layer 12B and the second layer 13 of the second stack SB2 to stop at the first layer 12A of the second stack SB2.In the fourth etching process, the fourth thinning mask layer can be formed by thinning the third thinning mask layer, and the third thinning etch can include: etching the fifth stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4; etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SB4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3; etching the first layer 12A of the third stack SB3, the fourth layer 14 between the third stack SB3 and the second stack SB2, and the third layer 12B and the second layer 13 of the second stack SB2 to stop at the first layer 12A of the second stack SB2. The thinning process for forming the thinning mask layer can refer to a process of horizontally reducing the width of the thinning mask layer.

[0127] By using the above-mentioned thinning mask layer and thinning etch, a plurality of steps ST1 to ST4 can be formed in the second region R2 and the third region R3, respectively. The steps ST1 to ST4 may not be formed in the first region. Among the steps ST1 to ST4, the second step ST2 and the third step ST3 may have a four-layer structure of the second layer 13, the third layer 12B, the fourth layer 14, and the first layer 12A stacked in the mentioned order. Among the steps ST1 to ST4, the first step ST1 may have a seven-layer structure of the second layer 13, the third layer 12B, the fourth layer 14, the first layer 12A, the second layer 13, the third layer 12B, and the second layer 13 stacked in the mentioned order. Among the steps ST1 to ST4, the fourth step ST4 may have a five-layer structure of the first layer 12A, the second layer 13, the third layer 12B, the fourth layer 14, and the first layer 12A stacked in the mentioned order.

[0128] After forming the steps ST1 to ST4, an interlayer dielectric layer ILD covering the steps ST1 to ST4 can be formed, as Figure 5C shown. According to another embodiment of the present disclosure, before forming the interlayer dielectric layer ILD, a stepped passivation layer PSL covering the profile of the steps ST1 to ST4 can be formed. The stepped passivation layer PSL and the interlayer dielectric layer ILD can include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0129] Figure 6A is a plan view at the level of the fourth layer 14 showing a method for forming the sacrificial vertical openings V1' and V2', Figure 6B is a cross-sectional view taken along the Figure 6A line A-A' shown in Figure 6C is a cross-sectional view taken along the Figure 6A line C-C' shown in

[0130] ReferenceFigures 6A to 6C A hard mask layer pattern 17 may be formed over the stack SB, the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a mask layer. The hard mask layer pattern 17 may have a plurality of hole-shaped openings defined therein.

[0131] A portion of the stack SB may be etched in the first region R1 by using the hard mask layer pattern 17 as an etching barrier. As a result, a plurality of sacrificial vertical openings V1’ and V2’ may be formed in the stack SB. The sacrificial vertical openings V1’ and V2’ may include a first sacrificial vertical opening V1’ and a second sacrificial vertical opening V2’. From a top view perspective, the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may be hole-shaped openings. The first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may vertically extend in a first direction D1. The first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may be formed by etching the stack SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1’ may be formed by etching the stack SB between the second sacrificial isolation layer 16B. The second sacrificial vertical opening V2’ may be formed by etching the stack SB between the first sacrificial isolation layer 16A. The first sacrificial vertical opening V1’ may be disposed between the second sacrificial isolation layer 16B in a third direction D3. The second sacrificial vertical opening V2’ may be disposed between the first sacrificial isolation layer 16A in a third direction D3. From a top view perspective, the cross-sections of the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may have a square, circular, or elliptical shape.

[0132] When forming the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’, a plurality of pad isolation openings V11’ and V12’ penetrating the stack SB in the second region R2 and the third region R3 may be formed simultaneously. The pad isolation openings V11’ and V12’ may include a linear pad isolation opening V11’ and a hole-shaped pad isolation opening V12’. The hole-shaped pad isolation opening V12’ may be disposed between the linear pad isolation openings V11’.

[0133] Figure 7A A plan view showing a method for forming the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20, Figure 7B and Figure 7C is Figure 7A a cross-sectional view taken along line A-A’ in Figure 7D is Figure 7A a cross-sectional view taken along line C-C’ in

[0134] Referring to Figures 7A to 7D, a part of the hard mask layer pattern 17 can be trimmed (see reference numeral "17T").

[0135] By using the trimmed hard mask layer pattern 17 as a barrier, the first layer 12A and the third layer 12B can be selectively removed from the first region R1, the second region R2, and the third region R3. The first layer 12A and the third layer 12B can be selectively removed from the first region R1 through the sacrificial vertical openings V1' and V2'. The first layer 12A and the third layer 12B can be selectively removed from the second region R2 and the third region R3 through the pad isolation openings V11' and V12'. The first layer 12A and the third layer 12B can be selectively removed based on the difference between the etching selectivity of the second layer 13 and the fourth layer 14 and the etching selectivity of the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B can be removed by a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer, and the second layer 13 and the fourth layer 14 include a single crystal silicon layer, the silicon germanium layer can be etched by using an etchant or etching gas selective to the single crystal silicon layer.

[0136] The second layer 13 and the fourth layer 14 can be recessed. The second layer 13 and the fourth layer 14 can be recessed by a wet etching process or a dry etching process. According to this embodiment of the present disclosure, the fourth layer 14 can be partially etched when the second layer 13 is removed. As a result, the second layer 13 can be removed, and the fourth layer 14 can be thinned, as shown by the reference numeral "14A". The recess process for forming the thin fourth layer 14A (i.e., the preliminary horizontal layer 14A) can be referred to as a thinning process or a trimming process of the fourth layer 14. By recessing the top surface, the bottom surface, and the side surface of the fourth layer 14, the preliminary horizontal layer 14A can be formed. The preliminary horizontal layer 14A can be referred to as a thin body active layer. The preliminary horizontal layer 14A can include a single crystal silicon layer. The recess process for forming the preliminary horizontal layer 14A can use, for example, HSC1 (hot SC-1). HSC1 can include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of approximately 1:4:20. The second layer 13 and the fourth layer 14 can be selectively etched by using HSC1.

[0137] The preliminary horizontal layer 14A can be formed by the recess process of the fourth layer 14 as described above, and the horizontal recess 18 can be formed between the preliminary horizontal layers 14A. Each of the top surface and the bottom surface of the preliminary horizontal layer 14A can include a flat surface. The preliminary horizontal layer 14A can horizontally extend from the first region R1 to the second region R2 and the third region R3. The preliminary horizontal layer 14A and the horizontal recess 18 can be formed in the first region R1, the second region R2, and the third region R3.

[0138] From the perspective of the top view, the preliminary horizontal layer 14A of the first region R1 may have a cross shape. The side surface of the preliminary horizontal layer 14A may have a curved shape or a circular shape. The preliminary horizontal layer 14A of the second region R2 and the third region R3 may have a flat shape.

[0139] After forming the preliminary horizontal layer 14A, the first sacrificial vertical opening V1', the second sacrificial vertical opening V2', and the pad isolation openings V11' and V12' may be expanded as shown by the reference numerals V1, V2, V11, and V12 in the drawings, respectively. The first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may have the same size. The preliminary horizontal layer 14A may be spaced apart from each other in the second direction D2 through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A may have a shape that combines multiple cross shapes in the third direction D3.

[0140] When forming the preliminary horizontal layer 14A, the surface of the lower structure 11 may be recessed by a predetermined depth. As a result, the depths of the first sacrificial vertical opening V1, the second sacrificial vertical opening V2, and the pad isolation openings V11 and V12 may be increased.

[0141] The first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be alternately disposed between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical opening V1 may be disposed between the second sacrificial isolation layers 16B in the third direction D3, while the second sacrificial vertical opening V2 may be disposed between the first sacrificial isolation layers 16A in the third direction D3.

[0142] Through the above-mentioned recessing process, the preliminary horizontal layer 14A and the horizontal recess 18 may be formed in the first region R1, the second region R2, and the third region R3. By simultaneously removing the first layer 12A, the second layer 13, and the third layer 12B from the first region R1, the second region R2, and the third region R3, the process can be simplified. In addition, residues of the first layer 12A, the second layer 13, and the third layer 12B will not remain at the boundary portions between the first region R1 and the second region R2 and between the first region R1 and the third region R3. Due to the formation of the linear pad isolation openings V11 and the hole-shaped pad isolation openings V12, it is beneficial to simultaneously remove the first layer 12A, the second layer 13, and the third layer 12B from the first region R1, the second region R2, and the third region R3. Through the combination of the linear pad isolation openings V11 and the hole-shaped pad isolation openings V12, the first layer 12A, the second layer 13, and the third layer 12B can be easily removed from the second region R2 and the third region R3 without leaving residues.

[0143] After forming the preliminary horizontal layer 14A, return to reference Figure 7C, a first dielectric layer 19 can be formed to completely cover the preliminary horizontal layer 14A. The first dielectric layer 19 can include silicon nitride. The first dielectric layer 19 can completely cover the top surface, bottom surface, and side surfaces of the preliminary horizontal layer 14A.

[0144] When forming the first dielectric layer 19, a dummy dielectric layer 19D can be formed on the surface of the lower structure 11. A part of the first dielectric layer 19 can completely cover the top surface, bottom surface, and side surfaces of the hard mask layer pattern 17.

[0145] Subsequently, a second dielectric layer 20 can be formed on the first dielectric layer 19. The second dielectric layer 20 can be filled between vertically adjacent first dielectric layers 19. The second dielectric layer 20 can include, for example, silicon oxide. A part of the second dielectric layer 20 can be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontal recess (see the reference numeral '18' shown in Figures 6B to 6C the attached drawing) can be filled with the first dielectric layer 19 and the second dielectric layer 20.

[0146] A sacrificial pillar 21 can be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial pillar 21 can include amorphous carbon as a sacrificial material. According to another embodiment of the present disclosure, a pillar capping layer can be further formed on the sacrificial pillar 21. The pillar capping layer can include a metal-based material. The pillar capping layer can include titanium nitride. Forming the sacrificial pillar 21 can include depositing the sacrificial material and planarizing the sacrificial material. The planarization process for forming the sacrificial pillar 21 can be performed until the uppermost first dielectric layer 19 is exposed. Subsequently, the uppermost second dielectric layer 20 can also be planarized until the uppermost first dielectric layer 19 is exposed. The sacrificial pillar 21 can not be formed between the vertically stacked first dielectric layers 19.

[0147] The second dielectric layer 20 and the sacrificial pillar 21 can form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2 that fill the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The first sacrificial pillar structure SV1 can fill the first sacrificial vertical opening V1, and the second sacrificial pillar structure SV2 can fill the second sacrificial vertical opening V2. According to another embodiment of the present disclosure, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present disclosure, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. Viewed from a top view, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be hole-shaped sacrificial pillars.

[0148] A portion of the first dielectric layer 19 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. Thus, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may also include a portion of the first dielectric layer 19.

[0149] The pad isolation openings V11 and V12 may also be filled with the first dielectric layer 19 and the second dielectric layer 20. The sacrificial pillar 21 may be formed on the second dielectric layer 20 located in the pad isolation openings V11 and V12.

[0150] The second dielectric layer 20 and the sacrificial pillar 21 may form pad isolation structures SV11 and SV12 that fill the pad isolation openings V11 and V12. The pad isolation structures SV11 and SV12 may include a linear pad isolation structure SV11 and a columnar pad isolation structure SV12. The linear pad isolation structure SV11 may fill the linear pad isolation opening V11, and the columnar pad isolation structure SV12 may fill the hole-shaped pad isolation opening V12. According to another embodiment of the present disclosure, the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present disclosure, the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 may include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0151] A portion of the first dielectric layer 19 may be conformally formed on the surfaces of the pad isolation openings V11 and V12, so that the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 may also include a portion of the first dielectric layer 19.

[0152] The first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may be formed in the first region R1, and the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 may be formed in the second region R2 and the third region R3.

[0153] The preliminary horizontal layer 14A may be formed between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B disposed in the second direction D2. The first dielectric layer 19 may be formed between the preliminary horizontal layers 14A, and the second dielectric layer 20 may be disposed within the first dielectric layer 19. The first dielectric layer 19 may surround the second dielectric layer 20. The first dielectric layer 19 may include a first surrounding portion and a second surrounding portion. Among them, the first surrounding portion may surround the preliminary horizontal layer 14A along the A-A' direction, and the second surrounding portion may surround the second dielectric layer 20 between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B disposed in the second direction D2.

[0154] As described above, when forming the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20, a unit mode structure can be formed in the first region R1. The unit mode structure can include a plurality of unit modes CM. Each unit mode CM can include a plurality of mode layers. The mode layers can refer to the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20. Each unit mode CM can include an oxide-nitride-silicon-nitride (ONSN) stack. Here, the ONSN stack can refer to a structure in which silicon oxide, first silicon nitride, single crystal silicon layer, and second silicon nitride are stacked in sequence. The silicon oxide can correspond to the second dielectric layer 20, the first silicon nitride and the second silicon nitride can correspond to the first dielectric layer 19, and the single crystal silicon layer can correspond to the preliminary horizontal layer 14A. The unit mode structure including a plurality of unit modes CM can be referred to as a vertical stack. From another perspective, the unit mode structure can include an oxide-nitride-silicon-nitride-oxide (ONSNO) stack. Here, the ONSNO stack can refer to a structure in which first silicon oxide, first silicon nitride, single crystal silicon layer, second silicon nitride, and second silicon oxide are stacked in sequence.

[0155] As described above, by following Figures 4A to 7D a series of processes, the sub-stack of the stack body SB can be replaced by unit modes. The first layer 12A, the second layer 13, and the third layer 12B can be replaced by the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 can become the preliminary horizontal layer 14A through a recess process. The first dielectric layer 19 can be referred to as the trimming target layer.

[0156] Figure 8A and Figure 8B are plan views showing a method for forming the unit isolation openings 22A and 22B and the horizontal layer 14B, Figure 8C is a cross-sectional view taken along Figure 8A and Figure 8B the line A1 - A1' shown in. Figure 8A is a plan view at the level of the horizontal layer 14B, Figure 8B is a plan view at the level of the first dielectric layer 19.

[0157] Refer to Figures 8A to 8C, the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B can be removed to form unit isolation openings 22A and 22B in the first region R1. The unit isolation openings 22A and 22B can include a first unit isolation opening 22A and a second unit isolation opening 22B. The first unit isolation opening 22A can be formed by removing the first sacrificial isolation layer 16A. The second unit isolation opening 22B can be formed by removing the second sacrificial isolation layer 16B. When removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be covered by a mask layer (not shown). The first unit isolation opening 22A and the second unit isolation opening 22B can expose the side surfaces of the preliminary horizontal layer 14A and the first dielectric layer 19 in the A1-A1' direction.

[0158] When removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, the edge sacrificial isolation layer 16C can be removed. As a result, edge isolation openings 22C can be formed at the boundary portions between the first region R1 and the second region R2 and between the first region R1 and the third region R3.

[0159] The side surfaces of the preliminary horizontal layer 14A can be trimmed in the second direction D2 and the third direction D3 through the first unit isolation opening 22A and the second unit isolation opening 22B. As a result, a trimmed horizontal layer 14B can be formed. A horizontal layer gap 14G can be formed on the side surface of the horizontal layer 14B. The horizontal layer gap 14G and the horizontal layer 14B can be disposed between the first dielectric layers 19. The horizontal layer 14B can be referred to as a "trimmed horizontal layer pattern".

[0160] When forming the horizontal layer 14B, the surface of the lower structure 11 (such as the bottom surfaces of the first unit isolation opening 22A and the second unit isolation opening 22B) can be extended.

[0161] The horizontal layer 14B can be disposed between the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 in the second direction D2. From a top view perspective, the horizontal layer 14B can have a cross shape. The size of the cross shape of the horizontal layer 14B can be smaller than that of the preliminary horizontal layer 14A. The preliminary horizontal layer 14A can have a shape formed by merging multiple cross shapes, and the horizontal layer 14B can have a shape of a cross separated individually in the third direction D3. Horizontal layer gaps 14G can be formed between the horizontal layers 14B disposed in the third direction D3. The first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be disposed between the horizontal layers 14B in the second direction D2.

[0162] The side surfaces of the preliminary horizontal layer 14A can be trimmed in the second direction D2 and the third direction D3 through the edge isolation openings 22C. As a result, a trimmed horizontal layer 14B can be formed in the first region R1, and a pad-level horizontal layer 14R can be formed in the second region R2. The pad-level horizontal layer 14R and the horizontal layer 14B can be spaced apart from each other. The pad-level horizontal layer 14R can be referred to as a pad-level semiconductor layer.

[0163] Figure 9A and 9B is a plan view showing a method for forming the horizontal layer-level spacer 23 and the first dielectric layer 19A, Figure 9C is along Figure 9A and Figure 9B is a cross-sectional view taken along the line A1 - A1' shown in Figure 9D is along Figure 9A is a cross-sectional view taken along the line B - B' shown in Figure 9A is a plan view at the level of the horizontal layer 14B, Figure 9B is a plan view at the level of the first dielectric layer 19A.

[0164] Referring to Figures 9A to 9D , the horizontal layer-level spacer 23 can be formed on the side surfaces of the horizontal layer 14B. Forming the horizontal layer-level spacer 23 can include forming a spacer material on the side surfaces of the horizontal layer 14B and etching the spacer material. The horizontal layer-level spacer 23 can include a dielectric material, such as silicon oxide. The horizontal layer-level spacer 23 can fill the horizontal layer-level gap 14G and can separate the horizontal layers 14B arranged in the third direction D3 from each other.

[0165] A part of the first dielectric layer 19 can be horizontally trimmed through the first unit isolation opening 22A and the second unit isolation opening 22B. After the trimming process, the first dielectric layer 19 can be retained, as indicated by the reference numeral "19A". Thus, from the perspective of the line A1 - A1', a pair of first dielectric layers 19A can be arranged between the horizontal layers 14B, and the second dielectric layer 20 can be arranged between this pair of first dielectric layers 19A.

[0166] According to Figures 9A to 9D , the width of the first dielectric layer 19A in the third direction D3 can be greater than the width of the horizontal layer 14B between the first unit isolation openings 22A and between the second unit isolation openings 22B. In summary, the trimming depth of the first dielectric layer 19 in the third direction D3 can be less than the trimming depth of the preliminary horizontal layer 14A.

[0167] A pair of first dielectric layers 19A can vertically overlap with one horizontal layer 14B. The trimmed first dielectric layer 19A can be referred to as a trimmed first dielectric layer.

[0168] Returning to the reference Figure 9D, the horizontal layer 14B can be disposed in the first region R1, and the pad-level horizontal layer 14R can be disposed in the second region R2 and the third region R3. The pad-level horizontal layers 14R can be vertically stacked in a stepped structure, and the horizontal lengths of the pad-level horizontal layers 14R can be different from each other.

[0169] Figure 10A and Figure 10B is a plan view showing a method for forming the cell isolation layers 24A and 24B, Figure 10C is along Figure 10A and Figure 10B the cross-sectional view taken along the line A1 - A1' shown in Figure 10A is a plan view at the horizontal level of the horizontal layer 14B showing a method for forming the cell isolation layers 24A and 24B, Figure 10B is a plan view at the horizontal level of the first dielectric layer 19A showing a method for forming the cell isolation layers 24A and 24B.

[0170] Referring to Figures 10A to 10C , the cell isolation layers 24A and 24B can be formed to fill the first cell isolation opening 22A and the second cell isolation opening 22B. The cell isolation layers 24A and 24B can include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B can include the same material. The first cell isolation layer 24A and the second cell isolation layer 24B can be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B can include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or a combination thereof. In a top view, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B can include, for example, silicon oxide.

[0171] Forming the first unit isolation layer 24A and the second unit isolation layer 24B may include forming unit isolation materials filling the unit isolation openings 22A and 22B, and planarizing the unit isolation materials and the topmost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first unit isolation layer 24A and the second unit isolation layer 24B may have different sizes or different volumes. The first unit isolation layer 24A and the second unit isolation layer 24B may include a dual structure of silicon oxide and silicon carbon oxide. For example, silicon carbon oxide may be deposited after depositing silicon oxide. According to another embodiment of the present disclosure, the first unit isolation layer 24A and the second unit isolation layer 24B may include embedded air gaps, and the embedded air gaps may be provided while depositing silicon carbon oxide. The second sacrificial column structure SV2 may be disposed between the first unit isolation layers 24A in the third direction D3, while the first sacrificial column structure SV1 may be disposed between the second unit isolation layers 24B in the third direction D3. The first unit isolation layer 24A and the second unit isolation layer 24B may vertically extend in the first direction D1.

[0172] The first unit isolation layer 24A and the second unit isolation layer 24B may correspond to Figure 2A and 2B the unit isolation layers ISOA and ISOB shown in. Each of the first unit isolation layer 24A and the second unit isolation layer 24B may include a stack of a unit isolation liner layer and a unit isolation gap fill layer. The unit isolation liner layer may include, for example, silicon oxide, while the unit isolation gap fill layer may include silicon carbon oxide. According to another embodiment of the present disclosure, the first unit isolation layer 24A and the second unit isolation layer 24B may include embedded air gaps, and the embedded air gaps may be provided when forming the unit isolation gap fill layer.

[0173] The first unit isolation layer 24A and the second unit isolation layer 24B and the first dielectric layer 19A may directly contact each other. The horizontal level spacer 23 may be disposed between the horizontal layer 14B and the first unit isolation layer 24A and the second unit isolation layer 24B.

[0174] Subsequently, a method for forming storage units (i.e., vertical wires, horizontal layers, dual horizontal wires, and data storage elements) will be described.

[0175] Figure 11A and Figure 11B is a plan view showing a method for forming the first dielectric layer pattern 19B, Figures 12A to 12D is a cross-sectional view taken along the line A-A' shown in Figure 11A and Figure 11B showing a method for forming the first dielectric layer pattern 19B. Figure 11A is a plan view at the level of the horizontal layer 14B, Figure 11Bis a plan view at the level of the first dielectric layer pattern 19B.

[0176] First, referring to Figure 12A , the hard mask layer 17 and the uppermost first dielectric layer 19A can be removed to form a hard mask layer level recess 25.

[0177] Referring to Figure 12B , a top dielectric layer 26 can be formed to fill the hard mask layer level recess 25. The top dielectric layer 26 can include, for example, silicon oxide.

[0178] Referring to Figure 12C , an initial vertical opening 27 can be formed by removing the first sacrificial pillar structure SV1.

[0179] Subsequently, the second dielectric layer 20 can be horizontally recessed. As a result, the first dielectric layer 19A and the dummy dielectric layer 19D can be exposed through the initial vertical opening 27.

[0180] Referring to Figure 12D , the first dielectric layer 19A and the dummy dielectric layer 19D can be selectively horizontally recessed. As a result, a first dielectric layer pattern 19B and a dielectric layer level recess 28 can be formed. A portion of the horizontal layer 14B can be exposed through the dielectric layer level recess 28.

[0181] The first dielectric layer pattern 19B and the dielectric layer level recess 28 can be formed in the first region R1. The first dielectric layer 19A can be retained in the second region R2 and the third region R3.

[0182] Figure 13A and Figure 13B are plan views showing a method for forming a vertical sacrificial structure 29 and a vertical level path 30, Figure 13C is along Figure 13A and Figure 13B is a cross-sectional view taken along the line A-A' shown in Figure 13A is a plan view at the level of the horizontal layer 14B, Figure 13B is a plan view at the level of the first dielectric layer pattern 19B.

[0183] Referring to Figures 13A to 13C , a vertical sacrificial structure 29 can be formed to fill the dielectric layer level recess 28 and the initial vertical opening 27. The vertical sacrificial structure 29 can include a sacrificial material. The vertical sacrificial structure 29 can include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0184] A vertical level path 30 can be formed by removing the sacrificial pillar 21 of the first sacrificial pillar structure SV1.

[0185] A lower layer gap 19D' can be formed by removing the dummy dielectric layer 19D below the vertical level path 30.

[0186] Figure 14A and Figure 14B is a plan view showing a method for forming a horizontal-level depression 33, Figure 14C is a cross-sectional view taken along line A-A' shown in Figure 14A and Figure 14B FIG. Figure 14D is a cross-sectional view taken along line C-C' shown in Figure 14A and Figure 14B FIG. Figure 14A is a plan view at the level of the horizontal layer 14B, Figure 14B is a plan view at the level of the horizontal-level depression 33.

[0187] Referring to Figures 14A to 14D , a first hole-shaped vertical opening 32 can be formed in the first region R1 by cutting the second dielectric layer 20 along the vertical-level path 30. When forming the first hole-shaped vertical opening 32, isolation trenches SVH11 and SVH12 can be formed in the second region R2 and the third region R3.

[0188] A first passivation layer BF1 can be formed to fill the lower-layer gap 19D'. The first passivation layer BF1 can include, for example, silicon oxide. Forming the first passivation layer BF1 can include depositing silicon oxide to fill the lower-layer gap 19D' and etching the silicon oxide.

[0189] A second passivation layer BF2 can be formed in the lower region of the first hole-shaped vertical opening 32. For example, the surface of the lower structure 11 can be oxidized to form the second passivation layer BF2.

[0190] To form the horizontal-level depression 33 in the first region R1, the first dielectric layer pattern 19B can be removed through the first hole-shaped vertical opening 32. A portion of the horizontal layer 14B can be exposed by the horizontal-level depression 33. The horizontal-level depression 33 can be provided between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal-level depressions 33 can face each other with a horizontal layer 14B therebetween.

[0191] To form the pad-level depression 33P in the second region R2 and the third region R3, the first dielectric layer pattern 19B can be removed through the isolation trenches SVH11 and SVH12. The pad-level depression 33P can expose the top surface and the bottom surface of the pad-level horizontal layer 14R1. The pad-level depression 33P can be provided between the second dielectric layer 20 and the pad-level horizontal layer 14R1. Two pad-level depressions 33P can face each other with a pad-level horizontal layer 14R1 therebetween.

[0192] Figure 15A is a plan view showing a method for forming a horizontal wire 35, Figure 15B is a cross-sectional view taken along line A-A' shown in Figure 15A FIG.Figure 15C is a cross-sectional view taken along the line C-C' shown in Figure 15A . Figure 15D is a cross-sectional view taken along the line B-B' shown in Figure 15A .

[0193] Referring to Figures 15A to 15D , an interlayer dielectric layer 34 may be formed over the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 may be referred to as a gate dielectric layer. The interlayer dielectric layer 34 may correspond to the interlayer dielectric layer GD shown in Figures 1A to 3B .

[0194] The interlayer dielectric layer 34 may be formed by oxidizing the surface of the horizontal layer 14B. According to another embodiment of the present disclosure, the interlayer dielectric layer 34 may be formed by a deposition process of silicon oxide. The interlayer dielectric layer 34 may include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 34 may include, for example, SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0195] A horizontal wire 35 may be formed over the interlayer dielectric layer 34 to fill the horizontal-level recess 33. Forming the horizontal wire 35 may include depositing a conductive material over the interlayer dielectric layer 34 to fill the horizontal-level recess 33 and etching back the conductive material. The horizontal wire 35 may include a pair of first horizontal wires 35A and second horizontal wires 35B facing each other, with the horizontal layer 14B therebetween. The first horizontal wire 35A and the second horizontal wire 35B may include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal wire 35A and the second horizontal wire 35B may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal wire 35A and the second horizontal wire 35B may include a TiN / W stack of titanium nitride and tungsten stacked in sequence. The first horizontal wire 35A and the second horizontal wire 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more.

[0196] The horizontal wire 35 may correspond to the second wire DWL shown in Figures 1A to 1D , and the first horizontal wire 35A and the second horizontal wire 35B may correspond to the upper horizontal line G1 and the lower horizontal line G2. Referring to Figures 1A to 1D , each of the first horizontal wire 35A and the second horizontal wire 35B may have a cross shape and may include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0197] The horizontal wire 35 may be formed in the first region R1 and may extend to be disposed in the second region R2 and the third region R3. The horizontal wire 35 may be formed in the horizontal-level recess 33 in the first region R1 and in the pad-level recesses 33P in the second region R2 and the third region R3. The interlayer dielectric layer 34 may also be formed in the first to third regions R1, R2, and R3, respectively.

[0198] Figure 16A and Figure 16B is a plan view showing a method for forming the vertical wire 39, Figure 16C is a cross-sectional view taken along Figure 16A and Figure 16B the line A-A' shown in

[0199] Referring to Figures 16A to 16C , a first covering layer 36 may be formed on the first side surface of the horizontal wire 35. The first covering layer 36 may include, for example, silicon oxide, silicon nitride, silicon carbon oxide, embedded air gaps, or a combination thereof. The first covering layer 36 may be formed by depositing a covering material and performing an etch-back process. When forming the first covering layer 36 or after forming the first covering layer 36, a portion of the interlayer dielectric layer 34 may be removed to expose the first edge portions of each horizontal layer 14B.

[0200] The vertical wire 39 may be formed to be coupled to the first edge portions of each horizontal layer 14B. The vertical wire 39 may fill the first hole-shaped vertical opening 32. The vertical wire 39 may be commonly coupled to the horizontal layer 14B disposed in the first direction D1. The vertical wire 39 may include titanium nitride, tungsten, or a combination thereof. The vertical wire 39 may be referred to as a bit line or a vertical bit line.

[0201] Before forming the vertical wire 39, a first doped region 37 and a first contact node 38 may be formed. The first doped region 37 may be formed in the first edge portions of the horizontal layer 14B. Forming the first doped region 37 may include depositing polysilicon doped with an N-type impurity, performing a heat treatment, and removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, the first doped region 37 may be formed by a doping process of doping impurities.

[0202] The first contact node 38 may include doped polysilicon. The first doped region 37 may include impurities diffused from the first contact node 38. A metal silicide layer may also be formed between the vertical wire 39 and the first contact node 38.

[0203] The vertical wire 39 may correspond to the first wire BL as Figures 1A to 3C shown.

[0204] Figure 17A is a plan view showing a method for forming the pad-level gap GP',Figure 17B is a cross-sectional view taken along Figure 17A the line B - B' shown in Figure 17C is a cross-sectional view taken along Figure 17A the line C - C' shown in

[0205] Referring to Figures 17A to 17C , a horizontal layer pattern 14B and a horizontal wire 35 can be formed in the first region R1, and a pad-level horizontal layer 14R1 and a horizontal wire 35 can be formed in the second region R2 and the third region R3. The first horizontal wire 35A and the second horizontal wire 35B of the horizontal wire 35 can face each other perpendicularly, with the horizontal layer pattern 14B therebetween, and they can include edge portions that extend to overlap with the pad-level horizontal layer 14R1.

[0206] The edge portions of the horizontal wire 35 can be disposed in the second region R2 and the third region R3.

[0207] The edge portions of the horizontal wire 35 can be formed into a stepped structure as Figure 5C shown.

[0208] All pad-level horizontal layers 14R1 can be removed from the second region R2 and the third region R3. As a result, a pad-level gap GP' can be formed between the horizontal wires 35. The pad-level gap GP' can be set to a stepped structure.

[0209] Figure 18A is a plan view showing a method for forming a pad portion GP, Figure 18B is a cross-sectional view taken along Figure 18A the line B - B' shown in Figure 18C is a cross-sectional view taken along Figure 18A the line C - C' shown in

[0210] Referring to Figures 18A to 18C , a pad portion GP can be formed to fill the pad-level gap GP'. The pad portion GP can couple the first horizontal wire G1 and the second horizontal wire G2 to each other. The pad portion GP, the first horizontal wire G1, and the second horizontal wire G2 can include the same material.

[0211] The process of forming the pad portion GP described above can be performed after forming the vertical wire 39. For example, after forming the vertical wire 39 in the first region R1, exposing the second region R2 and the third region R3 and masking the first region R1, removing the pad-level horizontal layer 14R1 from the second region R2 and the third region R3, and forming the pad portion GP can be sequentially performed.

[0212] Figure 19A is a plan view showing a method for forming a storage opening 41, Figure 19B is a cross-sectional view taken along Figure 19ACross-sectional view taken along line A-A' shown in

[0213] Reference Figure 19A and Figure 19B , a part of the vertical sacrificial structure 29 can be removed to form a second hole-shaped vertical opening 40. The first side surface of the horizontal layer 14B, i.e., the second edge portion, can be exposed through the second hole-shaped vertical opening 40. After forming the second hole-shaped vertical opening 40, a part of the vertical sacrificial structure 29 can be removed to form the lowermost dielectric layer 29L on one side of the first passivation layer BF1.

[0214] A third passivation layer BF3 can be formed on the surface of the lower structure 11. The third passivation layer BF3 can include, for example, silicon oxide.

[0215] The second edge portion of the horizontal layer 14B can be horizontally recessed in the second direction D2. Thus, the horizontal layer is retained, as indicated by the reference numeral "HL".

[0216] After forming the horizontal layer HL, the vertical sacrificial structure 29 can be selectively recessed to form a second covering layer 29C. The second covering layer 29C can include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0217] After forming the second covering layer 29C, a storage opening 41 that horizontally extends from the second hole-shaped vertical opening 40 can be formed. The storage opening 41 can be referred to as a capacitor opening.

[0218] The horizontal layer HL can include a first edge and a second edge. The first edge can refer to the portion coupled to the first contact node 38 and the vertical wire 39, while the second edge can refer to the portion exposed by the storage opening 41.

[0219] The storage opening 41 can be provided between the second dielectric layers 20. The second covering layer 29C can be respectively provided on the upper and lower portions of the horizontal layer HL.

[0220] As described above, forming the horizontal layer HL and the storage opening 41 can include forming the second hole-shaped vertical opening 40, recessing the horizontal layer 14B, and forming the second covering layer 29C.

[0221] Figure 20A is a plan view showing a method for forming the second contact node 42, Figure 20B is along Figure 20A Cross-sectional view taken along line A-A' shown in

[0222] Reference Figure 20A and 20B, a second doped region 43 can be formed in the second edge of the horizontal layer HL respectively. Forming the second doped region 43 can include depositing polysilicon doped with N-type impurities, performing a heat treatment, and removing the doped polysilicon. The second doped region 43 can include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, after performing the heat treatment, the doped polysilicon can be retained.

[0223] The second contact node 42 can be formed above the second edge of the horizontal layer HL. The second contact node 42 can include doped polysilicon. The second doped region 43 can include impurities diffused from the second contact node 42.

[0224] Each horizontal layer HL can include a first doped region 37, a second doped region 43, and a channel 44 that are horizontally arranged in the second direction D2. The channel 44 can be defined between the first doped region 37 and the second doped region 43. The channel 44 can vertically overlap with the horizontal wire 35. As Figures 1A to 1D shown, the horizontal layer HL can have a cross shape, and the channel 44 can also have a cross shape.

[0225] Figure 21A is a plan view showing a method for forming the first electrode 45, Figure 21B is along Figure 21A the cross-sectional view taken along the line A-A' shown.

[0226] Referring to Figure 21A and Figure 21B , the first electrode 45 of the data storage element can be formed above the second contact node 42. The first electrode 45 can have a horizontally oriented cylindrical shape. The first electrode 45 can be respectively disposed in the storage opening 41. The first electrodes 45 disposed adjacent to each other in the second direction D2 can be spaced apart from each other through the second hole-shaped vertical opening. The first electrodes 45 disposed adjacent to each other in the third direction D3 can be spaced apart from each other by the second unit isolation layer 24A.

[0227] Figure 22A is a plan view showing a method for forming the dielectric layer 47 and the second electrode 48, Figure 22B and Figure 22C is along Figure 22A the cross-sectional view taken along the line A-A' shown.

[0228] Referring to Figure 22A and Figure 22B , the second dielectric layer 20 can be horizontally recessed (see reference numeral '46'). Thus, the outer wall of the first electrode 45 can be exposed. The recessed second dielectric layer 20 can correspond to Figure 3B the inter-cell dielectric layer IL shown.

[0229] See Figure 22A and Figure 22C, the dielectric layer 47 and the second electrode 48 can be sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 can be a data storage element CAP.

[0230] Each first electrode 45 can include an internal space and a plurality of outer surfaces. The internal space of the first electrode 45 can include a plurality of inner surfaces. The outer surfaces of the first electrode 45 can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode 45 can vertically extend in a first direction D1, and the horizontal outer surfaces of the first electrode 45 can horizontally extend in a second direction D2 or a third direction D3. The internal space of the first electrode 45 can be a three-dimensional space. The dielectric layer 47 can conformally cover the inner and outer surfaces of the first electrode 45. The second electrode 48 can be disposed in the internal space of the first electrode 45 above the dielectric layer 47. Some of the outer surfaces of the first electrode 45 can be electrically connected to the second doped region 43 of the horizontal layer HL.

[0231] The first electrode 45 can have a cylindrical shape. The cylindrical shape of the first electrode 45 can include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode 45 can be electrically connected to the second doped region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 can be disposed on the cylindrical inner surface of the first electrode 45. The second electrode 48 can vertically extend in the first direction D1.

[0232] The first electrode 45 and the second electrode 48 can include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 can include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 48 can include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 can be a titanium nitride / silicon germanium / tungsten nitride stack (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, the silicon germanium can be a gap-filling material for filling the internal space of the first electrode 45, the titanium nitride (TiN) can be the second electrode 48 of the data storage element CAP, and the tungsten nitride can be a low-resistance material.

[0233] The dielectric layer 47 can be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 can include, for example, silicon oxide, silicon nitride, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The dielectric layer 47 can include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 47 can include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, an HA (HfO2 / Al2O3) stack, an HAH (HfO2 / Al2O3 / HfO2) stack, an HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or an HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0234] According to another embodiment of the present disclosure, an interface control layer for reducing leakage current can also be formed between the first electrode 45 and the dielectric layer 47. The interface control layer can include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or combinations thereof. The interface control layer can also be formed between the second electrode 45 and the dielectric layer 47.

[0235] Figures 23A to 23F is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0236] can be formed by performing a series of processes as Figures 4A to 7B shown to form the preliminary horizontal layer 14A.

[0237] Subsequently, referring to Figure 23A , an interlayer dielectric layer 34' that completely covers the preliminary horizontal layer 14A can be formed.

[0238] Subsequently, a conductive layer 35' that respectively surrounds the preliminary horizontal layer 14A can be formed on the interlayer dielectric layer 34'. When forming the conductive layer 35', a dummy conductive layer 35D can be formed on the surface of the lower structure 11.

[0239] A second dielectric layer 20 can be formed on the conductive layer 35'. A sacrificial pillar 21 can be formed on the second dielectric layer 20. The second dielectric layer 20 and the sacrificial pillar 21 can form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2.

[0240] Referring to Figure 23B, to form the first hole-shaped vertical opening 32, the sacrificial pillars 21 of the first sacrificial pillar structure SV1 can be removed. Subsequently, the second dielectric layer 20 (see reference numeral '31') can be cut.

[0241] After removing a part of the dummy conductive layer 35D', the first buffer layer BF1 can be formed. The first buffer layer BF1 can include, for example, silicon oxide. The surface of the lower structure 11 can be oxidized to form the second buffer layer BF2.

[0242] Reference Figure 23C , a first recess process can be performed on the conductive layer 35'.

[0243] Reference Figure 23D , the first contact node 38 and the vertical wire 39 can be formed to fill the first hole-shaped vertical opening 32. Before forming the first contact node 38, the first capping layer 36 can be formed. After forming the first capping layer 36, the first doped region 37 can be formed.

[0244] Reference Figure 23E , to form the second hole-shaped vertical opening 40, a part of each second sacrificial pillar structure SV2 can be removed.

[0245] Subsequently, a second recess process can be performed on the conductive layer 35'.

[0246] As a result, the double-level wire 35 including the first horizontal wire 35A and the second horizontal wire 35B can be formed. The first edge portion of the horizontal wire 35 can be defined by the first recess process (see Figure 23C ), and the second edge portion E2 of the horizontal wire 35 can be defined by the second recess process (see Figure 23E ).

[0247] Reference Figure 23F , the second capping layer 29C can be formed. The second capping layer 29C can be disposed between the second dielectric layers 20. The second capping layer 29C can be disposed on the second side surfaces of the first horizontal wire 35A and the second horizontal wire 35B.

[0248] The horizontal layer pattern 14B can be horizontally recessed. As a result, the horizontal layer HL can be formed. The storage opening 41 can be formed by forming the second capping layer 29C and the horizontal layer HL. The storage opening 41 can expose the end portion of the second side of the horizontal layer HL. The storage opening 41 can be disposed between the second dielectric layers 20.

[0249] Subsequently, reference Figures 21A to 22B , the data storage element CAP including the second doped region 43, the second contact node 42, the first electrode 45, the dielectric layer 47, and the second electrode 48 can be formed.

[0250] Figures 24A to 24CIt is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0251] Referring Figure 24A , a stack SB10 can be formed on the lower structure 11. The stack SB10 can include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack can include a plurality of silicon-germanium layers 12 and a plurality of single-crystalline silicon layers 14' alternately stacked by an epitaxial growth process. The silicon-germanium layer 12 can be a sacrificial layer, and the single-crystalline silicon layer 14' can be a recess target layer. The silicon-germanium layer 12 can correspond to Figure 4B the first layer 12A or the third layer 12B, and the single-crystalline silicon layer 14' can correspond to Figure 4B the fourth layer 14. Different from the stack SB Figure 4B , the stack SB10 can include an alternating stack of a silicon-germanium layer 12 and a single-crystalline silicon layer 14'.

[0252] Subsequently, a series of processes shown in Figures 4A to 5C can be performed. For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B can be formed in the stack SB10. The sacrificial isolation layers 16A and 16B can include a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap-fill layer L3, and a sacrificial capping layer L4.

[0253] Subsequently, referring Figure 24B , a hard mask layer pattern 17 can be formed on the stack SB10.

[0254] Subsequently, the stack SB10 can be etched by using the hard mask layer pattern 17 as an etching barrier. As a result, a plurality of first and second sacrificial vertical openings V1' and V2' can be formed in the stack SB10.

[0255] Referring Figure 24C , a preliminary horizontal layer 14A' and a horizontal recess 18 can be formed. The preliminary horizontal layer 14A' and the horizontal recess 18 can be formed by a process of recessing the silicon-germanium layer 12 and the single-crystalline silicon layer 14' as shown in Figure 24B . After removing the silicon-germanium layer 12, a process of recessing the single-crystalline silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to the preliminary horizontal layer 14A as shown in Figure 7B .

[0256] The silicon-germanium layer 12 can be recessed by a wet etching process or a dry etching process. The silicon-germanium layer 12 can be etched by using an etchant or an etching gas that is selective with respect to the single-crystalline silicon layer 14'.

[0257] The recess process of the single-crystalline silicon layer 14' for forming the preliminary horizontal layer 14A' may use, for example, HSC1 (thermal SC-1). HSC1 may include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of approximately 1:4:20. The single-crystalline silicon layer 14' may be selectively etched by using HSC1.

[0258] After forming the preliminary horizontal layer 14A', the first sacrificial vertical opening and the second sacrificial vertical opening may be enlarged as indicated by reference numerals 'V1' and 'V2'. The preliminary horizontal layer 14A' may be arranged to be spaced apart from each other through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 in the second direction D2. The preliminary horizontal layer 14A' may have a shape in which a plurality of crosses are combined in the third direction D3. When forming the preliminary horizontal layer 14A', the surface of the lower structure 11 may be recessed by a predetermined depth (see reference numeral '11A'). As a result, the depth of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 may be increased.

[0259] Subsequently, a series of processes as Figures 8A to 22C shown may be performed.

[0260] Figures 25 to 27 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. The memory cell arrays MCA100, MCA200, and MCA300 may be similar to the Figure 3A memory cell array MCA. Hereinafter, for the detailed description of the Figure 3A constituent elements that also appear in Figures 25 to 27 the above, reference may be made to the embodiments of the present disclosure described above.

[0261] Referring to Figure 25 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0262] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in the first direction D1, and the row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in the second direction D2 and the third direction D3.

[0263] Each memory cell MC10 may include a first wire BL, a switching element TR, and a data storage element CAP. For the detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0264] The switching element TR may include a horizontal layer HL and a second wire DWL. The horizontal layer HL may extend in a second direction D2. The second wire DWL may extend in a third direction D3.

[0265] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2 facing each other, with the horizontal layer HL therebetween. As Figure 3B shown, an interlayer dielectric layer GD may be formed on the top surface and the bottom surface of the horizontal layer HL.

[0266] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewall surfaces FS extending in the third direction D3. The flat sidewall surfaces FS may refer to vertical sidewall surfaces. The flat sidewall surfaces FS may have a linear shape extending in the third direction D3.

[0267] Referring Figure 26 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0268] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in the second direction D2 and the third direction D3.

[0269] Each memory cell MC20 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0270] The switching element TR may include a horizontal layer HL and a second wire SWL. The horizontal layer HL may extend in a second direction D2. The second wire SWL may extend in a third direction D3.

[0271] The second wire SWL may have a single structure. For example, the second wire SWL may be disposed above the horizontal layer HL. As Figure 3B shown, an interlayer dielectric layer GD may be formed between the top surface of the horizontal layer HL and the second wire SWL. According to another embodiment of the present disclosure, the second wire SWL may be disposed below the horizontal layer HL.

[0272] The second wire SWL may include a pair of flat sidewall surfaces FS extending in the third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0273] According to another embodiment of the present disclosure, as Figure 1C shown, the second wire SWL may include a channel overlap portion WLP and a channel non - overlap portion NOL.

[0274] Referring to Figure 27 , the memory cell array MCA300 may include a plurality of memory cells MC30.

[0275] The memory cell array MCA300 may include a three - dimensional array of memory cells MC30. The three - dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0276] Each memory cell MC30 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above - mentioned embodiments of the present disclosure.

[0277] The switching element TR may include a horizontal layer HL and a second wire GAA - WL. The horizontal layer HL may extend in a second direction D2. The second wire GAA - WL may extend in a third direction D3.

[0278] The second wire GAA - WL may have a gate - all - around structure GAA. For example, the second wire GAA - WL may extend in a third direction D3 while surrounding the horizontal layer HL. An inter - layer dielectric layer GD may be formed between the horizontal layer HL and the second wire GAA - WL. The inter - layer dielectric layer GD may surround each horizontal layer HL.

[0279] The second wire GAA - WL may include a pair of flat sidewall surfaces FS extending in a third direction D3. The flat sidewalls FS may also be referred to as "vertical sidewalls".

[0280] According to another embodiment of the present disclosure, each memory cell may include a first wire BL horizontally extending in a third direction D3, a second wire DWL vertically extending in a first direction D1, and a horizontal layer HL horizontally extending in a second direction D2. The second wire DWL may have a dual structure, or may be replaced by a single - structure or a gate - all - around structure.

[0281] According to an embodiment of the present disclosure, the sacrificial layer may be removed from the cell array region and the connection region simultaneously, thereby minimizing the process of removing the sacrificial layer.

[0282] According to an embodiment of the present disclosure, low power consumption and high integration of 3D memory cells can be achieved.

[0283] Although embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the present disclosure as defined by the appended claims. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stacked body by sequentially forming a first stack, a recessed target layer, and a second stack on a lower structure, the stacked body comprising a first region and a second region; forming a sacrificial isolation layer in the first region; forming a plurality of vertical openings in the first region; forming a plurality of pad isolation openings in the second region; removing the first stack and the second stack from the first region and the second region through the vertical opening and the pad isolation opening; as well as A preliminary horizontal layer is formed in each of the first region and the second region by recessing the recess target layer of the stacked body.

2. The method according to claim 1, further comprising: After forming the preliminary horizontal layer, forming a horizontal layer in the first region by patterning the preliminary horizontal layer; forming a horizontal conductive line intersecting the horizontal layer of the first region; forming a vertical conductive line, the vertical conductive line being adjacent to the horizontal conductive line and coupled to a first side edge portion of the horizontal layer; cutting a second side edge portion of the horizontal layer; as well as A data storage element is formed adjacent to the horizontal conductive line and coupled to the cut horizontal layer.

3. The method according to claim 2, wherein: The horizontal conductive line includes a pair of horizontal conductive lines vertically facing each other with the horizontal layer interposed therebetween.

4. The method according to claim 2, wherein: The data storage element includes a capacitor.

5. The method according to claim 1, further comprising: After forming the preliminary horizontal layer, forming a contact-level horizontal layer in the second region by patterning the preliminary horizontal layer; forming a first horizontal conductive line and a second horizontal conductive line facing each other vertically, with the contact-level horizontal layer interposed therebetween; forming a contact-level gap between the first horizontal conductive line and the second horizontal conductive line by removing the contact-level horizontal layer; as well as A pad portion is formed to fill the contact level gap.

6. The method according to claim 1, further comprising: After forming the preliminary horizontal layer, forming a horizontal layer in the first region and a contact-level horizontal layer in the second region by patterning the preliminary horizontal layer; forming a first horizontal conductive line and a second horizontal conductive line facing each other vertically with the horizontal layer interposed therebetween, the first horizontal conductive line and the second horizontal conductive line including edge portions extending to overlap the contact-level horizontal layer; forming a contact-level gap between an edge portion of the first horizontal conductive line and an edge portion of the second horizontal conductive line by removing the contact-level horizontal layer; as well as A pad portion is formed to fill the contact level gap.

7. The method according to claim 6, wherein: The edge portions of the first horizontal conductive line and the second horizontal conductive line include a stepped structure.

8. The method according to claim 1, further comprising: After forming the preliminary horizontal layer, forming a first dielectric layer covering each of a top portion and a bottom portion of the preliminary horizontal layer; forming a horizontal layer by patterning the preliminary horizontal layer; cutting two sides of the first dielectric layer to produce a cut first dielectric layer; as well as The cut first dielectric layer is replaced with a horizontal conductive line.

9. The method according to claim 1, wherein: The horizontal layer includes single crystal silicon.

10. The method according to claim 1, wherein: The cross section of the horizontal layer has a cross shape.

11. The method according to claim 1, wherein: Each of the first stack and the second stack is formed by sequentially stacking a first silicon germanium layer, a single crystal silicon layer, and a second silicon germanium layer.

12. The method according to claim 1, wherein: Each of the first stack and the second stack is formed by sequentially stacking a first silicon germanium layer, a first single crystal silicon layer, and a second silicon germanium layer in the order mentioned, and The recessed target layer includes a second single crystal silicon layer, and The second single crystal silicon layer is formed to be thicker than the first single crystal silicon layer.

13. A semiconductor device comprising: Lower structure; vertical stacking, including horizontal conductors stacked vertically from said lower structure; a stepped stack extending horizontally from the vertical stack and including edge portions of the horizontal conductors; Linear pad isolation gaps are formed on two sidewall surfaces of the stepped stack; as well as A hole-shaped pad isolation gap penetrates the stepped stack and extends vertically in the direction of the horizontal conductive line stack.

14. The semiconductor device according to claim 13, wherein: The linear pad isolation gap and the hole-shaped pad isolation gap include a dielectric material.

15. The semiconductor device according to claim 13, wherein: The vertical stack includes: a horizontal layer oriented horizontally in a direction crossing the horizontal conductive line; vertical conductive lines that are commonly coupled to the first side edge portions of the horizontal layers and extend vertically in a direction in which the horizontal conductive lines are stacked; and The data storage elements are respectively coupled to the second side edge portions of the horizontal layers.

16. The semiconductor device according to claim 15, wherein The horizontal layer includes single crystal silicon, polycrystalline silicon, oxide semiconductor material or a combination thereof.

17. The semiconductor device according to claim 15, further comprising: a first contact node located between the horizontal layer and the vertical conductive line; a first doped region coupled to the first contact node and disposed in the first side edge portion of the horizontal layer; a second contact node located between the horizontal layer and the data storage element; a second doped region coupled to the second contact node and disposed in the second side edge portion of the horizontal layer; as well as A channel is disposed in the horizontal layer between the first doping region and the second doping region.

18. The semiconductor device according to claim 13, wherein: Each of the horizontal conductive lines includes a double structure in which an upper horizontal line and a lower horizontal line are vertically arranged.

19. The semiconductor device according to claim 13, wherein: Each of the edge portions of the horizontal conductive lines of the step-like stack includes a double structure, in which the upper and lower horizontal lines are set vertically; as well as A pad portion is disposed between the upper horizontal line and the lower horizontal line.

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