Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. A method for manufacturing a semiconductor device includes: forming a stack including preliminary horizontal layers over a lower structure; forming a sacrificial slit in the stack; forming a pad isolation opening penetrating through the stack between the sacrificial slits; forming a pad-level horizontal layer by recessing the preliminary horizontal layer of the stack through the pad isolation opening; forming a first dielectric layer covering the pad-level horizontal layer; forming a second dielectric layer over the first dielectric layer; forming a slit opening by removing the sacrificial slit; trimming the first dielectric layer through the slit opening so as to produce a trimmed first dielectric layer; trimming a pad-level horizontal layer under the trimmed first dielectric layer; and forming a slit filling the slit opening.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2023 - 0197368, filed on December 29, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure generally relate to a semiconductor device, and more particularly, to a semiconductor device including three - dimensional memory cells and a method of manufacturing the same. Background Art

[0004] Recently, in order to meet the requirements of high capacity and miniaturization of memory devices, a three - dimensional (3D) memory device including a plurality of three - dimensionally stacked memory cells has been proposed. 3D memory devices are generally new and require further improvement. Summary of the Invention

[0005] Embodiments of the present disclosure relate to a 3D semiconductor device (hereinafter simply referred to as a semiconductor device) including highly integrated memory cells and a method of manufacturing the same.

[0006] According to an embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a stack including a preliminary horizontal layer over a lower structure; forming sacrificial slits in the stack; forming pad isolation openings penetrating the stack between the sacrificial slits; forming a pad - level horizontal layer by recessing the preliminary horizontal layer of the stack via the pad isolation openings; forming a first dielectric layer covering the pad - level horizontal layer; forming a second dielectric layer over the first dielectric layer; forming slit openings by removing the sacrificial slits; trimming the first dielectric layer through the slit openings to produce a trimmed first dielectric layer; trimming the pad - level horizontal layer under the trimmed first dielectric layer; and forming slits filling the slit openings.

[0007] According to another embodiment of the present disclosure, a method of manufacturing a semiconductor device includes: forming a stack including a preliminary semiconductor layer over a lower structure; forming sacrificial slits in the stack; forming pad isolation openings penetrating the stack between the sacrificial slits; forming a pad - level semiconductor layer by recessing the preliminary semiconductor layer of the stack via the pad isolation openings; forming a first dielectric layer covering the pad - level semiconductor layer; forming a second dielectric layer over the first dielectric layer; forming a vertical sacrificial structure filling the pad isolation openings; forming slit openings by removing the sacrificial slits; trimming the first dielectric layer through the slit openings to produce a trimmed first dielectric layer; trimming the pad - level semiconductor layer under the trimmed first dielectric layer; forming a slit liner over the slit openings; and forming a slit gap fill layer over the slit liner.

[0008] According to another embodiment of the present disclosure, a semiconductor device includes: a lower structure; a vertical stack including horizontal wires vertically and alternately stacked from the lower structure; a stepped stack horizontally extending from the vertical stack and including edge portions of the horizontal wires; linear pad isolation slits formed on two sidewalls of the stepped stack; hole-shaped pad isolation slits penetrating the stepped stack and vertically extending in a direction of stacking of the horizontal wires; and a plurality of support slits surrounding the hole-shaped pad isolation slits, penetrating the stepped stack, and vertically extending in the direction of stacking of the horizontal wires.

[0009] According to another embodiment of the present disclosure, a semiconductor device includes: a substrate including a connection region and a memory cell region; vertical bit lines extending in a first direction perpendicular to a top surface of the substrate and disposed spaced apart from each other in the memory cell region; horizontal layers stacked spaced apart from each other on the substrate, extending in a second direction intersecting the first direction, and electrically connected to the vertical bit lines; word lines overlapping the horizontal layers and extending in a third direction, and providing a stepped pad region in the connection region; and data storage elements electrically connected to the horizontal layers. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A is a schematic perspective view showing a memory cell according to an embodiment of the present disclosure.

[0011] Figure 1B is Figure 1A a schematic cross-sectional view of the memory cell shown in

[0012] Figure 1C is a plan view showing Figure 1A the switching element shown in

[0013] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present disclosure.

[0014] Figure 2A and Figure 2B is a schematic plan view showing a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 3A is a cross-sectional view taken along line A-A' shown in Figure 2A and Figure 2B shown.

[0016] Figure 3B is a cross-sectional view taken along line B-B' shown in Figure 2A and Figure 2B shown.

[0017] Figure 3C is a cross-sectional view taken along line Figure 2A and Figure 2BA cross-sectional view taken along line B1 - B1' shown.

[0018] Figure 3D is a cross-sectional view taken along Figure 2A and Figure 2B line C - C' shown.

[0019] FIG. 4A to FIG. 26C Shows a method for manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0020] FIG. 27A to FIG. 27F Is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0021] FIG. 28A to FIG. 28C Is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0022] Figure 29 to Figure 31 Is a perspective view showing a memory cell array according to other embodiments of the present disclosure. Detailed description of specific embodiments

[0023] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. However, the embodiments of the present disclosure can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete and will fully convey the scope of the present disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same parts in the multiple drawings and embodiments of the present disclosure.

[0024] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0025] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may be enlarged to clearly show the features of the embodiments. When a first layer is referred to as being "on" a second layer or "on" a substrate, it refers not only to the case where the first layer is directly formed on the second layer or the substrate, but also to the case where a third layer exists between the first layer and the second layer or between the first layer and the substrate.

[0026] The embodiments of the present disclosure described below relate to three-dimensional memory cells (hereinafter also simply referred to as memory cells). By vertically stacking memory cells, the density of the memory cells increases and the parasitic capacitance of the memory cells decreases.

[0027] Figure 1A Is a schematic perspective view showing a memory cell according to an embodiment of the present disclosure. Figure 1B is Figure 1A a schematic cross-sectional view of the memory cell shown, Figure 1C is Figure 1A a plan view of the switching element shown in

[0028] Referring to Figures 1A to 1C , the memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP that are arranged adjacent to each other in the horizontal direction.

[0029] The first wire BL may be linear and may be oriented in a first direction D1. The first direction D1 may be a vertical direction. The first wire BL may be, for example, a bit line. The first wire BL may be referred to as a vertical wire, a vertically oriented bit line, a vertically extending bit line, or a columnar bit line. The first wire BL may include a conductive material. The first wire BL may include, for example, a silicon-based material, a metal-based material, or a combination thereof. The first wire BL may include, for example, polysilicon, metal, metal nitride, metal silicide, or a combination thereof. The first wire BL may include, for example, polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first wire BL may include a stack of titanium nitride and tungsten (TiN / W).

[0030] The switching element TR may be spaced from the wire BL in a second direction D2. In a data write operation and a data read operation performed on the data storage element CAP, the switching element TR may control the supply of voltage (or current) to the data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The second wire DWL may include a horizontal wire. The second wire may be a horizontal word line. The horizontal layer HL may include an active layer. The switching element TR may be, for example, a transistor, and in this case, i.e., when the switching element TR is a transistor, the second wire DWL may be used as a gate electrode. The switching element TR may also be referred to as a cell transistor, an access element, or a selection element. The second wire DWL may be referred to as a horizontal gate electrode or a horizontal word line.

[0031] The horizontal layer HL may extend in a second direction D2 that intersects the first direction D1. The second wire DWL may extend in a third direction D3 that intersects the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction, and the third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3). The horizontal layer HL and the second wire DWL may intersect each other. The horizontal layer HL and the second wire DWL may be perpendicular to each other.

[0032] The horizontal layer HL can be horizontally oriented in a second direction D2 from the first wire BL. Accordingly, a first end of the horizontal layer HL can be in contact with the first wire BL. The second wire DWL can have a dual structure. For example, the second wire DWL can include an upper horizontal line G1 and a lower horizontal line G2 that face each other with the horizontal layer HL therebetween. An interlayer dielectric layer GD can be formed on a top surface and a bottom surface of the horizontal layer HL. The upper horizontal line G1 can be disposed above the horizontal layer HL, and the lower horizontal line G2 can be disposed below the horizontal layer HL. The upper horizontal line G1 and the lower horizontal line G2 can have the same structure. The second wire DWL can include a pair of the upper horizontal line G1 and the lower horizontal line G2. In the second wire DWL, the same driving voltage can be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 can form a pair coupled to a single memory cell MC. According to another embodiment of the present disclosure, different driving voltages can be applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, a horizontal line between the upper horizontal line G1 and the lower horizontal line G2 can be used as a back gate or a shielding gate.

[0033] The horizontal layer HL can include a semiconductor material. For example, the horizontal layer HL can include polysilicon, single-crystalline silicon, germanium, or silicon germanium. According to another embodiment of the present disclosure, the horizontal layer HL can include an oxide semiconductor material. For example, the oxide semiconductor material can include indium gallium zinc oxide (IGZO). According to another embodiment of the present disclosure, the horizontal layer HL can include a conductive metal oxide. According to another embodiment of the present disclosure, the horizontal layer HL can include a two-dimensional material. For example, the two-dimensional material can include MoS2, MoSe2, MoTe2, WS2, WSe2, or WTe2.

[0034] The top surface and the bottom surface of the horizontal layer HL can have flat surfaces. The top surface and the bottom surface of the horizontal layer HL can be parallel to each other in the second direction D2.

[0035] The horizontal layer HL can include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP. When the horizontal layer HL is formed of an oxide semiconductor material, the channel CH can be formed of the oxide semiconductor material, and the first doped region SR and the second doped region DR can be omitted. The horizontal layer HL can also be referred to as an active layer or a thin body layer.

[0036] In each of the upper horizontal line G1 and the lower horizontal line G2, a width in the second direction D2 (e.g., a width of an overlapping portion overlapping with the horizontal layer HL) can be greater than a width of a portion that does not overlap with the horizontal layer HL. Due to this width difference, the second wire DWL can have sidewalls with a notch shape. Return reference Figure 1C, the second conductive wire DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may refer to the portion that overlaps with the channel CH of the horizontal layer HL, and the channel non-overlap portion NOL may refer to the portion that does not overlap with the horizontal layer HL. The channel overlap portion WLP may be cross-shaped or diamond-shaped.

[0037] From a top view perspective, the horizontal layer HL may be cross-shaped or diamond-shaped. According to another embodiment of the present disclosure, the side surface of the horizontal layer HL may be a curved shape or a circular shape.

[0038] The channel CH and the channel overlap portion WLP of the second conductive wire DWL may overlap with each other. The channel CH may be cross-shaped or diamond-shaped. The size of the channel overlap portion WLP of the second conductive wire DWL may be larger than the size of the channel CH. The channel overlap portion WLP of the second conductive wire DWL may completely overlap with the channel CH.

[0039] The first doped region SR and the second doped region DR may be doped with impurities of the same conduction type. The first doped region SR and the second doped region DR may be doped with N-type conductive impurities or P-type conductive impurities. The first doped region SR and the second doped region DR may include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof. The first doped region SR may be coupled to the first conductive wire BL, and the second doped region DR may be coupled to the data storage element CAP. The first doped region SR and the second doped region DR may be referred to as the first source / drain region and the second source / drain region.

[0040] The second conductive wire DWL may include a metal-based material, a semiconductor material, or a combination thereof. The second conductive wire DWL may include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the second conductive wire DWL may include a TiN / W stack in which titanium nitride and tungsten are stacked in sequence. The second conductive wire DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function of about 4.5 eV or less, while the P-type work function material may have a high work function of about 4.5 eV or more. The second conductive wire DWL may include a stack of a low work function material and a high work function material.

[0041] An interlayer dielectric layer GD can be disposed between a horizontal layer HL and a second wire DWL. The interlayer dielectric layer GD can be referred to as a gate dielectric layer. The interlayer dielectric layer GD can be referred to as a side dielectric layer of the horizontal layer. The interlayer dielectric layer GD can include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer GD can include, for example, silicon SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer dielectric layer GD can be formed by thermal oxidation of a semiconductor material.

[0042] A data storage element CAP can include a storage element such as a capacitor. The data storage element CAP can be horizontally disposed from a switching element TR along a second direction D2. The data storage element CAP can include a first electrode SN that extends horizontally from the horizontal layer HL along the second direction D2. The data storage element CAP can further include a second electrode PN above the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE, and the second electrode PN can be horizontally disposed along the second direction D2. The first electrode SN can include an internal space and a plurality of outer surfaces, and the internal space of the first electrode SN can include a plurality of inner surfaces. The outer surfaces of the first electrode SN can include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode SN can vertically extend in a first direction D1, and the horizontal outer surfaces of the first electrode SN can horizontally extend in the second direction D2 or a third direction D3. The internal space of the first electrode SN can be a three-dimensional space. The dielectric layer DE can conformally cover the inner surfaces and the outer surfaces of the first electrode SN. The second electrode PN can be disposed in the internal space of the first electrode SN above the dielectric layer DE. Some of the outer surfaces of the first electrode SN can be electrically connected to a second doped region DR of the horizontal layer HL. The second electrode PN of the data storage element CAP can be coupled to a common plate PL.

[0043] The data storage element CAP can be a three-dimensional structure. The first electrode SN can have a three-dimensional structure. The three-dimensional first electrode SN can have a horizontally three-dimensional structure oriented in the second direction D2. For example, the first electrode SN can have a cylindrical shape including a cylindrical inner surface and a cylindrical outer surface. A portion of the cylindrical outer surface of the first electrode SN oriented in the third direction D3 can be electrically connected to the second doped region DR of the horizontal layer HL via a second contact node SNC. The dielectric layer DE and the second electrode PN can be disposed above the cylindrical inner surface of the first electrode SN. The dielectric layer DE and the second electrode PN can also be disposed above the horizontally oriented outer surfaces of the first electrode SN.

[0044] According to another embodiment of the present disclosure, the first electrode SN may have a cylindrical or columnar shape. The columnar shape refers to a structure in which the first electrode includes a combined (i.e., combined) first part having a cylindrical shape and a second part having a cylindrical shape. Columnar electrodes are known in the art, and therefore, it is not necessary to describe them in more detail.

[0045] The first electrode SN and the second electrode PN may include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, or combinations thereof. The second electrode PN may include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material filling the inside of the first electrode SN, titanium nitride (TiN) may be used as the second electrode PN of the capacitor CAP, and tungsten nitride may be a low-resistance material.

[0046] The dielectric layer DE may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer DE may include, for example, silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (LA2O3), titanium oxide (TiO2), tantalum oxide (TA2O5), niobium oxide (NB2O5), or strontium titanate (SrTiO3). According to another embodiment of the present disclosure, the dielectric layer DE may be formed of a composite layer including two or more layers of the above high-k materials.

[0047] The dielectric layer DE can be formed of a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure including zirconia (ZrO2). The dielectric layer DE can include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack can have a structure in which alumina (Al2O3) is stacked on zirconia (ZrO2). The ZAZ stack can have a structure in which zirconia (ZrO2), alumina (Al2O3), and zirconia (ZrO2) are sequentially stacked. The ZA stack and the ZAZ stack can be referred to as zirconia (ZrO2)-based layers. According to another embodiment of the present disclosure, the dielectric layer DE can be formed of a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure including hafnia (HfO2). The dielectric layer DE can include an HA (HfO2 / Al2O3) stack or an HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack can have a structure in which alumina (Al2O3) is stacked on hafnia (HfO2). The HAH stack can have a structure in which hafnia (HfO2), alumina (Al2O3), and hafnia (HfO2) are sequentially stacked. The HA stack and the HAH stack can be referred to as hafnia (HfO2)-based layers. In the ZA stack, the ZAZ stack, the HA stack, and the HAH stack, alumina (Al2O3) can have a larger bandgap energy than zirconia (ZrO2) and hafnia (HfO2). Alumina (Al2O3) can have a lower dielectric constant than zirconia (ZrO2) and hafnia (HfO2). Accordingly, the dielectric layer DE can include a stack of a high-k material and a high-bandgap material having a larger bandgap energy than the high-k material. The dielectric layer DE can include, for example, silicon dioxide (SiO2) as the high-bandgap material in addition to alumina (Al2O3). Since the dielectric layer DE includes the high-bandgap material, leakage current can be suppressed. The high-bandgap material can be thinner than the high-k material. According to another embodiment of the present disclosure, the dielectric layer DE can include a stacked structure in which the high-k material and the high-bandgap material are alternately stacked. For example, the dielectric layer DE can include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O2 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAA (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack. In the above stacked structures, alumina (Al2O3) can be thinner than zirconia (ZrO2) and hafnia (HfO2).

[0048] According to another embodiment of the present disclosure, the dielectric layer DE can include a high-k material and a high-bandgap material, and can have a laminated structure in which a plurality of high-k materials and a plurality of high-bandgap materials are stacked, or a hybrid structure in which the high-k material and the high-bandgap material are mixed with each other.

[0049] According to another embodiment of the present disclosure, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include hafnium zirconium oxide (HfZrO).

[0050] According to another embodiment of the present disclosure, the dielectric layer DE may include a combination of a high-k material and a ferroelectric material, a combination of a high-k material and an antiferroelectric material, a high-k material, or a combination of a ferroelectric material and an antiferroelectric material.

[0051] According to another embodiment of the present disclosure, the dielectric layer DE may include a perovskite dielectric material. The perovskite dielectric material may include SrTiO3, (Ba, Sr)TiO3, BaTiO3, PbTiO3, PZT, PLZT, or PbTiO3.

[0052] According to another embodiment of the present disclosure, an interface control layer (not shown) may also be formed between the first electrode SN and the dielectric layer DE to improve the leakage current. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0053] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP may include a metal-insulator-metal (MIM) capacitor.

[0054] The data storage element CAP may be replaced with other data storage materials. For example, the data storage material may be a thyristor, a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material. For example, the storage cell MC may include a thyristor, and the first wire BL may be a cathode wire, and the data storage element CAP may be replaced with an anode wire. Thus, the horizontal layer HL may include four semiconductor layers stacked in the second direction D2. The thyristor may include a first diode and a second diode connected in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor may have a high conductance state in which a large amount of current flows therethrough, or a low conductance state in which a small amount of current flows therethrough or no current flows therethrough. The storage cell MC according to this embodiment of the present disclosure may have a '1' state and a '0' state respectively according to the high conductance state and the low conductance state of the thyristor.

[0055] Return reference Figure 1A and Figure 1B, the memory cell MC may further include a first contact node BLC and a second contact node SNC. The first contact node BLC may surround the outer wall of the first wire BL. The first contact node BLC may be electrically connected to the first wire BL and the horizontal layer HL. The second contact node SNC may be disposed between the horizontal layer HL and the first electrode SN. The second contact node SNC may be electrically connected to the horizontal layer HL and the first electrode SN. The first contact node BLC and the second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten, or a combination thereof. According to another embodiment of the present invention, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC.

[0056] Figure 1D is a schematic cross-sectional view showing a memory cell according to another embodiment of the present disclosure. Figure 1D The memory cell MC1 may be similar to Figures 1A to 1C the memory cell MC. Hereinafter, the detailed description of the components that also appear in Figures 1A to 1C will be omitted.

[0057] The memory cell MC1 may include a first wire BL, a switching element TR, and a data storage element CAP. The switching element TR may include a horizontal layer HL, an interlayer dielectric layer GD, and a second wire DWL. The horizontal layer HL may include a first doping region SR, a second doping region DR, and a channel CH. The data storage element CAP may include a first electrode SN, a second electrode PN, and a dielectric layer DE.

[0058] The memory cell MC1 may further include a first contact node BLC between the first wire BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP.

[0059] The second wire DWL may include an upper horizontal line G1 and a lower horizontal line G2. Each of the upper horizontal line G1 and the lower horizontal line G2 may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be horizontally arranged in a second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be in direct contact with each other. The second work function electrode G12 may be arranged adjacent to the first wire BL, and the third work function electrode G13 may be arranged adjacent to the data storage element CAP. The first work function electrode G11 may be disposed between the second work function electrode G12 and the third work function electrode G13. The thickness of the horizontal layer HL may be thinner than that of the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0060] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may be formed of different work function materials. The first work function electrode G11 may have a higher work function than the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include low work function materials. The second work function electrode G12 and the third work function electrode G13 may have a work function lower than the mid-gap work function of silicon. For example, the high work function material may have a work function higher than about 4.5 eV, while the low work function material may have a work function lower than about 4.5 eV. In an embodiment, the first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may include semiconductor materials.

[0061] The second work function electrode G12 and the third work function electrode G13 may include polysilicon doped with an N-type dopant. The first work function electrode G11 may include a metal, a metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0062] According to this embodiment of the present disclosure, each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may be horizontally arranged in the second direction D2 in the order of the second work function electrode G12 - the first work function electrode G11 - the third work function electrode G13. For example, the first work function electrode G11 may include a metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0063] Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may have a PMP (Poly - Si - Metal - Poly - Si, i.e., polysilicon - metal - polysilicon) structure, in which polysilicon, metal, and polysilicon are horizontally arranged in the second direction D2. In the PMP structure, the first work function electrode G11 may be a metal - based material, while the second work function electrode G12 and the third work function electrode G13 may be doped polysilicon doped with an N - type dopant. The N - type dopant may include phosphorus or arsenic.

[0064] The first barrier layer G12L may be disposed between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L may be disposed between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride, or molybdenum nitride. The second barrier layer G13L may cover the top surface, the bottom surface, and the side adjacent to the third work function electrode G13 of the first work function electrode G11.

[0065] The first work function electrode G11 may have a larger volume than the second work function electrode G12 and the third work function electrode G13. Thus, the second wire DWL may have a low resistance. The first work function electrodes G11 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, with the horizontal layer HL therebetween. The second work function electrodes G12 and the third work function electrodes G13 of the upper horizontal line G1 and the lower horizontal line G2 may vertically overlap each other in the first direction D1, with the horizontal layer HL therebetween. The overlapping area between the first work function electrode G11 and the horizontal layer HL may be larger than the overlapping areas between the second work function electrode G12 and the third work function electrodes G13 and the horizontal layer HL. The first work function electrode G11 may extend in the third direction D3, and the second work function electrode G12 and the third work function electrodes G13 may have an independent structure overlapping with the horizontal layer HL. For example, the first work function electrode G11 may include a channel overlapping portion WLP and a channel non - overlapping portion NOL, and the second work function electrode G12 and the third work function electrodes G13 may be part of the channel overlapping portion WLP. The second work function electrode G12 and the third work function electrodes G13 and the first work function electrode G11 may be in direct contact with each other.

[0066] As described above, each of the upper horizontal line G1 and the lower horizontal line G2 may have a triple work function electrode structure including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second wire DWL may include a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13 extending in a third direction D3 intersecting the horizontal layer HL, with the horizontal layer HL interposed therebetween. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0067] As Figure 1C shown, each second wire DWL may include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP may have a cross shape or a diamond shape. The channel overlap portion WLP may completely overlap the channel CH. The second wire DWL extending in the third direction D3 may have a notch-shaped sidewall surface through the channel overlap portion WLP and the channel non-overlap portion NOL. From a top view perspective, the notch-shaped sidewall surface may be provided by a protruding portion formed by the channel overlap portion WLP and a recessed portion formed by the channel non-overlap portion NOL. The channel overlap portion WLP may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, and the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 may vertically overlap the channel CH.

[0068] In the second direction D2, the high work function first work function electrode G11 may be disposed at the center of the second wire DWL, and the low work function second work function electrode G12 and third work function electrode G13 may be disposed at both ends of the second wire DWL, thereby reducing leakage current such as gate-induced drain leakage (GIDL).

[0069] Since the high work function first work function electrode G11 is disposed at the center of the second wire DWL, the threshold voltage of the switching element TR may increase. Since the second work function electrode G12 of the second wire DWL has a low work function, a low electric field may be formed between the first wire BL and the second wire DWL. Since the third work function electrode G13 of the second wire DWL has a low work function, a low electric field may be formed between the data storage element CAP and the second wire DWL.

[0070] As described above, the memory cell MC1 may include a second wire DWL having a triple work function electrode structure. Each of the upper horizontal line G1 and the lower horizontal line G2 of the second wire DWL may include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The first work function electrode G11 may overlap with the channel CH. The second work function electrode G12 may be disposed adjacent to the first wire BL and the first doped region SR. The third work function electrode G13 may be disposed adjacent to the data storage element CAP and the second doped region DR. Due to the low work function of the second work function electrode G12, a low electric field may be formed between the second wire DWL and the first wire BL, thereby reducing the leakage current. Due to the low work function of the third work function electrode G13, a low electric field may be formed between the second wire DWL and the data storage element CAP, thereby reducing the leakage current. Due to the high work function of the first work function electrode G11, the threshold voltage of the switching element TR may be increased. In addition, due to the high work function of the first work function electrode G11, the height of the memory cell MC1 may be reduced, which is advantageous for integration.

[0071] Figure 2A and Figure 2B is a schematic plan view showing a semiconductor device 100 according to an embodiment of the present disclosure. Figure 3A is along Figure 2A and Figure 2B The cross-sectional view taken along the line A-A' shown. Figure 3B is along Figure 2A and Figure 2B The cross-sectional view taken along the line B-B' shown, Figure 3C is along Figure 2A and Figure 2B The cross-sectional view taken along the line B1-B1' shown.

[0072] Figure 3D is along Figure 2A and Figure 2B The cross-sectional view taken along the line C-C' shown. Figure 2A is a plan view at the second wire level, Figure 2B is a plan view at the horizontal layer level. FIG. 3A to FIG. 3D shows a memory cell array MCA1.

[0073] Refer to Figure 2A 、 Figure 2B 、 Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D, the semiconductor device 100 may include a plurality of memory cell arrays MCA1, MCA2, MCA3, and MCA4. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a plurality of memory cells MC. For a detailed description of each memory cell MC, reference may be made to Figures 1A to 1C . Each memory cell MC may include a first wire BL, a switching element TR, and a data storage element CAP.

[0074] The semiconductor device 100 may include a three-dimensional array of memory cells MC. The three-dimensional array of memory cells MC may include a column array of memory cells MC and a row array of memory cells MC. The column array of memory cells MC may include a plurality of memory cells MC stacked along a first direction D1, and the row array of memory cells MC may include a plurality of memory cells MC arranged horizontally along a second direction D2 and a third direction D3. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a column array of memory cells MC.

[0075] The semiconductor device 100 may include a plurality of sub-memory cell arrays. For example, the semiconductor device 100 may include first to fourth sub-memory cell arrays. The first sub-memory cell array may include a row array of memory cells MC arranged adjacent to each other in the second direction D2, and the first sub-memory cell array may have a mirror-type structure in which adjacent memory cells MC share the first wire BL. The second sub-memory cell array may include two memory cells MC arranged adjacent to each other in the second direction D2, and the second sub-memory cell array may have a mirror-type structure in which adjacent memory cells MC share the second electrode PN of the data storage element CAP. In the third sub-memory cell array, the memory cells MC may be vertically stacked in the first direction D1. The fourth sub-memory cell array may include a plurality of memory cells MC arranged horizontally in the third direction D3. By combining the first sub-memory cell array and the second sub-memory cell array, the data storage element CAP, the switching element TR, the first wire BL, and the switching element TR may be alternately arranged in the second direction D2 in the above order.

[0076] An inter-cell dielectric layer IL may be provided between the memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include, for example, silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The inter-cell dielectric layer IL may be referred to as a horizontal inter-cell dielectric layer. A top dielectric layer TIL may be provided above the uppermost inter-cell dielectric layer IL.

[0077] Cell isolation layers ISOA and ISOB may be provided between the memory cells MC arranged adjacent to each other along the third direction D3 (see Figure 2A)。The unit isolation layers ISOA and ISOB can be referred to as vertical inter-unit dielectric layers. The unit isolation layers ISOA and ISOB can include, for example, silicon oxide, silicon carbon oxide (SiCO), silicon nitride, or a combination thereof. The unit isolation layers ISOA and ISOB can include a first unit isolation layer ISOA and a second unit isolation layer ISOB. The first and second unit isolation layers ISOA and ISOB can vertically extend in a first direction D1. The first unit isolation layer ISOA and the second unit isolation layer ISOB can have a columnar structure that vertically extends in the first direction D1. The first unit isolation layer ISOA and the second unit isolation layer ISOB can be alternately arranged in a second direction D2. The first unit isolation layer ISOA can be disposed between data storage elements CAP in a third direction D3. The second unit isolation layer ISOB can be disposed between first wires BL in the third direction D3. A second wire DWL can be disposed between the first unit isolation layer ISOA and the second unit isolation layer ISOB in the second direction D2.

[0078] Memory cell arrays MCA1, MCA2, MCA3, and MCA4 can be disposed on a lower structure LS.

[0079] Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 can include a plurality of second wires DWL vertically stacked in a first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 can include a plurality of horizontal layers HL vertically stacked in a first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 can include a plurality of data storage elements CAP vertically stacked in a first direction D1. Each of the memory cell arrays MCA1, MCA2, MCA3, and MCA4 can include a plurality of first wires BL vertically extending in a first direction D1.

[0080] As Figure 1C shown, each second wire DWL can include a channel overlap portion WLP and a channel non-overlap portion NOL. The channel overlap portion WLP can have a cross shape or a diamond shape. The channel overlap portion WLP can completely overlap with a channel CH. The second wire DWL extending in the third direction D3 can include a plurality of channel overlap portions WLP. Since the channel overlap portions WLP and the channel non-overlap portions NOL are alternately repeated in the third direction D3, the second wire DWL can have a notch-shaped sidewall.

[0081] A plurality of first passivation layers BF1 may be disposed between the lowermost second wire DWL in the second wire DWL and the lower structure LS. A second passivation layer BF2 may be disposed between the first wire BL and the lower structure LS. A third passivation layer BF3 may be disposed between the data storage element CAP and the lower structure LS. The first to third passivation layers BF1, BF2, and BF3 may include a dielectric material. The first to third passivation layers BF1, BF2, and BF3 may include, for example, silicon oxide. The first wire BL, the second wire DWL, and the data storage element CAP may be electrically disconnected from the lower structure LS through the first to third passivation layers BF1, BF2, and BF3. The first to third passivation layers BF1, BF2, and BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. The lowermost inter-level dielectric layer LIL may be disposed between the first passivation layer BF1 and the data storage element CAP.

[0082] The first wire BL may vertically extend along a first direction D1 from an upper portion of the lower structure LS. A horizontal layer HL may extend along a second direction D2 intersecting the first direction D1. The second wire DWL may extend in a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 may be a vertical direction, the second direction D2 may be a first horizontal direction. The third direction D3 may be a second horizontal direction. The horizontal layer HL may extend in the first horizontal direction (i.e., the second direction D2), and the second wire DWL may extend in the second horizontal direction (i.e., the third direction D3).

[0083] Viewed from a top view perspective, the horizontal layer HL may have a cross shape or a rhombus shape. According to another embodiment of the present disclosure, a side surface of the horizontal layer HL may have a curved shape or a circular shape. As Figure 1B shown, the horizontal layer HL may include a channel CH, a first doped region SR between the channel CH and the first wire BL, and a second doped region DR between the channel CH and the data storage element CAP.

[0084] Inter-level dielectric layers GD may be respectively formed on a first surface (or a top surface) and a second surface (or a bottom surface) of the horizontal layer HL.

[0085] Horizontal layer spacers HLS may be formed on sidewalls of the horizontal layer HL. The horizontal layer spacers HLS may include a dielectric material. The horizontal layer spacers HLS may include, for example, silicon oxide. The horizontal layer spacers HLS may directly contact the unit isolation layers ISOA and ISOB. Horizontally adjacent horizontal layers HL disposed in the third direction D3 may be separated from each other by the horizontal layer spacers HLS.

[0086] The first covering layer BC can be disposed between the second wire DWL and the first wire BL. The second covering layer CC can be disposed between the second wire DWL and the first electrode SN of the data storage element. The first covering layer BC can be disposed between the upper horizontal line G1 and the first wire BL. In addition, the first covering layer BC can be disposed between the lower horizontal line G2 and the first wire BL. The second covering layer CC can be disposed between the upper horizontal line G1 and the first electrode SN of the data storage element CAP. In addition, the second covering layer CC can be disposed between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. A memory cell MC can include a pair of first covering layers BC and a pair of second covering layers CC.

[0087] The first covering layer BC and the second covering layer CC can include a dielectric material. The first covering layer BC and the second covering layer CC can include, for example, silicon oxide, silicon nitride, silicon carbon oxide, an air gap, or a combination thereof. The first covering layer BC can include, for example, silicon oxide, while the second covering layer CC can include a stack of silicon oxide and silicon nitride.

[0088] The memory cell MC can further include a first contact node BLC and a second contact node SNC. The first contact node BLC can surround the outer wall of the first wire BL. The second contact node SNC can be disposed between the horizontal layer HL and the first electrode SN. The first contact node BLC can include a metal-based material or a semiconductor material. The second contact node SNC can include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC can include titanium, titanium nitride, tungsten, or a combination thereof. In addition, the first contact node BLC and the second contact node SNC can include doped polysilicon, and the first doping region SR and the second doping region DR can respectively include impurities diffused from the first contact node BLC and the second contact node SNC.

[0089] The horizontal layer HL of the switching element TR horizontally disposed in the third direction D3 can share a second wire DWL. The horizontal layer HL of the switching element TR horizontally disposed in the third direction D3 can be coupled to different first wires BL. The switching elements TR stacked in the first direction D1 can share a first wire BL. The switching elements TR horizontally disposed in the third direction D3 can share the second wire DWL.

[0090] The first unit isolation layer ISOA can be disposed between the first electrodes SN of the data storage element CAP in the third direction D3. The first electrodes SN can be separated from each other by the first unit isolation layer ISOA. The second electrode PN of the data storage element CAP can be coupled to the common plate PL.

[0091] The lower structure LS may include a semiconductor substrate, a metal interconnect structure, a dielectric structure, a conductive structure, a bonding pad structure, another memory, or a peripheral circuit portion.

[0092] For example, the lower structure LS may include a structure in which a peripheral circuit portion, a metal interconnect structure, and a bonding pad structure are stacked in the above order. The memory cell arrays MCA1, MCA2, MCA3, and MCA4 and the peripheral circuit portion of the lower structure LS may be bonded by wafer bonding.

[0093] The peripheral circuit portion of the lower structure LS may be disposed at a level lower than the memory cell arrays MCA1, MCA2, MCA3, and MCA4. This may be referred to as a COP (Cells on Periphery) structure. The peripheral circuit portion may include at least one control circuit for driving the memory cell arrays MCA1, MCA2, MCA3, and MCA4. At least one control circuit of the peripheral circuit portion may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. At least one control circuit of the peripheral circuit portion may include an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit portion may include a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (FinFET), etc.

[0094] For example, the peripheral circuit portion may include a sub-word line driver and a sense amplifier. The first wire BL may be coupled to the sense amplifier, and the second wire DWL may be coupled to the sub-word line driver.

[0095] According to another embodiment of the present disclosure, the peripheral circuit portion may be disposed at a level higher than the memory cell arrays MCA1, MCA2, MCA3, and MCA4. This may be referred to as a POC (Periphery on Cells) structure.

[0096] According to another embodiment of the present disclosure, the memory cell arrays MCA1, MCA2, MCA3, and MCA4 may include a dynamic random access memory (DRAM), an embedded DRAM, a NAND, a ferroelectric RAM (FeRAM), a spin transfer torque RAM (STTRAM), a phase change RAM (PCRAM), or a resistive RAM (ReRAM).

[0097] According to another embodiment of the present disclosure, each memory cell MC may be replaced with Figure 1D the memory cell MC1 shown in

[0098] The semiconductor device 100 may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a memory cell region where memory cells MC are formed, and the second region R2 and the third region R3 may be connection regions. The second region R2 and the third region R3 may be regions where edge portions of a second wire DWL for the memory cells MC are formed. Memory cells MC of memory cell arrays MCA1, MCA2, MCA3, and MCA4 may be disposed in the first region R1. Edge portions of the second wire DWL of the memory cell arrays MCA1 and MCA3 may be disposed in the second region R2. Edge portions of the second wire DWL of the memory cell arrays MCA2 and MCA4 may be disposed in the third region R3. A plurality of third cell isolation layers ISOC may be formed between the first region R1 and the second region R2. A plurality of third cell isolation layers ISOC may be formed between the first region R1 and the third region R3. The third cell isolation layer ISOC may be formed of the same material as that of the first cell isolation layer ISOA and the second cell isolation layer ISOB.

[0099] Edge portions of the second wire DWL may include a stepped structure. Hereinafter, the structure including the edge portions of the second wire DWL may be simply referred to as a "stepped stack WLE". The stepped stack WLE may be disposed in the second region R2 and the third region R3. The stepped stack WLE may also be referred to as a junction stack, a pad stack, or an edge stack.

[0100] A first support slit SL1, a second support slit SL2, a first pad isolation slit WSL1, and a second pad isolation slit WSL2 may be formed in the second region R2 and the third region R3.

[0101] The first support slit SL1 may extend in a third direction D3. A length of the first support slit SL1 in the third direction D3 may be greater than a length of the first support slit SL1 in a second direction D2.

[0102] A length of the first pad isolation slit WSL1 in the third direction D3 may be greater than the length of the first support slit SL1 in the third direction D3. A length of the first pad isolation slit WSL1 in the second direction D2 may be greater than the length of the first support slit SL1 in the second direction D2.

[0103] The second pad isolation slit WSL2 can be disposed between the first pad isolation slits WSL1. The second pad isolation slit WSL2 can be disposed between the first support slit SL1 and the second support slit SL2. The length of the second pad isolation slit WSL2 in the second direction D2 can be greater than the length in the third direction D3. The length of the second pad isolation slit WSL2 in the second direction D2 can be greater than the length of the second support slit SL2 in the second direction D2. The length of the second pad isolation slit WSL2 in the third direction D3 can be greater than the length of the second support slit SL2 in the third direction D3. The second pad isolation slit WSL2 can extend in the second direction D2. The second pad isolation slit WSL2 can include a dielectric material. The first pad isolation slit WSL1 can be referred to as a linear pad isolation slit, and the second pad isolation slit WSL2 can be referred to as a hole-shaped pad isolation slit.

[0104] The second pad isolation slit WSL2, the first support slit SL1, and the second support slit SL2 can penetrate the stepped stack WLE.

[0105] The first pad isolation slit WSL1, the second pad isolation slit WSL2, the first support slit SL1, and the second support slit SL2 can include the same material. For example, the first pad isolation slit WSL1, the second pad isolation slit WSL2, the first support slit SL1, and the second support slit SL2 can include silicon oxide, silicon nitride, silicon oxycarbide, or a combination thereof.

[0106] The second pad isolation slit WSL2 can be surrounded by the first support slit SL1 and the second support slit SL2. The first support slit SL1 and the second support slit SL2 can be referred to as "supports".

[0107] The stepped stack WLE can be supported by the first support slit SL1 and the second support slit SL2. The first support slit SL1 and the second support slit SL2 can be referred to as "support slits". The second pad isolation slit WSL2 can be referred to as a "columnar isolation slit". The second pad isolation slit WSL2 can inhibit the bending of the stepped stack WLE through the first support slit SL1 and the second support slit SL2. Therefore, the second pad isolation slit WSL2 can increase the structural strength of the stepped stack WLE through the first support slit SL1 and the second support slit SL2.

[0108] The first pad isolation slit WSL1 can be disposed between the memory cell arrays MCA1 and MCA3 in the second region R2. The stepped stacks WLE of the memory cell arrays MCA1 and MCA3 can be spaced apart from each other by the first pad isolation slit WSL1. The first pad isolation slit WSL1 can be disposed between the memory cell arrays MCA2 and MCA4 in the third region R3. The stepped stacks WLE of the memory cell arrays MCA2 and MCA4 can be spaced apart from each other by the first pad isolation slit WSL1.

[0109] Return reference FIG. 3A to FIG. 3D , the memory cell array MCA1 can include a vertical stack WLS extending from the first region R1 to the second region R2. A portion of the vertical stack WLS disposed in the second region R2 can be simply referred to as a stepped stack WLE. The other memory cell arrays MCA2, MCA3, and MCA4 can also include a vertical stack WLS and a stepped stack WLE.

[0110] The vertical stack WLS can include a plurality of second conductive wires DWL and an inter-cell dielectric layer IL stacked in a first direction D1. Each second conductive wire DWL of the vertical stack WLS can have a dual structure including an upper horizontal line G1 and a lower horizontal line G2. The vertical stack WLS can further include a horizontal layer HL, an inter-layer dielectric layer GD, and a horizontal layer spacer HLS. The horizontal layer spacer HLS can be horizontally disposed between the horizontal layers HL. The inter-layer dielectric layer GD can be respectively disposed on the top surface and the bottom surface of the horizontal layer HL.

[0111] The stepped stack WLE can include a plurality of second conductive wires DWL and an inter-cell dielectric layer IL stacked in a first direction D1. Each second conductive wire DWL of the stepped stack WLE can have a dual structure including an upper horizontal line G1 and a lower horizontal line G2. The stepped stack WLE can further include a pad portion GP between the upper horizontal line G1 and the lower horizontal line G2. The pad portion GP can electrically connect the upper horizontal line G1 and the lower horizontal line G2 to each other. The upper horizontal line G1 and the lower horizontal line G2 can be electrically connected through the pad portion GP. The upper horizontal line G1, the lower horizontal line G2, and the pad portion GP can include the same material. For example, the upper horizontal line G1, the lower horizontal line G2, and the pad portion GP can include a metal-based material. The stepped stack WLE can include a plurality of steps (or steps), the lengths of which gradually decrease in the stacking direction (i.e., the first direction D1). The length of the pad portion GP can gradually decrease in the stacking direction (i.e., the first direction D1). The horizontal length of the pad portion GP in the third direction D3 can be different for each layer. For example, the horizontal length of the lowermost pad portion GP can be the largest, while the horizontal length of the uppermost pad portion GP can be the smallest.

[0112] The second wire DWL of the stepped stacked WLE can be coupled to the contact plug CT respectively.

[0113] As described above, the memory cell array MCA1 of the semiconductor device 100 may include a vertical stacked WLS, a stepped stacked WLE, and a second pad isolation slit WSL2 on the lower structure LS. The vertical stacked WLS includes second wires DWL vertically and alternately stacked starting from the upper part of the lower structure LS, with a first pad isolation slit WSL1 therebetween. The stepped stacked WLE extends from the second wire DWL. The second pad isolation slit WSL2 extends vertically in the stacking direction of the second wires DWL while penetrating the stepped stacked WLE. In addition, a plurality of first support slits SL1 and second support slits SL2 extend vertically in the stacking direction of the second wires DWL while surrounding the second pad isolation slit WSL2 and penetrating the stepped stacked WLE.

[0114] According to the above embodiments of the present disclosure, the second pad isolation slit WSL2 can prevent bridging between the second wires DWL in the second region R2 through the first support slit SL1 and the second support slit SL2. In addition, when forming the pad portion GP, the second pad isolation slit WSL2, the first support slit SL1, and the second support slit SL2 can be used as a wet barrier, thereby further preventing bridging between the vertically stacked second wires DWL. In particular, when the second pad isolation slit WSL2, the first support slit SL1, and the second support slit SL2 include silicon oxycarbide, they can be used as a wet barrier when forming the pad portion GP, and thus, bridging between the vertically stacked second wires DWL can be further prevented.

[0115] FIG. 4A to FIG. 26C An example of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure is shown.

[0116] Figure 4A It is a plan view of the fourth layer 14 showing a method for forming a stack SB and sacrificial isolation openings 15A, 15B, and 15C. Figure 4B is along Figure 4A the cross-sectional view taken along the line A - A' shown in Figure 4C is along Figure 4A the cross-sectional view taken along the line A1 - A1' shown in

[0117] Refer to FIG. 4A to FIG. 4C, a stack SB can be formed on the lower structure 11. The lower structure 11 can be a material suitable for semiconductor processing, including at least one of a conductive material, a dielectric material, and a semiconductor material. A variety of materials can be formed on the lower structure 11. The lower structure 11 can include a semiconductor substrate. The lower structure 11 can include a silicon-containing material. The lower structure 11 can include silicon, single-crystalline silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single-crystalline silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or multiple layers thereof. The lower structure 11 can further include other semiconductor materials such as germanium. The lower structure 11 can include a III / V semiconductor substrate, for example, a compound semiconductor substrate such as gallium arsenide (GaAs). The lower structure 11 can include, for example, a silicon-on-insulator (SOI) substrate.

[0118] The stack SB can include a plurality of sub-stacks stacked alternately. Each sub-stack can include a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14 stacked in that order. The first layer 12A and the third layer 12B can be formed of the same material and can include silicon germanium or single-crystalline silicon germanium. The second layer 13 and the fourth layer 14 can be formed of the same material and can include single-crystalline silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 can be formed by an epitaxial growth process. The lowermost first layer 12A can be used as a seed layer during the epitaxial growth process. The first layer 12A can be thinner than the second layer 13, and the fourth layer 14 can be thicker than the second layer 13.

[0119] According to this embodiment of the present disclosure, the stack SB can include a plurality of fourth layers 14, a first stack SB1, a second stack SB2, a third stack SB3, and a fourth stack SB4. The stack SB can include the first stack SB1, the fourth layer 14, the second stack SB2, the fourth stack 14, the third stack SB3, the fourth layer 14, and the fourth stack SB4 stacked in that order. The stack SB can further include a fifth stack SB5 disposed on the uppermost layer. Each of the first stack SB1, the second stack SB2, the third stack SB3, and the fourth stack SB4 can include a three-layer stack of the first layer 12A / second layer 13 / third layer 12B. For example, when the first layer 12A and the third layer 12B include silicon germanium layers and the second layer 13 includes a single-crystalline silicon layer, the first stack SB1, the second stack SB2, the third stack SB3, and the fourth stack SB4 can include a stack of first silicon germanium / single-crystalline silicon / second silicon germanium (SiGe / Si / SiGe). The fifth stack SB5 can further include the second layer 13 on top of the three-layer stack of the first layer 12A / second layer 13 / third layer 12B.

[0120] The second layer 13 may include a first single-crystalline silicon layer, and the fourth layer 14 may include a second single-crystalline silicon layer. The second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer. For example, the second single-crystalline silicon layer may be disposed between the first stack SB1 and the second stack SB2. Each of the first stack SB1 to the fourth stack SB4 may include a stack of a first silicon-germanium layer / a first single-crystalline silicon layer / a second silicon-germanium layer, and the second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer.

[0121] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as "sacrificial layers", and the fourth layer 14 may be referred to as a "recess target layer". The stack SB may be referred to as a vertical stack. The stack SB may be formed by alternating a plurality of sacrificial layers and recess target layers. The sacrificial layers may include the first stack SB1 to the fourth stack SB4, and each of the first stack SB1 to the fourth stack SB4 may include a three-layer stack of the first layer 12A / the second layer 13 / the third layer 12B. The recess target layer may include the fourth layer 14. Each sacrificial layer may include a three-layer stack of a first silicon-germanium layer / a first single-crystalline silicon layer / a second silicon-germanium layer, and each recess target layer may include a single layer of the second single-crystalline silicon layer, and the second single-crystalline silicon layer may be thicker than the first single-crystalline silicon layer.

[0122] Referring to FIGS. 2 to Figure 3D , when the memory cells MC are vertically stacked, the first stack SB1, the fourth layer 14, the second stack SB2, the fourth layer 14, the third stack SB3, the fourth layer 14, and the fourth stack SB4 may be alternately stacked several times in the above order.

[0123] The stack SB may include a first region R1, a second region R2, and a third region R3. The first region R1 may be a region where memory cells are to be formed, and the second region R2 and the third region R3 may be regions where pad portions are to be formed. The first region R1 may be disposed between the second region R2 and the third region R3.

[0124] Subsequently, portions of the stack SB can be etched to form a plurality of sacrificial isolation openings 15A, 15B, and 15C. The sacrificial isolation openings 15A and 15B can be initial openings for cell isolation and can include a first sacrificial isolation opening 15A and a second sacrificial isolation opening 15B. The first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B can be formed in the first region R1. When forming the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B, a third sacrificial isolation opening 15C can be formed at a boundary portion between the first region R1 and the second region R2 and at a boundary portion between the first region R1 and the third region R3. The size of the first sacrificial isolation opening 15A can be larger than that of the second sacrificial isolation opening 15B. The third sacrificial isolation opening 15C can be larger than the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B. A portion of the third sacrificial isolation opening 15C can be larger than the second sacrificial isolation opening 15B and smaller than the first sacrificial isolation opening 15A. From a top view perspective, the first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can have a rectangular shape. According to another embodiment of the present disclosure, the first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can have a circular or oval shape.

[0125] According to another embodiment of the present disclosure, the sacrificial isolation openings 15A, 15B, and 15C can be referred to as sacrificial isolation trenches.

[0126] The first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can extend vertically in a first direction D1. In the first region R1, the first sacrificial isolation opening 15A and the second sacrificial isolation opening 15B can be alternately arranged in a second direction D2. A plurality of first sacrificial isolation openings 15A can be arranged in a third direction D3. A plurality of second sacrificial isolation openings 15B can be arranged in a third direction D3. The first sacrificial isolation opening 15A, the second sacrificial isolation opening 15B, and the third sacrificial isolation opening 15C can penetrate the stack SB in the first direction D1.

[0127] After forming the sacrificial isolation openings 15A, 15B, and 15C, portions of the lower structure 11 exposed below the sacrificial isolation openings 15A, 15B, and 15C can be etched. Thus, the bottom surfaces of the sacrificial isolation openings 15A, 15B, and 15C can extend into the lower structure 11. The bottom surfaces of the sacrificial isolation openings 15A, 15B, and 15C can include a U-shaped profile. Due to the sacrificial isolation openings 15A, 15B, and 15C, the fourth layer 14 can have a mesh pattern.

[0128] Figure 5AIt is a plan view of the fourth layer 14 showing a method for forming the sacrificial isolation layers 16A, 16B, and 16C, Figure 5B is a cross-sectional view taken along Figure 5A the line A1 - A1' shown. Figure 5C is a cross-sectional view taken along Figure 5A the line B1 - B1' shown.

[0129] Referring to FIG. 5A to FIG. 5C , the sacrificial isolation layers 16A, 16B, and 16C can be formed to fill the sacrificial isolation openings 15A, 15B, and 15C. The sacrificial isolation layers 16A, 16B, and 16C can include a first sacrificial isolation layer 16A, a second sacrificial isolation layer 16B, and a third sacrificial isolation layer 16C. The first sacrificial isolation layer 16A can fill the first sacrificial isolation opening 15A, the second sacrificial isolation layer 16B can fill the second sacrificial isolation opening 15B. The third sacrificial isolation layer 16C can fill the third sacrificial isolation opening 15C.

[0130] The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include the same material. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can be formed of a dielectric material. For example, the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include silicon oxide, silicon nitride, silicon carbon oxide, silicon carbon nitride, or a combination thereof. Forming the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can include forming a sacrificial isolation material on the stack SB to fill the sacrificial isolation openings 15A, 15B, and 15C, and planarizing the sacrificial isolation material to expose the uppermost layer of the stack SB. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C can have different sizes and different volumes. For example, the size (or volume) of the first sacrificial isolation layer 16A can be larger than that of the second sacrificial isolation layer 16B. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B can have the same length in the third direction D3, and can have different lengths in the second direction D2. The length of the first sacrificial isolation layer 16A in the second direction D2 can be greater than the length of the second sacrificial isolation layer 16B. The size (or volume) of the third sacrificial isolation layer 16C can be larger than that of the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B.

[0131] The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C may vertically extend in a first direction D1. The first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B may be alternately arranged in a second direction D2 in a first region R1. A plurality of first sacrificial isolation layers 16A may be arranged in a third direction D3. A plurality of second sacrificial isolation layers 16B may be arranged in the third direction D3. The first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C may penetrate the stack SB in the first direction D1.

[0132] Each of the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C may include a stack of a sacrificial liner layer and a sacrificial gap filling layer. The sacrificial liner layer and the sacrificial gap filling layer may include, for example, silicon oxide, silicon nitride, silicon oxycarbide, amorphous carbon, or a combination thereof. The sacrificial liner layer may be used as a barrier layer to prevent loss of the sacrificial gap filling layer during a subsequent recess process of the fourth layer 14.

[0133] After forming the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16C, a stepped structure ST may be formed in each of a second region R2 and a third region R3 by etching the stack SB.

[0134] To form Figure 5CThe shown stepped structure ST can form multiple thinning mask layers and can perform multiple thinning etches. The thinning mask layer can include a photoresist pattern, and the thinning etch can be a process of sequentially etching the stack SB starting from the topmost layer. For example, a first etching process including a first thinning mask layer and a first thinning etch, a second etching process including a second thinning mask layer and a second thinning etch, a third etching process including a third thinning mask layer and a third thinning etch, and a fourth etching process including a fourth thinning mask layer and a fourth thinning etch can be sequentially performed. The first etching process can include etching the fifth stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4. In the second etching process, the second thinning mask layer can be formed by thinning the first thinning mask layer, and the second thinning etch can include: etching the fifth stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4; and etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SBS4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3. In the third etching process, the third thinning mask layer can be formed by thinning the second thinning mask layer, and the third thinning etch can include: etching the stack SB5, the fourth layer 14 between the fifth stack SB5 and the fourth stack SB4, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4; etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SB4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3; etching the first layer 12A of the third stack SB3, the fourth layer 14 between the third stack SB3 and the second stack SB2, and the third layer 12B and the second layer 13 of the second stack SB2 to stop at the first layer 12 of the second stack SB2.In the fourth etching process, the fourth thinning mask layer can be formed by thinning the third thinning mask layer, and the third thinning etch can include: etching the fourth layer 14 between the fifth stack SB5 and the fourth stack SBR, and the third layer 12B and the second layer 13 of the fourth stack SB4 to stop at the first layer 12A of the fourth stack SB4; etching the first layer 12A of the fourth stack SB4, the fourth layer 14 between the fourth stack SB4 and the third stack SB3, and the third layer 12B and the second layer 13 of the third stack SB3 to stop at the first layer 12A of the third stack SB3; etching the first layer 12A of the third stack SB3, the fourth layer 14 between the third stack SB3 and the second stack SB2, and the third layer 12B and the second layer 13 of the second stack SB2 to stop at the first layer 12A of the second stack SB2. The thinning process for forming the thinning mask layer can refer to a process of horizontally reducing the width of the thinning mask layer.

[0135] By using the thinning mask layer and the thinning etch as described above, a plurality of steps ST1 to ST4 can be formed in the second region R2 and the third region R3, respectively. The steps ST1 to ST4 may not be formed in the first region. Among the steps ST1 to ST4, the second step ST2 and the third step ST3 may have a four-layer structure of the second layer 13, the third layer 12B, the fourth layer 14, and the first layer 12A stacked in this order. Among the steps ST1 to ST4, the first step ST1 may have a seven-layer structure of the second layer 13, the third layer 12B, the fourth layer 14, the first layer 12A, the second layer 13, the third layer 12B, and the second layer 13 stacked in this order. Among the steps ST1 to ST4, the fourth step ST4 may have a five-layer structure of the first layer 12A, the second layer 13, the third layer 12B, the fourth layer 14, and the first layer 12A stacked in this order.

[0136] After forming the steps ST1 to ST4, an interlayer dielectric layer ILD covering the steps ST1 to ST4 can be formed, as Figure 5C shown. According to another embodiment of the present disclosure, before forming the interlayer dielectric layer ILD, a step passivation layer PSL covering the profile of the steps ST1 to ST4 can be formed. The step passivation layer PSL and the interlayer dielectric layer ILD can include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0137] Fig. 6A is a plan view of the fourth layer 14 showing a method for forming the sacrificial slit openings SLH1' and SLH2', Figure 6B is a cross-sectional view taken along the Fig. 6A line B1 - B1' shown. Figure 6C is a cross-sectional view taken along the Fig. 6A line C - C' shown.

[0138] Reference FIG. 6A to FIG. 6C Multiple sacrificial slit openings SLH1' and SLH2' that penetrate the stack SB of the second region R2 and the third region R3 can be formed. The sacrificial slit openings SLH1' and SLH2' can be formed by etching the stack SB of the second region R2 and the third region R3.

[0139] The sacrificial slit openings SLH1' and SLH2' can include a first sacrificial slit opening SLH1' and a second sacrificial slit opening SLH2'. From a top view perspective, the first sacrificial slit opening SLH1' and the second sacrificial slit opening SLH2' can have a rectangular or linear shape. According to another embodiment of the present invention, the first sacrificial slit opening SLH1' and the second sacrificial slit opening SLH2' can have a circular or elliptical shape (not shown). The first sacrificial slit opening SLH1' can extend in the third direction D3, and the second sacrificial slit opening SLH2' can extend in the second direction D2. The first sacrificial slit opening SLH1' and the second sacrificial slit opening SLH2' can be arranged to be spaced apart from each other. The first sacrificial slit opening SLH1' can simultaneously penetrate adjacent steps. The second sacrificial slit opening SLH2' can vertically penetrate each step.

[0140] Fig. 7A is a plan view of the fourth layer 14 showing a method for forming the sacrificial vertical openings V1' and V2', Figure 7B is along Fig. 7A the cross-sectional view taken along the line A - A' shown in Figure 7C is along Fig. 7A the cross-sectional view taken along the line B1 - B1' shown in Fig.7D is along Fig. 7A the cross-sectional view taken along the line C - C' shown in

[0141] Reference FIG. 7A to FIG. 7D Multiple sacrificial slits SL1' and SL2' can be formed to fill the sacrificial slit openings SLH1' and SLH2' respectively. The sacrificial slits SLH1' and SLH2' can include a dielectric material.

[0142] The sacrificial slits SL1' and SL2' can include a first sacrificial slit SL1' and a second sacrificial slit SL2'. From a top view perspective, the first sacrificial slit SL1' and the second sacrificial slit SL2' can have a rectangular or linear shape. According to another embodiment of the present invention, the first sacrificial slit SL1' and the second sacrificial slit SL2' can have a circular or elliptical shape (not shown). The first sacrificial slit SL1' can extend in the third direction D3, and the second sacrificial slit SL2' can extend in the second direction D2. The first sacrificial slit SL1' and the second sacrificial slit SL2' can be arranged to be spaced apart from each other.

[0143] Reference Figure 7B , a hard mask layer pattern 17 may be formed over the stack SB, the first sacrificial isolation layer 16A, the second sacrificial isolation layer 16B, and the third sacrificial isolation layer 16. The hard mask layer pattern 17 may include silicon nitride. The hard mask layer pattern 17 may be formed by an etching process using a mask layer. The hard mask layer pattern 17 may have a plurality of hole-shaped openings.

[0144] By using the hard mask layer pattern 17 as an etch stop, a portion of the stack SB may be etched in the first region R1. As a result, a plurality of sacrificial vertical openings V1’ and V2’ may be formed in the stack SB. The sacrificial vertical openings V1’ and V2’ may include a first sacrificial vertical opening V1' and a second sacrificial vertical opening V2'. From a top view perspective, the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may be hole-shaped openings. The first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may vertically extend in a first direction D1. The first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may be formed by etching the stack SB between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The first sacrificial vertical opening V1’ may be formed by etching the stack SB between the second sacrificial isolation layers 16B. The second sacrificial vertical opening V2’ may be formed by etching the stack SB between the first sacrificial isolation layers 16A. The first sacrificial vertical opening V1’ may be disposed between the second sacrificial isolation layers 16B along a third direction D3. The second sacrificial vertical opening V2’ may be disposed between the first sacrificial isolation layers 16A along the third direction D3. From a top view perspective, the cross-sections of the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’ may have a rectangular, circular, or elliptical shape.

[0145] Referring to Figure 7C and Fig.7D , when forming the first sacrificial vertical opening V1’ and the second sacrificial vertical opening V2’, a plurality of pad isolation openings V11’ and V12’ penetrating the stack SB in the second region R2 and the third region R3 may be formed simultaneously. The pad isolation openings V11’ and V12’ may include a linear pad isolation opening V11’ and a hole-shaped pad isolation opening V12’. The hole-shaped pad isolation opening V12’ may be disposed between the linear pad isolation openings V11’. The hole-shaped pad isolation opening V12’ may be disposed between the sacrificial slits SL1’ and SL2’. For example, the hole-shaped pad isolation opening V12’ may be disposed between the second sacrificial slits SL2’.

[0146] Fig. 8A is a plan view showing a method for forming the preliminary horizontal layer 14A, Figure 8B is a cross-sectional view taken along the Fig. 8A line A-A’ shown. Figure 8C is along Fig. 8A A cross-sectional view taken along line B1-B1' as shown, and Fig.8D is a cross-sectional view taken along Fig. 8A line C-C' as shown.

[0147] Referring to FIG. 8A to FIG. 8D , a part of the hard mask layer pattern 17 can be trimmed (see reference numeral '17T' in Figure 8B ).

[0148] By using the trimmed hard mask layer pattern 17 as a mask, the first layer 12A and the third layer 12B can be selectively removed from the first region R1, the second region R2, and the third region R3. The first layer 12A and the third layer 12B can be selectively removed from the first region R1 by sacrificing the vertical openings V1' and V2'. The first layer 12A and the third layer 12B can be selectively removed from the second region R2 and the third region R3 through the pad isolation openings V11' and V12'. The first layer 12A and the third layer 12B can be selectively removed based on the difference between the etching selectivity of the second layer 13 and the fourth layer 14 and the etching selectivity of the first layer 12A and the third layer 12B. The first layer 12A and the third layer 12B can be removed by a wet etching process or a dry etching process. For example, when the first layer 12A and the third layer 12B include a silicon-germanium layer and the second layer 13 and the fourth layer 14 include a single-crystalline silicon layer, the silicon-germanium layer can be etched by using an etchant or etching gas that is selective to the single-crystalline silicon layer.

[0149] The second layer 13 and the fourth layer 14 can be recessed, for example, by a wet etching process or a dry etching process. According to this embodiment of the present disclosure, the fourth layer 14 can be partially etched while removing the second layer 13. As a result, the second layer 13 can be removed and the fourth layer 14 can be thinned, as shown by the reference numeral '14A'. The recess process for forming the thin fourth layer 14A, that is, the preliminary horizontal layer 14A, can be referred to as a thinning process or a trimming process of the fourth layer 14. The preliminary horizontal layer 14A can be formed by recessing the top surface, bottom surface, and side surfaces of the fourth layer 14. The preliminary horizontal layer 14A can be referred to as a thin-body active layer. The preliminary horizontal layer 14A can include a single-crystalline silicon layer. The recess process for forming the preliminary horizontal layer 14A can use, for example, HSC1 (Hot SC-1). HSC1 can include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of approximately 1:4:20. The second layer 13 and the fourth layer 14 can be selectively etched by using HSC1.

[0150] The preliminary horizontal layer 14A can be formed by the recess process for the fourth layer 14 as described above, and the horizontal recess 18 can be formed between the preliminary horizontal layers 14. Each of the top surface and the bottom surface of the preliminary horizontal layer 14A can include a flat surface. The preliminary horizontal layer 14A can extend horizontally from the first region R1 to the second region R2 and the third region R3. The preliminary horizontal layer 14A and the horizontal recess 18 can be formed in the first region R1, the second region R2, and the third region R3.

[0151] Viewed from the top view, the preliminary horizontal layer 14A in the first region R1 can have a cross shape. The side surface of the preliminary horizontal layer 14A can have a curved shape or a circular shape. The preliminary horizontal layers 14A in the second region R2 and the third region R3 can have a flat shape.

[0152] After the preliminary horizontal layer 14A is formed, the first sacrificial vertical opening V1’, the second sacrificial vertical opening V2’, and the pad isolation openings V11’ and V12’ can be extended, as indicated by the reference numerals V1, V2, V11, and V12, respectively. The first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can have the same size. The preliminary horizontal layers 14A can be spaced apart from each other in the second direction D2 through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A can have a shape in which a plurality of cross shapes are merged in the third direction D3.

[0153] When the preliminary horizontal layer 14A is formed, the surface of the lower structure 11 can be recessed to a predetermined depth. As a result, the depths of the first sacrificial vertical opening V1, the second sacrificial vertical opening V2, and the pad isolation openings V11 and V12 can be increased.

[0154] The first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can be alternately disposed between the preliminary horizontal layers 14A in the second direction D2. The first sacrificial vertical opening V1 can be disposed between the second sacrificial isolation layers 16B in the third direction D3, and the second sacrificial vertical opening V2 can be disposed between the first sacrificial isolation layers 16A in the third direction D3.

[0155] Through the above-mentioned recess process, a preliminary horizontal layer 14A and a horizontal recess 18 can be formed in the first region R1, the second region R2, and the third region R3. The process can be simplified by simultaneously removing the first layer 12A, the second layer 13, and the third layer 12B from the first region R1, the second region R2, and the third region R3. In addition, residues of the first layer 12A, the second layer 13, and the third layer 12B may not be retained at the boundary portions between the first region R1 and the second region R2 and between the first region R1 and the third region R3. Since the linear pad isolation opening V11 and the via-shaped pad isolation opening V12 are formed, it can be advantageous to simultaneously remove the first layer 12A, the second layer 13, and the third layer 12B from the first region R1, the second region R2, and the third region R3. Through the combination of the linear pad isolation opening V11 and the via-shaped pad isolation opening V12, the first layer 12A, the second layer 13, and the third layer 12B can be easily removed from the second region R2 and the third region R3 without leaving residues.

[0156] Fig.9A is a plan view showing a method for forming a first dielectric layer 19 and a second dielectric layer 20, Fig. 9B is along Fig.9A the sectional view taken along the line A-A' shown. Fig. 9C is along Fig.9A the sectional view taken along the line B1-B1' shown, Fig.9D is along Fig.9A the sectional view taken along the line C-C' shown.

[0157] Referring to 9A to 9D , a first dielectric layer 19 covering the preliminary horizontal layer 14A can be formed. The first dielectric layer 19 may include silicon nitride. The first dielectric layer 19 may completely cover the top surface, bottom surface, and side surfaces of the preliminary horizontal layer 14A.

[0158] When forming the first dielectric layer 19, a dummy dielectric layer 19D can be formed on the surface of the lower structure 11. A part of the first dielectric layer 19 may completely cover the top surface, bottom surface, and side surfaces of the hard mask layer pattern 17.

[0159] Subsequently, a second dielectric layer 20 can be formed on the first dielectric layer 19. The second dielectric layer 20 can be filled between vertically adjacent first dielectric layers 19. The second dielectric layer 20 may include, for example, silicon oxide. A part of the second dielectric layer 20 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The horizontal recess (see the reference numeral '18' shown in Figures 8B to 8D ) may be filled with the first dielectric layer 19 and the second dielectric layer 20.

[0160] The sacrificial pillar 21 may be formed on the second dielectric layer 20 disposed in the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The sacrificial pillar 21 may include amorphous carbon as a sacrificial material. According to another embodiment of the present disclosure, a pillar capping layer may be further formed on the sacrificial pillar 21. The pillar capping layer may include a metal-based material. The pillar capping layer may include titanium nitride. Forming the sacrificial pillar 21 may include depositing the sacrificial material and planarizing the sacrificial material. A planarization process for forming the sacrificial pillar 21 may be performed until the uppermost first dielectric layer 19 is exposed. Subsequently, the uppermost second dielectric layer 20 may also be planarized until the uppermost first dielectric layer 19 is exposed. The sacrificial pillar 21 may not be formed between the vertically stacked first dielectric layers 19.

[0161] The second dielectric layer 20 and the sacrificial pillar 21 may form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2 that fill the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The first sacrificial pillar structure SV1 may fill the first sacrificial vertical opening V1, and the second sacrificial pillar structure SV2 may fill the second sacrificial vertical opening V2. According to another embodiment of the present disclosure, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present disclosure, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. From a top view perspective, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may be hole-shaped sacrificial pillars.

[0162] A portion of the first dielectric layer 19 may be conformally formed on the surfaces of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2, so the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 may also include a portion of the first dielectric layer 19.

[0163] The pad isolation openings V11 and V12 may also be filled with the first dielectric layer 19 and the second dielectric layer 20. The sacrificial pillar 21 may be formed on the second dielectric layer 20 disposed in the pad isolation openings V11 and V12.

[0164] The second dielectric layer 20 and the sacrificial posts 21 can form pad isolation structures SV11 and SV12 that fill the pad isolation openings V11 and V12. The pad isolation structures SV11 and SV12 can include a linear pad isolation structure SV11 and a columnar pad isolation structure SV12. The linear pad isolation structure SV11 can fill the linear pad isolation opening V11, and the columnar pad isolation structure SV12 can fill the via pad isolation opening V12. According to another embodiment of the present disclosure, the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 can include a dielectric material, a carbon-containing material, a metal-based material, or a combination thereof. According to another embodiment of the present disclosure, the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 can include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0165] A portion of the first dielectric layer 19 can be conformally formed on the surfaces of the pad isolation openings V11 and V12, such that the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 can also include a portion of the first dielectric layer 19.

[0166] The first sacrificial post structure SV1 and the second sacrificial post structure SV2 can be formed in the first region R1, and the linear pad isolation structure SV11 and the columnar pad isolation structure SV12 can be formed in the second region R2 and the third region R3.

[0167] The preliminary horizontal layer 14A can be formed between a first sacrificial isolation layer 16A and a second sacrificial isolation layer 16B disposed along the second direction D2, and the first dielectric layer 19 can be formed between the preliminary horizontal layers 14, and the second dielectric layer 20 can be disposed within the first dielectric layer 19. The first dielectric layer 19 can surround the second dielectric layer 20. The first dielectric layer 19 can include a first surrounding portion and a second surrounding portion, wherein the first surrounding portion can surround the preliminary horizontal layer 14A along the A-A' direction, and the second surrounding portion can surround the second dielectric layer 20 between the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B disposed in the second direction D2.

[0168] As described above, when forming the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20, a unit mode structure can be formed in the first region R1. The unit mode structure can include a plurality of unit modes CM. Each unit mode CM can include a plurality of mode layers. The mode layers can refer to the preliminary horizontal layer 14A, the first dielectric layer 19, and the second dielectric layer 20. Each unit mode CM can include an oxide-nitride-silicon-nitride (ONSN) stack. Here, the ONSN stack can refer to a structure in which silicon oxide, first silicon nitride, a single-crystalline silicon layer, and second silicon nitride are sequentially stacked. The silicon oxide can correspond to the second dielectric layer 20, the first silicon nitride and the second silicon nitride can correspond to the first dielectric layer 19, and the single-crystalline silicon layer can correspond to the preliminary horizontal layer 14A. The unit mode structure including a plurality of unit modes CM can be referred to as a vertical stack. From another perspective, the unit mode structure can include an oxide-nitride-silicon-nitride-oxide (ONSNO) stack. Here, the ONSNO stack can refer to a structure in which first silicon oxide, first silicon nitride, a single-crystalline silicon layer, second silicon nitride, and second silicon oxide are sequentially stacked.

[0169] As described above, the sub-stack of the stack body SB can be replaced with unit modes by a series of processes according to FIG. 4A to FIG. 10C The first layer 12A, the second layer 13, and the third layer 12B can be replaced with the first dielectric layer 19 and the second dielectric layer 20. The fourth layer 14 can become the preliminary horizontal layer 14A through a recess process. The first dielectric layer 19 can be referred to as a trimming target layer.

[0170] Fig. 10A and Fig. 10B are plan views showing a method for forming the unit isolation openings 22A and 22B and the horizontal layer 14B, Fig. 10C is a cross-sectional view taken along the line A1 - A1' shown in Fig. 10A and Fig. 10B The horizontal layer 14B is a plan view of the plane, Fig. 10A is a plan view of the plane of the first dielectric layer 19. Fig. 10B

[0171] FIG. 10A to FIG. 10C Refer to FIG. 10A to FIG. 10C, unit isolation openings 22A and 22B can be formed in the first region R1 by removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B. The unit isolation openings 22A and 22B can include a first unit isolation opening 22A and a second unit isolation opening 22B. The first unit isolation opening 22A can be formed by removing the first sacrificial isolation layer 16A. The second unit isolation opening 22B can be formed by removing the second sacrificial isolation layer 16B. When removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be covered by a mask layer (not shown). The side surfaces of the preliminary horizontal layer 14A and the first dielectric layer 19 can be exposed by the first unit isolation opening 22A and the second unit isolation opening 22B in the A1 - A1' direction.

[0172] When removing the first sacrificial isolation layer 16A and the second sacrificial isolation layer 16B, the edge sacrificial isolation layer 16C can be removed. As a result, edge isolation openings 22C can be formed at the boundary portions between the first region R1 and the second region R2 and at the boundary portions between the first region R1 and the third region R3.

[0173] The side surfaces of the preliminary horizontal layer 14A can be trimmed in the second direction D2 and the third direction D3 through the first unit isolation opening 22A and the second unit isolation opening 22B. As a result, a trimmed horizontal layer 14B can be formed. A horizontal layer - level gap 14G can be formed on the side surface of the horizontal layer 14B. The horizontal layer - level gap 14G and the horizontal layer 14B can be disposed between the first dielectric layers 19. The horizontal layer 14B can be referred to as a "trimmed horizontal layer pattern".

[0174] When forming the horizontal layer 14B, the surface of the lower structure 11 (for example, the bottom surfaces of the first unit isolation opening 22A and the second unit isolation opening 22B) can be expanded.

[0175] The horizontal layer 14B can be disposed between the first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 in the second direction D2. From a top - view perspective, the horizontal layer 14B can have a cross - shape. The horizontal layer 14B can have a cross - shape with dimensions smaller than those of the preliminary horizontal layer 14A. The preliminary horizontal layer 14A can have a shape formed by merging multiple cross - shapes, and the horizontal layer 14B can have a shape in which the cross - shapes are separately separated in the third direction D3. The horizontal layer - level gap 14G can be formed between the horizontal layers 14B disposed along the third direction D3. The first sacrificial pillar structure SV1 and the second sacrificial pillar structure SV2 can be disposed between the horizontal layers 14B in the second direction D2.

[0176] The side surfaces of the preliminary horizontal layer 14A can be trimmed in the second direction D2 and the third direction D3 through the edge isolation openings 22C. As a result, a trimmed horizontal layer 14B can be formed in the first region R1, and a pad-level horizontal layer 14R can be formed in the second region R2. The pad-level horizontal layer 14R and the horizontal layer 14B can be spaced apart from each other. The pad-level horizontal layer 14R can be referred to as a pad-level semiconductor layer.

[0177] Fig.11A and Fig. 11B is a plan view showing a method for forming the horizontal layer spacer 23 and the first dielectric layer 19A, Fig. 11C is along Fig.11A and 11B the cross-sectional view taken along the line A1 - A1' shown in. Fig.11D is along Fig.11A the cross-sectional view taken along the line B - B' shown in. Fig.11A is a plan view of the plane of the horizontal layer 14B, Fig. 11B is a plan view of the plane of the first dielectric layer 19A.

[0178] Referring to FIG. 11A to FIG. 11D , the horizontal layer spacer 23 can be formed on the side surfaces of the horizontal layer 14B. Forming the horizontal layer spacer 23 can include forming a spacer material on the side surfaces of the horizontal layer 14B and etching the spacer material. The horizontal layer spacer 23 can include a dielectric material, such as silicon oxide. The horizontal layer spacer 23 can fill the horizontal layer gap 14G and can separate the horizontal layers 14B disposed in the third direction D3 from each other.

[0179] A part of the first dielectric layer 19 can be horizontally trimmed through the first unit isolation opening 22A and the second unit isolation opening 22B. After the trimming process, the first dielectric layer 19 can be retained as indicated by the reference numeral '19A'. Thus, from the perspective of the line A1 - A1', a pair of first dielectric layers 19A can be disposed between the horizontal layers 14B, while the second dielectric layer 20 can be disposed between the pair of first dielectric layers 19A.

[0180] According to FIG. 10A to FIG. 11D , the width of the first dielectric layer 19A in the third direction D3 can be greater than the width of the horizontal layer 14B between the first unit isolation openings 22A and between the second unit isolation openings 22B. In summary, the trimming depth of the first dielectric layer 19 in the third direction D3 can be less than the trimming depth of the preliminary horizontal layer 14A.

[0181] A pair of first dielectric layers 19A can vertically overlap with one horizontal layer 14B. The trimmed first dielectric layer 19A can be referred to as the trimmed first dielectric layer.

[0182] Returning to the reference Fig.11D , the horizontal layer 14B can be disposed in the first region R1, and the pad-level horizontal layer 14R can be disposed in the second region R2 and the third region R3. The pad-level horizontal layers 14R can be vertically stacked in a stepped structure, and the horizontal lengths of the pad-level horizontal layers 14R can be different from each other.

[0183] Fig. 12A and Fig. 12B is a plan view showing a method for forming the cell isolation layers 24A and 24B, Fig. 12C is along Fig. 12A and Fig. 12B the cross-sectional view taken along the line A1 - A1' shown. Fig. 12A is a plan view showing the plane of the horizontal layer 14B for a method of forming the cell isolation layers 24A and 24B. Fig. 12B is a plan view showing the plane of the first dielectric layer 19A for a method of forming the cell isolation layers 24A and 24B.

[0184] Referring to FIG. 12A to FIG. 12C , the cell isolation layers 24A and 24B can be formed to fill the first cell isolation opening 22A and the second cell isolation opening 22B. The cell isolation layers 24A and 24B can include a first cell isolation layer 24A and a second cell isolation layer 24B. The first cell isolation layer 24A and the second cell isolation layer 24B can include the same material. The first cell isolation layer 24A and the second cell isolation layer 24B can be formed of a dielectric material. For example, the first cell isolation layer 24A and the second cell isolation layer 24B can include, for example, silicon oxide, silicon nitride, silicon carbon oxide, silicon carbon nitride, or a combination thereof. From a top view perspective, the outermost material of the first cell isolation layer 24A and the second cell isolation layer 24B can include, for example, silicon oxide.

[0185] Forming the first unit isolation layer 24A and the second unit isolation layer 24B may include forming a unit isolation material filling the unit isolation openings 22A and 22B, and planarizing the unit isolation material and the topmost first dielectric layer 19A to expose the surface of the hard mask layer pattern 17. The first unit isolation layer 24A and the second unit isolation layer 24B may have different sizes or different volumes. The first unit isolation layer 24A and the second unit isolation layer 24B may include a dual structure of silicon oxide and silicon oxycarbide. For example, silicon oxycarbide may be deposited after depositing silicon oxide. According to another embodiment of the present disclosure, the first unit isolation layer 24A and the second unit isolation layer 24B may include an embedded air gap, and an embedded air gap may be provided when depositing silicon oxycarbide. The second sacrificial pillar structure SV2 may be disposed between the first unit isolation layers 24A in the third direction D3, and the first sacrificial pillar structure SV1 may be disposed between the second unit isolation layers 24B in the third direction D3. The first unit isolation layer 24A and the second unit isolation layer 24B may vertically extend in the first direction D1.

[0186] The first unit isolation layer 24A and the second unit isolation layer 24B may correspond to Figure 2A and Figure 2B the unit isolation layers ISOA and ISOB shown in. Each of the first unit isolation layer 24A and the second unit isolation layer 24B may include a stack of a unit isolation liner layer and a unit isolation gap fill layer. The unit isolation liner layer may include, for example, silicon oxide, and the unit isolation gap fill layer may include silicon oxycarbide. According to another embodiment of the present disclosure, the first unit isolation layer 24A and the second unit isolation layer 24B may include an embedded air gap, and an embedded air gap may be provided when forming the unit isolation gap fill layer.

[0187] The first unit isolation layer 24A and the second unit isolation layer 24B and the first dielectric layer 19A may directly contact each other. The horizontal level spacer 23 may be disposed between the horizontal layer 14B and the first unit isolation layer 24A and the second unit isolation layer 24B.

[0188] Fig.13A and Fig. 13B are plan views showing a method for trimming the pad-level horizontal layer 14R in the second region R2 and the third region R3, Fig. 13C and Fig.13D are cross-sectional views taken along lines B1 - B1' and C - C' shown in the figure showing the manufacturing method, Fig.13A and 13B shown. Fig.13A is a plan view of the horizontal layer 14B level, Fig. 13B is a plan view of the first dielectric layer 19A level.

[0189] Referring to FIG. 13A to FIG. 13D, the slit openings SLH1” and SLH2” can be formed by removing the sacrificial slits SL1’ and SL2’ from the second region R2 and the third region R3. A slit opening mask can be used to remove the sacrificial slits SL1’ and SL2’. The slit opening mask can cover the first region R1. The slit openings SLH1” and SLH2” can have the same dimensions as Fig. 6A the slit openings SLH1' and SLH2' shown therein.

[0190] The first dielectric layer 19A and the pad-level horizontal layer 14R can be trimmed (or cut) in the second region R2 and the third region R3 through the slit openings SLH1” and SLH2”. The trimmed pad-level horizontal layer can be retained, as indicated by the reference numeral ‘14R1’ in the drawings.

[0191] Since the first dielectric layer 19A and the pad-level horizontal layer 14R are trimmed in the second region R2 and the third region R3, a step height difference between the first dielectric layer 19A and the pad-level horizontal layer 14R1 can be prevented.

[0192] By trimming the first dielectric layer 19A, the first dielectric layer 19A can be separated from each other in the upper and lower portions of the pad-level horizontal layer 14R1.

[0193] Fig.14A And Fig. 14B is a plan view showing a method for forming the support slits SL1 and SL2 in the second region R2 and the third region R3, Fig. 14C is a cross-sectional view taken along the lines B1 - B1’ and C - C’ shown in Fig.14A and 14B showing the manufacturing method. Fig.14A is a plan view of the level of the horizontal layer 14B, Fig. 14B is a plan view of the level of the first dielectric layer 19A.

[0194] Referring to FIG. 14A to FIG. 14D , the support slits SL1 and SL2 that fill the slit openings SLH1 and SLH2 in the second region R2 and the third region R3 can be formed. The support slits SL1 and SL2 can include a dielectric material. The support slits SL1 and SL2 can be referred to as supports. The support slits SL1 and SL2 can include silicon carbon oxide (SiCO), silicon oxide, spin-on dielectric material (SOD), or a combination thereof. For example, the support slits SL1 and SL2 can include a stack of a slit liner L1 and a slit gap-fill layer L2. The slit liner L1 can include silicon carbon oxide (SiCO), and the slit gap-fill layer L2 can include silicon oxide or spin-on dielectric material (SOD). The support slits SL1 and SL2 can be dielectric slits or dielectric supports.

[0195] Subsequently, a method for forming a memory cell (i.e., a vertical wire, a horizontal layer, a dual horizontal wire, and a data storage element) will be described.

[0196] Fig.15A and 15B is a plan view showing a method for forming a first dielectric layer pattern 19B, FIG. 16A to FIG. 16D is a cross-sectional view taken along line A-A' shown in Fig.15A and Fig. 15B showing the method for forming the first dielectric layer pattern 19B. Fig.15A is a plan view of the plane of the horizontal layer 14B, Fig. 15B is a plan view of the plane of the first dielectric layer pattern 19B.

[0197] First, referring to Fig.16A , the hard mask layer 17 and the uppermost first dielectric layer 19A can be removed to form a hard mask layer-level depression 25.

[0198] Referring to Fig. 16B , a top dielectric layer 26 filling the hard mask layer-level depression 25 can be formed. The top dielectric layer 26 can include silicon oxide.

[0199] Referring to Fig. 16C , an initial vertical opening 27 can be formed by removing the second sacrificial pillar structure SV2.

[0200] Subsequently, the second dielectric layer 20 can be horizontally recessed. As a result, the first dielectric layer 19A and the dummy dielectric layer 19D can be exposed through the initial vertical opening 27.

[0201] Referring to Fig.16D , the first dielectric layer 19A and the dummy dielectric layer 19D can be selectively horizontally recessed. As a result, a first dielectric layer pattern 19B and a dielectric layer-level depression 28 can be formed. A portion of the horizontal layer 14B can be exposed by the dielectric layer-level depression 28.

[0202] The first dielectric layer pattern 19B and the dielectric layer-level depression 28 can be formed in the first region R1. The first dielectric layer 19A can be retained in the second region R2 and the third region R3.

[0203] Fig.17A and Fig. 17B is a plan view showing a method for forming a vertical sacrificial structure 29 and a vertical-level path 30, Fig. 17C is a cross-sectional view taken along line A-A' shown in Fig.17A and Fig. 17B showing the method for forming the vertical sacrificial structure 29 and the vertical-level path 30. Fig.17A is a plan view of the plane of the horizontal layer 14B, Fig. 17B is a plan view of the plane of the first dielectric layer pattern 19B.

[0204] Reference FIG. 17A to FIG. 17C A vertical sacrificial structure 29 can be formed to fill the dielectric layer recess 28 and the initial vertical opening 27. The vertical sacrificial structure 29 can include a sacrificial material. The vertical sacrificial structure 29 can include, for example, silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0205] A vertical-level path 30 can be formed by removing the sacrificial posts 21 of the first sacrificial post structure SV1.

[0206] A lower-level gap 19D' can be formed by removing the dummy dielectric layer 19D below the vertical-level path 30.

[0207] Fig.18A and Fig.18B is a plan view showing a method for forming a horizontal-level recess 33, Fig.18C is a cross-sectional view taken along the line A-A' shown in Fig.18A and Fig.18B FIG. Fig.18D is a cross-sectional view taken along the line B1-B1' shown in Fig.18A FIG., Fig.18E is a cross-sectional view taken along the line C-C' shown in Fig.18A and Fig.18B FIG. Fig.18A is a plan view of the plane of the horizontal layer 14B, Fig.18B is a plan view of the plane of the horizontal-level recess 33.

[0208] Referring to 18A to 18E FIG., a first hole-shaped vertical opening 32 can be formed in the first region R1 by cutting the second dielectric layer 20 via the vertical-level path 30. When forming the first hole-shaped vertical opening 32, isolation trenches SVH11 and SVH12 can be formed in the second region R2 and the third region R3.

[0209] A first passivation layer BF1 can be formed to fill the lower-level gap 19D'. The first passivation layer BF1 can include, for example, silicon oxide. Forming the first passivation layer BF1 can include depositing silicon oxide to fill the lower-level gap 19D' and etching the silicon oxide.

[0210] A second passivation layer BF2 can be formed in the lower region of the first hole-shaped vertical opening 32. For example, the surface of the lower structure 11 can be oxidized to form the second passivation layer BF2.

[0211] To form a horizontal-level recess 33 in the first region R1, the first dielectric layer pattern 19B can be removed through the first hole-shaped vertical opening 32. A portion of the horizontal layer 14B can be exposed through the horizontal-level recess 33. The horizontal-level recess 33 can be provided between the second dielectric layer 20 and the horizontal layer 14B. Two horizontal-level recesses 33 can face each other with a horizontal layer 14B therebetween.

[0212] To form the pad-level recesses 33P in the second region R2 and the third region R3, the first dielectric layer pattern 19B can be removed through the isolation trenches SVH11 and SVH12. The pad-level recesses 33P can expose the top surface and the bottom surface of the pad-level horizontal layer 14R1. The pad-level recesses 33P can be disposed between the second dielectric layer 20 and the pad-level horizontal layer 14R1. Two pad-level recesses 33P can face each other with a pad-level horizontal layer 14R1 therebetween.

[0213] Fig.19A is a plan view showing a method for forming the horizontal wire 35, Fig.19B is along Fig.19A the cross-sectional view taken along the line A-A’ shown. Fig.19C is along Fig.19A the cross-sectional view taken along the line B1-B1’ shown. Fig.19D is along Fig.19A the cross-sectional view taken along the line C-C’ shown. Fig.19E is along Fig.19A the cross-sectional view taken along the line B-B’ shown.

[0214] Referring to FIG. 19A to FIG. 19E , an interlayer dielectric layer 34 can be formed over the exposed portion of the horizontal layer 14B. The interlayer dielectric layer 34 can be referred to as a gate dielectric layer. The interlayer dielectric layer 34 can correspond to the interlayer dielectric layer GD as shown in Figures 1A to 3B .

[0215] The interlayer dielectric layer 34 can be formed by oxidizing the surface of the horizontal layer 14B. According to another embodiment of the present disclosure, the interlayer dielectric layer 34 can be formed by a deposition process of silicon oxide. The interlayer dielectric layer 34 can include, for example, silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, antiferroelectric material, or a combination thereof. The interlayer dielectric layer 34 can include, for example, silicon SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0216] The horizontal wire 35 filling the horizontal-level recess 33 can be formed over the interlayer dielectric layer 34. Forming the horizontal wire 35 can include depositing a conductive material filling the horizontal-level recess 33 over the interlayer dielectric layer 34 and etching back the conductive material. The horizontal wire 35 can include a pair of a first horizontal wire 35A and a second horizontal wire 35B that face each other with the horizontal layer 14B therebetween. The first horizontal wire 35A and the second horizontal wire 35B can include a metal-based material, a semiconductor material, or a combination thereof. The first horizontal wire 35A and the second horizontal wire 35B can include titanium nitride, tungsten, polysilicon, or a combination thereof. For example, the first horizontal wire 35A and the second horizontal wire 35B can include a TiN / W stack in which titanium nitride and tungsten are stacked in sequence. The first horizontal wire 35A and the second horizontal wire 35B can include an N-type work function material or a P-type work function material. The N-type work function material can have a low work function of about 4.5 eV or less, while the P-type work function material can have a high work function of about 4.5 eV or more.

[0217] The horizontal wire 35 can correspond to the second wire DWL as Figures 1A to 1D shown, and the first horizontal wire 35A and the second horizontal wire 35B can correspond to the upper horizontal line G1 and the lower horizontal line G2. Referring to Figures 1A to 1D , each of the first horizontal wire 35A and the second horizontal wire 35B can have a cross shape and can include a channel overlap portion WLP and a channel non-overlap portion NOL.

[0218] The horizontal wire 35 can be formed in the first region R1 and can extend to be disposed in the second region R2 and the third region R3. The horizontal wire 35 can be formed in the horizontal-level recess 33 in the first region R1 and in the pad-level recess 33P formed in the second region R2 and the third region R3. The interlayer dielectric layer 34 can also be formed in the first region R1, the second region R2, and the third region R3, respectively.

[0219] Fig. 20A and Fig. 20B are plan views showing a method for forming the vertical wire 39, Fig. 20C is a cross-sectional view taken along the line Fig. 20A and 20B shown by the line A-A'.

[0220] Referring to FIG. 20A to FIG. 20C , a first covering layer 36 can be formed on the first side of the horizontal wire 35. The first covering layer 36 can include, for example, silicon oxide, silicon nitride, silicon carbon oxide, an embedded air gap, or a combination thereof. The first covering layer 36 can be formed by depositing a covering material and performing an etching-back process. When forming the first covering layer 36 or after forming the first covering layer 36, a part of the interlayer dielectric layer 34 can be removed to expose the first edge portions of each horizontal layer 14B.

[0221] A vertical wire 39 can be formed that is coupled to the first edge portion of each horizontal layer 14B. The vertical wire 39 can fill the first hole-shaped vertical opening 32. The vertical wires 39 can be commonly coupled to the horizontal layers 14B arranged along the first direction D1. The vertical wire 39 can include titanium nitride, tungsten, or a combination thereof. The vertical wire 39 can be referred to as a bit line or a vertical bit line.

[0222] Before forming the vertical wire 39, a first doped region 37 and a first contact node 38 can be formed. The first doped region 37 can be formed in the first edge portion of the horizontal layer 14B. Forming the first doped region 37 can include: depositing polysilicon doped with an N-type impurity; performing a heat treatment; and removing the doped polysilicon. The first doped region 37 can include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, the first doped region 37 can be formed by a doping process of doping impurities.

[0223] The first contact node 38 can include doped polysilicon. The first doped region 37 can include impurities diffused from the first contact node 38. A metal silicide layer can also be formed between the vertical wire 39 and the first contact node 38.

[0224] The vertical wire 39 can correspond to the first wire BL as Figures 1A to 3C shown.

[0225] Fig.21A is a plan view showing a method for forming a pad-level gap GP’, Fig. 21B is a cross-sectional view taken along the line B-B’ as Fig.21A shown. Fig. 21C is a cross-sectional view taken along the line B1-B1’ as Fig.21A shown, Fig.21D is a cross-sectional view taken along the line C-C’ as Fig.21A shown.

[0226] Referring to FIG. 21A to FIG. 21D , the horizontal layer pattern 14B and the horizontal wire 35 can be formed in the first region R1, and the pad-level horizontal layer 14R1 and the horizontal wire 35 can be formed in the second region R2 and the third region R3. The first horizontal wire 35A and the second horizontal wire 35B of the horizontal wire 35 can face each other perpendicularly, with the horizontal layer pattern 14B therebetween, and can include edge portions that extend to overlap with the pad-level horizontal layer 14R1.

[0227] The edge portions of the horizontal wire 35 can be disposed in the second region R2 and the third region R3.

[0228] The edge portions of the horizontal wire 35 can be formed as a stepped structure, as Figure 5C shown.

[0229] All pad-level horizontal layers 14R1 can be removed from the second region R2 and the third region R3. As a result, a pad-level gap GP' can be formed between the horizontal wires 35. The pad-level gap GP' can be provided in a stepped structure. Since the slit liner L1 supporting the slits SL1 and SL2 contains silicon carbon oxide (SiCO), it can be used as a wet barrier when forming the pad-level gap GP'.

[0230] Fig.22A is a plan view showing a method for forming a pad portion GP, Fig. 22B is a sectional view taken along Fig.22A the line B-B' shown.

[0231] Referring to FIG. 22A to FIG. 22B , a pad portion GP can be formed to fill the pad-level gap GP'. The pad portion GP can couple the first horizontal wire G1 and the second horizontal wire G2 to each other. The pad portion GP, the first horizontal wire G1, and the second horizontal wire G2 can include the same material.

[0232] The above process of forming the pad portion GP can be performed after forming the vertical wire 39. For example, after forming the vertical wire 39 in the first region R1, the second region R2 and the third region R3 can be exposed and the first region R1 can be masked in sequence, the pad-level horizontal layer 14R1 can be removed from the second region R2 and the third region R3, and the pad portion GP can be formed.

[0233] Since the slit liner L1 supporting the slits SL1 and SL2 contains silicon carbon oxide (SiCO), bridging between the vertically stacked horizontal wires 35 can be prevented when forming the pad portion GP.

[0234] Fig.23A is a plan view showing a method for forming a storage opening 41, Fig. 23B is a sectional view taken along Fig.23A the line A-A' shown.

[0235] Referring to Fig.23A and Fig. 23B , a part of the vertical sacrificial structure 29 can be removed to form a second hole-shaped vertical opening 40. The first side (i.e., the second edge portion) of the horizontal layer 14B can be exposed through the second hole-shaped vertical opening 40. After forming the second hole-shaped vertical opening 40, a part of the vertical sacrificial structure 29 can be removed to form the lowermost dielectric layer 29L on one side of the first passivation layer BF1.

[0236] A third passivation layer BF3 can be formed on the surface of the lower structure 11. The third passivation layer BF3 can include, for example, silicon oxide.

[0237] The second edge portion of the horizontal layer 14B may be horizontally recessed in the second direction D2. Thus, the horizontal layer is retained as indicated by the reference numeral "HL".

[0238] After forming the horizontal layer HL, the vertical sacrificial structure 29 may be selectively recessed to form a second capping layer 29C. The second capping layer 29C may include, for example, silicon oxide, silicon nitride, or a combination thereof.

[0239] After forming the second capping layer 29C, a storage opening 41 that horizontally extends from the second hole-shaped vertical opening 40 may be formed. The storage opening 41 may be referred to as a capacitor opening.

[0240] The horizontal layer HL may include a first edge and a second edge. The first edge may refer to the portion coupled to the first contact node 38 and the vertical wire 39, and the second edge may refer to the portion exposed by the storage opening 41.

[0241] The storage opening 41 may be disposed between the second dielectric layers 20. The second capping layer 29C may be disposed on the upper and lower portions of the horizontal layer HL, respectively.

[0242] As described above, forming the horizontal layer HL and the storage opening 41 may include forming the second hole-shaped vertical opening 40, recessing the horizontal layer 14B, and forming the second capping layer 29C.

[0243] Fig.24A is a plan view showing a method for forming a second contact node 42, Fig. 24B is a cross-sectional view taken along the line A-A' shown in Fig.24A As shown.

[0244] Referring to Fig.24A and Fig. 24B , second doped regions 43 may be formed in the second edge of the horizontal layer HL, respectively. Forming the second doped regions 43 may include depositing polysilicon doped with an N-type impurity, performing a heat treatment, and removing the doped polysilicon. The second doped regions 43 may include impurities diffused from the doped polysilicon. According to another embodiment of the present disclosure, the doped polysilicon may be retained after performing the heat treatment.

[0245] The second contact node 42 may be formed on the second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doped regions 43 may include impurities diffused from the second contact node 42.

[0246] Each horizontal layer HL may include a first doped region 37, a second doped region 43, and a channel 44 that are horizontally arranged in the second direction D2. The channel 44 may be defined between the first doped region 37 and the second doped region 43. The channel 44 may vertically overlap with the horizontal wire 35. As Figures 1A to 1DAs shown, the horizontal layer HL may have a cross shape, and the channel 44 may also have a cross shape.

[0247] Fig.25A is a plan view showing a method for forming the first electrode 45, Fig.25B is along Fig.25A the cross-sectional view taken along the line A-A' shown.

[0248] Referring to Figure 25A and Figure 25B , the first electrode 45 of the data storage element may be formed over the second contact node 42. The first electrode 45 may have a horizontally oriented cylindrical shape. The first electrode 45 may be disposed in the storage openings 41 respectively. The first electrodes 45 disposed adjacent to each other in the second direction D2 may be spaced apart from each other through the second hole-shaped vertical opening 40. The first electrodes 45 disposed adjacent to each other in the third direction D3 may be spaced apart from each other through the second cell isolation layer 24A.

[0249] Figure 26A is a plan view showing a method for forming the dielectric layer 47 and the second electrode 48, Figure 26B and Figure 26C is along Figure 26A the cross-sectional view taken along the A-A' line shown.

[0250] Referring to Figure 26A and Figure 26B , the second dielectric layer 20 may be horizontally recessed (see reference numeral '46'). As a result, the outer wall of the first electrode 45 may be exposed. The recessed second dielectric layer 20 may correspond to the inter-cell dielectric layer IL as shown in Figure 3B .

[0251] Referring to Figure 26A and 26C , the dielectric layer 47 and the second electrode 48 may be sequentially formed over the first electrode 45. The first electrode 45, the dielectric layer 47, and the second electrode 48 may be the data storage element CAP.

[0252] Each first electrode 45 may include an internal space and a plurality of outer surfaces, and the internal space of the first electrode 45 may include a plurality of inner surfaces. The outer surfaces of the first electrode 45 may include vertical outer surfaces and a plurality of horizontal outer surfaces. The vertical outer surfaces of the first electrode 45 may vertically extend in the first direction D1, and the horizontal outer surfaces of the first electrode 45 may horizontally extend in the second direction D2 or the third direction D3. The internal space of the first electrode 45 may be a three-dimensional space. The dielectric layer 47 may conformally cover the inner surfaces and the outer surfaces of the first electrode 45. The second electrode 48 may be disposed in the internal space of the first electrode 45 over the dielectric layer 47. Some of the outer surfaces of the first electrode 45 may be electrically connected to the second doped region 43 of the horizontal layer HL.

[0253] The first electrode 45 may have a cylindrical shape. The cylindrical shape of the first electrode 45 may include a cylindrical inner surface and a cylindrical outer surface. Some of the cylindrical outer surfaces of the first electrode 45 may be electrically connected to the second doped region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 may be disposed on the cylindrical inner surface of the first electrode 45. The second electrode 48 may vertically extend in the first direction D1.

[0254] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode 45 and the second electrode 48 may include titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), a titanium nitride / tungsten (TiN / W) stack, a tungsten nitride / tungsten (WN / W) stack, or a combination thereof. The second electrode 48 may include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap-filling material that fills the internal space of the first electrode 45, and titanium nitride (TiN) may be used as the second electrode 48 of the data storage element CAP, and tungsten nitride may be a low-resistance material.

[0255] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a storage layer. The dielectric layer 47 may include, for example, silicon oxide, silicon nitride, a high-k material, a ferroelectric material, an antiferroelectric material, or a combination thereof. The dielectric layer 47 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanate (SrTiO3). The dielectric layer 47 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, an HA (HfO2 / Al2O3) stack, an HAH (HfO2 / Al2O3 / HfO2) stack, an HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or an HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0256] According to another embodiment of the present disclosure, an interface control layer for reducing leakage current may also be formed between the first electrode 45 and the dielectric layer 47. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 48 and the dielectric layer 47.

[0257] Figures 27A to 27F is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0258] A preliminary horizontal layer 14A may be formed by performing a series of processes as Figures 4A to 8D shown.

[0259] Subsequently, referring to Figure 27A , an interlayer dielectric layer 34' that completely covers the preliminary horizontal layer 14A may be formed.

[0260] Subsequently, conductive layers 35' surrounding the preliminary horizontal layer 14A may be formed on the interlayer dielectric layer 34'. When forming the conductive layers 35', dummy conductive layers 35D may be formed on the surface of the lower structure 11.

[0261] A second dielectric layer 20 may be formed on the conductive layers 35'. Sacrificial pillars 21 may be formed on the second dielectric layer 20. The second dielectric layer 20 and the sacrificial pillars 21 may form a first sacrificial pillar structure SV1 and a second sacrificial pillar structure SV2.

[0262] Referring to Figure 27B , in order to form a first hole-shaped vertical opening 32, the sacrificial pillars 21 of the first sacrificial pillar structure SV1 may be removed. Subsequently, the second dielectric layer 20 may be cut (see reference numeral 31).

[0263] After partially removing the dummy conductive layer 35D', a first buffer layer BF1 may be formed. The first buffer layer BF1 may include, for example, silicon oxide. The surface of the lower structure 11 may be oxidized to form a second buffer layer BF2.

[0264] Referring to Figure 27C , a first recess process may be performed on the conductive layers 35'.

[0265] Referring to Figure 27D , a first contact node 38 and a vertical wire 39 may be formed to fill the first hole-shaped vertical opening 32. Before forming the first contact node 38, a first capping layer 36 may be formed. After forming the first capping layer 36, a first doped region 37 may be formed.

[0266] Referring to Figure 27E, to form the second hole-shaped vertical opening 40, a part of each second sacrificial pillar structure SV2 can be removed.

[0267] Subsequently, a second recess process can be performed on the conductive layer 35'.

[0268] As a result, a dual-level wire 35 of the first horizontal wire 35A and the second horizontal wire 35B can be formed. The first edge portion of the horizontal wire 35 can be defined by the first recess process (see Figure 27C ), and the second edge portion E2 of the horizontal wire 35 can be defined by the second recess process (see Figure 27E ).

[0269] Referring to Figure 27F , a second cover layer 29C can be formed. The second cover layer 29C can be disposed between the second dielectric layers 20. The second cover layer 29C can be disposed on the second side surfaces of the first horizontal wire 35A and the second horizontal wire 35B.

[0270] The horizontal layer pattern 14B can be horizontally recessed. As a result, a horizontal layer HL can be formed. The storage opening 41 can be formed by forming the second cover layer 29C and the horizontal layer HL. The storage opening 41 can expose the end portion of the second side of the horizontal layer HL. The storage opening 41 can be disposed between the second dielectric layers 20.

[0271] Subsequently, referring to Figures 24A to 26B , a data storage element CAP including a second doped region 43, a second contact node 42, a first electrode 45, a dielectric layer 47, and a second electrode 48 can be formed.

[0272] Figures 28A to 28C is a cross-sectional view showing a method for manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0273] Referring to Figure 28A , a stack SB10 can be formed on the lower structure 11. The stack SB10 can include an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, the alternating stack can include a plurality of silicon-germanium layers 12 and a plurality of single-crystalline silicon layers 14' alternately stacked by an epitaxial growth process. The silicon-germanium layer 12 can be a sacrificial layer, and the single-crystalline silicon layer 14' can be a recess target layer. The silicon-germanium layer 12 can correspond to Figure 4B the first layer 12A or the third layer 12B of Figure 4B , and the single-crystalline silicon layer 14' can correspond to Figure 4B the fourth layer 14 of

[0274] Subsequently, Figures 4A to 5CA series of processes shown in. For example, sacrificial isolation openings 15A and 15B and sacrificial isolation layers 16A and 16B can be formed in the stack SB10. The sacrificial isolation layers 16A and 16B can include a barrier layer L1, a sacrificial liner layer L2, a sacrificial gap-fill layer L3, and a sacrificial capping layer L4.

[0275] Subsequently, referring to Figure 28B , a hard mask layer pattern 17 can be formed over the stack SB10.

[0276] Subsequently, the stack SB can be etched by using the hard mask layer pattern 17 as an etch stop. As a result, a plurality of first sacrificial vertical openings V1' and second sacrificial vertical openings V2' can be formed in the stack SB10.

[0277] Referring to Figure 28C , a preliminary horizontal layer 14A' and a horizontal recess 18 can be formed. The preliminary horizontal layer 14A' and the horizontal recess 18 can be formed by a process of recessing the silicon-germanium layer 12 and the single-crystalline silicon layer 14' as shown in Figure 28B . After the silicon-germanium layer 12 is removed, a process of recessing the single-crystalline silicon layer 14' can be performed. The preliminary horizontal layer 14A' can correspond to the preliminary horizontal layer 14A shown in Figure 7B .

[0278] The silicon-germanium layer 12 can be recessed by a wet etching process or a dry etching process. The silicon-germanium layer 12 can be etched by using an etchant or an etch gas that is selective with respect to the single-crystalline silicon layer 14'.

[0279] The recessing process of the single-crystalline silicon layer 14' for forming the preliminary horizontal layer 14A' can use, for example, HSC1 (Hot SC-1). HSC1 can include a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) mixed in a ratio of approximately 1:4:20. The single-crystalline silicon layer 14' can be selectively etched by using HSC1.

[0280] After the preliminary horizontal layer 14A' is formed, the first and second sacrificial vertical openings can be extended as indicated by the reference numerals 'V1' and 'V2'. The preliminary horizontal layer 14A' can be arranged to be spaced apart from each other in the second direction D2 through the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2. The preliminary horizontal layer 14A' can have a shape in which a plurality of cross shapes are merged in the third direction D3. When the preliminary horizontal layer 14A' is formed, the surface of the lower structure 11 can be recessed to a predetermined depth (see the reference numeral '11A'). As a result, the depths of the first sacrificial vertical opening V1 and the second sacrificial vertical opening V2 can be increased.

[0281] Subsequently, a series of processes shown in Figures 8A to 25B can be performed.

[0282] Figures 29 to 31 is a perspective view showing a memory cell array according to other embodiments of the present disclosure. The memory cell arrays MCA100, MCA200, and MCA300 may be similar to the Figure 3A memory cell array MCA. Hereinafter, for a detailed description of the constituent elements that also appear in Figure 3A the Figures 29 to 31 above embodiments of the present disclosure may be referred to.

[0283] Referring to Figure 29 , the memory cell array MCA100 may include a plurality of memory cells MC10.

[0284] The memory cell array MCA100 may include a three-dimensional array of memory cells MC10. The three-dimensional array of memory cells MC10 may include a column array of memory cells MC10 and a row array of memory cells MC10. The column array of memory cells MC10 may include a plurality of memory cells MC10 stacked in a first direction D1, and the row array of memory cells MC10 may include a plurality of memory cells MC10 horizontally arranged in a second direction D2 and a third direction D3.

[0285] Each memory cell MC10 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, the above embodiments of the present disclosure may be referred to.

[0286] The switching element TR may include a horizontal layer HL and a second wire DWL. The horizontal layer HL may extend in a second direction D2. The second wire DWL may extend in a third direction D3.

[0287] The second wire DWL may have a dual structure. For example, the second wire DWL may include an upper horizontal line G1 and a lower horizontal line G1 facing each other, with the horizontal layer HL therebetween. As Figure 3B shown, an interlayer dielectric layer GD may be formed on the top surface and the bottom surface of the horizontal layer HL.

[0288] Each of the upper horizontal line G1 and the lower horizontal line G2 may include a pair of flat sidewall surfaces FS extending in a third direction D3. The flat sidewall surfaces FS may refer to vertical sidewall surfaces. The flat sidewall surfaces FS may have a linear shape extending in a third direction D3.

[0289] Referring to Figure 30 , the memory cell array MCA200 may include a plurality of memory cells MC20.

[0290] The memory cell array MCA200 may include a three-dimensional array of memory cells MC20. The three-dimensional array of memory cells MC20 may include a column array of memory cells MC20 and a row array of memory cells MC20. The column array of memory cells MC20 may include a plurality of memory cells MC20 stacked in a first direction D1, and the row array of memory cells MC20 may include a plurality of memory cells MC20 horizontally arranged in a second direction D2 and a third direction D3.

[0291] Each memory cell MC20 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0292] The switching element TR may include a horizontal layer HL and a second wire SWL. The horizontal layer HL may extend in a second direction D2. The second wire SWL may extend in a third direction D3.

[0293] The second wire SWL may have a single structure. For example, the second wire SWL may be disposed above the horizontal layer HL. As Figure 3B shown, an interlayer dielectric layer GD may be formed between the top surface of the horizontal layer HL and the second wire SWL. According to another embodiment of the present disclosure, the second wire SWL may be disposed below the horizontal layer HL.

[0294] The second wire SWL may include a pair of flat sidewall surfaces FS extending in a third direction D3. The flat sidewall FS may refer to a vertical sidewall.

[0295] According to another embodiment of the present disclosure, the second wire SWL may include a channel overlap portion WLP and a channel non-overlap portion NOL, as Figure 1C shown.

[0296] Reference Figure 31 is made to, the memory cell array MCA300 may include a plurality of memory cells MC30.

[0297] The memory cell array MCA300 may include a three-dimensional array of memory cells MC30. The three-dimensional array of memory cells MC30 may include a column array of memory cells MC30 and a row array of memory cells MC30. The column array of memory cells MC30 may include a plurality of memory cells MC30 stacked in a first direction D1, and the row array of memory cells MC30 may include a plurality of memory cells MC30 horizontally arranged in a second direction D2 and a third direction D3.

[0298] Each memory cell MC30 may include a first wire BL, a switching element TR, and a data storage element CAP. For a detailed description of the first wire BL and the data storage element CAP, reference may be made to the above embodiments of the present disclosure.

[0299] The switching element TR may include a horizontal layer HL and a second wire GAA-WL. The horizontal layer HL may extend in a second direction D2. The second wire GAA-WL may extend in a third direction D3.

[0300] The second wire GAA-WL may have a gate-all-around structure GAA. For example, the second wire GAA-WL may extend in the third direction D3 while surrounding the horizontal layer HL. An interlayer dielectric layer GD may be formed between the horizontal layer HL and the second wire GAA-WL. The interlayer dielectric layer GD may surround each horizontal layer HL.

[0301] The second wire GAA-WL may include a pair of flat sidewall surfaces FS extending in the third direction D3. The flat sidewalls FS may refer to vertical sidewalls.

[0302] According to another embodiment of the present disclosure, each memory cell may include a first wire BL extending horizontally in a third direction D3, a second wire DWL extending vertically in a first direction D1, and a horizontal layer HL extending horizontally in a second direction D2. The second wire DWL may have a dual structure, or may be replaced with a single structure or a gate-all-around structure.

[0303] According to an embodiment of the present disclosure, bridging between horizontally stacked wires vertically stacked in a stepped stacking manner can be prevented.

[0304] According to an embodiment of the present disclosure, since the support slit includes silicon oxycarbide, bridging between horizontal wires can be prevented when forming the pad portion.

[0305] According to an embodiment of the present disclosure, low power consumption and high integration of three-dimensional (3D) memory cells can be achieved.

[0306] Although the embodiments of the present disclosure have been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the following claims. In addition, these embodiments can be combined to form additional embodiments.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a preliminary horizontal layer above the lower structure; forming a sacrificial slit in the stack; forming a pad isolation opening penetrating the stack between the sacrificial slits; forming a pad-level horizontal layer by recessing the preliminary horizontal layer of the stack through the pad isolation opening; forming a first dielectric layer covering the pad-level horizontal layer; forming a second dielectric layer over the first dielectric layer; forming a slit opening by removing the sacrificial slit; trimming the first dielectric layer through the slit opening to produce a trimmed first dielectric layer; trimming the pad-level horizontal layer beneath the trimmed first dielectric layer; as well as A slit is formed that fills the slit opening.

2. The method according to claim 1, wherein: The forming of the slit opening by removing the sacrificial slit is performed by using a slit opening mask that selectively exposes the sacrificial slit.

3. The method according to claim 1, wherein: The slot includes a stack of a slot liner and a slot gap filling layer.

4. The method according to claim 1, wherein: The slit includes a stack of silicon oxycarbide and silicon oxide.

5. The method according to claim 1, wherein: The preliminary horizontal layer includes single crystal silicon.

6. The method according to claim 1, further comprising: After forming the slit filling the slit opening: replacing the trimmed first dielectric layer with a first horizontal conductive line and a second horizontal conductive line, wherein the first horizontal conductive line and the second horizontal conductive line are formed to face each other vertically with a pad-level horizontal layer interposed therebetween; forming a pad-level gap between the first horizontal conductive line and the second horizontal conductive line by removing the pad-level horizontal layer; and A pad portion is formed to fill the pad-level gap.

7. A method for manufacturing a semiconductor device, the method comprising: forming a stack including a preliminary semiconductor layer over the lower structure; forming a sacrificial slit in the stack; forming a pad isolation opening penetrating the stack between the sacrificial slits; forming a pad-level semiconductor layer by recessing the preliminary semiconductor layer of the stack through the pad isolation opening; forming a first dielectric layer covering the pad-level semiconductor layer; forming a second dielectric layer over the first dielectric layer; forming a vertical sacrificial structure filling the pad isolation opening; forming a slit opening by removing the sacrificial slit; trimming the first dielectric layer through the slit opening to produce a trimmed first dielectric layer; trimming the pad-level semiconductor layer below the trimmed first dielectric layer; forming a slit liner over the slit opening; as well as A slit gap filling layer is formed over the slit liner.

8. The method according to claim 7, further comprising: After forming the slit gap filling layer on the slit liner: replacing the trimmed first dielectric layer with a first horizontal conductive line and a second horizontal conductive line, wherein the first horizontal conductive line and the second horizontal conductive line are formed to face each other vertically with the pad-level semiconductor layer interposed therebetween; forming a pad-level gap between the first horizontal conductive line and the second horizontal conductive line by removing the pad-level semiconductor layer; and A pad portion is formed to fill the pad-level gap.

9. The method according to claim 7, wherein: The slot liner includes silicon oxycarbide.

10. The method according to claim 7, wherein: The slit gap filling layer includes silicon oxide.

11. The method according to claim 7, wherein: The preliminary semiconductor layer includes single crystal silicon.

12. The method according to claim 7, wherein: The stack also includes: A plurality of sacrificial layer structures are respectively formed in the lower portion and the upper portion of the preliminary semiconductor layer.

13. The method according to claim 12, wherein: Each of the sacrificial layer structures includes a stack of first single crystal silicon and silicon germanium, and The preliminary semiconductor layer includes a second single crystal silicon, The second single crystal silicon is formed to be thicker than the first single crystal silicon.

14. A semiconductor device comprising: Substructure; a vertical stack comprising horizontal conductors stacked alternately vertically from the substructure; a staircase stack extending horizontally from the vertical stack and including edge portions of the horizontal conductors; Linear pad isolation slits formed on two sidewalls of the step stack; a hole-shaped pad isolation slit penetrating the step stack and extending vertically in the direction of the horizontal conductor stack; as well as A plurality of supporting slits surround the hole-shaped pad isolation slits, penetrate the step stack, and extend vertically in the direction of the horizontal conductive line stack.

15. The semiconductor device according to claim 14, wherein: Each of the support slits comprises: Slit gaskets; and A slit gap filling layer is located on the slit liner.

16. The semiconductor device according to claim 14, wherein Each of the support slits comprises: Silicon oxycarbide; and Silicon oxide is disposed on the silicon oxycarbide.

17. The semiconductor device according to claim 14, wherein: The vertical stack also includes: a horizontal layer oriented horizontally in a direction intersecting the horizontal conductive line; bit lines commonly coupled to the first side edge of the horizontal layer and extending vertically in the direction of the horizontal conductive line stack; and Data storage elements are respectively coupled to the second side edges of the horizontal layers.

18. The semiconductor device according to claim 17, wherein: The horizontal layer includes single crystal silicon, polycrystalline silicon, oxide semiconductor material or a combination thereof.

19. The semiconductor device according to claim 17, further comprising: a first contact node located between the horizontal layer and the bit line; a first doped region coupled to the first contact node and disposed in the first side edge of the horizontal layer; a second contact node located between the horizontal layer and the data storage element; a second doped region coupled to the second contact node and disposed in the second side edge of the horizontal layer; as well as A channel is disposed between the first doping region and the second doping region in the horizontal layer.

20. The semiconductor device according to claim 14, wherein Each of the horizontal conductive lines includes a double structure in which an upper horizontal line and a lower horizontal line are vertically arranged.

21. The semiconductor device according to claim 20, wherein: Each of the edge portions of the horizontal conductive line comprises: A dual structure in which the upper horizontal line and the lower horizontal line are arranged vertically; and A pad portion is disposed between the upper horizontal line and the lower horizontal line.

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