Semiconductor device and method of manufacturing the same

Abstract

A manufacturing method of a semiconductor device includes forming a substrate layer and a cushion layer over the substrate layer; forming an isolation layer in the substrate layer and the cushion layer, wherein the isolation layer divides the substrate layer and the cushion layer into a first substrate layer and a first cushion layer located above the first substrate layer, and a second substrate layer and a second cushion layer located above the second substrate layer; removing the second cushion layer; lowering a top surface of the second substrate layer; and forming a semiconductor layer on the second substrate layer, wherein a top surface of the semiconductor layer is substantially flush with a top surface of the first substrate layer. Based on this configuration, the stability and efficiency of the semiconductor device may be improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. Background Art

[0002] Dynamic random access memory (DRAM) is a random access semiconductor memory that stores each bit of data in a memory cell. DRAM is known for its high-speed operation, high density, and scalability. However, as the scale of DRAM production increases, the manufacture of DRAM becomes more challenging and more prone to defects. These defects may cause device errors and / or failures. For example, the step height difference of a metal oxide semiconductor device, such as the step height difference between an N-channel field effect transistor (NMOS) and a P-channel field effect transistor (PMOS), may be detrimental to subsequent processes, such as photolithography and implantation processes. Therefore, there is a need for an efficient semiconductor device and a method for manufacturing the same. Summary of the invention

[0003] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: forming a base layer and a pad layer located above the base layer; forming an isolation layer in the base layer and the pad layer, wherein the isolation layer separates the base layer and the pad layer into a first base layer and a first pad layer located above the first base layer, and a second base layer and a second pad layer located above the second base layer; removing the second pad layer; lowering the top surface of the second base layer; and forming a semiconductor layer on the second base layer, wherein the top surface of the semiconductor layer is substantially flush with the top surface of the first base layer.

[0004] In some embodiments, lowering the top surface of the second base layer includes performing an etching process using hydrogen chloride (HCl) and hydrogen (H 2 ).

[0005] In some embodiments, lowering the top surface of the second substrate layer is performed at a temperature below the melting point of the material of the second substrate layer.

[0006] In some embodiments, the temperature is in the range of 930°C ± 20°C.

[0007] In some embodiments, lowering the top surface of the second substrate layer is performed within 5 seconds ± 1 second.

[0008] In some embodiments, lowering the top surface of the second base layer comprises etching the second base layer a vertical length of 8 nm to 10 nm from the top surface of the second base layer.

[0009] In some embodiments, forming a semiconductor layer on the second substrate layer is / second to within a deposition rate range of / second.

[0010] In some embodiments, the formation of the semiconductor layer on the second base layer is carried out at a deposition temperature within the range of 700 °C ± 50 °C.

[0011] In some embodiments, the formation of the semiconductor layer on the second base layer is carried out at a deposition pressure within the range of 5 mTorr to 30 mTorr.

[0012] In some embodiments, the formation of the semiconductor layer on the second base layer includes a silicon (Si) precursor, where the silicon precursor is dichlorosilane (DCS; SiH2Cl2) or silane (SiH4), and a germanium (Ge) precursor, where the germanium precursor is germanium tetrafluoride (GeF4).

[0013] A semiconductor device includes: a base layer having a first region and a second region; an isolation layer located between the first region and the second region of the base layer; a first transistor located above the first region of the base layer and including: a first portion of the base layer; and a first gate structure located above the first portion of the base layer; and a second transistor located above the second region of the base layer and including: a second portion of the base layer; a semiconductor layer located above the second portion of the base layer, where the top surface of the semiconductor layer is substantially flush with the top surface of the first portion of the base layer; and a second gate structure located above the semiconductor layer.

[0014] In some embodiments, the top surface of the second portion of the base layer is lower than the top surface of the first portion of the base layer.

[0015] In some embodiments, the vertical length of the semiconductor layer is 8 nm to 10 nm.

[0016] In some embodiments, the isolation layer has a stepped top surface profile.

[0017] In some embodiments, the isolation layer includes a first portion closer to the first region of the base layer, where the top surface of the first portion of the isolation layer is substantially flush with the surface of the first portion of the base layer.

[0018] In some embodiments, the isolation layer includes a second portion closer to the second region of the base layer, where the top surface of the second portion of the isolation layer is at a lower vertical level than the top surface of the second portion of the base layer.

[0019] In some embodiments, the semiconductor layer and the first portion of the base layer are made of different semiconductor materials.

[0020] In some embodiments, the semiconductor layer is made of silicon germanium (SiGe), and the base layer is made of silicon (Si).

[0021] In some embodiments, the first transistor includes a first source / drain region located in a first portion of the base layer and on opposite sides of the first gate structure, and the second transistor includes a second source / drain region located in the semiconductor layer and on opposite sides of the second gate structure, wherein the first source / drain region includes an N-type dopant and the second source / drain region includes a P-type dopant.

[0022] In some embodiments, the second source / drain region extends to a second portion of the base layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0024] Figure 1 FIG. 1 is a schematic diagram of a semiconductor device in accordance with some embodiments of the present invention.

[0025] Figure 2 FIG. 2 is a schematic diagram of a memory cell in accordance with some embodiments of the present invention.

[0026] Figure 3 FIG. 3 is a flowchart of a method of manufacturing a semiconductor device in accordance with some embodiments of the present invention.

[0027] Figures 4 to 15 FIGS. 4A-4F are schematic diagrams of different steps of a method of manufacturing a semiconductor device in accordance with some embodiments of the present invention. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, in various examples, the present disclosure may repeat reference numerals and / or letters. This repetition is for simplicity and clarity purposes and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0029] In addition, for ease of description, spatial relative terms such as "beneath", "below", "lower", "above", "upper", and the like may be used herein to describe the relationship of one element or feature of an icon in a figure to another element or feature. In addition to the orientation depicted in the figures, these spatial relative terms are intended to also encompass different orientations of the elements during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and likewise, the spatial relative descriptors used herein may be interpreted accordingly.

[0030] As used herein, "about", "approximately", "substantially", or "essentially" generally may mean within 20%, or within 10%, or within 5% of a given value or range. The values given herein are approximate, which means that the terms "about", "approximately", "substantially", or "essentially" may be inferred if not explicitly stated. However, those skilled in the art will recognize that the values or ranges recited throughout the description are merely examples and may decrease or vary as the integrated circuit is scaled down.

[0031] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise. It should also be understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Example embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized example embodiments (and intermediate structures). As such, variations in the illustrated shapes are to be expected due to, for example, manufacturing techniques and / or tolerances. Accordingly, example embodiments should not be construed as limited to the particular shapes of regions illustrated herein but include, for example, shape deviations resulting from manufacturing. For example, an implantation region illustrated as rectangular will typically have rounded or curved features and / or an implantation concentration gradient at its edges rather than a binary change from the implanted region to the non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the invention.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It should also be understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0034] Hereinafter, exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0035] Figure 1 is a schematic diagram of a semiconductor device according to some embodiments of the present invention. Refer to Figure 1 , the semiconductor system 5 is a system-on-chip (SOC) device. The semiconductor system 5 is made of different semiconductor materials on a single semiconductor substrate 20. In addition, the semiconductor system 5 is designed to undergo a semiconductor packaging process, rather than a system-in-package (SiP) process, for example, for integrating two separate chips.

[0036] The semiconductor system 5 includes a processing unit 12 and a semiconductor memory 14. If appropriate, the semiconductor memory 14 may be referred to as a first semiconductor memory.

[0037] The role of the processing unit 12 is to follow the instruction cycle. The processing unit 12 follows the instruction cycle to process instructions from startup until, for example, the computer is shut down. The instruction cycle consists of three main stages: the fetch stage, the decode stage, and the run time.

[0038] In some embodiments, the processing unit 12 includes a standard processor, such as a field programmable gate array (FPGA), a central processing unit (CPU), a graphics processing unit (GPU), an application specific integrated circuit (ASIC), an application specific standard part (ASSP), a micro control unit (MCU). However, the present invention is not limited thereto. In some embodiments, the processing unit 12 may include another suitable processing device.

[0039] The processing unit 12 includes a logic circuit having a control unit (CU) 120 and an arithmetic logic unit (ALU) 122, a static random access memory (SRAM) 124, and a processing peripheral circuit (PPC) 126.

[0040] The role of the CU 120 is to direct the operations within the processing unit 12. In some embodiments, the CU 120 directs the logic unit, memory, and input and output devices of the computer in response to instructions received from a program.

[0041] The ALU 122 coupled to the CU 120 is used to perform bitwise operations and mathematical operations on binary numbers. The ALU 122 is the last component in the processing unit 12 to perform calculations. The ALU 122 performs operations on the input data according to the received operands and codes. After the information is processed by the ALU 122, it is sent to the semiconductor memory 14.

[0042] The SRAM 124 is coupled to the CU 120 and the ALU 122 and is used as a cache for the processing unit 12, where the SRAM 124 is a level-1 cache. If appropriate, the SRAM 124 can be referred to as the second semiconductor memory.

[0043] The PPC 126 serves as a communication interface between the logic circuit of the processing unit 12 and electrical components external to the processing unit 12 (such as the semiconductor memory 14). For example, structurally, the logic circuit is not directly coupled to the semiconductor memory 14. Instead, the logic circuit is directly coupled to the PPC 126 and then indirectly coupled to the semiconductor memory 14 via the PPC 126.

[0044] The semiconductor memory 14 is coupled to the processing unit 12 for storing instructions required during the instruction cycle and serves as the main memory of the processing unit 12.

[0045] In some embodiments, the semiconductor memory 14 includes volatile memory or non-volatile memory. The non-volatile memory includes magnetoresistive random access memory (MRAM), resistive random access memory (ReRAM), conductive bridge memory (CBM), phase change memory (PCM), nanotube memory (NRAM), ferroelectric field effect transistor (FeFET) memory, 3D XPoint (3DXP) memory, or flash memory. The volatile memory includes dynamic random access memory (DRAM).

[0046] The semiconductor memory 14 includes a memory cell array 142 and a memory peripheral circuit (MPC) 140. The memory cell array 142 contains a plurality of word lines WL1 to WLn, a plurality of bit lines BL1 to BLm, and a plurality of memory cells 144, where n and m are positive integers greater than 1. The memory cells 144 are arranged in columns and rows.

[0047] The memory cells 144 are set at each intersection of the word lines and the bit lines and are used to store data in digital binary form. The memory cells 144 include, for example, a storage device for storing data and a storage transistor for performing cell selection. In an embodiment where the semiconductor memory 14 is DRAM, the storage device includes a capacitor. In another embodiment where the semiconductor memory 14 is MRAM, the storage device includes a magnetic tunnel junction (MJT) transistor.

[0048] The MPC 140 serves as a communication interface between the memory cell array 142 and electrical components (such as the processing unit 12) external to the semiconductor memory 14. Structurally, for example, the memory cell array 142 is not directly coupled to the processing unit 12. Instead, the memory cell array 142 is directly coupled to the MPC 140 and then indirectly coupled to the processing unit 12 via the MPC 140.

[0049] In addition, the MPC 140 functions to control the memory cell array 142. The MPC 140 includes, for example, a row decoder, a column decoder, an address buffer, an input / output (I / O) buffer, a clock generator, a direct current (DC) generator, and a sense amplifier (S / A).

[0050] In operation, the processing unit 12 generates and provides a data signal Data, an address signal Address, and a memory control signal Control to the MPC 140 to access the memory cell array 142. In some embodiments, the memory control signal Control includes a command signal. However, the present disclosure is not limited thereto. In some embodiments, the memory control signal control includes other suitable signals.

[0051] Figure 2 A schematic diagram of a memory cell according to some embodiments of the present invention. Specifically, Figure 2 is Figure 1 a close-up view of. In some embodiments, the memory cell 144 includes an access transistor 144T and a storage capacitor 144C electrically connected to the access transistor 144T. In some embodiments, the access transistor 144T is an NMOS transistor and is configured to control the channel to the memory cell 144 by turning on or off the gate of the access transistor 144T.

[0052] In some embodiments, the storage capacitor 144C is configured to store information according to the state of the charge stored therein. The storage capacitor 144C in an empty state (i.e., not charged) is represented as having a logic value equivalent to 0. The storage capacitor 144C in a fully charged state is represented as having a logic value equivalent to 1. The memory cell 144 stores bit data using two extreme charge states stored in the storage capacitor 144C. In some embodiments, a word line WL1 connected to the access transistor 144T is used to control the gate of the access transistor 144T by applying a voltage to the gate of the access transistor 144T. In some embodiments, a bit line BL1 is perpendicular to the arrangement of the word line WL1 and is also connected to the access transistor 144T. When the gate of the access transistor 144T is turned on, the access transistor 144T connects the storage capacitor 144C to the bit line BL1 such that the logic value stored in the storage capacitor 144C will be read on the bit line BL1.

[0053] Figure 3 It is a flowchart of a method for manufacturing a semiconductor device according to some embodiments of the present invention. Figures 4 to 15 It is a schematic diagram of different steps of a method for manufacturing a semiconductor device according to some embodiments of the present invention.

[0054] will be discussed in conjunction with Figures 4 to 15 a semiconductor device and a manufacturing method M10. As Figure 3 shown, the manufacturing method M10 may include the following operations S100, operation S200, operation S300, operation S400, operation S500, operation S600, operation S700, operation S800, operation S900, operation S1000, operation S1100, and operation S1200.

[0055] Various operations of the embodiments are provided herein. The order of describing some or all of the operations should not be construed as implying that these operations necessarily depend on the order. Alternative orderings will be understood to benefit from this description. In addition, it should be understood that not all operations must be present in each embodiment provided herein. Moreover, it should be understood that not all operations are required in some embodiments.

[0056] The method M10 starts with operation S100 to form a base layer and a buffer layer. Referring to Figure 4 , a base layer 100 and a buffer layer 200 are formed.

[0057] In some embodiments, the base layer 100 is made of silicon (Si). In some embodiments, the base layer 100 is configured to serve as a base structure for supporting N-type metal oxide semiconductor (NMOS) elements and / or P-type metal oxide semiconductor (PMOS) elements formed in subsequent processes.

[0058] In some embodiments, the buffer layer 200 is formed on the base layer 100. In some embodiments, the buffer layer 200 is made of a dielectric material. In some embodiments, the buffer layer 200 is a pad oxide. In some embodiments, the buffer layer 200 is made of silicon dioxide (SiO2).

[0059] In some embodiments, the buffer layer 200 is formed using a thermal oxidation process. In some embodiments, the buffer layer 200 can be formed by chemical vapor deposition (CVD). In some embodiments, the vertical thickness of the buffer layer 200 is about 10 nm to 500 nm.

[0060] The method M10 proceeds to operation S200 to form an opening in the base layer and the buffer layer. Referring to Figure 5 , an opening 300 is formed in the base layer 100 and the buffer layer 200 to separate the base layer 100 and the buffer layer 200 into two regions - a first region 500A and a second region 500B.

[0061] In some embodiments, a patterned mask layer (not shown) may be formed on top of the buffer layer 200 in the first region 500A and the second region 500B. The patterned mask layer is configured to serve as an etching protection layer for the buffer layer 200 above the first region 500A and the second region 500B in subsequent etching processes. In some embodiments, the patterned mask layer may not cover the central region of the buffer layer 200.

[0062] Subsequently, an etching process may be performed to etch the central region of the buffer layer 200 and a portion of the base layer 100 through the patterned mask layer. Then, the formation of the opening 300 separates the base layer 100 and the buffer layer 200 into two regions - the first region 500A and the second region 500B. Due to the formation of the opening 300, the first region 500A includes the first base layer 100A and the first buffer layer 200A. On the other side, the second region 500B includes the second base layer 100B and the second buffer layer 200B.

[0063] The method M10 proceeds to operation S300 to form an isolation layer in the opening. Refer to Figure 6 , the isolation layer 400 is formed within the opening 300.

[0064] In some embodiments, the isolation layer 400 is made of a dielectric material. In some embodiments, the isolation layer 400 is configured to provide electrical isolation between the first base layer 100A and the second base layer 100B. In some embodiments, the isolation layer 400 is a shallow trench isolation (STI) structure.

[0065] The isolation layer 400 may be deposited using chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), or other suitable deposition processes. A planarization process may use a chemical mechanical polishing (CMP) process to remove the excess portion of the isolation layer 400 and make the isolation layer 400 flush with the buffer layer 200.

[0066] The method M10 proceeds to operation S400 to form a patterned photoresist on the first region of the base layer. Refer to Figure 7 , a patterned photoresist 600 is formed above the first region 500A of the base layer 100.

[0067] A photoresist material layer (not shown) may be formed over the first region 500A using a suitable deposition process (e.g., spin coating). The photoresist material layer is then exposed to a light source through a photomask having a specific pattern (not shown). In some embodiments, the regions of the photoresist material layer become soluble when exposed to light. In this way, the exposed regions of the photoresist material layer can be washed away to define the patterned photoresist 600.

[0068] In some embodiments, the patterned photoresist 600 may be formed on top of the first cushion layer 200A. In some embodiments, the patterned photoresist 600 may also cover a portion of the isolation layer 400, leaving another portion of the isolation layer 400 exposed. In some embodiments, the portion of the isolation layer 400 covered by the patterned photoresist 600 may be closer to the first region 500A than to the second region 500B.

[0069] The patterned photoresist 600 is configured to serve as an etch protection layer for the lower first cushion layer 200A over the first base layer 100A in a subsequent etching process. The patterned photoresist 600 may also be configured to act as an etch protection layer for the underlying portion of the isolation layer 400 in a subsequent etching process.

[0070] Method M10 proceeds to operation S500 to etch a portion of the cushion layer over the second region of the base layer. Refer to Figure 8 , an etching process is performed on the second region 500B of the base layer 100 through the photoresist 600. In some embodiments, the second cushion layer 200B is etched through the photoresist 600 such that the top surface of the second base layer 100B is exposed.

[0071] In some embodiments, since the isolation layer 400 and the second cushion layer 200B may include the same material, such as silicon oxide, the portion of the isolation layer 400 not covered by the photoresist 600 is partially etched away through the photoresist 600. Thus, once the etching process is completed, the isolation layer 400 may include a stepped top surface profile.

[0072] In some embodiments, the second base layer 100B may have a higher etch resistance to the etching process than the second cushion layer 200B and the isolation layer 400. Thus, once the second cushion layer 200B is removed, the exposed second base layer 100B can serve as an etch stop layer for the etching process, and the etching process can continue to etch the isolation layer 400. Therefore, the top surface of the isolation layer 400 after etching may be at a lower vertical level than the second base layer 100B exposed after the etching process.

[0073] In some embodiments, the etching process may stop when the second base layer 100B is exposed. In some embodiments, the etching process may be a dry etching process or a wet etching process.

[0074] Method M10 proceeds to operation S600 to remove the photoresist. Refer to Figure 9 , after the etching process, the photoresist 600 is removed.

[0075] In some embodiments, the removal of the photoresist 600 includes using a liquid resist stripper (not shown), which chemically changes the photoresist 600 such that the photoresist 600 no longer adheres to the first cushion layer 200A or the isolation layer 400. In some embodiments, the removal of the photoresist 600 exposes the unetched portions of the first cushion layer 200A and the isolation layer 400.

[0076] Method M10 proceeds to operation S700 to etch a second region of the base layer. Refer to Figure 10 , the second base layer 100B is etched. In some embodiments, since the first base layer 100A is protected by the first cushion layer 200A during the etching process, when the etching process is completed, the top surface of the second base layer 100B is at a lower height than the top surface of the first base layer 100A.

[0077] In certain embodiments, the etching process can be a wet etching process. In some embodiments, the etching process can include certain etchants such as hydrogen chloride (HCl) and hydrogen (H2) for etching the second base layer 100B. In some embodiments, the first cushion layer 200A and the isolation layer 400 can have a higher etching resistance to the etching process of the second base layer 100B such that once the second base layer 100B is etched, the first cushion layer 200A and the isolation layer 400 can remain substantially intact.

[0078] In some embodiments, the etching process can be performed at an etching temperature below the melting point of the material of the second base layer 100B. In some embodiments, the etching process can be performed within an etching temperature range of about 930°C ± 20°C. In some embodiments, the etching temperature range of about 930°C ± 20°C is conducive to the second base layer 100B having a smooth top surface after the etching process. In some embodiments, the temperature of about 930°C ± 20°C has not reached the melting point of the material (such as silicon) of the second base layer 100B, thus avoiding an unexpected physical change in the shape of the second base layer 100B.

[0079] In some embodiments, the etching process can be completed within a time period of about 5 seconds ± 1 second. In some embodiments, the etching process can etch a vertical length of about 8 nm to about 10 nm from the top surface of the second base layer 100B. In some embodiments, the top surface of the etched second base layer 100B and the top surface of the etched portion of the isolation layer 400 can be at substantially the same level.

[0080] Method M10 continues to operation S800 to form a semiconductor layer over the second region of the base layer. Refer toFigure 11 A semiconductor layer 700 is formed on the second base layer 100B.

[0081] In some embodiments, the semiconductor layer 700 may be made of a semiconductor material different from that of the base layer 100 (e.g., silicon). In some embodiments, the semiconductor layer 700 may be made of silicon germanium (SiGe). In some embodiments, the semiconductor layer 700 can be used as a channel layer for semiconductor devices formed in subsequent processes.

[0082] In some embodiments, the semiconductor layer 700 may be deposited on the second base layer 100B. The semiconductor layer 700 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0083] In some embodiments, the semiconductor layer 700 has a low deposition rate to facilitate the growth of a smooth top surface. In some embodiments, the deposition rate of the semiconductor layer 700 is in the range of about / second to about / second. Additionally, the low deposition rate is beneficial for controlling the thickness of the semiconductor layer 700.

[0084] In some embodiments, the semiconductor layer 700 has a low deposition temperature to facilitate the growth of a smooth top surface. In some embodiments, the deposition temperature of the semiconductor layer 700 is in the range of about 700 °C ± 50 °C. In some embodiments, the deposition pressure of the semiconductor layer 700 is in the range of about 5 mTorr to about 30 mTorr.

[0085] In some embodiments, the deposition of the semiconductor layer 700 can use a silicon (Si) precursor, a germanium (Ge) precursor, and HCl. In some embodiments, the Si precursor can be dichlorosilane (DCS; SiH2Cl2) or silane (SiH4). In some embodiments, the flow rate of the Si precursor can be in the range of about 100 standard cubic centimeters per minute (sccm) to 180 sccm.

[0086] In some embodiments, the Ge precursor can be germanium tetrafluoride (GeF4) in gaseous form. In some embodiments, the flow rate of the Ge precursor can be in the range of about 10 sccm to 90 sccm. In some embodiments, the flow rate of HCl can be in the range of about 50 sccm to 150 sccm.

[0087] In some embodiments, the semiconductor layer 700 may replace a portion of the second base layer 100B that is etched in operation S700. In some embodiments, the semiconductor layer 700 has a substantially same vertical length as the portion of the second base layer 100B that is etched in operation S700. In some embodiments, the third semiconductor layer 700 has a vertical length of about 8 nm to about 10 nm.

[0088] In some embodiments, the top surface of the semiconductor layer 700 is at a substantially same vertical level as the top surface of the first base layer 100A. In some embodiments, the top surface of the semiconductor layer 700 may be substantially flat or smooth.

[0089] Method M10 proceeds to operation S900 to remove the cushion layer within the first region of the base layer. Refer to Figure 12 , and the first cushion layer 200A is removed using an appropriate etching process. In some embodiments, since the isolation layer 400 and the first cushion layer 200A may be made of the same material, such as an oxide, the isolation layer 400 may also be etched during the etching process.

[0090] After the etching process is completed, the isolation layer 400 may include a first portion 400A and a second portion 400B located in the first base layer 100A and the second base layer 100B, respectively. In some embodiments, the first portion 400A may be thicker than the second portion 400B.

[0091] In some embodiments, the bottom surface of the first portion 400A may be substantially flush with the bottom surface of the second portion 400B, while the top surface of the first portion 400A may be higher than the top surface of the second portion 400B. In some embodiments, the top surface of the first portion 400A of the isolation layer 400 may be substantially flush with the top surface of the first base layer 100A, while the top surface of the second portion 400B of the isolation layer 400 may be lower than the top surface of the second base layer 100B.

[0092] Method M10 proceeds to operation S1000 to form gate structures above the first region and the second region of the base layer, respectively. Refer to Figure 13 , and gate structures 800A and 800B are formed above the first region 500A and the second region 500B of the base layer 100, respectively.

[0093] Specifically, the formation of the gate structure 800A contacts the top surface of the first base layer 100A, and the formation of the gate structure 800B contacts the top surface of the semiconductor layer 700.

[0094] In some embodiments, each of the gate structures 800A and 800B may include a gate dielectric layer 801, a high-k dielectric layer 802, a first conductive layer 803, a second conductive layer 804, a third conductive layer 805, and a dielectric capping layer 806.

[0095] The gate dielectric layer 801 can be deposited over the first base layer 100A and the semiconductor layer 700. In some embodiments, the gate dielectric layer 801 can be made of a dielectric material. In some embodiments, the gate dielectric layer 801 can be made of an oxide. In some embodiments, the gate dielectric layer 801 can include silicon oxide (SiO2) or aluminum oxide (Al2O3).

[0096] In some embodiments, the gate dielectric layer 801 is configured to electrically isolate the first base layer 100A and / or the semiconductor layer 700 from the conductive structures in the gate structures 800A and 800B that will be formed in subsequent processes. The gate dielectric layer 801 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0097] The high-k dielectric layer 802 can be deposited on the gate dielectric layer 801. In some embodiments, the high-k dielectric layer 802 can be made of a dielectric material. In some embodiments, the high-k dielectric layer 802 can be made of a dielectric material having a high dielectric constant (high-k), such as zirconium dioxide (ZrO2), hafnium dioxide (HfO2), etc.

[0098] In some embodiments, similar to the gate dielectric layer 801, the high-k dielectric layer 802 is configured to electrically isolate the first base layer 100A and / or the semiconductor layer 700 from the conductive structures in the gate structures 800A and 800B that will be formed in subsequent processes. The high-k dielectric layer 802 can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0099] After forming the high-k dielectric layer 802, the first conductive layer 803, the second conductive layer 804, and the third conductive layer 805 can be sequentially deposited over the high-k dielectric layer 802.

[0100] In some embodiments, the first conductive layer 803, the second conductive layer 804, and the third conductive layer 805 can be made of a conductive material. In some embodiments, the first conductive layer 803, the second conductive layer 804, and the third conductive layer 805 can be made of a metal. In some embodiments, the first conductive layer 803 can be made of titanium nitride (TiN). In some embodiments, the second conductive layer 804 can be made of polysilicon. In some embodiments, the third conductive layer 805 can be made of tungsten (W).

[0101] In some embodiments, the first conductive layer 803, the second conductive layer 804, and the third conductive layer 805 can be gate electrodes, which can be electrically connected to the first base layer 100A and / or the second base layer 100B and the semiconductor layer 700. The first conductive layer 803, the second conductive layer 804, and the third conductive layer 805 can be deposited by CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0102] The dielectric capping layer 806 can be deposited over the third conductive layer 805. In some embodiments, the dielectric capping layer 806 can be made of a dielectric material. In some embodiments, the gate dielectric layer 801 can be made of silicon nitride (SiN). The dielectric capping layer 806 can be deposited by CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0103] Next, gate spacers 900 are formed along the sidewalls of the gate structures 800A and 800B, respectively. In some embodiments, the gate spacers 900 can include a first gate spacer layer 901, a second gate spacer layer 902 located above the first gate spacer layer 901, and a third gate spacer layer 903 located above the second gate spacer layer 902.

[0104] In some embodiments, the gate spacers 900 are made of a dielectric material. In some embodiments, the first gate spacer layer 901 is made of silicon nitride (SiN). In some embodiments, the second gate spacer layer 902 is made of silicon oxide (SiO). In some embodiments, the third gate spacer layer 903 is made of silicon nitride (SiN).

[0105] In some embodiments, the gate spacers 900 are configured to laterally offset the gate structures 800A and 800B from their corresponding source / drain regions.

[0106] The first gate spacer layer 901, the second gate spacer layer 902, and the third gate spacer layer 903 can all be deposited by CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes

[0107] In some embodiments, the first gate spacer layer 901, the second gate spacer layer 902, and the third gate spacer layer 903 can be deposited in a conformal manner. Subsequently, an etching process can be performed to remove the horizontal portions of the gate spacers 900, leaving only the vertical portions of the gate spacers 900 along the sidewalls of the gate structures 800A and 800B.

[0108] Method M10 continues to operation S1100 to form a first source / drain region and a second source / drain region in the first region and the second region, respectively. Refer toFigure 14 , a first source / drain region 1000A and a second source / drain region 1000B are respectively formed in a first region 500A and a second region 500B.

[0109] Specifically, the first source / drain region 1000A is formed in the first base layer 100A and is located on opposite sides of the gate structure 800A. On the other hand, the second source / drain region 1000B is formed in the semiconductor layer 700 and is located on opposite sides of the gate structure 800B.

[0110] In some embodiments, the source / drain regions 1000A and 1000B are formed by one or more ion implantation processes. In some embodiments, the source / drain regions 1000A and 1000B are implanted with certain substances that change the conduction type of the thin film.

[0111] In some embodiments, the first base layer 100A may be implanted with an N-type dopant. In some embodiments, the first base layer 100A may be implanted with phosphorus (P) and / or arsenic (As).

[0112] In some embodiments, the semiconductor layer 700 may be implanted with a P-type dopant. In some embodiments, the semiconductor layer 700 and / or the second base layer 100B may be implanted with boron (B), gallium (Ga), and / or indium (In).

[0113] In some embodiments, the upper portion of the second base layer 100B may also be implanted with a P-type dopant. In some embodiments, the upper portion of the second base layer 100B may have a higher P-type dopant concentration than the bottom of the second base layer 100B, such as boron (B), gallium (Ga), and / or indium (In). Therefore, in some embodiments, the source / drain region 1000B may be formed in the semiconductor layer 700 and may extend to the upper portion of the second base layer 100B.

[0114] After the source / drain regions 1000A and 1000B are formed, a first semiconductor device TR1 and a second semiconductor device TR2 are formed, wherein the first semiconductor device TR1 is formed above the first region 500A of the base layer 100, and the second semiconductor device TR2 is formed above the second region 500B of the base layer 100.

[0115] Regarding the first semiconductor device TR1, the first semiconductor device TR1 includes a first base layer 100A (e.g., a channel layer), a gate structure 800A located above the first base layer 100A, and source / drain regions 1000A located on opposite sides of the gate structure 800A.

[0116] Regarding the second semiconductor device TR2, the second semiconductor device TR2 includes a semiconductor layer 700 (e.g., a channel layer), a gate structure 800B located above the semiconductor layer 700, and source / drain regions 1000B located on opposite sides of the semiconductor layer 700.

[0117] In some embodiments, the first semiconductor device TR1 can be an N-type device, such as an NMOS device. On the other hand, the second semiconductor device TR2 can be a P-type device, such as a PMOS device.

[0118] Method M10 proceeds to operation S1200 to form an interlayer dielectric layer and source / drain electrodes. Refer to Figure 15 , an interlayer dielectric layer (ILD layer) 1100 is formed above the base layer 100, covering the source / drain regions 1000A and 1000B, and laterally surrounding the gate structures 800A and 800B.

[0119] In some embodiments, the ILD layer 1100 is formed over the base layer 100 and then a planarization process (e.g., a CMP process) is performed to make the ILD layer 1100 flush with the gate structures 800A and 800B.

[0120] In some embodiments, the ILD layer 1100 can include multiple layers formed of various dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, tetraethyl orthosilicate (TEOS) oxide, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), low-k dielectric materials, and / or other suitable dielectric materials.

[0121] Then, a first source / drain electrode 1200A and a second source / drain electrode 1200B are formed in the ILD layer 1100 and are electrically connected to the first source / drain region 1000A and the second source / drain region 1000B, respectively.

[0122] In some embodiments, the first source / drain electrode 1200A and the second source / drain electrode 1200B can be formed by, for example, patterning the ILD layer 1100 to form openings in the ILD layer 1100 that expose the source / drain regions 1000A and 1000B, depositing a conductive material in the openings, and then performing a planarization process, such as CMP, to remove the excess conductive material until the ILD layer 1100 is exposed.

[0123] The first source / drain electrode 1200A and the second source / drain electrode 1200B can be deposited using CVD, PECVD, ALD, PVD, LPCVD, FCVD, or other suitable deposition processes.

[0124] The first source / drain electrode 1200A and the second source / drain electrode 1200B can be made of a conductive material. The first source / drain electrode 1200A and the second source / drain electrode 1200B can be configured to be electrically connected to the first source / drain region 1000A and the second source / drain region 1000B, respectively. In some embodiments, the top surface of the first source / drain electrode 1200A or the second source / drain electrode 1200B can have a greater horizontal width than its bottom surface.

[0125] Figure 15 The combination of the elements in can be referred to as the semiconductor device 10. In some embodiments, the semiconductor device 10 can be located in the memory peripheral circuit (MPC) 140 of the semiconductor memory 14. Please refer to Figure 1 .

[0126] In summary, the present invention provides a method of reducing the top surface of the second base layer 100B by performing an additional etching process, which will result in the subsequently formed semiconductor layer 700 having a top surface that is substantially flush with the second base layer 100B.

[0127] Therefore, the top surfaces of the gate structures 800A above the first base layer 100A and the gate structures 800B above the semiconductor layer 700 are substantially at the same vertical level, which is beneficial for subsequent processes, such as lithography processes, implantation processes, etc., thereby improving device performance.

[0128] The foregoing has outlined the features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations can be made therein without departing from the spirit and scope of the present disclosure.

[0129]

Symbol Description

[0130] 5: Semiconductor system

[0131] 10: Semiconductor device

[0132] 12: Processing unit

[0133] 14: Semiconductor memory

[0134] 20: Substrate

[0135] 100: Base layer

[0136] 100A: First base layer

[0137] 100B: Second base layer

[0138] 120: Control Unit (CU)

[0139] 122: Arithmetic Logic Unit (ALU)

[0140] 124: Static Random Access Memory (SRAM)

[0141] 126: Processing Peripheral Circuit (PPC)

[0142] 140: Memory Peripheral Circuit (MPC)

[0143] 142: Memory cell array

[0144] 144: Memory cell

[0145] 144C: Memory capacitor

[0146] 144T: Access transistor

[0147] 200: Buffer layer

[0148] 200A: First buffer layer

[0149] 200B: Second buffer layer

[0150] 300: Opening

[0151] 400: Isolation layer

[0152] 400A: First part

[0153] 400B: Second part

[0154] 500A: First region

[0155] 500B: Second region

[0156] 600: Photoresist

[0157] 700: Semiconductor layer

[0158] 800A: Gate structure

[0159] 800B: Gate structure

[0160] 801: Gate dielectric layer

[0161] 802: High-k dielectric layer

[0162] 803: First conductive layer

[0163] 804: Second conductive layer

[0164] 805: Third conductive layer

[0165] 806: Dielectric Overlayer

[0166] 900: Gate Spacer

[0167] 901: First Gate Spacer Layer

[0168] 902: Second Gate Spacer Layer

[0169] 903: Third Gate Spacer Layer

[0170] 1000A: Source / Drain Region

[0171] 1000B: Source / Drain Region

[0172] TR1: First Semiconductor Device

[0173] TR2: Second Semiconductor Device

[0174] 1100: Interlayer Dielectric Layer (ILD Layer)

[0175] 1200A: First Source / Drain Electrode

[0176] 1200B: Second Source / Drain Electrode

[0177] M10: Method

[0178] S100: Operation

[0179] S200: Operation

[0180] S300: Operation

[0181] S400: Operation

[0182] S500: Operation

[0183] S600: Operation

[0184] S700: Operation

[0185] S800: Operation

[0186] S900: Operation

[0187] S1000: Operation

[0188] S1100: Operation

[0189] S1200: Operation

[0190] WL1 - WLn: Word Line

[0191] BL1 - BLm: Bit Line

[0192] Data: Data Signal

[0193] Address: Address signal

[0194] Control: Control signal.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a base layer and a cushion layer located above the base layer; forming an isolation layer in the base layer and the cushion layer, wherein the isolation layer separates the base layer and the cushion layer into a first base layer and a first cushion layer located above the first base layer, and a second base layer and a second cushion layer located above the second base layer; removing the second cushion layer; lowering the top surface of the second substrate layer; as well as A semiconductor layer is formed on the second substrate layer, wherein a top surface of the semiconductor layer is flush with a top surface of the first substrate layer. 2 . The method of claim 1 , wherein lowering the top surface of the second base layer comprises performing an etching process using hydrogen chloride and hydrogen gas. 3 . The method of claim 1 , wherein lowering the top surface of the second substrate layer is performed at a temperature below a melting point of a material of the second substrate layer.

4. The method according to claim 3, wherein the temperature is in the range of 930°C ± 20°C.

5. The method of claim 1, wherein lowering the top surface of the second substrate layer is performed within 5 seconds ± 1 second. 6 . The method of claim 1 , wherein lowering the top surface of the second base layer comprises etching the second base layer a vertical length of 8 nm to 10 nm from the top surface of the second base layer.

7. The method according to claim 1, wherein forming the semiconductor layer on the second substrate layer is / second to The deposition rate is within the range of 2000 ℃ and 1000 ℃.

8. The method according to claim 1, wherein forming the semiconductor layer on the second base layer is performed at a deposition temperature within a range of 700°C ± 50°C. 9 . The method of claim 1 , wherein forming the semiconductor layer on the second base layer is performed at a deposition pressure in a range of 5 mTorr to 30 mTorr.

10. The method according to claim 1, wherein forming the semiconductor layer on the second base layer comprises a silicon precursor, wherein the silicon precursor is dichlorosilane or silane, and a germanium precursor, wherein the germanium precursor is germanium tetrafluoride.

11. A semiconductor device, characterized in that: include: a base layer having a first region and a second region; An isolation layer, located between the first region and the second region of the base layer; The first transistor is located above the first region of the base layer and includes: a first portion of the base layer; and a first gate structure located above the first portion of the base layer; and The second transistor is located above the second region of the base layer and includes: a second portion of the base layer; a semiconductor layer located above the second portion of the base layer, wherein a top surface of the semiconductor layer is flush with a top surface of the first portion of the base layer; and A second gate structure is located above the semiconductor layer. 12 . The semiconductor device according to claim 11 , wherein a top surface of the second portion of the base layer is lower than the top surface of the first portion of the base layer. 13 . The semiconductor device according to claim 11 , wherein a vertical length of the semiconductor layer is 8 nm to 10 nm. The semiconductor device according to claim 11 , wherein the isolation layer has a stepped top surface profile. 15 . The semiconductor device according to claim 14 , wherein the isolation layer comprises a first portion closer to the first region of the base layer, wherein a top surface of the first portion of the isolation layer is flush with the surface of the first portion of the base layer. 16 . The semiconductor device of claim 15 , wherein the isolation layer comprises a second portion closer to the second region of the base layer, wherein a top surface of the second portion of the isolation layer is at a lower vertical level than the top surface of the second portion of the base layer. 17 . The semiconductor device according to claim 11 , wherein the semiconductor layer and the first portion of the base layer are made of different semiconductor materials.

18. The semiconductor device according to claim 17, wherein the semiconductor layer is made of silicon germanium, and the base layer is made of silicon.

19. A semiconductor device according to claim 11, wherein the first transistor includes a first source / drain region located in the first portion of the base layer and on the opposite side of the first gate structure, and the second transistor includes a second source / drain region located in the semiconductor layer and on the opposite side of the second gate structure, wherein the first source / drain region includes N-type dopants and the second source / drain region includes P-type dopants. 20 . The semiconductor device of claim 19 , wherein the second source / drain region extends to the second portion of the base layer.

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