Semiconductor structure and preparation method thereof, and memory system

Abstract

The invention provides a semiconductor structure, a preparation method and a memory system. The semiconductor structure comprises a laminated structure and a channel structure. The laminated structure comprises first dielectric layers and gate layers which are alternately stacked in the first direction. The channel structure extends in the laminated structure in the first direction, the channel structure comprises a functional layer, a channel layer located on the surface of the functional layer and a semiconductor material filling layer located on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium and zinc.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and fabrication, and more particularly, to semiconductor structures, methods of fabricating semiconductor structures, and memory systems. Background Art

[0002] Taking a three-dimensional memory as an example, a semiconductor structure may include a stacked structure and a channel structure. The stacked structure may be formed by alternately stacking gate layers and first dielectric layers, and the channel structure extends in the stacked structure along the stacking direction and may include a functional layer and a channel layer on the surface of the functional layer.

[0003] With the improvement of semiconductor integration, such as the increase in the number of stacked layers in a three-dimensional memory and the increasing depth of the channel layer, how to improve the overall performance of the semiconductor structure is an urgent problem to be solved at present. Summary of the Invention

[0004] This application provides a semiconductor structure, a method of fabricating a semiconductor structure, and a memory system that can at least partially solve the above problems.

[0005] On the one hand, this application provides a semiconductor structure, including: a stacked structure including a first dielectric layer and a gate layer alternately stacked along a first direction; and a channel structure extending in the stacked structure along the first direction, wherein the channel structure includes a functional layer, a channel layer on the surface of the functional layer, and a semiconductor material filling layer on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

[0006] In an embodiment of this application, the channel layer includes at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide.

[0007] In an embodiment of this application, the semiconductor material filling layer includes a first part and a second part connected to each other, wherein the first part extends along the first direction and is surrounded by the channel layer; and the second part extends along a second direction intersecting the first direction and covers a part of the surface of the channel layer.

[0008] In an embodiment of this application, the semiconductor material filling layer contains P-type conductive impurities.

[0009] In an embodiment of this application, the semiconductor structure further includes a conductive layer and a semiconductor material connection layer, wherein the conductive layer extends along a second direction intersecting the first direction; and the semiconductor material connection layer is located between the semiconductor material filling layer and the conductive layer along the first direction and is connected to the semiconductor material filling layer and the conductive layer.

[0010] In one embodiment of the present application, the semiconductor material filling layer contains P-type conductive impurities; and the semiconductor material connecting layer contains N-type conductive impurities.

[0011] In one embodiment of the present application, the semiconductor material connecting layer and the conductive layer contain the same type of conductive impurities.

[0012] In one embodiment of the present application, the impurity doping concentration of the semiconductor material connecting layer is less than that of the conductive layer.

[0013] In one embodiment of the present application, the channel layer includes a first end and a second end opposite to each other along the first direction, and sidewalls located between the first end and the second end. Wherein, the semiconductor material filling layer is located on the surfaces of the sidewalls and the first end; and the semiconductor structure further includes a channel contact structure, and the channel contact structure is connected to the second end.

[0014] In one embodiment of the present application, in a direction intersecting the first direction, the extension dimension of the second end is greater than that of the first end.

[0015] In one embodiment of the present application, the functional layer includes a blocking layer, a charge trapping layer located on the surface of the blocking layer, and a tunneling layer located on the surface of the charge trapping layer.

[0016] In one embodiment of the present application, the functional layer includes a ferroelectric material layer or an antiferroelectric material layer.

[0017] On the other hand, the present application provides a method for manufacturing a semiconductor structure, including: forming a stacked structure, where the stacked structure includes a first dielectric layer and a gate layer alternately stacked along a first direction; and forming a channel structure extending in the stacked structure along the first direction, where the channel structure includes a functional layer, a channel layer located on the surface of the functional layer, and a semiconductor material filling layer located on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

[0018] In one embodiment of the present application, forming a channel structure extending in the stacked structure along the first direction includes: forming a channel hole extending in the stacked structure along the first direction, and forming an initial functional layer in the channel hole, and filling a channel sacrificial layer in the remaining space of the channel hole; after completing the front-side process, removing part of the initial functional layer from the back side opposite to the front side to form the functional layer; removing the channel sacrificial layer from the back side to expose the surface of the functional layer; and forming the channel layer on the exposed surface of the functional layer.

[0019] In one embodiment of the present application, the front-side process includes: forming a channel contact structure connected to the channel sacrificial layer on the front side; and connecting the stacked structure having the channel contact structure formed thereon to an external circuit chip.

[0020] In one embodiment of the present application, forming a channel structure extending in the stacked structure along the first direction further includes: filling the remaining space of the channel hole from the back side to form a part of the semiconductor material filling layer; and forming another part of the semiconductor material filling layer on the exposed surface of the part of the semiconductor material filling layer and the exposed surface of the channel layer.

[0021] In one embodiment of the present application, the method further includes: forming a semiconductor material connection layer connected to the semiconductor material filling layer, wherein the semiconductor material filling layer contains P-type conductive impurities; and the semiconductor material connection layer contains N-type conductive impurities.

[0022] In one embodiment of the present application, forming another part of the semiconductor material filling layer includes: forming a sealing layer, wherein the sealing layer covers the surface of the functional layer on the back side and exposes the surface of a part of the channel layer and the semiconductor material filling layer on the back side; and forming another part of the semiconductor material filling layer on the exposed surface of the part of the semiconductor material filling layer and the surface of the channel layer.

[0023] In one embodiment of the present application, forming another part of the semiconductor material filling layer includes: removing a part of the channel layer to expose the surface of a part of the semiconductor material filling layer; forming an initial filling layer, wherein the initial filling layer at least fills the void formed after removing the part of the channel layer; and removing a part of the initial filling layer to form another part of the semiconductor material filling layer. In another aspect of the present application, a memory system is provided. The memory system includes the semiconductor structure provided in one aspect of the present application and a controller coupled to the semiconductor structure. The controller is configured to store data in the semiconductor structure.

[0024] A semiconductor structure, a manufacturing method thereof, and a memory system according to at least one embodiment of the present application. The semiconductor structure includes a stacked structure and a channel structure extending in a stacking direction in the stacked structure. The channel structure includes a channel layer and a semiconductor material filling layer located on the surface of the channel layer and connected to the channel layer. The channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc. Using an oxide semiconductor material containing at least one of indium, gallium, and zinc as the channel layer material can improve the uniformity of the channel layer and the consistency between multiple channel layers. In addition, forming a semiconductor material filling layer connected to the channel layer inside the channel structure can improve the problem that the GIDL (Gate Induced Drain Leakage) erasure speed of the channel layer becomes slow after using an oxide semiconductor layer containing at least one of indium, gallium, and zinc as the channel layer, improving the overall performance of the semiconductor structure while enhancing the uniformity and stability of the channel layer. Description of the Drawings

[0025] Other features, objects, and advantages of the present application will become more apparent from the following detailed description of non-limiting embodiments when read in conjunction with the accompanying drawings. In the drawings:

[0026] Figure 1 is a cross-sectional view of a semiconductor structure according to an embodiment of the present application;

[0027] Figure 2 is a cross-sectional view of a semiconductor structure according to another embodiment of the present application;

[0028] Figure 3 is Figure 1 an enlarged schematic view of part A in

[0029] Figure 4 is a cross-sectional view of a semiconductor structure according to an embodiment;

[0030] Figure 5A is Figure 3 a schematic view of the structure after being flipped 180°;

[0031] Figure 5B are respectively Figure 5A schematic diagrams of the principles at parts B and C in

[0032] Figure 6 is a schematic diagram of the GIDL erasure principle of a semiconductor structure according to an embodiment of the present application;

[0033] Figure 7 is a flowchart of a manufacturing method of a semiconductor structure according to an embodiment of the present application;

[0034] Figures 8 - 30are respectively process schematic diagrams of a method for manufacturing a semiconductor structure according to an embodiment of the present application; and

[0035] Figure 31 is a schematic diagram of a memory system structure according to an embodiment of the present application.

[0036] Specific manner

[0037] The present application will be described in detail below with reference to the accompanying drawings. The exemplary embodiments mentioned herein are only used to explain the present application and are not used to limit the scope of the present application. Throughout the specification, the same reference numerals refer to the same elements.

[0038] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used to denote approximation rather than degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0039] It should also be understood that the expression "and / or" includes any and all combinations of one or more of the associated listed items. Expressions such as "comprising", "including", "having", "having", and / or "having had" are open-ended rather than closed-ended expressions in this specification, which mean the presence of the stated features, elements, and / or components, but do not exclude the presence or addition of one or more other features, elements, components, and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just an individual element in the list. When describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0040] In addition, when expressions such as "connected", "covered", and / or "formed on..." are used in the present application, it may indicate direct or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. In addition, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0042] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. In addition, unless explicitly defined or contradictory to the context, the specific steps in the methods described in the present application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel. The present application will be described in detail below with reference to the drawings and in combination with the embodiments.

[0043] Figure 1 FIG. 4 is a cross-sectional view of a semiconductor structure 1000 according to an embodiment of the present application. Figure 2 FIG. 6 is a cross-sectional view of a semiconductor structure 1000 according to another embodiment of the present application.

[0044] As Figures 1 - 2 shown, the semiconductor structure 1000 may include: a stacked structure 200 and a channel structure 300. The stacked structure 200 includes a first dielectric layer 210 and a gate layer 220 alternately stacked along a first direction (z direction). The channel structure 300 extends in the stacked structure 200 along the z direction. The channel structure 300 includes a functional layer 320, a channel layer 330 on the surface of the functional layer 320, and a semiconductor material filling layer 340 on the surface of the channel layer 330, wherein the channel layer 330 is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

[0045] Figure 3 is Figure 1 an enlarged schematic view of portion A in Figure 4 FIG. 19 is a cross-sectional view of a semiconductor structure 1 according to an embodiment.

[0046] As Figure 1 and Figure 2 shown, the stacked structure 200 may include a plurality of stacked layers formed by stacking a first dielectric layer 210 and a gate layer 220 along the z direction. Each stacked layer may include a first dielectric layer 210 and a gate layer 220. The gate layer 220 may include any suitable conductive material layer, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The first dielectric layer 210 may include any suitable dielectric material. Exemplary materials for forming the first dielectric layer 210 may include silicon oxide, and the first dielectric layer 210 can be used as an isolation stacked layer. In addition, the number of layers of the stacked structure 200 is not limited to the number shown in the figure and can be set additionally as needed, such as 32 layers, 64 layers, 128 layers, etc.

[0047] In addition, as the demand for the storage capacity of semiconductor structures such as three-dimensional memories continues to increase, the number of the above-mentioned stacked layers is gradually increasing. The stacked structure 200 may include a plurality of sub-stacked structures formed by using, for example, a double-stacked technology or a multi-stacked technology. The plurality of sub-stacked structures may be sequentially stacked in a direction perpendicular to their thickness directions to form the stacked structure 200, wherein each sub-stacked structure may include a plurality of first dielectric layers and gate layers alternately stacked. The number of layers of each sub-stacked structure may be the same or different. The content described below for a single stacked structure may be fully or partially applicable to the stacked structure formed by a plurality of sub-stacked structures, and thus the related or similar content will not be described in detail.

[0048] The channel structure 300 may include a channel hole (not shown) filled with a semiconductor layer and a composite dielectric layer, such as a functional layer 320 and a channel layer 330 sequentially formed on the inner wall of the channel hole, wherein the channel layer 330 can be used to transport the required charges (electrons or holes). Optionally, the functional layer 320 may include a first functional layer 320-1 and a second functional layer 320-2, wherein the first functional layer 320-1 and the second functional layer 320-2 are two different structures respectively.

[0049] As an option, as Figure 1 and Figure 3 shown, the first functional layer 320-1 may include a blocking layer 321, a charge trapping layer 322 located on the surface of the blocking layer 321, and a tunneling layer 333 located on the surface of the charge trapping layer 322. As another option, as Figure 2 shown, the second functional layer 320-2 may include a ferroelectric material layer or an antiferroelectric material layer.

[0050] Specifically, as an option, the channel hole may have a cylindrical or columnar shape penetrating the stacked structure 200 in the z direction. The first functional layer 320-1 may include a blocking layer 321, a charge trapping layer 322, and a tunneling layer 323 sequentially arranged on the inner wall of the channel hole. The blocking layer 321 may include one or more layers, and the one or more layers may include one or more materials. The materials for the blocking layer 321 may include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (K) dielectric materials such as aluminum oxide or hafnium oxide, etc. The charge trapping layer 322 may include one or more layers, and the one or more layers may include one or more materials. The materials for the charge trapping layer 322 may include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, etc. The tunneling layer 323 may include one or more layers, and the one or more layers may include one or more materials. The materials for the tunneling layer 323 may include silicon oxide, silicon nitride, silicon oxynitride, high K dielectric materials such as aluminum oxide or hafnium oxide, etc.

[0051] As another alternative, the second functional layer 320-2 may include a ferroelectric material layer or an antiferroelectric material layer. Taking a semiconductor structure 1000 including a ferroelectric material layer (hereinafter referred to as a ferroelectric memory structure) as an example, data storage is achieved by utilizing the ferroelectric effect of the ferroelectric material layer. The ferroelectric effect means that when an electric field is applied to the ferroelectric memory structure, the central atom of the ferroelectric material layer of the ferroelectric memory structure stops at the low-energy state I position along the electric field. When the externally applied electric field is reversed and applied to the same ferroelectric memory structure, the central atom will move in the crystal along the direction of the electric field and stop at another low-energy state II. Therefore, a large number of central atoms in the ferroelectric material layer move and couple in the crystal unit cell to form ferroelectric domains, and the ferroelectric domains form polarization charges under the action of an electric field. The polarization charges formed by the reversal of the ferroelectric domains under the electric field are higher, and the polarization charges formed by the non-reversal of the ferroelectric domains under the electric field are lower. This binary stable state of the ferroelectric material enables the ferroelectric material to be used as a memory.

[0052] Optionally, the ferroelectric material or the antiferroelectric material may include: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ), or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0053] As Figure 4 shown, in some embodiments, the semiconductor structure 1 includes a substrate 11, a stacked structure 12 located on the substrate 11, and a channel structure 30 extending in the z direction in the stacked structure 12. The channel structure 30 includes a functional layer 32 formed on the inner wall of a channel hole (not shown), a channel layer 33 located on the surface of the functional layer 32, and a filling dielectric layer 35 filling the remaining space of the channel hole. The channel layer 33 may include silicon, such as amorphous silicon, polycrystalline silicon, or single-crystalline silicon. For example, the material of the channel layer 33 includes but is not limited to N-type doped polycrystalline silicon. The filling dielectric layer 35 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, high-K dielectric materials such as aluminum oxide or hafnium oxide, etc.

[0054] Taking a 3D memory as an example, the semiconductor structure may adopt a method of vertically stacking multiple data storage units to implement a stacked 3D storage structure, where the channel layer may be configured to connect the columns or strings of the storage units along the z direction and connect to the bit lines of the semiconductor structure. As Figure 4As shown, the channel layer 33 can generally be formed of a polysilicon material. For example, a doped amorphous silicon is covered on the surface of the functional layer 32, and a laser anneal process is used for crystallization to form a doped polysilicon layer as the channel layer 33. However, the above laser anneal process not only takes a long time but also has a high temperature, so it causes great damage to the material, resulting in defects on the surface of the formed doped polysilicon layer, such as excessive surface roughness and poor grain uniformity. This will lead to a reduction in the electrical performance of the channel layer 33 and an increase in the difference between multiple channel layers 33, thereby affecting the overall performance of the semiconductor structure 1.

[0055] Reference Figure 1 and Figure 2 , according to at least one embodiment of the present application, the channel layer 330 can be an oxide semiconductor layer containing at least one of indium, gallium, and zinc, such as Indium Gallium Zinc Oxide (IGZO), Indium Tungsten Oxide (IWO), Indium Tin Oxide (ITO), indium-zinc oxide (IZO), or a combination thereof, etc. The influence of the crystalline structure on the electron mobility of the oxide semiconductor layer containing at least one of indium, gallium, and zinc is relatively small. In addition, the electron mobility of the oxide semiconductor layer containing at least one of indium, gallium, and zinc is also less affected by temperature. Therefore, the uniformity of the channel layer of the oxide semiconductor layer containing at least one of indium, gallium, and zinc is better, the conductivity is better, and the consistency between multiple channel layers is also higher.

[0056] Taking IGZO as an example, the conduction band of IGZO is mainly composed of the 5s orbitals of indium ions (In 3+ ). The 5s orbitals of In 3+ are spherical, have an isotropic spatial distribution, and have a relatively large principal quantum number, thus resulting in a relatively large conduction band broadening, a relatively small electron effective mass, and a relatively large electron mobility of amorphous IGZO. In addition, although the atomic arrangement of amorphous IGZO has lattice disorder compared with crystalline IGZO, because In 3+The degree of overlap of the 5s orbitals is not affected by lattice disorder. Therefore, whether it is amorphous IGZO or crystalline IGZO, compared with crystalline silicon materials, it has a larger conduction band broadening, a smaller effective electron mass, and a larger electron mobility. Therefore, compared with the doped polysilicon channel layer, the IGZO channel layer has a higher electron mobility, its electron mobility is less affected by temperature, the IGZO channel layer has better uniformity, better conductivity, and higher consistency between multiple IGZO channel layers. Therefore, using an oxide semiconductor layer containing at least one of indium, gallium, and zinc as the channel layer can improve the electrical performance and stability of the semiconductor structure.

[0057] In addition, when the functional layer 320 is the second functional layer 320-2, no natural oxide layer will appear at the interface between the oxide semiconductor layer channel layer containing at least one of indium, gallium, and zinc and the second functional layer 320-2. Therefore, compared with the silicon material channel layer, the oxide semiconductor layer channel layer containing at least one of indium, gallium, and zinc has higher electrical performance and stability.

[0058] Figure 5A Yes Figure 3 Schematic diagram of the structure after being flipped 180°. Figure 5B Respectively Figure 5A Schematic diagrams of the principles at points B and C in Figure 6 It is the GIDL erasure principle diagram of the semiconductor structure 1000 according to an embodiment of the present application.

[0059] In addition, as Figures 1 - 3 , Figures 5A - 5B shown, the channel structure 300 further includes a semiconductor material filling layer 340 on the surface of the channel layer 330. In other words, the semiconductor material filling layer 340 and the functional layer 320 are located on opposite sides of the channel layer 330. Taking the channel layer 330 as an IGZO material layer as an example, IGZO is an N-type semiconductor material with a relatively large electron mobility, but most of its holes 331 are bound, so the hole carriers are insufficient. If IGZO is used as the channel layer 330, due to the insufficient hole carriers, the erasure speed of the semiconductor structure 1000 may be slowed down.

[0060] Specifically, the erasure of the semiconductor structure 1000 may include GIDL erasure. GIDL erasure uses the GIDL effect to generate electron-hole pairs, sweeps the holes 331 into the channel structure 300, tunnels from the channel layer 330 to the charge storage area 322 of the functional layer 320, and recombines with the electrons therein to reduce the voltage of the storage unit and achieve the erasure of the semiconductor structure 1000. The insufficient hole carriers in the IGZO channel layer are not conducive to performing GIDL erasure.

[0061] As Figure 5A ,Figure 5B and Figure 6 As shown in Figure 6 , the semiconductor material filling layer 340 of the semiconductor structure 1000 may include P-type conductive impurities. Taking the material of the channel layer 330 as IGZO as an example, the semiconductor material filling layer 340 may include a nickel oxide (NiO) layer, where IGZO is an N-type semiconductor material and IGZO is a P-type semiconductor material. In the case of GIDL erasure, an erasure voltage (V Erase ) may be applied to the semiconductor material filling layer 340. Since the semiconductor material filling layer 340 contains P-type conductive impurities, it has more hole carriers. These hole carriers flow from the semiconductor material filling layer 340 (NiO) to the channel layer 330 (IGZO). Therefore, the overall number of hole carriers can be increased, the slow GIDL erasure speed of the IGZO channel layer can be improved, and while improving the uniformity and stability of the channel layer, the overall performance of the semiconductor structure is improved.

[0062] In addition, as described above, when the channel layer 330 is a P-type semiconductor material layer or an N-type semiconductor material layer, and the semiconductor material filling layer 340 is an N-type semiconductor material layer or a P-type semiconductor material layer, a PN junction may be formed between the semiconductor material filling layer 340 and the channel layer 330, and this PN junction can reduce the leakage current generated in the semiconductor structure 1000 during the read operation.

[0063] Optionally, as Figure 3 shown, the semiconductor material filling layer 340 may include a first part 340-1 and a second part 340-2 connected to each other. Among them, the first part 340-1 extends along the z direction and is surrounded by the channel layer 330; the second part 340-2 extends along a second direction (for example, the x direction or the y direction) intersecting the z direction and covers a part of the surface of the channel layer 330. For example, the cross-section of the semiconductor material filling layer 340 parallel to the z direction may be a "T" shape. This setting increases the contact area between the semiconductor material filling layer 340 and the semiconductor material connection layer described later, enabling effective connection between the two.

[0064] Referring to Figure 1 , Figure 2 and Figure 5A , Figure 5B , in some embodiments of the present application, in order to reduce the leakage current generated in the semiconductor structure during the read operation, the semiconductor structure 1000 may further include a semiconductor material connection layer 350.

[0065] Specifically, the semiconductor structure 1000 further includes a conductive layer 110. The stacked structure 200 is located on the substrate 100, and the conductive layer 110 is located in the substrate 100. The conductive layer 110 extends along a second direction (e.g., the x direction or the y direction) intersecting with the z direction and can be connected to a plurality of channel layers 330. Optionally, the semiconductor material connection layer 350 is located between the semiconductor material filling layer 340 and the conductive layer 110 along the z direction and is connected to the semiconductor material filling layer 340 and the conductive layer 110. Optionally, the semiconductor material connection layer 350 is in direct contact with the semiconductor material filling layer 340 and in direct contact with the conductive layer 110. In other words, a direct connection is adopted between the semiconductor material connection layer 350 and the semiconductor material filling layer 340 or between the semiconductor material connection layer 350 and the conductive layer 110 to form a connection. In addition, the connection manner between the semiconductor material connection layer 350 and the semiconductor material filling layer 340 or between the semiconductor material connection layer 350 and the conductive layer 110 can also select other indirect connection manners, which are not limited in this application. As an option, the semiconductor material filling layer 340 may contain P-type conductive impurities, and the semiconductor material connection layer 350 may contain N-type conductive impurities; or the semiconductor material filling layer 340 may contain N-type conductive impurities, and the semiconductor material connection layer 350 may contain P-type conductive impurities.

[0066] Taking the example that the semiconductor material filling layer 340 contains P-type conductive impurities, the semiconductor material filling layer 340 is located on the surface of the channel layer 330 and is connected to the channel layer 330. Thus, the channel layer 330 is connected to the conductive layer 110 via the semiconductor material filling layer 340. Refer to Figure 5A and Figure 5B , in some embodiments of the present application, the semiconductor material connection layer 350 contains N-type conductive impurities. Thus, a PN junction is formed between the semiconductor material filling layer 340 and the semiconductor material connection layer 350, and the leakage current situation caused by the reverse voltage can be reduced.

[0067] In addition, as shown in Figure 1 , Figure 2 , Figure 5A and Figure 5B , in some embodiments of the present application, to increase the conductivity of the semiconductor material connection layer and the conductive layer and improve the electrical performance of the semiconductor structure, the semiconductor material connection layer 350 and the conductive layer 110 may contain the same type of conductive impurities. For example, both the semiconductor material connection layer 350 and the conductive layer 110 may contain P-type conductive impurities; or both the semiconductor material connection layer 350 and the conductive layer 110 may contain N-type conductive impurities.

[0068] Optionally, to enhance the above beneficial effects, the impurity doping concentration of the semiconductor material connection layer 350 may be less than the impurity doping concentration of the conductive layer 110, so as to form a concentration gradient of conductive impurities on the path connecting the channel layer 330, thereby improving the electrical performance of the semiconductor structure.

[0069] In addition, if Figure 4 As shown, in some embodiments, the semiconductor structure 1 further includes a channel plug 35, and the channel layer 33 is connected to the channel contact structure 36 via the channel plug 35. In other words, the channel layer 33 includes two opposite ends in the z direction, wherein the first end and the conductive layer 13 can be connected by, for example, direct contact; the second end and the channel plug 35 can be connected by, for example, direct contact, so that the channel layer 33 and the channel contact structure 36 are connected, wherein the channel plug 35 can be made of the same material as the channel layer 33, such as N-type doped polysilicon. In addition, the conductive impurity doping concentration of the channel plug 35 may be different from the conductive impurity doping concentration of the channel layer 33. In this embodiment, the cross-section of the channel layer 33 in a plane parallel to the z direction may be an inverted "冂" shape, wherein the first end thereof has a larger extension dimension in the x direction or the y direction, and the second end thereof has a smaller extension dimension in the x direction or the y direction. Therefore, in order to achieve effective connection and reduce the occurrence of leakage, a channel plug 35 is formed at the second end of the channel layer 33, and the second end and the channel contact structure 36 are connected by the channel plug 35. Compared with the second end, the extension size of the channel plug 35 in the x direction or the y direction is larger, so that the second end of the channel layer 33 and the channel contact structure 36 can be effectively connected. In other words, the channel layer 33 and the channel contact structure 36 are connected by indirect connection.

[0070] like Figures 1 - 3 As shown, in some embodiments of the present application, the formation process of the channel layer 330 includes: forming a plurality of channel holes extending along the z direction from the front side of the intermediate body; forming a functional layer on the sidewall and bottom surface of the channel hole; filling the remaining space of the channel hole with a channel sacrificial layer; after completing the front side process, removing the channel sacrificial layer from the back side opposite to the front side; and forming a channel layer on the surface of the functional layer. Therefore, in this embodiment, the cross-section of the channel layer 330 in a plane parallel to the z direction may be a positive "冂" shape. In other words, the channel layer 330 includes a first end 301 and a second end 302 opposite to each other along the z direction, and a sidewall 303 located between the first end 301 and the second end 302, wherein the semiconductor material filling layer 340 is located on the surface of the sidewall 303 and the surface of the first end 301; the channel contact structure 360 ​​of the semiconductor structure 1000 is connected to the second end 302 by, for example, direct contact.

[0071] Optionally, in a direction (x - direction or y - direction) intersecting with the z - direction, the extension dimension D1 of the second end 302 is greater than the extension dimensions D2+D3 of the first end 301. In other words, in this embodiment, the second end 302 of the channel layer 330 has a relatively large extension dimension compared with Figure 4 the second end of the channel layer 33 shown, and thus it is not necessary to additionally provide a channel plug on the semiconductor structure to achieve an effective connection between the channel layer and the channel contact structure.

[0072] According to the semiconductor structure provided by at least one embodiment of the present application, the semiconductor structure includes a stacked structure and a channel structure extending along the stacking direction in the stacked structure, wherein the channel structure includes a channel layer and a semiconductor material filling layer located on the surface of the channel layer and connected to the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc. Using an oxide semiconductor material containing at least one of indium, gallium, and zinc as the channel layer material can improve the uniformity of the channel layer and the consistency between multiple channel layers. In addition, forming a semiconductor material filling layer connected to the channel layer inside the channel structure can improve the problem that the GIDL erasure speed of the channel layer becomes slow after using an oxide semiconductor layer containing at least one of indium, gallium, and zinc as the channel layer, and while improving the uniformity and stability of the channel layer, the overall performance of the semiconductor structure is improved.

[0073] Figure 7 is a flowchart of a manufacturing method 2000 of a semiconductor structure according to an embodiment of the present application. Figures 8 - 30 are respectively process schematic diagrams of a manufacturing method of a semiconductor structure according to an embodiment of the present application.

[0074] As Figure 7 shown, the manufacturing method 2000 of the semiconductor structure may include:

[0075] S1, forming a stacked structure, where the stacked structure includes a first dielectric layer and a gate layer alternately stacked along a first direction.

[0076] S2, forming a channel structure extending along the first direction in the stacked structure, where the channel structure includes a functional layer, a channel layer located on the surface of the functional layer, and a semiconductor material filling layer located on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

[0077] Next, the specific processes of each step of the above - mentioned manufacturing method 2000 in the first embodiment of the present application will be described in detail; in combination with Figures 8 - 20 the specific processes of each step of the above - mentioned manufacturing method 2000 in the second embodiment of the present application will be described in detail; in combination with Figures 21 - 24 the specific processes of each step of the above - mentioned manufacturing method 2000 in the second embodiment of the present application will be described in detail; in combination with Figures 25 - 27Detail the specific processes of each step of the above preparation method 2000 in the third embodiment of the present application; and in combination with Figures 28 - 30 Detail the specific processes of each step of the above preparation method 2000 in the fourth embodiment of the present application.

[0078] Example 1

[0079] Step S1

[0080] Figure 8 is a schematic cross-sectional view of the structure formed after forming the stacked structure 200 according to an embodiment of the present application.

[0081] As Figure 8 shown, step S1 forms a stacked structure, where the stacked structure includes a first dielectric layer and a gate layer alternately stacked along the first direction. For example, it may include: providing an initial substrate 100'; alternately stacking the first dielectric layer 210 and a gate sacrificial layer (not shown); and removing the gate line sacrificial layer, and forming the gate layer 220 in the void formed after removing the gate line sacrificial layer.

[0082] Specifically, in an embodiment of the present application, the material for preparing the initial substrate 100' can be selected from any suitable semiconductor material, such as single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi), silicon carbide (SiC), silicon on insulator (SOI), germanium on insulator (GOI), or group III-V compounds such as gallium arsenide. Further, the initial substrate 100' can be selected as single crystal silicon.

[0083] In an embodiment of the present application, the initial substrate 100' can be, for example, a composite substrate for supporting the device structure thereon. Multiple layers prepared from different materials can be sequentially provided through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the initial substrate 100'.

[0084] The initial substrate 100' can include a substrate sacrificial layer for subsequently forming a conductive layer connecting the channel layer. The substrate sacrificial layer can include a single layer, multiple layers, or a suitable composite layer. For example, the substrate sacrificial layer can include any one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. As an option, the substrate sacrificial layer can be a high-k dielectric layer. As another option, the substrate sacrificial layer can include a dielectric layer, a sacrificial layer, and a dielectric layer provided in sequence, where the dielectric layer can be a silicon nitride layer and the sacrificial layer can be a silicon oxide layer. As another option, the substrate sacrificial layer can include any one or more of a dielectric material, a semiconductor material, and a conductive material. For example, the sacrificial layer can be single crystal silicon or polycrystalline silicon. Specifically, in an embodiment of the present application, an exemplary material for forming the sacrificial layer can be polycrystalline silicon.

[0085] Portions of the initial substrate 100' may also form well regions doped with N-type or P-type dopants through ion implantation or diffusion processes. The dopants may include any one or a combination of phosphorus (P), arsenic (As), and antimony (Sb). In some embodiments of the present application, the well regions may be prepared with the same dopants or different dopants. Further, the doping concentrations of the well regions may be the same or different, and the present application does not limit this.

[0086] After forming the initial substrate 100', an initial stack structure (not shown) may be formed on the initial substrate 100' through one or more thin film deposition processes. The thin film deposition processes may include, but are not limited to, Physical Vapor Deposition (PVD), such as Molecular Beam Epitaxy (MBE), etc., or Chemical Vapor Deposition (CVD), such as Plasma Enhanced Chemical Vapor Deposition (PECVD), or High Density Plasma (HDP) or Atomic Layer Deposition (ALD), etc.

[0087] The initial stack structure may include multiple pairs of first dielectric layers 210 and gate sacrificial layers stacked alternately with each other. For example, the initial stack structure may include 64 pairs, 128 pairs, or more than 128 pairs of first dielectric layers 210 and gate sacrificial layers.

[0088] In other words, the initial stack structure may include a plurality of initial stacked layers (not shown) formed by stacking the gate first dielectric layer 210 and the gate sacrificial layer along the first direction (z direction). In some embodiments, the first dielectric layer 210 and the gate sacrificial layer may respectively include a first dielectric material and a second dielectric material different from the first dielectric material. Exemplary materials for forming the first dielectric layer 210 and the gate sacrificial layer may include silicon oxide and silicon nitride, respectively. The silicon oxide layer may be used as an isolation stacked layer, while the silicon nitride layer may be used as a sacrificial stacked layer. Subsequently, the sacrificial stacked layer may be etched away and replaced with a conductor layer including a conductive material to form the gate layer of the semiconductor structure.

[0089] The method for preparing a single initial stacked structure has been described above. In fact, as the demand for the storage capacity of semiconductor structures such as three-dimensional memories continues to increase, the number of stacked layers gradually increases. To break through the limitations of process limits, a double stacking technique or a multi-stacking technique can also be used to form an initial stacked structure by successively stacking a plurality of sub-stacked structures in the stacking direction. Among them, each sub-stacked structure may include a plurality of first dielectric layers and gate sacrificial layers alternately stacked. The number of layers of each sub-stacked structure may be the same or different. Since the content and structure involved in the preparation process of the single initial stacked structure described above can fully or partially apply technical effects to the initial stacked structure including a plurality of sub-stacked structures described here, the related or similar content will not be repeated. However, those skilled in the art can understand that subsequent preparation processes can be carried out on the basis of a multi-stacked structure or a single-stacked structure.

[0090] After forming the initial stacked structure, the gate sacrificial layer in the initial stacked structure can be removed by processes such as wet etching to form a void (not shown) for accommodating the gate layer. Specifically, a gate line gap (not shown) extending through the initial stacked structure in the z direction can be formed, and the gate line gap can also extend in a direction intersecting the z direction (for example, the x direction or the y direction). The gate line gap can serve as a passage (process window) for providing etchant and chemical precursors, and the gate sacrificial layer in the initial stacked structure can be removed by using processes such as wet etching, thereby forming a void for accommodating the gate layer.

[0091] After forming the void, a gate layer 220 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The gate layer 220 can include any suitable conductive material layer, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0092] Optionally, in some embodiments of the present application, before forming the gate layer 220, the method 2000 for preparing a semiconductor structure further includes forming a channel hole 310 extending in the z direction in the initial stacked structure. Specifically, the channel hole 310 can be formed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as a patterning process including lithography, cleaning, and chemical mechanical polishing. The channel hole 310 can have a cylindrical or columnar shape extending through the initial stacked structure 200' in the z direction. As an option, the channel hole 310 can extend into the initial substrate 100' in the z direction. After forming the gate layer 220, the initial stacked structure is formed into a stacked structure 200.

[0093] Step S2

[0094] Figure 9 It is a cross-sectional schematic view of the structure formed after forming the initial functional layer 320' according to an embodiment of the present application. Figure 10 It is a cross-sectional schematic view of the structure formed after forming the channel sacrificial layer 330' according to an embodiment of the present application. Figure 11 It is a cross-sectional schematic view of the structure formed after forming the channel contact structure 360 according to an embodiment of the present application. Figure 12 It is a cross-sectional schematic view of the structure formed after forming the functional layer 320 according to an embodiment of the present application. Figure 13 It is a cross-sectional schematic view of the structure formed after forming the backside dielectric layer 120' according to an embodiment of the present application. Figure 14 It is a cross-sectional schematic view of the structure formed after forming the first opening 1 according to an embodiment of the present application. Figure 15 It is a cross-sectional schematic view of the structure formed after forming the initial encapsulation layer 130 according to an embodiment of the present application. Figure 16 It is a cross-sectional schematic view of the structure formed after forming the second opening 2 according to an embodiment of the present application. Figure 17 It is a cross-sectional schematic view of the structure formed after forming the initial second part 340-2' according to an embodiment of the present application. Figure 18 It is a cross-sectional schematic view of the structure formed after forming the second part 340-2 according to an embodiment of the present application.

[0095] As Figures 8 - 18 shown, in step S2, a channel structure extending in the first direction in the stacked structure is formed, where the channel structure includes a functional layer, a channel layer on the surface of the functional layer, and a semiconductor material filling layer on the surface of the channel layer. The channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc. For example, it may include: forming the functional layer 320; forming the channel layer 330 on the surface of the functional layer 320; and forming the semiconductor material filling layer 340 on the surface of the channel layer 330.

[0096] Specifically, as Figures 8 - 12 shown, in some embodiments of the present application, forming the functional layer 320 and forming the channel layer 330 on the surface of the functional layer 320 may include: forming a channel hole 310 extending in the z direction in the stacked structure 200, forming an initial functional layer 320' in the channel hole 310, and filling the remaining space in the channel hole 310 with the channel sacrificial layer 330'; after completing the front-side process, removing a part of the initial functional layer 320' from the backside 202 opposite to the front side 201 to form the functional layer 320; removing the channel sacrificial layer 330' from the backside 202 to expose the surface of the functional layer 320; and forming the channel layer 330 on the exposed surface of the functional layer 320.

[0097] Specifically, asFigure 8 As shown, as an option, before forming the gate layer 220, a channel hole 310 extending in the z direction can be formed in the initial stack structure as described in step S1. After removing the gate sacrificial layer to form the gate layer 220, the initial stack structure is formed into the stack structure 200, and the channel hole 310 extends in the z direction in the stack structure 200. As another option, part of the stack structure 200 can also be removed from the front side 201 of the stack structure 200, for example, by a dry etching process or a combination of dry and wet etching processes; or other manufacturing processes can be performed, such as a patterning process including photolithography, cleaning, and chemical mechanical polishing, etc., to form a channel hole 310 extending in the z direction.

[0098] As Figures 8 - 9 shown, forming the initial functional layer 320' in the channel hole 310 can include, for example: forming the initial functional layer 320' on the sidewalls and bottom surface of the channel hole 310 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, where the initial functional layer 320' includes an initial barrier layer 321' formed on the sidewalls and surface of the channel hole 310, an initial charge trapping layer 322' formed on the surface of the initial barrier layer 321', and an initial tunneling layer 323' formed on the surface of the initial charge trapping layer 322'.

[0099] The initial barrier layer 321' can include one or more layers, and the one or more layers can include one or more materials. The materials for the initial barrier layer 321' can include silicon oxide, silicon nitride, silicon oxynitride, high dielectric constant (K) dielectric materials such as aluminum oxide or hafnium oxide, etc. The initial charge trapping layer 322' can include one or more layers, and the one or more layers can include one or more materials. The materials for the initial charge trapping layer 322' can include polysilicon, silicon nitride, silicon oxynitride, nanocrystalline silicon, etc. The initial tunneling layer 323' can include one or more layers, and the one or more layers can include one or more materials. The materials for the initial tunneling layer 323' can include silicon oxide, silicon nitride, silicon oxynitride, high K dielectric materials such as aluminum oxide or hafnium oxide, etc.

[0100] As Figures 9 - 10As shown, after forming the initial functional layer 320' in the channel hole 310, the remaining space in the channel hole 310 can be filled with a channel sacrificial layer 330'. For example, through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, the remaining space in the channel hole 310 is filled with the channel sacrificial layer 330'. Optionally, the channel sacrificial layer 330' can be formed of a material with a high deposition rate to facilitate rapid filling of the remaining space in the channel hole 310, and the channel sacrificial layer 330' should be any material with a high dry etching selectivity relative to the initial tunneling layer 323' to facilitate removal in subsequent steps. In one embodiment of the present application, the channel sacrificial layer 330' can include an oxide dielectric layer, such as a silicon oxide layer, etc. In addition, the channel sacrificial layer 330' can also be a semiconductor layer, such as a polysilicon layer, etc.

[0101] In addition, after forming the channel sacrificial layer 330', a top isolation layer 372 can be formed on the channel sacrificial layer 330'. The top isolation layer 372 is used to isolate the subsequently formed channel layer from the stacked structure to reduce the leakage of the channel layer. Optionally, the top isolation layer 372 can include a high-K dielectric material layer, etc.

[0102] As Figures 8 - 11 shown, in some embodiments of the present application, the method 2000 for preparing a semiconductor structure can include a front-side process and a back-side process. The front-side process can include forming a channel hole 310; forming an initial functional layer 320'; forming a channel sacrificial layer 330'; forming a channel contact structure 360, and connecting the peripheral circuit chip to the stacked structure 200, etc.; and the back-side process can include subsequent formation of a channel layer, formation of a semiconductor material filling layer, formation of a semiconductor material connection layer, and formation of a conductive layer, etc.

[0103] Specifically, as Figures 10 - 11 shown, after forming the channel sacrificial layer 330', the front-side process can further include: forming a channel contact structure 360 connected to the channel sacrificial layer 330' on the front side 201; and connecting the stacked structure 200 formed with the channel contact structure 360 to the peripheral circuit chip 400.

[0104] Optionally, the channel contact structure 360 may be in direct contact with the channel sacrificial layer 330', so as to facilitate the subsequent formation of a connection between the channel layer formed based on the space where the channel sacrificial layer 330' is located and the channel contact structure 360 in a direct contact manner. Specifically, forming the channel contact structure 360 may include, for example: after forming the channel sacrificial layer 330', forming a second dielectric layer 230 that at least covers the channel sacrificial layer 330' and the initial functional layer 320' through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; through, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the second dielectric layer 230 to form a channel contact hole (not shown) extending in the z direction to the channel sacrificial layer 330'; filling the channel contact hole with a conductive material through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof to form the channel contact structure 360.

[0105] Optionally, the second dielectric layer 230 may include any suitable dielectric material, and exemplary materials for forming the second dielectric layer 230 may include silicon oxide. The channel contact structure 360 may be a composite structure. For example, the channel contact structure 360 may include a channel contact adhesion layer and a channel contact conductive layer surrounded by the channel contact adhesion layer. As an option, the channel contact adhesion layer may include a titanium nitride (TiN) layer, and the channel contact conductive layer may include any suitable conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide.

[0106] After forming the channel contact structure 360, a third dielectric layer that at least covers the channel contact structure 360 may be formed, where the third dielectric layer may be prepared from the same material as the second dielectric layer 230. In this case, there is no obvious boundary between the third dielectric layer and the second dielectric layer 230.

[0107] The peripheral circuit chip 400 may include a peripheral circuit, which can be understood as a circuit for facilitating the operation of multiple memory cells formed in the stacked structure 200. The peripheral circuit may include any suitable digital, analog, and / or mixed-signal circuits for facilitating the operation of multiple memory cells. For example, the peripheral circuit may include one or more of a page buffer, a decoder (e.g., a row decoder and a column decoder), a sensing structure (e.g., a bit line sense amplification structure), a driving structure (e.g., a word line driving structure), an input / output circuit, a charge pump, a voltage source or generator, a current or voltage reference, any part of the above functional circuits (e.g., a sub-circuit), or any active or passive components of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor), which is not limited in this application.

[0108] In some embodiments of the present application, multiple memory cells and the peripheral circuit structure connected to the multiple memory cells may generally be formed on two different chips respectively, such as a memory array chip including the stacked structure 200 and a channel structure (subsequently formed into multiple memory cells), and a peripheral circuit chip 400 including a peripheral circuit. The memory array chip and the peripheral circuit chip 400 may be bonded together through a process such as bonding, and the peripheral circuit and multiple memory cells may be connected together through an interconnect structure such as an interconnect structure.

[0109] It should be noted that the peripheral circuit chip 400 is located on the front side 201 of the stacked structure 200, and a channel layer will be formed on the back side 202 of the stacked structure 200 subsequently.

[0110] Figure 12 To Figure 11 After being flipped 180°, the initial substrate 100' and part of the initial functional layer 320' are removed, and a cross-sectional view is formed after the first part 340-1 of the channel layer 330 and the semiconductor material filling layer are formed. As Figure 11 and Figure 12 shown, in some embodiments of the present application, after the front side process is completed, part of the initial functional layer 320' is removed from the back side 202 opposite to the front side 201 to form the functional layer 320; the channel sacrificial layer 330' is removed from the back side 202 to expose the surface of the functional layer 320; and the channel layer 330 is formed on the exposed surface of the functional layer 320.

[0111] Specifically, the initial substrate 100' may be removed from the back side 202 through, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes may also be performed, such as a patterning process including lithography, cleaning, and chemical mechanical polishing.

[0112] Thereafter, it is possible to continue, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove a part of the initial functional layer 320'. The removed part of the initial functional layer 320' may include the part of the initial functional layer 320' located in the initial substrate 100'; or the part of the initial functional layer 320' located at the bottom surface of the channel hole 310 (as Figure 8 shown). After removing a part of the initial functional layer 320', the remaining part of the initial functional layer 320' can be formed into a functional layer 320, where the functional layer 320 may include a barrier layer 321, a charge trapping layer 322 located on the surface of the barrier layer 321, and a tunneling layer 333 located on the surface of the charge trapping layer 322. In other words, the functional layer 320 formed in Embodiment 1 is Figure 1 the first functional layer 320-1 shown.

[0113] After forming the functional layer 320, it is possible to continue, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove the channel sacrificial layer 330', exposing the surface of the functional layer 320.

[0114] A channel layer 330 is formed on the exposed surface of the functional layer 320 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, where the channel layer 330 is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

[0115] As Figures 11 - 18 shown, in some embodiments of the present application, after forming the channel layer 330, a semiconductor material filling layer 340 connected to the channel layer 330 can be formed. In some embodiments of the present application, the semiconductor material filling layer 340 can be formed step by step. For example, the semiconductor material filling layer 340 may include two parts, a first part 340-1 extending along the z direction and surrounded by the channel layer 330, and a second part 340-2 extending in a second direction (x direction or y direction) intersecting the z direction and covering a part of the surface of the channel layer 330. In this embodiment, the first part 340-1 of the semiconductor material filling layer 340 can be formed first, and then the second part 340-2 of the semiconductor material filling layer 340 can be formed.

[0116] Specifically, as Figures 11 - 12 shown, after forming the channel layer 330, it is possible to continue by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, in the channel hole 310 (as Figure 8A first part 340-1 is formed in the remaining space (as shown). The first part 340-1 extends in the z direction and is surrounded by the channel layer 330. Optionally, the first part 340-1 contains P-type conductive impurities. For example, the first part 340-1 includes a NiO layer.

[0117] After forming the first part 340-1, a planarization process may also be performed on the functional layer 320, the channel layer 330, and the surfaces of the first part 340-1 exposed on the back side 202. For example, a planarization process such as a chemical mechanical polishing process (Buffer CMP) with a relatively low polishing rate may be performed on the above surfaces. Through the planarization process, it is possible to more easily make the above surfaces form a flat coplanar surface, which is beneficial to forming a good connection between the second part of the semiconductor material filling layer formed in the subsequent steps and the first part 340-1 and the channel layer 330.

[0118] As Figures 12 - 18 shown, in some embodiments of the present application, forming the second part of the semiconductor material filling layer includes: forming a sealing layer 130, where the sealing layer 130 covers the surface of the functional layer 320 on the back side 202 and exposes the surfaces of the channel layer 330 and the first part 340-1 on the back side 202; and forming a second part 340-2 on the exposed surfaces of the channel layer 330 and the first part 340-1.

[0119] Specifically, as Figures 12 - 13 shown, a backside isolation layer 120' may be formed on the back side 202 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, where the backside isolation layer 120' covers at least the functional layer 320, the channel layer 330, and the first part 340-1.

[0120] In addition, a backside dielectric layer 110' may continue to be formed on the surface of the backside isolation layer 120' through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0121] Optionally, the backside isolation layer 120' may include any suitable conductive material layer, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicide. The backside dielectric layer 110' may include any suitable dielectric material. As an option, the backside isolation layer 120' may be prepared with the same material as the gate 220, and the backside dielectric layer 110' may be prepared with the same material as the first dielectric layer 210. After subsequent processing, the remaining backside isolation layer 120'-1 and the remaining backside dielectric layer 110'-1 may be used as the bottom select gate structure of the finally formed semiconductor structure.

[0122] AsFigures 13 - 14 As shown, part of the backside dielectric layer 120' can be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to form the first opening 22. The first opening 22 can expose partial surfaces of the functional layer 320, the channel layer 330, and the first part 340-1.

[0123] As Figures 13 - 15 shown, an initial capping layer 130 can be formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial capping layer 130 covers the remaining backside isolation layer 120' and the exposed partial surfaces of the functional layer 320, the channel layer 330, and the first part 340-1. The initial capping layer 130 can include any suitable dielectric material, such as silicon oxide.

[0124] As Figures 15 - 16 shown, part of the initial capping layer 130 can be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to form the second opening 23. The second opening 23 can expose the channel layer 330 and the partial surface of the first part 340-1. In other words, after removing part of the initial capping layer 130, the remaining initial capping layer 130 is formed as the capping layer 130, and the capping layer 130 covers the surface of the functional layer 320 so that the second part of the subsequently formed semiconductor material filling layer is not connected to the functional layer 320.

[0125] As Figures 16 - 18 shown, forming the second part 340-2 on the exposed surfaces of the channel layer 330 and the first part 340-1 can, for example, include: forming an initial second part 340-2' by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. The initial second part 340-2' at least covers the surface of the remaining backside dielectric layer 110'-1, the exposed surface of the channel layer 330, and the exposed surface of the first part 340-1. Then, part of the initial second part 340-2' can be removed, for example, by a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including photolithography, cleaning, and chemical mechanical polishing, etc., to form the second part 340-2.

[0126] Optionally, the second part 340-2 and the first part 340-1 may be made of the same material. In this case, there is no obvious boundary between the second part 340-2 and the first part 340-1. The second part 340-2 and the first part 340-1 are formed into a semiconductor material filling layer 340.

[0127] In addition, as Figures 18 - 20 shown, the method 2000 for preparing a semiconductor structure further includes forming a semiconductor material connection layer 350 and a conductive layer 110.

[0128] Specifically, as Figures 18 - 19 shown, in some embodiments of the present application, a semiconductor material connection layer 350 is formed on the exposed surface of the second part 340 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the semiconductor material filling layer 340 may contain P-type conductive impurities, and the semiconductor material connection layer 350 may contain N-type conductive impurities.

[0129] As Figures 19 - 20 shown, in some embodiments of the present application, a conductive layer 110 is formed on the semiconductor material connection layer 350 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. Optionally, the conductive layer 110 extends in a second direction (e.g., the x direction or the y direction) intersecting the z direction. In addition, the semiconductor material connection layer 350 and the conductive layer 110 may contain the same type of conductive impurities. For example, both the semiconductor material connection layer 350 and the conductive layer 110 may contain P-type conductive impurities; or both the semiconductor material connection layer 350 and the conductive layer 110 may contain N-type conductive impurities. Additionally, the impurity doping concentration of the conductive layer 110 may be greater than that of the semiconductor material connection layer 350.

[0130] The following will describe in detail the specific processes of each step of the above preparation method 2000 in Example 2 in conjunction with Figures 21 - 24 The above preparation method 2000 will be described in detail in Example 2.

[0131] Example 2

[0132] Since the content involved in the method 2000 for preparing a semiconductor structure described in the above Example 1 can be fully or partially applied to the method for preparing a semiconductor structure described here (Example 2), the related or similar content will not be repeated. However, those skilled in the art can understand that a semiconductor device 1000 can be formed according to the method 2000 for preparing a semiconductor structure described in Example 1 (as Figure 1As shown, the semiconductor device 1000 may also be formed according to the manufacturing method 2000 of the semiconductor device described in Embodiment 2 (as Figure 1 shown). Based on this, the manufacturing methods 2000 of the semiconductor devices described in Embodiments 1 and 2 both have the same beneficial effects as the semiconductor structure 1000, which will not be elaborated here.

[0133] Step S2

[0134] Figure 21 is a schematic cross-sectional view of the structure formed after forming a part 340-3' of the semiconductor material filling layer according to an embodiment of the present application. Figure 22 is a schematic cross-sectional view of the structure formed after forming the channel layer 330 according to an embodiment of the present application. Figure 23 is a schematic cross-sectional view of the structure formed after forming the initial filling layer 340-4' according to an embodiment of the present application. Figure 24 is a schematic cross-sectional view of the structure formed after forming the initial semiconductor material connection layer 350' according to an embodiment of the present application.

[0135] As Figures 21 - 24 shown, in some embodiments of the present application, the semiconductor material filling layer 340 may be formed step by step. For example, the semiconductor material filling layer 340 may include two parts, one part 340-3' of which may be formed in the remaining space of the channel hole 310 (as Figure 8 shown), and the other part 340-4' may be formed by removing part of the initial filling layer 340-4'.

[0136] Specifically, in combination with Figure 8 , Figure 11 and Figures 21 - 24 forming the channel structure includes: filling the remaining space of the channel hole 310 from the back side 202 to form a part 340-3' of the semiconductor material filling layer; and forming another part of the semiconductor material filling layer 340 on the exposed surface of the part 340-3' of the semiconductor material filling layer and the exposed surface of the channel layer 330.

[0137] In some embodiments, as Figures 21 - 24 shown, forming another part of the semiconductor material filling layer 340 may include: removing part of the channel layer 330", exposing the surface of a part 340-3' of the semiconductor material filling layer; forming the initial filling layer 340-4', where the initial filling layer 340-4' at least fills the void 24 formed after removing part of the channel layer 330"; and removing part of the initial filling layer 340-4' to form another part of the conductor material filling layer 340.

[0138] It should be noted that the functional layer 320 formed in Embodiment 2 isFigure 1 The first functional layer 320-1 shown.

[0139] As Figures 21 - 22 shown, part of the channel layer 330” can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc. After removing part of the channel layer 330”, the remaining channel layer 330 and a part 340-3’ of the semiconductor material filling layer are at different heights in the z direction. After removing part of the channel layer 330”, a void 24 is formed between the remaining channel layer 330 and a part 340-3’ of the semiconductor material filling layer.

[0140] Optionally, the extension depth of the void 24 in the z direction can be equal to the thicknesses of the subsequently formed second part 340-2 and the semiconductor material connection layer 350 in the z direction. After this step, a part 340-3’ of the semiconductor material filling layer is exposed on the surface of the back side 202 and on the surfaces in the directions (x direction or y direction) intersecting with the z direction.

[0141] As Figures 22 - 23 shown, an initial filling layer 340-4’ is formed by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, where the initial filling layer 340-4’ at least fills the void 24. The initial filling layer 340-4’ is in direct contact with the remaining channel layer 330 and a part 340-3’ of the semiconductor material filling layer.

[0142] As Figures 23 - 24 shown, part of the initial filling layer 340-4’ can be removed by, for example, a dry etching process or a combination of dry and wet etching processes; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to form the semiconductor material filling layer 340. It should be noted that a part 340-3’ and the initial filling layer 340-4’ can be prepared from the same material, in which case there is no obvious boundary between them. In addition, in the process of removing part of the initial filling layer 340-4’, the part of the part 340-3’ connected to the initial filling layer 340-4’ is also removed.

[0143] The semiconductor material filling layer 340 may include two parts, a first part 340-1 extending along the z direction and surrounded by the channel layer 330, and a second part 340-2 extending in a second direction (x direction or y direction) intersecting the z direction and covering a partial surface of the remaining channel layer 330. The second part 340-2 and the first part 340-1 may be prepared from the same material, and in this case, there is no obvious demarcation between the second part 340-2 and the first part 340-1. In this embodiment, the first part 340-1 of the semiconductor material filling layer 340 and a part of the second part 340-2 may be formed first, and then another part of the second part 340-2 of the semiconductor material filling layer 340 may be formed.

[0144] The following will combine Figures 25 - 27 to detail the specific processes of each step of the above preparation method 2000 in Embodiment 3.

[0145] Example 3

[0146] Since the content involved in the preparation method 2000 of the semiconductor structure described in Embodiment 1 above may be fully or partially applicable to the preparation method of the semiconductor structure described herein (Embodiment 3), the related or similar content will not be elaborated again. In addition, the preparation method 2000 of the semiconductor device described in Embodiment 3 has the same beneficial effects as the semiconductor structure 1000 (as Figure 2 shown), which will not be elaborated here.

[0147] Step S2

[0148] Figure 25 is a schematic cross-sectional view of the structure formed after forming the channel layer 330 according to an embodiment of the present application. Figure 26 is a schematic cross-sectional view of the structure formed after forming the semiconductor material filling layer 340 and the semiconductor material connection layer 350 according to an embodiment of the present application. Figure 27 is a schematic cross-sectional view of the structure formed after forming the conductive layer 110 according to an embodiment of the present application.

[0149] As Figure 8 and Figure 25 shown, forming a channel structure extending in the first direction in the stacked structure may include: forming a functional layer 320; forming a channel layer 330 on the surface of the functional layer 320; and forming a semiconductor material filling layer 340 on the surface of the channel layer 330. It should be noted that the functional layer 320 formed in Embodiment 3 is the Figure 2 shown second functional layer 320-2.

[0150] Specifically, the second functional layer 320-2 may include a ferroelectric material layer or an antiferroelectric material layer. Optionally, the ferroelectric material or the antiferroelectric material may include: hafnium dioxide (HfO2), silicon-doped hafnium dioxide (Si a (HfO2) b ), aluminum-doped hafnium dioxide (Al a (HfO2) b ), zirconium-doped hafnium dioxide (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0151] The second functional layer 320-2 can be formed on the sidewalls and bottom surface of the channel hole 310 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof.

[0152] As an option, after forming the channel layer 330, the first part 340-1 can be continuously formed in the remaining space of the channel hole 310 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof. The first part 340-1 extends in the z direction and is surrounded by the channel layer 330. Optionally, the first part 340-1 contains a P-type conductive impurity. For example, the first part 340-1 includes a NiO layer.

[0153] Optionally, a backside isolation layer 120' is formed on the backside 202 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or any combination thereof, and a backside dielectric layer 110' is formed on the surface of the backside isolation layer 120'.

[0154] As Figures 25 - 26 shown, after closing the second functional layer 320-2, the second part 340-2 can be formed on the exposed surfaces of the channel layer 330 and the first part 340-1. Optionally, the second part 340-2 and the first part 340-1 can be prepared from the same material. In this case, there is no obvious boundary between the second part 340-2 and the first part 340-1. The second part 340-2 and the first part 340-1 are formed into a semiconductor material filling layer 340.

[0155] In addition, as Figures 26 - 27As shown, in some embodiments of the present application, a semiconductor material connection layer 350 is formed on the exposed surface of the second part 340 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and a conductive layer 110 is formed on the semiconductor material connection layer 350. Optionally, the conductive layer 110 extends in a second direction (e.g., the x - direction or the y - direction) intersecting the z - direction. In addition, the semiconductor material connection layer 350 and the conductive layer 110 may contain the same type of conductive impurities.

[0156] The following will combine Figures 28 - 30 to detail the specific processes of each step of the above - mentioned preparation method 2000 in Example 4.

[0157] Example 4

[0158] Since the content involved in the preparation method 2000 of the semiconductor structure described in Example 2 above can be fully or partially applied to the preparation method of the semiconductor structure described here (Example 4), the related or similar content will not be repeated. In addition, the preparation method 2000 of the semiconductor device described in Example 4 has the same beneficial effects as the semiconductor structure 1000 (as Figure 2 shown), which will not be elaborated here.

[0159] Step S2

[0160] Figure 28 is a schematic cross - sectional view of the structure formed after forming a part 340 - 3' of the semiconductor material filling layer according to an embodiment of the present application. Figure 29 is a schematic cross - sectional view of the structure formed after forming the semiconductor material connection layer 350 according to an embodiment of the present application. Figure 27 is a schematic cross - sectional view of the structure formed after forming the conductive layer 110 according to an embodiment of the present application.

[0161] As Figure 8 and Figure 28 shown, forming a channel structure extending in the first direction in the stacked structure may include: forming a functional layer 320; forming a channel layer 330 on the surface of the functional layer 320; and forming a semiconductor material filling layer 340 on the surface of the channel layer 330. It should be noted that the functional layer 320 formed in Example 4 is Figure 2 the second functional layer 320 - 2 shown.

[0162] Specifically, the second functional layer 320 - 2 may include a ferroelectric material layer or an antiferroelectric material layer. Optionally, the ferroelectric material or the antiferroelectric material may include: hafnium dioxide (HfO2), silicon - doped hafnium dioxide (Si a(HfO2) b ) hafnium dioxide doped with aluminum (Al a (HfO2) b ) hafnium dioxide doped with zirconium (Zr a (HfO2) b ) or zirconium oxide (ZrO), etc., where a and b are positive numbers.

[0163] Through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, a second functional layer 320-2 can be formed on the sidewalls and bottom surface of the channel hole 310.

[0164] It should be noted that after the channel layer is formed on the surface of the functional layer 320, for example, a dry etching process or a combination of dry and wet etching processes can be used; other manufacturing processes can also be performed, such as patterning processes including lithography, cleaning, and chemical mechanical polishing, etc., to remove part of the channel layer, and the remaining channel layer is formed into the channel layer 330 of the final semiconductor structure.

[0165] As Figures 28 - 29 shown, in some embodiments of the present application, the semiconductor material filling layer 340 can be formed step by step. First, a part 340-3' of the semiconductor material filling layer 340 is formed, and then another part of the conductor material filling layer 340 is formed. For example, filling the remaining space of the channel hole 310 (as Figure 8 shown) from the back side 202 to form a part 340-3' of the semiconductor material filling layer; and forming another part of the semiconductor material filling layer 340 on the exposed surface of a part 340-3' of the semiconductor material filling layer and the exposed surface of the channel layer 330.

[0166] In some embodiments, forming another part of the semiconductor material filling layer 340 may include: removing part of the channel layer, where the remaining channel layer is formed into the channel layer 330 and the surface of a part 340-3' of the semiconductor material filling layer is exposed; forming an initial filling layer (not shown), where the initial filling layer at least fills the void 24 formed after removing part of the channel layer; and removing part of the initial filling layer to form another part of the conductor material filling layer 340.

[0167] The semiconductor material filling layer 340 may include two parts, a first part 340-1 extending along the z direction and surrounded by the channel layer 330, and a second part 340-2 extending in a second direction (x direction or y direction) intersecting the z direction and covering a partial surface of the remaining channel layer 330. The second part 340-2 and the first part 340-1 may be prepared from the same material, and in this case, there is no obvious boundary between the second part 340-2 and the first part 340-1. In this embodiment, the first part 340-1 of the semiconductor material filling layer 340 and a part of the second part 340-2 may be formed first, and then another part of the second part 340-2 of the semiconductor material filling layer 340 may be formed.

[0168] In addition, in some embodiments of the present application, a semiconductor material connection layer 350 may be formed on the exposed surface of the second part 340 through a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, and a conductive layer 110 may be formed on the semiconductor material connection layer 350. Optionally, the conductive layer 110 extends in a second direction (e.g., x direction or y direction) intersecting the z direction. In addition, the semiconductor material connection layer 350 and the conductive layer 110 may contain the same type of conductive impurities.

[0169] Figure 31 It is a schematic structural diagram of a memory system 30000 according to an embodiment of the present application.

[0170] As Figure 31 shown, at least one embodiment of another aspect of the present application further provides a storage system 30000. The storage system 30000 may include a semiconductor structure 20000 and a controller 32000. The semiconductor structure 20000 may be the same as the semiconductor device described in any of the above embodiments, and the present application will not elaborate on this. The semiconductor structure 20000 may be a two-dimensional semiconductor device or a three-dimensional semiconductor device, or even a part of a two-dimensional semiconductor device or a part of a three-dimensional semiconductor device. Hereinafter, a three-dimensional semiconductor device will be taken as an example for illustration.

[0171] As an option, the three-dimensional semiconductor device may include at least one of a three-dimensional NAND memory and a three-dimensional NOR memory.

[0172] The storage system 30000 may include a semiconductor structure 20000 and a controller 32000. The semiconductor structure 20000 may be the same as the semiconductor device described in any of the above embodiments, and details thereof will not be elaborated in this application. The controller 32000 may control the semiconductor structure 20000 through a channel CH, and the semiconductor structure 20000 may perform operations based on the control of the controller 32000 in response to requests from a host 31000. The semiconductor structure 20000 may receive a command CMD and an address ADDR from the controller 32000 through the channel CH and access a region selected from a memory cell array in response to the address. In other words, the semiconductor structure 20000 may perform an internal operation corresponding to the command on the region selected by the address.

[0173] In some embodiments, the three-dimensional storage system may be implemented as a storage device in the form of, for example, a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a multimedia card such as MMC, eMMC, RS-MMC, and micro MMC, a Secure Digital card such as SD, mini SD, and micro SD, a storage device of the Personal Computer Memory Card International Association (PCMCIA) card type, a storage device of the Peripheral Component Interconnect (PCI) type, a high-speed PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media card, or a Memory Stick. The storage system provided in this application has the same beneficial effects as the semiconductor device due to the provision of the semiconductor device provided in this application, and details thereof will not be elaborated here.

[0174] Although exemplary preparation methods and structures of the semiconductor device are described herein, it can be understood that one or more features may be omitted, substituted, or added to the structure of the semiconductor device. In addition, the materials of the exemplified layers are merely exemplary.

[0175] The above description is only a preferred embodiment of the present application and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solutions formed by the selected combination of the above technical features, but also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, a technical solution formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Claims

1. A semiconductor structure, characterized in that, Comprising: A stacked structure including a first dielectric layer and a gate layer alternately stacked along a first direction; And A channel structure extending in the stacked structure along the first direction, wherein the channel structure includes a functional layer, a channel layer on the surface of the functional layer, and a semiconductor material filling layer on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

2. The semiconductor structure according to claim 1, wherein The channel layer includes at least one of indium gallium zinc oxide, indium tungsten oxide, indium tin oxide, and indium zinc oxide.

3. The semiconductor structure according to claim 1, wherein The semiconductor material filling layer includes a first part and a second part connected to each other, wherein the first part extends along the first direction and is surrounded by the channel layer; and The second part extends along a second direction intersecting the first direction and covers a partial surface of the channel layer.

4. The semiconductor structure according to claim 1, wherein The semiconductor material filling layer contains P-type conductive impurities.

5. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes a conductive layer and a semiconductor material connection layer, wherein the conductive layer extends along a second direction intersecting the first direction; and The semiconductor material connection layer is located between the semiconductor material filling layer and the conductive layer along the first direction and is connected to the semiconductor material filling layer and the conductive layer.

6. The semiconductor structure according to claim 5, wherein The semiconductor material filling layer contains P-type conductive impurities; and The semiconductor material connection layer contains N-type conductive impurities.

7. The semiconductor structure according to claim 5, wherein The semiconductor material connection layer and the conductive layer contain the same type of conductive impurities.

8. The semiconductor structure according to claim 7, wherein The impurity doping concentration of the semiconductor material connection layer is less than that of the conductive layer.

9. The semiconductor structure according to claim 5, wherein The channel layer includes a first end and a second end opposite to each other along the first direction, and sidewalls between the first end and the second end, wherein the semiconductor material filling layer is located on the surface of the sidewalls and the surface of the first end; and The semiconductor structure further includes a channel contact structure connected to the second end.

10. The semiconductor structure according to claim 9, wherein In a direction intersecting the first direction, the extension dimension of the second end is greater than that of the first end.

11. The semiconductor structure according to any one of claims 1-10, wherein The functional layer includes a blocking layer, a charge trapping layer on the surface of the blocking layer, and a tunneling layer on the surface of the charge trapping layer.

12. The semiconductor structure according to any one of claims 1-10, wherein The functional layer includes a ferroelectric material layer or an antiferroelectric material layer.

13. A method for preparing a semiconductor structure, characterized in that, Comprising: Forming a stacked structure, wherein the stacked structure includes a first dielectric layer and a gate layer alternately stacked along a first direction; And Form a channel structure extending in the laminated structure along the first direction. Wherein, the channel structure includes a functional layer, a channel layer located on the surface of the functional layer, and a semiconductor material filling layer located on the surface of the channel layer, and the channel layer is an oxide semiconductor layer containing at least one of indium, gallium, and zinc.

14. The method according to claim 13, wherein Forming a channel structure extending in the laminated structure along the first direction includes: Forming a channel hole extending in the laminated structure along the first direction, forming an initial functional layer in the channel hole, and filling a channel sacrificial layer in the remaining space of the channel hole; After completing the front-side process, removing a part of the initial functional layer from the back side opposite to the front side to form the functional layer; Removing the channel sacrificial layer from the back side to expose the surface of the functional layer; and Forming the channel layer on the exposed surface of the functional layer.

15. The method according to claim 14, wherein, The front-side process includes: Forming a channel contact structure connected to the channel sacrificial layer on the front side; and Connecting the laminated structure formed with the channel contact structure to a peripheral circuit chip.

16. The method according to claim 14, wherein Forming a channel structure extending in the laminated structure along the first direction further includes: Filling the remaining space of the channel hole from the back side to form a part of the semiconductor material filling layer; and Forming another part of the semiconductor material filling layer on the exposed surface of a part of the semiconductor material filling layer and the exposed surface of the channel layer.

17. The method according to claim 16, wherein The method further includes: Forming a semiconductor material connection layer connected to the semiconductor material filling layer, Wherein, the semiconductor material filling layer contains a P-type conductive impurity; and The semiconductor material connection layer contains an N-type conductive impurity.

18. The method according to claim 16, wherein Forming another part of the semiconductor material filling layer includes: Forming a sealing layer, wherein the sealing layer covers the surface of the functional layer on the back side and exposes a part of the surface of the channel layer and the semiconductor material filling layer on the back side; and Forming another part of the semiconductor material filling layer on the exposed surface of a part of the semiconductor material filling layer and the surface of the channel layer.

19. The method according to claim 16, wherein, Forming another part of the semiconductor material filling layer includes: Removing a part of the channel layer to expose the surface of a part of the semiconductor material filling layer; Forming an initial filling layer, wherein the initial filling layer at least fills the void formed after removing a part of the channel layer; and Removing a part of the initial filling layer to form another part of the semiconductor material filling layer.

20. A memory system, characterized in that, Includes: At least one semiconductor structure as described in any one of claims 1-12; And A controller, coupled to the semiconductor structure and used to control the semiconductor structure to store data.

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