Ferroelectric capacitor and preparation method thereof, memory array, memory and electronic equipment

Abstract

The embodiment of the invention provides a ferroelectric capacitor and a preparation method thereof, a storage array, a memory and electronic equipment, relates to the technical field of semiconductors, and is used for reducing M phases in a ferroelectric layer in the ferroelectric capacitor and improving the reliability of the ferroelectric capacitor. The ferroelectric capacitor includes a first electrode, a second electrode, and a ferroelectric layer between the first electrode and the second electrode. Wherein the first electrode is a polycrystal, the first electrode comprises a first columnar crystal grain, a first included angle exists between the extension direction of the first columnar crystal grain and the first reference plane, and the first included angle is larger than 0 degree or equal to 90 degrees. The ratio of the number of the first columnar crystal grains to the number of all crystal grains in the first electrode is greater than or equal to 50%. The first reference plane is parallel to a portion of the surface of the ferroelectric layer opposite the first columnar grains. A ferroelectric capacitor is applied to an electronic device to improve the performance of the electronic device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a ferroelectric capacitor, a preparation method thereof, a storage array, a memory and an electronic device. Background Art

[0002] At present, ferroelectric random access memory (Ferroelectric Random Access Memory, abbreviated as FeRAM in English and ferroelectric memory in Chinese) has been widely used due to its characteristics such as non-volatility of stored data and fast access rate.

[0003] Generally, a ferroelectric memory includes a plurality of ferroelectric capacitors. A ferroelectric capacitor includes two relatively arranged electrodes and a ferroelectric layer located between the two electrodes. Under the action of the two electrodes, the ferroelectric layer undergoes a high-temperature crystallization process to form a polycrystalline thin film mixed with orthorhombic (O phase), tetragonal (T phase) and monoclinic (M phase). Among them, the O phase and T phase enable the ferroelectric layer to have ferroelectric properties, and the M phase enables the ferroelectric layer to exhibit dielectric properties. The oxygen ions in the O phase can deviate from the equilibrium point under the drive of voltage, generating two polarization states in opposite directions, so as to store 0 / 1 information. If there is more M phase in the ferroelectric layer, the ferroelectric layer is prone to problems such as fatigue and breakdown, which seriously affect the reliability of the ferroelectric memory. Summary of the Invention

[0004] Embodiments of this application provide a ferroelectric capacitor, a preparation method thereof, a storage array, a memory and an electronic device, which are used to reduce the M phase in the ferroelectric layer of the ferroelectric capacitor and improve the reliability of the ferroelectric capacitor.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a ferroelectric capacitor is provided. The ferroelectric capacitor includes a first electrode, a second electrode and a ferroelectric layer. The ferroelectric layer is located between the first electrode and the second electrode. Among them, the first electrode is a polycrystal, the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane. The first included angle is greater than 0 degree and less than or equal to 90 degrees, and the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to 50%. The first reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the first columnar grains.

[0007] Such a setting can make the first electrode have a preferred orientation that hardly exhibits the (200) crystal orientation, so that less M phase and more O phase can be generated in the ferroelectric layer. With less M phase and more O phase in the ferroelectric layer, on the one hand, the coercive electric field of the ferroelectric capacitor can be reduced, and the operating voltage of the ferroelectric capacitor can be lowered. As a result, when the storage unit using the ferroelectric capacitor provided by the embodiment of the present application performs read and write operations, the operating voltage can be smaller and the power consumption can be lower. On the other hand, the fatigue period of the ferroelectric capacitor can be delayed, and the leakage current of the ferroelectric capacitor can be reduced, thereby increasing the storage times of the ferroelectric capacitor, ensuring the storage window of the ferroelectric capacitor after multiple storages, improving the reliability of the ferroelectric capacitor, and further ensuring the accuracy of the read and write operations of the storage unit using the ferroelectric capacitor provided by the embodiment of the present application, and improving the performance of the memory.

[0008] At the same time, with less M phase and more O phase in the ferroelectric layer, the film layer bearing capacity of the ferroelectric layer can be better, and the structure of the ferroelectric capacitor can be more stable, so as to ensure the storage capacity of the ferroelectric capacitor, improve the reliability of the ferroelectric capacitor, reduce the storage window loss rate of the storage array (memory) using the ferroelectric capacitor, ensure the accuracy of the read and write operations of the storage array, and reduce the misreading rate.

[0009] In some embodiments, the ferroelectric capacitor further includes a third electrode, and the third electrode is located on the side of the first electrode away from the ferroelectric layer; the third electrode is an amorphous or polycrystal with a randomly distributed crystallization orientation.

[0010] In this way, the first electrode and the third electrode are located on the same side of the ferroelectric layer, and the first electrode and the third electrode can jointly provide clamping stress for the ferroelectric layer, and the thickness of the first electrode can be smaller. In the process of manufacturing the ferroelectric capacitor, in order to make the first electrode a polycrystal, and the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and the first reference plane, and the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to 50%, when manufacturing the first electrode, the process conditions need to be adjusted, such as adjusting the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the first electrode can make the preparation time of the first electrode shorter, which is beneficial to reducing the manufacturing difficulty and the process complexity of the ferroelectric capacitor, and improving the manufacturing efficiency of the ferroelectric capacitor.

[0011] In some embodiments, the ferroelectric capacitor further includes a first buffer layer, and the first buffer layer is located between the first electrode and the ferroelectric layer and is in contact with the ferroelectric layer.

[0012] By such an arrangement, on the one hand, a first buffer layer is provided between the first electrode and the ferroelectric layer, which can also adjust the stress between the first electrode and the ferroelectric layer and improve the structural stability of the ferroelectric capacitor. On the other hand, providing the first buffer layer can also inhibit the diffusion of metal particles in the first electrode into the ferroelectric layer and inhibit the diffusion of oxygen atoms in the ferroelectric layer into the first electrode, reduce the oxygen vacancies formed due to the movement of oxygen ions in the ferroelectric layer, weaken the oxidation effect between the electrode and oxygen ions, avoid the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor, preventing the ferroelectric capacitor from being broken down, and increasing the service life of the ferroelectric capacitor. At the same time, with fewer oxygen vacancies in the ferroelectric layer, the polarization fatigue and imprint effect caused by oxygen vacancies can also be improved, and the accuracy of reading and writing data of the storage unit using the ferroelectric capacitor can be increased.

[0013] In some embodiments, the second electrode is polycrystalline, the second electrode includes second columnar grains, and there is a second included angle between the extending direction of the second columnar grains and a second reference plane, the second included angle is greater than 0 degree and less than or equal to 90 degrees. The ratio of the number of the second columnar grains to the number of all grains in the second electrode is greater than or equal to fifty percent, and the second reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the second columnar grains. In this way, the second electrode also has a preferred orientation with almost no (200) crystal orientation, so that less M phase can be generated in the ferroelectric layer and more O phase can be generated.

[0014] In some embodiments, the ferroelectric capacitor further includes a fourth electrode, and the fourth electrode is located on the side of the second electrode away from the ferroelectric layer; the fourth electrode is amorphous or polycrystalline with randomly distributed crystallization orientations.

[0015] In this way, the second electrode and the fourth electrode are located on the same side of the ferroelectric layer, and the second electrode and the fourth electrode can jointly provide a clamping stress for the ferroelectric layer, and the thickness of the second electrode can be smaller. In the process of manufacturing the ferroelectric capacitor, in order to make the second electrode include second columnar grains, there is a second included angle between the extending direction of the second columnar grains and the second reference plane, and the ratio of the number of the second columnar grains to the number of all grains in the second electrode is greater than or equal to fifty percent, it is necessary to adjust the process conditions during the preparation of the second electrode, such as adjusting the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The smaller thickness of the second electrode can make the preparation time of the second electrode shorter, which is beneficial to reducing the manufacturing difficulty and process complexity of the ferroelectric capacitor and increasing the manufacturing efficiency of the ferroelectric capacitor.

[0016] In some embodiments, the ferroelectric capacitor further includes a second buffer layer, which is located between the second electrode and the ferroelectric layer and is in contact with the ferroelectric layer. Similar to the principle of action of the first buffer layer in the above embodiments, the setting of the second buffer layer can improve the service life of the ferroelectric capacitor, improve the accuracy of reading and writing data of the memory cell using the ferroelectric capacitor, and improve the structural stability of the ferroelectric capacitor.

[0017] In some embodiments, the material of the ferroelectric layer includes a hafnium oxide-based material and a doping element; the doping element includes at least one of zirconium, lanthanum, aluminum, titanium, and niobium.

[0018] In some embodiments, the material of the first electrode includes at least one of a metal, a conductive oxide, and a conductive nitride; and / or, the material of the second electrode includes at least one of a metal, a conductive oxide, and a conductive nitride.

[0019] In some embodiments, both the first electrode and the second electrode are planar electrodes, and the first electrode and the second electrode are stacked. In this way, the structure of the ferroelectric capacitor can be relatively simple, which is beneficial to simplifying the manufacturing process of the ferroelectric capacitor and reducing the manufacturing cost.

[0020] In some embodiments, the surface of the first electrode close to the ferroelectric layer includes a connection surface, a first side surface, and a second side surface. The first side surface and the second side surface are located on opposite sides of the connection surface and are both connected to the connection surface. The extending directions of the first side surface and the second side surface are different from the extending direction of the connection surface; the ferroelectric layer is disposed opposite to the connection surface, the first side surface, and the second side surface; the second electrode is located on the side of the ferroelectric layer away from the first electrode and is disposed opposite to the connection surface, the first side surface, and the second side surface.

[0021] In this way, the facing area between the first electrode and the second electrode of the ferroelectric capacitor can be relatively large, so that the capacitance value of the ferroelectric capacitor can be relatively large. When applying the ferroelectric capacitor provided in the embodiments of the present application to a memory, even if the occupied area of the ferroelectric capacitor is small, the capacitance value of the ferroelectric capacitor can meet the requirements of the memory, which is beneficial to reducing the size of the memory and achieving miniaturization and high integration.

[0022] Second aspect: A method for manufacturing a ferroelectric capacitor is provided. The manufacturing method includes forming a first electrode, forming a ferroelectric layer, and forming a second electrode. The ferroelectric layer is located between the first electrode and the second electrode. The first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane. The first included angle is greater than 0 degrees and less than or equal to 90 degrees. The ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent. The first reference plane is parallel to a part of the surface of the ferroelectric layer that faces the first columnar grains.

[0023] Third aspect: A storage array is provided. The storage array includes a plurality of storage units. The plurality of storage units include a transistor and a ferroelectric capacitor as described in any one of the above embodiments. The transistor is connected to the ferroelectric capacitor.

[0024] Fourth aspect: A memory is provided. The memory includes a controller and a storage array as described in any one of the above embodiments. The controller is electrically connected to the storage array.

[0025] Fifth aspect: An electronic device is provided. The electronic device includes a circuit board and a memory as described in any one of the above embodiments. The memory is located on the circuit board and is electrically connected to the circuit board.

[0026] Among them, for the technical effects brought by any one of the design manners in the second aspect to the fifth aspect, reference may be made to the technical effects brought by different design manners in the first aspect, which will not be elaborated herein. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions in the present application, the drawings required for use in some embodiments of the present application will be briefly introduced below. Obviously, the drawings in the following description are only the drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams and do not limit the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present application.

[0028] Figure 1 It is a schematic structural diagram of an electronic device according to some embodiments;

[0029] Figure 2 It is a schematic structural diagram of a memory according to some embodiments;

[0030] Figure 3 It is a schematic structural diagram of another memory according to some embodiments;

[0031] Figure 4Schematic structural diagram of a storage array according to some embodiments;

[0032] Figure 5 Schematic structural diagram of another storage array according to some embodiments;

[0033] Figure 6 Schematic structural diagram of a ferroelectric capacitor according to some embodiments;

[0034] Figure 7 Schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0035] Figure 8 XRD test result diagram of the first electrode and the control electrode;

[0036] Figure 9 TEM test result diagram of the first electrode and the control electrode;

[0037] Figure 10 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0038] Figure 11 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0039] Figure 12 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0040] Figure 13 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0041] Figure 14 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0042] Figure 15 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0043] Figure 16 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0044] Figure 17 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0045] Figure 18 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0046] Figure 19 Schematic structural diagram of yet another ferroelectric capacitor according to some embodiments;

[0047] Figure 20ASchematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0048] Figure 20B Schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0049] Figure 21 Schematic structural diagram of another ferroelectric capacitor according to some embodiments;

[0050] Figure 22 Flowchart of a method for manufacturing a ferroelectric capacitor according to some embodiments. Detailed implementation manners

[0051] The following will clearly and completely describe the technical solutions in some embodiments of the present application with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present application fall within the scope of protection of the present application.

[0052] In the description of the present application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present application.

[0053] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0054] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present application, unless otherwise stated, the meaning of "a plurality" is two or more.

[0055] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0056] In addition, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0057] In the context of this application, the meanings of "on", "above", and "over" should be interpreted in the broadest possible way such that "on" not only means "directly on something", but also includes "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intermediate features or layers therebetween (i.e., directly on something).

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of the regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] Embodiments of the present application provide an electronic device. The electronic device may be, for example, a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, or a communication electronic product. Among them, consumer electronic products such as mobile phones, tablets, laptop computers, e-readers, game consoles, cameras, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearable products (e.g., smart watches, smart bracelets), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products such as smart door locks, TVs, remote controls, refrigerators, small household appliances for charging (e.g., soymilk makers, floor cleaning robots), set-top boxes, etc. Vehicle-mounted electronic products such as vehicle navigation devices, vehicle-mounted high-density digital video discs (DVDs), vehicle automatic auxiliary driving systems, navigation and infotainment systems, powertrain and battery management systems, etc. Financial terminal products such as automated teller machines (ATMs), terminals for self-service business handling of POS (Point of sales) function machines, etc. Embodiments of the present application do not impose special restrictions on the specific form of the electronic device.

[0060] Figure 1 FIG. 4 is a schematic structural diagram of an electronic device 100 provided by an embodiment of the present application. As Figure 1 shown, the electronic device 100 may include a bus 110 and a system on chip (SOC) 120 connected to the bus 110. The SOC 120 may be used to process data, such as processing data of application programs, processing image data, and caching temporary data. In one implementation, the SOC 120 may include an application processor (AP) 121 for processing application programs, a graphics processing unit (GPU) 122 for processing image data, and a first random access memory (RAM) 123 for caching high-speed data. The first RAM 123 may be a static random access memory (SRAM), etc. The above AP 121, GPU 122, and the first RAM 123 may be integrated in a single die or may be separately provided in multiple dies.

[0061] For another example Figure 1 As shown, the electronic device 100 may further include a second RAM 130 connected to the SOC 120 via a bus 110. The second RAM 130 may be a dynamic random access memory (DRAM). The second RAM 130 may be used to store volatile data, such as temporary data generated by the SOC 120. The storage capacity of the second RAM 130 is generally larger than that of the first RAM 123, but the reading speed is generally slower than that of the first RAM 123.

[0062] In addition, the electronic device 100 may further include a communication chip 140 and a power management chip 150 connected to the SOC 120 via the bus 110. The communication chip 140 may be used for protocol stack processing, or for amplifying, filtering, etc. of analog radio frequency signals, or for implementing the above functions simultaneously. The power management chip 150 may be used to supply power to other chips. In one implementation, the SOC 120 and the second RAM 130 may be encapsulated in a package structure, such as using 2.5D (dimension) or 3D packaging, etc., to obtain a faster inter-chip data transfer rate.

[0063] Figure 2 It is a circuit block diagram of a memory 200 that can be applied in an electronic device provided by an embodiment of the present application. In one implementation, the memory 200 may be the first RAM 123 as Figure 1 shown, or may be the second RAM 130. The application scenario of the memory 200 of the present application is not limited. In one possible implementation, the memory 200 may also be a RAM disposed outside the SOC 120. The present application does not limit the position of the memory 200 in the electronic device and the positional relationship with the SOC 120.

[0064] For example Figure 2 As shown, the memory 200 includes a storage array 300. In addition, the memory 200 may further include a controller 210 for accessing the storage array 300, where the controller 210 is used to control the read and write operations of the storage array 300.

[0065] It can be understood that the memory 200 may include at least one storage array 300, that is, the memory 200 may include one or more storage arrays.

[0066] The storage array 300 and the controller 210 have various encapsulation structures that can be implemented. For example, the storage array 300 and the controller 210 are two independent chips, and the storage array 300 and the controller 210 are respectively integrated on a substrate. For instance, the storage array 300 and the controller 210 can be electrically connected through metal traces disposed on the substrate. In this structure, since the storage array 300 and the controller 210 are two independent chips, the storage array 300 can be referred to as a stand-alone memory.

[0067] Alternatively, the storage array 300 and the controller 210 are stacked. For example, the storage array 300 and the controller 210 can be electrically connected through through-silicon vias (TSVs) or redistribution layers (RDLs).

[0068] Alternatively, the storage array 300 and the controller 210 are integrated into the same chip, and the chip is integrated on a substrate. Therefore, the storage array 300 can be referred to as an embedded memory.

[0069] In some examples, as Figure 3 shown, the storage array 300 can include multiple storage units 310, where each storage unit 310 can be used to store 1 bit or multiple bits of data. The storage array 300 can also include signal lines such as word lines (WLs) and bit lines (BLs). Each storage unit 310 is electrically connected to the corresponding word line and bit line. Different storage units 310 can be electrically connected through word lines and bit lines. One or more of the above word lines and bit lines are used to select the storage unit 310 to be read or written in the storage array by receiving the control level output by the control circuit, thereby implementing data read and write operations.

[0070] The controller 210 in the memory can include Figure 3 one or more circuit structures such as the decoder 211, driver 212, timing controller 213, buffer 214, or input / output driver 215 as shown.

[0071] In Figure 3In the structure of the memory 200 shown, the decoder 211 is used to perform decoding according to the received address to determine the memory cell 310 to be accessed. The driver 212 is used to control the level of the signal line according to the decoding result generated by the decoder 211, so as to realize the access to the specified memory cell 310. The buffer 214 is used to cache the read data. For example, a first-in first-out (FIFO) can be used for caching. The timing controller 213 is used to control the timing of the buffer 214 and control the driver 212 to drive the signal lines in the memory array 300. The input / output driver 215 is used to drive the transmission signal, such as driving the received data signal and driving the data signal to be sent, so that the data signal can be transmitted over a long distance.

[0072] The above-mentioned memory array 300, decoder 211, driver 212, timing controller 213, buffer 214 and input / output driver 215 can be integrated on one chip or separately integrated on multiple chips.

[0073] The memory involved in this application can be a ferroelectric random access memory (FeRAM), or a ferroelectric field-effect transistor (FeFET) memory or a ferroelectric tunnel junction (FTJ) memory, and can also be a resistive random access memory (RRAM).

[0074] Figure 4 and Figure 5 show the circuit structure diagrams of two possible memory arrays 300 provided by the embodiments of the present application. As Figure 4 and Figure 5 shown, the memory array 300 may include multiple memory cells 310. The memory cell 310 includes a transistor T and a ferroelectric capacitor C. The memory array may also include a word line WL, a bit line BL and a source line SL. Figure 4 shows 4 memory cells 310 in the memory array 300. In the memory cell 310, the first end of the ferroelectric capacitor C is connected to the first pole of the transistor T, the second end of the ferroelectric capacitor C is connected to the source line SL, the second pole of the transistor T is connected to the bit line BL, and the control end (such as the gate) of the transistor T is connected to the word line WL.

[0075] Figure 5 Similarly shows 4 memory cells 310 in the memory array 300, and is the same as Figure 4Different from the storage cell 310 shown, in the storage cell 310, the first end of the ferroelectric capacitor C is connected to the control terminal (such as the gate) of the transistor T, the second end of the ferroelectric capacitor C is connected to the word line WL, the first pole of the transistor T is connected to the source line SL, and the second pole of the transistor T is connected to the bit line BL.

[0076] It can be understood that Figure 4 and Figure 5 the number of the storage cells 310 shown does not limit the number of the storage cells 310 in the storage array 300 provided by the embodiments of the present application. The number of the storage cells 310 in the storage array 300 provided by the embodiments of the present application can be designed according to actual needs. The structure of the storage cell 310 in the embodiments of the present application is not limited to only Figure 4 and Figure 5 the structure shown. A single storage cell 310 may also include multiple transistors T and multiple ferroelectric capacitors C.

[0077] Generally, a ferroelectric capacitor includes two relatively arranged electrodes and a ferroelectric layer located between the two electrodes. Under the clamping action of the two electrodes, the ferroelectric layer undergoes a high-temperature crystallization process to form a polycrystalline thin film mixed with orthorhombic (O phase), tetragonal (T phase), and monoclinic (M phase). Among them, the presence of the O phase and the T phase enables the ferroelectric layer to have ferroelectric properties, and the M phase enables the ferroelectric layer to exhibit dielectric characteristics.

[0078] Crystals in the ferroelectric phase (i.e., orthorhombic and tetragonal phases) are formed in the ferroelectric layer. When an electric field is applied to the ferroelectric layer, the central atoms of the crystals stop at the low-energy state along the electric field. When the reversed electric field is applied to the ferroelectric layer, the central atoms move along the direction of the electric field in the crystal and stop at another low-energy state. The movement and coupling of a large number of central atoms in the crystal unit cell form ferroelectric domains. The ferroelectric domains form polarization charges under the action of the electric field. The energy levels of the polarization charges formed before and after the reversal of the ferroelectric domains under the electric field are different. This binary stable state will cause the ferroelectric capacitor to charge and discharge, and thus can be recognized by the external circuit, realizing the "0" or "1" storage state.

[0079] The electrodes of ferroelectric capacitors are crucial for imparting ferroelectric properties to the ferroelectric layer. Electrodes of existing ferroelectric capacitors generally use conductive materials such as titanium nitride (TiN), tungsten (W), and ruthenium (Ru), resulting in an amorphous or polycrystalline state with randomly distributed crystalline orientations in the microscopic morphology of the electrodes. Using electrodes in an amorphous or polycrystalline state with randomly distributed crystalline orientations cannot effectively induce the ferroelectric layer, leading to the easier generation of the M phase in the ferroelectric layer, causing problems such as easy fatigue and easy breakdown in the ferroelectric layer, seriously affecting the usage effect of the memory and the product competitiveness.

[0080] Based on this, as Figure 6 shown, an embodiment of the present application provides a ferroelectric capacitor C, which includes a first electrode 10, a second electrode 20, and a ferroelectric layer 30 located between the first electrode 10 and the second electrode 20. Among them, the first electrode 10 is a polycrystal, the first electrode 10 includes first columnar grains Q1, and there is a first included angle α between the extending direction L1 of the first columnar grains Q1 and a first reference plane U1. The first included angle α is greater than 0 degree and less than or equal to 90 degrees, and the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to 50%. The first reference plane U1 is parallel to the part of the surface of the ferroelectric layer 30 opposite to the first columnar grains Q1.

[0081] Figure 6 In all of them, it is taken as an example for illustration that the extending direction L of the first columnar grains Q1 is perpendicular to the first reference plane U1, that is, the included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1 is 90 degrees. Of course, the first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1 can also be 30 degrees, 45 degrees, 60 degrees, 70 degrees, 75 degrees, 80 degrees, etc.

[0082] It can be understood that the polycrystal includes multiple first columnar grains Q1, and the included angles between the extending directions L1 of different first columnar grains Q1 and the first reference plane U1 can be different. That is, among the multiple first columnar grains Q1 in the polycrystal, the extending directions L1 of different first columnar grains Q1 can be different. For example, the extending directions L1 of a part of the multiple first columnar grains Q1 are different, and the extending directions L1 of another part are the same. Another example is that there is at least one first columnar grain Q1 among the multiple first columnar grains Q1 whose extending direction L1 is different from the extending directions L1 of the multiple first columnar grains Q1 around it.

[0083] In the embodiments of the present application, there are no restrictions on the height, cross-sectional shape, and cross-sectional size of the first columnar grains Q1. Among the multiple first columnar grains Q1 of the polycrystal, the heights of different first columnar grains Q1 may be the same or different. The cross-sectional shapes of different first columnar grains Q1 may be the same or different. The cross-sectional sizes of different first columnar grains Q1 may be the same or different.

[0084] Figure 6 Taking the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 as 100% as an example for illustration. In some other possible examples, the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 may be 50%, 60%, 70%, 80%, 90%, etc.

[0085] In some examples, the materials of the first electrode 10 and the second electrode 20 may include at least one of metals, conductive oxides, and conductive nitrides. Metals may be, for example: W (tungsten), Pt (platinum), Sr (strontium), Ru (ruthenium), La (lanthanum), Mn (manganese), Ti (titanium), Au (gold), Ag (silver), Al (aluminum), etc. Conductive oxides may be, for example: TiO (titanium oxide), NbO (niobium oxide), RuO2 (ruthenium oxide), IrO (iridium oxide), ITO (indium tin oxide), AZO (aluminum-doped zinc oxide), FTO (fluorine-doped tin oxide), etc. Conductive nitrides may be, for example: TiN (titanium nitride), TiAlN (titanium aluminum nitride), WN (tungsten nitride), TaN (tantalum nitride), etc.

[0086] When preparing the above-mentioned "metals, conductive oxides, conductive nitrides" using different processes, the structures of the "metals, conductive oxides, conductive nitrides" can be different, that is, the above-mentioned "metals, conductive oxides, conductive nitrides" can be amorphous, polycrystals with randomly distributed crystal orientations, or columnar grains.

[0087] It can be understood that when the material of the first electrode 10 includes at least one of metals, conductive oxides, and conductive nitrides, the above-mentioned "metals, conductive oxides, conductive nitrides" are all polycrystals and include the first columnar grains Q1. There is a first angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1, and the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent.

[0088] Exemplarily, the thickness of the first electrode 10 can be 10 nm to 300 nm. For example, the thickness of the first electrode 10 is 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 200 nm, 300 nm, etc. In this way, the thickness of the first electrode 10 will not be too small, and the structural stability of the first electrode 10 can be relatively high, so as to ensure the clamping effect of the first electrode 10 on the ferroelectric layer 30 and ensure the generation of the ferroelectric phase in the ferroelectric layer 30. At the same time, the thickness of the first electrode 10 will not be too large, so that the manufacturing cost of the first electrode 10 will not be too large and the manufacturing time will not be too long, which is beneficial to controlling the cost and manufacturing efficiency of the ferroelectric capacitor C.

[0089] Exemplarily, the thickness of the second electrode 20 can be 10 nm to 300 nm. For example, the thickness of the second electrode 20 is 10 nm, 20 nm, 30 nm, 50 nm, 60 nm, 80 nm, 100 nm, 200 nm, 300 nm, etc. In this way, the thickness of the second electrode 20 will not be too small, and the structural stability of the second electrode 20 can be relatively high, so as to ensure the clamping effect of the second electrode 20 on the ferroelectric layer 30 and ensure the generation of the ferroelectric phase in the ferroelectric layer 30. At the same time, the thickness of the second electrode 20 will not be too large, so that the manufacturing cost of the second electrode 20 will not be too large and the manufacturing time will not be too long, which is beneficial to controlling the cost and manufacturing efficiency of the ferroelectric capacitor C.

[0090] It can be understood that the thicknesses of the first electrode 10 and the second electrode 20 in the embodiments of the present application are not limited to the above examples.

[0091] In some examples, the material of the ferroelectric layer 30 can include hafnium oxide-based materials and doping elements. Among them, the hafnium oxide-based materials can include hafnium oxide or hafnium zirconium oxide, and the doping elements can include at least one of zirconium (Zr), lanthanum (La), aluminum (Al), titanium (Ti), and niobium (Nb). It can be understood that when the doping element is zirconium, the material of the ferroelectric layer 30 can also include zirconium oxide; when the doping element is lanthanum, the material of the ferroelectric layer 30 can also include lanthanum oxide; when the doping element is aluminum, the material of the ferroelectric layer 30 can also include aluminum oxide; when the doping element is Ti, the material of the ferroelectric layer 30 can also include titanium oxide; when the doping element is niobium, the material of the ferroelectric layer 30 can also include niobium oxide. Of course, in order to provide doping elements to the ferroelectric layer 30, the ferroelectric layer 30 can also include other materials containing lanthanum, aluminum, titanium, and niobium.

[0092] In some examples, as Figure 6 shown, the ferroelectric layer 30 can be a single-layer structure. In other examples, as Figure 7 shown, the ferroelectric layer 30 can be a multi-layer structure.

[0093] Taking hafnium oxide as the material of the ferroelectric layer 30 and zirconium as the doping element as an example, when the ferroelectric layer 30 is a single-layer structure, the ferroelectric layer 30 can be an alloy structure in which single-molecule layers of hafnium oxide and zirconium oxide are intertwined. When the ferroelectric layer 30 is a multi-layer structure, the ferroelectric layer 30 can include a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked. Alternatively, when the ferroelectric layer 30 is a multi-layer structure, the ferroelectric layer 30 can include a plurality of hafnium zirconium oxide layers rich in hafnium elements (with ferroelectric properties) and a plurality of hafnium zirconium oxide layers rich in zirconium elements (with antiferroelectric properties) that are alternately stacked. The so-called "rich in hafnium elements" means that the content of hafnium elements in the hafnium zirconium oxide layer is higher than that of zirconium elements, and "rich in zirconium elements" means that the content of zirconium elements in the hafnium zirconium oxide layer is higher than that of hafnium elements.

[0094] In the case where the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked, the film layer closest to the first electrode 10 in the ferroelectric layer 30 can be a hafnium oxide layer 31, and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can be a zirconium oxide layer 32; or, the film layer closest to the first electrode 10 in the ferroelectric layer 30 can be a zirconium oxide layer 32, and the film layer closest to the first electrode 10 in the ferroelectric layer 30 can be a hafnium oxide layer 31. Of course, in the case where the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked, the film layer closest to the first electrode 10 and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can both be hafnium oxide layers 31 or both be zirconium oxide layers 32.

[0095] It can be understood that due to the different bond strengths between hafnium and oxygen and between zirconium and oxygen, the binding effects of the hafnium oxide layer 31 and the zirconium oxide layer 32 on oxygen ions are different, and the oxygen ion concentrations in the hafnium oxide layer and the zirconium oxide layer are different. At the same time, the lattice matching degree between the hafnium oxide layer 31 and the first electrode 10 is different from the lattice matching degree between the zirconium oxide layer 32 and the first electrode 10. Therefore, the stress between the hafnium oxide layer 31 and the first electrode 10 is different from the stress between the zirconium oxide layer 32 and the first electrode 10. Of course, the lattice matching degree between the hafnium oxide layer 31 and the second electrode 20 is also different from the lattice matching degree between the zirconium oxide layer 32 and the second electrode 20. Therefore, the stress between the hafnium oxide layer 31 and the second electrode 20 is also different from the stress between the zirconium oxide layer 32 and the second electrode 20.

[0096] The stress magnitude applied by the first electrode 10 and the second electrode 20 to the ferroelectric layer 30, and the magnitude of the oxygen ion concentration in the ferroelectric layer 30 both have an impact on the generation of the M phase and the O phase in the ferroelectric layer, thereby affecting the properties of the ferroelectric capacitor C. Therefore, when the ferroelectric layer 30 includes a plurality of hafnium oxide layers 31 and a plurality of zirconium oxide layers 32 that are alternately stacked, the performance of the ferroelectric capacitor C can be improved by adjusting the number and order of the film layers of the hafnium oxide layer 31 and the zirconium oxide layer 32 in the ferroelectric layer 30.

[0097] For example, when the film layer closest to the first electrode 10 and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can both be hafnium oxide layers 31, the storage window of the ferroelectric capacitor C can be relatively large. When the film layer closest to the first electrode 10 and the film layer closest to the second electrode 20 in the ferroelectric layer 30 can both be zirconium oxide layers 32, the ferroelectric capacitor C is not likely to have reliability problems such as easy fatigue or easy breakdown.

[0098] Of course, the performance of the ferroelectric capacitor C when the ferroelectric layer 30 is a single-layer structure is also different from that when the ferroelectric layer 30 is a multi-layer structure. For example, when the ferroelectric layer 30 is an alloy structure in which single molecules of hafnium oxide and zirconium oxide are intertwined, the storage time of the ferroelectric capacitor using the ferroelectric layer 30 can be relatively long. When the ferroelectric layer 30 is a multi-layer structure, the storage window of the ferroelectric capacitor using the ferroelectric layer 30 can be relatively large, the number of read and write operations can be relatively large, and the reliability of the ferroelectric capacitor C can be relatively high.

[0099] The embodiments of the present application do not limit the thickness of the ferroelectric layer 30, which can be designed according to actual requirements. When the ferroelectric layer 30 is a multi-layer structure, the thickness of each sub-layer (for example, the above-mentioned hafnium oxide layer and zirconium oxide layer) in the ferroelectric layer 30 can also be designed according to actual requirements. Exemplarily, when the ferroelectric layer 30 includes a plurality of hafnium oxide layers and a plurality of zirconium oxide layers that are alternately stacked, the thicknesses of the hafnium oxide layer and the zirconium oxide layer can be on the nanometer scale.

[0100] By using X-ray Diffraction (XRD) technology, the first electrode 10 and the reference electrode (a polycrystalline electrode with a random crystal orientation) are respectively detected, and the test result graph as shown in Figure 8 can be obtained. Among them, the materials of the first electrode 10 and the reference electrode are both tungsten (W).

[0101] Figure 8In the test result graph shown, the horizontal label is 2theta, which is the diffraction angle, and the unit is degree (°). The diffraction angle is the angle between the incident X-ray and the diffraction line. Theta is called the diffraction half angle, which is the angle between the incident X-ray and the crystal plane that meets the diffraction conditions. The vertical axis is the intensity, which is the intensity of the X-ray after diffraction. The unit of the vertical axis is au (arbitrary unit). Figure 8 In the figure, the “solid line” represents the diffraction curve of the first electrode 10, and the “dashed line” represents the diffraction curve of the reference electrode.

[0102] like Figure 8 As shown in the figure, there are three higher peaks in the detection curve of the control electrode, and from left to right, the three peaks respectively indicate that the control electrode has (110) crystal orientation, (200) crystal orientation and (211) crystal orientation. However, there are only two higher peaks in the detection curve of the first electrode, and from left to right, the two peaks respectively indicate that the first electrode has (110) crystal orientation and (211) crystal orientation, and the first electrode basically does not have (200) crystal orientation.

[0103] Through transmission electron microscopy observation of the first electrode and the reference electrode, it can be obtained Figure 9 The results shown in the figure, where the observation results of the control electrode are Figure 9 In (a), the observation result of the first electrode is shown as follows: Figure 9 Refer to (b) in Figure 9 In (a), due to the random distribution of crystal orientation of the grains in the control electrode, the grains in the control electrode are easy to combine with each other to form a larger overall structure, and the growth rate of the single grains in the control electrode in different directions is balanced, so that the size of the single grain in different directions is larger, and the volume of the single grain is also larger. However, the first electrode 10 provided in the embodiment of the present application has a preferred orientation that hardly presents the (200) crystal direction, and the growth rate of the first columnar grains in the first electrode 10 in different directions is uneven, so the first columnar grains Q1 in the first electrode can be columnar and extend along the thickness direction of the first electrode 10.

[0104] After research, it was found that the (200) crystal orientation in the electrode of the ferroelectric capacitor easily induces the generation of the M phase in the ferroelectric layer, while the (110) crystal orientation in the electrode easily induces the generation of the O phase in the ferroelectric layer. Therefore, in the case where the (200) crystal orientation is substantially absent in the first electrode, the M phase in the ferroelectric layer of the ferroelectric capacitor provided in the embodiment of the present application can be less, while the O phase can be more.

[0105] Based on this, in the ferroelectric capacitor C provided in the embodiments of the present application, the first electrode 10 is a polycrystal, and the first electrode 10 includes first columnar grains Q1. There is a first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1. The first included angle α is greater than 0 degree and less than or equal to 90 degrees. When the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to 50%, the M phase generated in the ferroelectric layer 30 can be reduced, and the O phase generated can be increased.

[0106] When there is less M phase and more O phase in the ferroelectric layer 30, on the one hand, the coercive electric field of the ferroelectric capacitor C can be reduced, and the operating voltage of the ferroelectric capacitor C can be lowered. Thus, when the storage unit using the ferroelectric capacitor C provided in the embodiments of the present application performs read and write operations, the operating voltage can be smaller and the power consumption can be lower. On the other hand, the fatigue period of the ferroelectric capacitor C can be delayed, and the leakage current of the ferroelectric capacitor C can be reduced, thereby increasing the storage times of the ferroelectric capacitor C, ensuring the storage window of the ferroelectric capacitor C after multiple storages, improving the reliability of the ferroelectric capacitor, and further ensuring the accuracy of the read and write operations of the storage unit 310 using the ferroelectric capacitor C provided in the embodiments of the present application, and improving the performance of the memory.

[0107] At the same time, when there is less M phase and more O phase in the ferroelectric layer 30, the film layer bearing capacity of the ferroelectric layer 30 can be better, and the structure of the ferroelectric capacitor C can be more stable. Thus, the storage capacity of the ferroelectric capacitor C can be ensured, the reliability of the ferroelectric capacitor can be improved, the storage window loss rate of the storage array (memory) using the ferroelectric capacitor C can be reduced, the accuracy of the read and write operations of the storage array can be ensured, and the misreading rate can be reduced.

[0108] In some examples, the first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1 can be greater than or equal to 30 degrees and less than or equal to 90 degrees. In this way, the (200) crystal orientation is less likely to be generated in the first electrode 10, thereby further reducing the M phase in the ferroelectric layer 30 and making the O phase in the ferroelectric layer 30 more.

[0109] In some embodiments, as Figure 10 shown, the ferroelectric capacitor C may further include a third electrode 40, and the third electrode 40 is located on the side of the first electrode 10 away from the ferroelectric layer 30. Among them, the third electrode 40 is an amorphous or polycrystal with randomly distributed crystallization orientations.

[0110] In this way, the first electrode 10 and the third electrode 40 are located on the same side of the ferroelectric layer 30. The first electrode 10 and the third electrode 40 can jointly provide clamping stress for the ferroelectric layer 30, and the thickness of the first electrode 10 can be relatively small. During the preparation of the ferroelectric capacitor C, in order to make the first electrode 10 a polycrystal, and the first electrode 10 includes first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, and the ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent. When preparing the first electrode 10, it is necessary to adjust the process conditions, such as adjusting the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The relatively small thickness of the first electrode 10 can make the preparation time of the first electrode 10 shorter, which is beneficial to reducing the preparation difficulty and process complexity of the ferroelectric capacitor and improving the preparation efficiency of the ferroelectric capacitor.

[0111] In some embodiments, referring to Figure 10 , when the first electrode 10 is a polycrystal, the first electrode 10 includes first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, the second electrode 20 can be an amorphous or polycrystal with randomly distributed crystal orientations.

[0112] In other embodiments, as Figure 11 shown, when the first electrode 10 is a polycrystal, the first electrode 10 includes first columnar grains Q1, and there is a first angle α between the extension direction L1 of the first columnar grains Q1 and the first reference plane U1, the second electrode 20 can be a polycrystal, the second electrode 20 includes second columnar grains Q2, and there is a second angle β between the extension direction of the second columnar grains Q2 and the second reference plane U2, the second angle β is greater than 0 degree and less than or equal to 90 degrees, and the ratio of the number of the second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to fifty percent. The second reference plane U2 is parallel to the part of the surface of the ferroelectric layer 30 opposite to the second columnar grains Q2.

[0113] Figure 11 In

[0114] It can be understood that the second electrode 20 includes a plurality of second columnar grains Q2, and the second included angles between the extending directions L2 of different second columnar grains Q2 and the second reference plane U2 can be different. That is, among the plurality of second columnar grains Q2 in the polycrystal, the extending directions L2 of different second columnar grains Q2 can be different. For example, the extending directions L2 of a part of the plurality of second columnar grains Q2 are different, and the extending directions L2 of another part are the same. For another example, there is at least one second columnar grain Q2 among the plurality of second columnar grains Q2 whose extending direction L2 is different from the extending directions L2 of the plurality of second columnar grains Q2 around this second columnar grain Q2.

[0115] Figure 11 Taking the ratio of the number of the second columnar grains Q2 to the number of all grains in the second electrode 20 as 100% as an example for illustration. In some other possible examples, the ratio of the number of the second columnar grains Q2 to the number of all grains in the second electrode 20 can be 50%, 60%, 70%, 80%, 90%, etc.

[0116] In the ferroelectric capacitor C provided in the embodiment of the present application, the second electrode 20 is a polycrystal, and the second electrode 20 includes second columnar grains Q2. There is a second included angle β between the extending direction of the second columnar grains Q2 and the second reference plane U2. The second included angle β is greater than 0 degree and less than or equal to 90 degrees. The ratio of the number of the second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to fifty percent. The second electrode 20 also has almost no preferred orientation of the (200) crystal orientation, so that less M phase can be generated in the ferroelectric layer 30 and more O phase can be generated.

[0117] In some examples, the second included angle β between the extending direction L2 of the second columnar grains Q2 and the second reference plane U2 can be greater than or equal to 30 degrees and less than or equal to 90 degrees. In this way, it is more difficult to generate the (200) crystal orientation in the second electrode 20, so that the M phase in the ferroelectric layer 30 can be further reduced and more O phase can be in the ferroelectric layer 30.

[0118] In some embodiments, as Figure 12 shown, when the second electrode 20 is a polycrystal, the second electrode 20 includes second columnar grains Q2, and there is a second included angle β between the extending direction L2 of the second columnar grains Q2 and the second reference plane U2, the ferroelectric capacitor C can further include a fourth electrode 50. The fourth electrode 50 is located on the side of the second electrode 20 away from the ferroelectric layer 30. Among them, the fourth electrode 50 is an amorphous or polycrystal with randomly distributed crystallization orientations.

[0119] In this way, the second electrode 20 and the fourth electrode 50 are located on the same side of the ferroelectric layer 30. The second electrode 20 and the fourth electrode 50 can jointly provide clamping stress for the ferroelectric layer 30, and the thickness of the second electrode 20 can be relatively small. During the preparation of the ferroelectric capacitor C, in order to make the second electrode 20 include second columnar grains Q2, and there is a second included angle β between the extending direction of the second columnar grains Q2 and the second reference plane U2, and the ratio of the number of the second columnar grains β to the number of all grains in the second electrode 20 is greater than or equal to 50%, when preparing the second electrode 20, it is necessary to adjust the process conditions, such as adjusting the temperature, the flow rate of the reaction gas, and the power of the reaction equipment. The relatively small thickness of the second electrode 20 can make the preparation time of the second electrode 20 shorter, which is beneficial to reducing the preparation difficulty and process complexity of the ferroelectric capacitor C and improving the preparation efficiency of the ferroelectric capacitor C.

[0120] In some embodiments, as Figure 13 shown, when the first electrode 10 is polycrystalline, the first electrode 10 includes first columnar grains Q1, there is a first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1, the second electrode 20 is polycrystalline, the second electrode 20 includes second columnar grains Q2, and there is a second included angle β between the extending direction L2 of the second columnar grains Q2 and the second reference plane U2, the ferroelectric capacitor C can include the third electrode 40 and the fourth electrode 50 at the same time.

[0121] In this way, the first electrode 10 and the third electrode 40 are located on the same side of the ferroelectric layer 30. The first electrode 10 and the third electrode 40 can jointly provide clamping stress for the ferroelectric layer 30. The second electrode 20 and the fourth electrode 50 are located on the same side of the ferroelectric layer 30. The second electrode 20 and the fourth electrode 50 can jointly provide clamping stress for the ferroelectric layer 30. The thicknesses of the first electrode 10 and the second electrode 20 can both be relatively small, which is beneficial to shortening the preparation time of the first electrode 10 and the second electrode 20 during the preparation of the ferroelectric capacitor C and improving the preparation efficiency of the ferroelectric capacitor C.

[0122] Figure 14 and Figure 15 respectively show the structural schematic diagrams of two ferroelectric capacitors C provided by the embodiments of the present application. In some embodiments, as Figure 14 and Figure 15 shown, the ferroelectric capacitor C may further include a first buffer layer 60. The first buffer layer 60 is located between the first electrode 10 and the ferroelectric layer 30 and is in contact with the ferroelectric layer 30. Among them, Figure 15 the ferroelectric capacitor C shown in Figure 14 compared with the ferroelectric capacitor C shown in Figure 15 the ferroelectric capacitor C shown in

[0123] Exemplarily, the material of the first buffer layer 60 may include materials such as titanium oxide, niobium oxide, cerium oxide, and silicon nitride. In the embodiments of the present application, the thickness of the first buffer layer 60 is not limited and can be designed according to actual requirements.

[0124] In the embodiments of the present application, by providing the first buffer layer 60 between the first electrode 10 and the ferroelectric layer 30, on the one hand, the stress between the first electrode 10 and the ferroelectric layer 30 can be adjusted by the first buffer layer 60, improving the structural stability of the ferroelectric capacitor C. On the other hand, it can also inhibit the diffusion of metal particles in the first electrode 10 into the ferroelectric layer 30, inhibit the diffusion of oxygen atoms in the ferroelectric layer 30 into the first electrode 10, reduce the oxygen vacancies formed due to the movement of oxygen ions in the ferroelectric layer, weaken the oxidation effect between the electrode and oxygen ions, avoid the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor and preventing the ferroelectric capacitor from being broken down, and improving the service life of the ferroelectric capacitor. At the same time, the reduction of oxygen vacancies in the ferroelectric layer 30 can also improve the polarization fatigue and imprint effect caused by oxygen vacancies, and improve the accuracy of reading and writing data of the storage unit 310 using the ferroelectric capacitor C.

[0125] Figure 16 and Figure 17 respectively show the structural schematic diagrams of two ferroelectric capacitors C provided by the embodiments of the present application. In some embodiments, as Figure 16 and Figure 17 shown, the ferroelectric capacitor C may further include a second buffer layer 70. The second buffer layer 70 is located between the second electrode 20 and the ferroelectric layer 30 and is in contact with the ferroelectric layer 30. Among them, Figure 17 the ferroelectric capacitor C shown Figure 16 compared with the ferroelectric capacitor shown Figure 17 in the ferroelectric capacitor C shown, a fourth electrode 50 is further provided. When the ferroelectric capacitor C includes the second buffer layer 70, the ferroelectric capacitor C may include the first buffer layer 60 (as Figure 16 shown), that is, it may not include the first buffer layer 60 (as Figure 17 shown).

[0126] Exemplarily, the material of the second buffer layer 70 may include materials such as titanium oxide, niobium oxide, cerium oxide, and silicon nitride. In the embodiments of the present application, the thickness of the second buffer layer 70 is not limited and can be designed according to actual requirements.

[0127] Among them, the material of the second buffer layer 70 may be the same as or different from the material of the first buffer layer 60. The thickness of the second buffer layer 70 may be the same as or different from the thickness of the first buffer layer 60.

[0128] In the embodiment of the present application, by providing a second buffer layer 70 between the second electrode 20 and the ferroelectric layer 30, on the one hand, it can inhibit the diffusion of metal particles in the second electrode 20 into the ferroelectric layer 30, inhibit the diffusion of oxygen atoms in the ferroelectric layer 30 into the second electrode 20, reduce the oxygen vacancies formed in the ferroelectric layer due to the movement of oxygen ions, weaken the oxidation effect between the electrode and oxygen ions, avoid the formation of a conductive path in the ferroelectric layer, thereby reducing the leakage current of the ferroelectric capacitor, preventing the ferroelectric capacitor from being broken down, and improving the service life of the ferroelectric capacitor. At the same time, with fewer oxygen vacancies in the ferroelectric layer 30, it can also improve the polarization fatigue and imprint effect caused by oxygen vacancies, and improve the accuracy of reading and writing data of the storage unit 310 using the ferroelectric capacitor C. On the other hand, by providing a second buffer layer 70 between the second electrode 20 and the ferroelectric layer 30, it can also adjust the stress between the second electrode 20 and the ferroelectric layer 30, and improve the structural stability of the ferroelectric capacitor C.

[0129] Figure 18 Fig. shows a schematic structural diagram of a ferroelectric capacitor C provided by an embodiment of the present application. In still other embodiments, such as Figure 18 shown, in addition to the first electrode 10, the second electrode 20, and the ferroelectric layer 30, the ferroelectric capacitor C may further include a third electrode 40, a fourth electrode 50, a first buffer layer 60, and a second buffer layer 70. Among them, the functions of the third electrode 40, the fourth electrode 50, the first buffer layer 60, and the second buffer layer 70 can refer to the above examples and will not be elaborated here.

[0130] In some embodiments, the ferroelectric capacitor C may be a two-dimensional structure. At this time, as Figure 18 shown, the first electrode 10 and the second electrode 20 may both be planar electrodes, and the first electrode 10 and the second electrode 20 are stacked. In this way, the structure of the ferroelectric capacitor C can be relatively simple, which is conducive to simplifying the manufacturing process of the ferroelectric capacitor C and reducing the manufacturing cost.

[0131] In other embodiments, the ferroelectric capacitor C may be a three-dimensional structure. At this time, as Figure 19 shown, the surface of the first electrode 10 close to the ferroelectric layer 30 includes a connection surface S1, a first side surface S2, and a second side surface S3. The first side surface S2 and the second side surface S3 are located on opposite sides of the connection surface S1 and are both connected to the connection surface S1. The extending directions of the first side surface S2 and the second side surface S3 are different from the extending direction of the connection surface S1. The ferroelectric layer 30 is disposed opposite to the connection surface S1, the first side surface S2, and the second side surface S3. The second electrode 20 is located on the side of the ferroelectric layer 30 away from the first electrode 10 and is disposed opposite to the connection surface S1, the first side surface S2, and the second side surface S3.

[0132] In this way, the facing area between the first electrode 10 and the second electrode 20 of the ferroelectric capacitor C can be relatively large, so that the capacitance value of the ferroelectric capacitor C can be relatively large. When applying the ferroelectric capacitor C provided by the embodiments of the present application to a memory, even if the occupied area of the ferroelectric capacitor C is small, the capacitance value of the ferroelectric capacitor C can still meet the requirements of the memory, which is beneficial to reducing the size of the memory and achieving miniaturization and high integration.

[0133] In some examples, as Figure 20A shown, the ferroelectric capacitor C may be located on the substrate 101. The substrate 101 has a groove H, and the ferroelectric capacitor C is located in the groove H to serve as a trench capacitor.

[0134] In some possible examples, the second electrode of the ferroelectric capacitor C covers the bottom wall and the side wall of the groove, the ferroelectric layer is located inside the second electrode, the first electrode is located inside the ferroelectric layer, and fills the groove.

[0135] Figure 20A The ferroelectric capacitor C including the first electrode 10, the second electrode 20, the ferroelectric layer 30, the third electrode 40, the fourth electrode 50, the first buffer layer 60, and the second buffer layer 70 is taken as an example for illustration. In some other possible examples, as Figure 20A shown, the fourth electrode 50 is located in the groove H of the substrate 101 and covers the bottom wall and the inner wall of the groove H. The second electrode 20 is located inside the fourth electrode 50. The second buffer layer 70 is located inside the second electrode 20. The ferroelectric layer 30 is disposed inside the second buffer layer 70. The first buffer layer 60 is disposed inside the ferroelectric layer 30. The first electrode 10 is disposed inside the first buffer layer 60. The third electrode 40 is disposed inside the first electrode 10 and fills the groove H. Of course, when the ferroelectric capacitor C is a trench capacitor, the structure of the ferroelectric capacitor C is not limited thereto.

[0136] In some other examples, the ferroelectric capacitor C may be located on the substrate 101, and the ferroelectric capacitor C may be a fin capacitor. At this time, referring to Figure 19 , the first electrode 10 may be a cuboid. The first electrode 10 includes a connecting surface S1, a first side surface S2, and a second side surface S3. The first side surface S2 and the second side surface S3 are respectively located on both sides of the connecting surface and are both connected to the connecting surface. The extending directions of the first side surface S1 and the second side surface S2 are different from the extending direction of the connecting surface S1. The ferroelectric layer 30 covers the first electrode 10 and is disposed opposite to the connecting surface S1, the first side surface S2, and the second side surface S3. The second electrode 20 is located on the side of the ferroelectric layer 30 away from the first electrode 10 and is disposed opposite to the connecting surface S1, the first side surface S2, and the second side surface S3.

[0137] Figure 20BTaking the ferroelectric capacitor C including the first electrode 10, the second electrode 20, the ferroelectric layer 30, the third electrode 40, the fourth electrode 50, the first buffer layer 60 and the second buffer layer 70 as an example for illustration. In some other possible examples, refer to Figure 20B , the fourth electrode 50 can be fin-shaped. The second electrode 20 covers the surface of the fourth electrode 50. The second buffer layer 70, the ferroelectric layer 30, the first buffer layer 60, the first electrode 10 and the third electrode 40 are sequentially covered on the surface of the second electrode 20.

[0138] In still other examples, such as Figure 21 shown, the first electrode 10 of the ferroelectric capacitor C can be a planar electrode, the second electrode 20 can be a columnar electrode, the second electrode 20 penetrates the first electrode 10 (that is, the first electrode 10 is arranged around the second electrode 20), and the ferroelectric layer 30 is located between the first electrode 10 and the second electrode 20.

[0139] Refer to Figure 21 , in addition to the above-mentioned first electrode 10, second electrode 20 and ferroelectric layer 30, the ferroelectric capacitor C can also include a first buffer layer 60 and a second buffer layer 70. The first buffer layer 60 is located between the first electrode 10 and the ferroelectric layer 30, and the second buffer layer 70 is located between the second electrode 20 and the ferroelectric layer 30.

[0140] In still other examples, when the ferroelectric capacitor C includes the first electrode 10, the second electrode 20, the ferroelectric layer 30, the third electrode 40, the fourth electrode 50, the first buffer layer 60, and the second buffer layer 70, the third electrode 40 can be a planar electrode, the fourth electrode 50 can be a columnar electrode, the fourth electrode 50 penetrates the third electrode 40, and between the fourth electrode 50 and the third electrode 40, along the direction from the fourth electrode 50 to the third electrode 40, the second electrode 20, the second buffer layer 70, the ferroelectric layer 30, the first buffer layer 60 and the first electrode 10 are arranged in sequence.

[0141] The above embodiments of the present application show three possible structures of the ferroelectric capacitor C when it is a three-dimensional structure, but it can be understood that the structure of the ferroelectric capacitor C is not limited to this.

[0142] Such as Figure 22 shown, the embodiments of the present application provide a method for manufacturing a ferroelectric capacitor, and the manufacturing method includes step S100, step S200 and step S300. S100: Form the first electrode 10. S200: Form the ferroelectric layer 30. S300: Form the first electrode 20.

[0143] Among them, the ferroelectric layer 30 is located between the first electrode 10 and the second electrode 20. The first electrode 10 is polycrystalline. The first electrode 10 includes first columnar grains Q1, and there is a first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1. The first included angle α is greater than 0 degree and less than or equal to 90 degrees. The ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent. The first reference plane U1 is parallel to the part of the surface of the ferroelectric layer 30 opposite to the first columnar grains Q1.

[0144] In the above preparation method, for the optional materials of the first electrode 10, the second electrode 20, and the ferroelectric layer 30, reference can be made to the above description of the structure of the ferroelectric capacitor C of the present application, which will not be elaborated here.

[0145] When preparing the first electrode 10, the second electrode 20, or the ferroelectric layer 30, magnetron sputtering deposition can be used, or thin film deposition methods can be used, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD) and other deposition processes. In this way, the prepared first electrode 10, second electrode 20, or ferroelectric layer 30 can be relatively uniform, have a high flatness, and high conformal properties, that is, the shape and surface flatness of each layer structure are basically the same.

[0146] When the ferroelectric capacitor C is a three-dimensional structure, during the process of preparing the first electrode 10, the second electrode 20, or the ferroelectric layer 30, photolithography processes, etching processes (such as dry etching processes, wet etching processes, etc.), chemical mechanical polishing (CMP) processes, etc. can also be used.

[0147] Exemplarily, by controlling process conditions, the first electrode 10 can be a polycrystal. The first electrode 10 includes first columnar grains Q1, and there is a first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1. The first included angle α is greater than 0 degree and less than or equal to 90 degrees. The ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent. For example, process conditions such as temperature, reaction gas flow rate, and reaction equipment power can be adjusted so that the first electrode 10 includes first columnar grains Q1, and there is a first included angle α between the extending direction L1 of the first columnar grains Q1 and the first reference plane U1. The first included angle α is greater than 0 degree and less than or equal to 90 degrees. The ratio of the number of the first columnar grains Q1 to the number of all grains in the first electrode 10 is greater than or equal to fifty percent. It can be understood that when different preparation materials of the first electrode 10 are selected, the adjustment trend (increase or decrease) of the process conditions can also be different.

[0148] In the embodiments of the present application, the order of steps S100, S200, and S300 is not limited and can be designed according to actual situations. Figure 22 A flowchart of a possible method for preparing a ferroelectric capacitor is provided. As Figure 22 shown, the second electrode 20 can be formed first (step S300), and then the ferroelectric layer 30 can be formed (step S200). The ferroelectric layer 30 is located on one side of the second electrode 20. Finally, the first electrode 10 can be formed (step S100). The first electrode 10 is located on the side of the ferroelectric layer 30 away from the second electrode 20. That is, the ferroelectric capacitor is prepared in the order of step S300, step S200 to step S100.

[0149] In the description of this specification, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples. As described above, only the specific embodiments of the present application are provided, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A ferroelectric capacitor, characterized in that, Comprising: A first electrode and a second electrode, A ferroelectric layer located between the first electrode and the second electrode; Wherein, the first electrode is a polycrystal, the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane, the first included angle is greater than 0 degrees and less than or equal to 90 degrees, and the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent; the first reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the first columnar grains.

2. The ferroelectric capacitor according to claim 1, wherein Further comprising: A third electrode located on the side of the first electrode away from the ferroelectric layer; The third electrode is an amorphous or polycrystal with randomly distributed crystal orientations.

3. The ferroelectric capacitor according to claim 1 or 2, characterized in that, Further comprising: A first buffer layer located between the first electrode and the ferroelectric layer and in contact with the ferroelectric layer.

4. The ferroelectric capacitor according to any one of claims 1 to 3, characterized in that, The second electrode is a polycrystal, the second electrode includes second columnar grains, and there is a second included angle between the extending direction of the second columnar grains and a second reference plane, the second included angle is greater than 0 degrees and less than or equal to 90 degrees; the ratio of the number of the second columnar grains to the number of all grains in the second electrode is greater than or equal to fifty percent, and the second reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the second columnar grains.

5. The ferroelectric capacitor according to claim 4, characterized in that, Further comprising: A fourth electrode located on the side of the second electrode away from the ferroelectric layer; The fourth electrode is an amorphous or polycrystal with randomly distributed crystal orientations.

6. The ferroelectric capacitor according to any one of claims 1 to 5, characterized in that, Further comprising: A second buffer layer located between the second electrode and the ferroelectric layer and in contact with the ferroelectric layer.

7. The ferroelectric capacitor according to any one of claims 1 to 6, characterized in that The material of the ferroelectric layer includes a hafnium oxide-based material and a doping element; the doping element includes at least one of zirconium, lanthanum, aluminum, titanium, and niobium.

8. The ferroelectric capacitor according to any one of claims 1 to 7, characterized in that, The material of the first electrode includes at least one of a metal, a conductive oxide, and a conductive nitride; and / or, The material of the second electrode includes at least one of a metal, a conductive oxide, and a conductive nitride.

9. The ferroelectric capacitor according to any one of claims 1 to 8, characterized in that, The first electrode and the second electrode are both planar electrodes, and the first electrode and the second electrode are stacked.

10. The ferroelectric capacitor according to any one of claims 1 to 8, characterized in that, The surface of the first electrode close to the ferroelectric layer includes a connecting surface, a first side surface, and a second side surface. The first side surface and the second side surface are located on opposite sides of the connecting surface and are both connected to the connecting surface. The extending directions of the first side surface and the second side surface are different from the extending direction of the connecting surface; the ferroelectric layer is disposed opposite to the connecting surface, the first side surface, and the second side surface; the second electrode is located on the side of the ferroelectric layer away from the first electrode and is disposed opposite to the connecting surface, the first side surface, and the second side surface.

11. A method for preparing a ferroelectric capacitor, characterized in that, Comprising: Forming a first electrode; Forming a ferroelectric layer; And, Forming a second electrode; Wherein, the ferroelectric layer is located between the first electrode and the second electrode; the first electrode is a polycrystal, the first electrode includes first columnar grains, and there is a first included angle between the extending direction of the first columnar grains and a first reference plane, the first included angle is greater than 0 degree and less than or equal to 90 degrees; the ratio of the number of the first columnar grains to the number of all grains in the first electrode is greater than or equal to fifty percent; the first reference plane is parallel to the part of the surface of the ferroelectric layer opposite to the first columnar grains.

12. A storage array, characterized in that, Comprising: A plurality of memory cells, including a transistor and a ferroelectric capacitor as described in any one of claims 1 to 10, the transistor being connected to the ferroelectric capacitor.

13. A memory, characterized in that, Comprising: A memory array as described in claim 12; A controller, electrically connected to the memory array.

14. An electronic device, characterized in that, Comprising: A memory as described in claim 13; A circuit board, the memory being located on the circuit board and electrically connected to the circuit board.

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