Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, the semiconductor structure comprises a substrate, a first metal layer is formed in the substrate, a mask layer is formed on the surface of the substrate and the surface of the first metal layer, and a bottom electrode which penetrates through the mask layer and is electrically connected with the first metal layer is formed in the mask layer; the first interlayer dielectric layer is located on the surface of the mask layer and the surface of the bottom electrode, and the first interlayer dielectric layer comprises a first opening exposing the bottom electrode; the resistive layer and the top electrode are sequentially located at the bottom and the side wall of the first opening, and the bottom electrode, the resistive layer and the top electrode form a memory unit; the second interlayer dielectric layer covers the first interlayer dielectric layer and the memory unit, and the second interlayer dielectric layer comprises a second opening exposing the top electrode; and the second metal layer is positioned in the second opening and is electrically connected with the top electrode. The problem of poor etching precision can be avoided, and the quality of the interlayer dielectric layer can be improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Generally, the method for forming a current RRAM structure is as follows: First, deposit a bottom electrode, a resistive switching layer, and a top electrode material, and then etch the bottom electrode, the resistive switching layer, and the top electrode material to form a memory cell composed of the bottom electrode, the resistive switching layer, and the top electrode. However, due to the relatively thick thicknesses of the bottom electrode, the resistive switching layer, and the top electrode, the alignment signal of the previous layer for overlay etching will be blocked, resulting in poor accuracy of the etching process. In addition, due to the relatively thick thicknesses of the bottom electrode, the resistive switching layer, and the top electrode, voids are likely to be generated in the interlayer dielectric layer when forming the dielectric layer covering the memory cell.

[0003] Therefore, it is necessary to provide a more effective and reliable technical solution to avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer.

[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a substrate in which a first metal layer is formed, forming a mask layer on the surfaces of the substrate and the first metal layer, and forming a bottom electrode in the mask layer that penetrates the mask layer and is electrically connected to the first metal layer; forming a first interlayer dielectric layer on the surfaces of the mask layer and the bottom electrode, where the first interlayer dielectric layer includes a first opening exposing the bottom electrode; sequentially forming a resistive switching layer and a top electrode at the bottom and sidewalls of the first opening, and the bottom electrode, the resistive switching layer, and the top electrode form a memory cell; forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer to cover the first interlayer dielectric layer and the memory cell, where the second interlayer dielectric layer includes a second opening exposing the top electrode; and forming a second metal layer in the second opening that is electrically connected to the top electrode.

[0006] In some embodiments of this application, the substrate includes a semiconductor substrate and a dielectric layer on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

[0007] In some embodiments of this application, the first opening partially or completely exposes the bottom electrode.

[0008] In some embodiments of this application, the thickness of the resistive switching layer at the bottom of the first opening is greater than the thickness of the resistive switching layer at the sidewalls of the first opening.

[0009] In some embodiments of the present application, the ratio of the thickness of the resistive switching layer at the bottom of the first opening to the thickness of the resistive switching layer on the sidewall of the first opening is 1:(0.1 - 1).

[0010] Another aspect of the present application further provides a semiconductor structure, including: a substrate, a first metal layer is formed in the substrate, a mask layer is formed on the surfaces of the substrate and the first metal layer, and a bottom electrode that penetrates the mask layer and is electrically connected to the first metal layer is formed in the mask layer; a first interlayer dielectric layer located on the surfaces of the mask layer and the bottom electrode, the first interlayer dielectric layer includes a first opening exposing the bottom electrode; a resistive switching layer and a top electrode sequentially located at the bottom and sidewalls of the first opening, the bottom electrode, the resistive switching layer and the top electrode constitute a memory cell; a second interlayer dielectric layer covering the first interlayer dielectric layer and the memory cell, the second interlayer dielectric layer includes a second opening exposing the top electrode; a second metal layer located in the second opening and electrically connected to the top electrode.

[0011] In some embodiments of the present application, the substrate includes a semiconductor substrate and a dielectric layer on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

[0012] In some embodiments of the present application, the first opening partially or completely exposes the bottom electrode.

[0013] In some embodiments of the present application, the thickness of the resistive switching layer at the bottom of the first opening is greater than the thickness of the resistive switching layer on the sidewall of the first opening.

[0014] In some embodiments of the present application, the ratio of the thickness of the resistive switching layer at the bottom of the first opening to the thickness of the resistive switching layer on the sidewall of the first opening is 1:(0.1 - 1).

[0015] The present application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching accuracy and improve the quality of the interlayer dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.

[0017] Wherein:

[0018] Figures 1 to 5 are schematic structural diagrams of each step in the method for forming the semiconductor structure according to the embodiments of the present application. Detailed implementation manners

[0019] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but has the broadest scope consistent with the claims.

[0020] The technical solution of the present invention will be described in detail below in conjunction with embodiments and the accompanying drawings.

[0021] Figures 1 to 5 It is a schematic structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application will be described in detail below in conjunction with the accompanying drawings.

[0022] Refer to Figure 1 As shown, a substrate is provided, and a first metal layer 120 is formed in the substrate.

[0023] In some embodiments of the present application, the substrate includes a semiconductor substrate 100 and a dielectric layer 110 on the surface of the semiconductor substrate 100, and the first metal layer 120 is located in the dielectric layer 110. The semiconductor substrate 100 may include active devices formed in the front-end semiconductor process.

[0024] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.

[0025] In some embodiments of the present application, the semiconductor substrate 100 includes a first region 101 and a second region 102. Among them, the first region 101 is used to form memory cells, and the second region 102 is used to form metal interconnect structures.

[0026] In some embodiments of the present application, the material of the dielectric layer 110 includes silicon oxide, etc. The dielectric layer 110 is used to form part of the metal interconnect structures in the back-end process. Among them, the metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any metal layer of the metal interconnect structure in the back-end process.

[0027] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. Here, in the present application, only two first metal layers 120 in the first region 101 and one first metal layer 120 in the second region 102 are taken as an example. The first metal layers 120 in the first region 101 are arranged according to the number of memory cells.

[0028] Continuing to refer to Figure 1 As shown, a mask layer 130 is formed on the surface of the substrate (specifically, the dielectric layer 110) and the first metal layer 120. A plurality of bottom electrodes 141 are formed in the mask layer 130 in the first region 101, penetrating through the mask layer 130 and electrically connecting the first metal layers 120 in the first region 101 respectively.

[0029] In some embodiments of the present application, the material of the mask layer 130 includes silicon nitride.

[0030] In some embodiments of the present application, the material of the bottom electrode 141 includes titanium nitride.

[0031] Referring to Figure 2 As shown, a first interlayer dielectric layer 150 is formed on the surface of the mask layer 130 and the bottom electrode 141. The first interlayer dielectric layer 150 includes a first opening 151 exposing the bottom electrode 141.

[0032] In some embodiments of the present application, the method of forming the first interlayer dielectric layer 150 includes: depositing a first dielectric layer 150 on the surface of the mask layer 130 and the bottom electrode 141; etching the first interlayer dielectric layer 150 by a photolithography process to form the first opening 151. The mask used in the photolithography process is the same as the mask for fabricating the metal interconnect structure (subsequent steps attached Figure 4 later) in the back-end process of logic devices.

[0033] In some embodiments of the present application, the material of the first interlayer dielectric layer 150 includes silicon oxide.

[0034] In some embodiments of the present application, the first opening 151 partially or completely exposes the bottom electrode 141. That is to say, the width of the first opening 151 can be greater than or equal to the width of the bottom electrode 141 to completely expose the bottom electrode 141; the width of the first opening 151 can also be less than the width of the bottom electrode 141 to partially expose the bottom electrode 141.

[0035] Referring to Figure 3 As shown, a resistive switching layer 142 and a top electrode 143 are sequentially formed at the bottom and sidewalls of the first opening 151. The bottom electrode 141, the resistive switching layer 142 and the top electrode 143 constitute a memory cell 140.

[0036] In some embodiments of the present application, the method of forming the resistive change layer 142 and the top electrode 143 includes: sequentially depositing a resistive change layer material and a top electrode material at the bottom and sidewalls of the first opening 151 and on the surface of the first interlayer dielectric layer 150 to fill the first opening 151; removing the portions of the resistive change layer material and the top electrode material outside the first opening 151 (above the surface of the first interlayer dielectric layer 150), and the remaining resistive change layer material and top electrode material in the first opening 151 form the resistive change layer 142 and the top electrode 143.

[0037] In some embodiments of the present application, the material of the resistive change layer 142 includes HfO2 and Ta2O5. The thickness of the resistive change layer 142 is 1 to 10 nanometers.

[0038] In some embodiments of the present application, the material of the top electrode 143 includes TiN, TaN, W, Ti, Ta, Al, Ir, Cu, etc. The thickness of the top electrode 143 is less than or equal to 100 nanometers.

[0039] In some embodiments of the present application, an oxygen transport layer (OEL) may be further formed at the bottom and sidewalls of the resistive change layer 142 (SWL) between the resistive change layer 142 and the bottom electrode 141. The material of the OEL layer includes Ta, TaOx, TaN, TaOxNy, TiOx, etc., where x and y are any positive integers. The thickness of the OEL layer is less than or equal to 50 nanometers.

[0040] Continue to refer to Figure 3 As shown, in some embodiments of the present application, the thickness of the resistive change layer 142 at the bottom of the first opening 151 is greater than the thickness of the resistive change layer 142 at the sidewalls of the first opening 151.

[0041] In some embodiments of the present application, the ratio of the thickness of the resistive change layer 142 at the bottom of the first opening 151 to the thickness of the resistive change layer 142 at the sidewalls of the first opening 151 is 1:(0.1 - 1) (excluding 1).

[0042] The memory cell 140 in the technical solution of the present application mainly includes a bottom electrode 141, a resistive change layer 142, and a top electrode 143 stacked in sequence. Therefore, the main part for realizing the function of the memory cell 140 is a stacked structure in the longitudinal direction. Therefore, the part of the resistive change layer at the bottom of the first opening is the main part, and the part of the resistive change layer at the sidewalls of the first opening is the secondary part. Therefore, the thickness of the resistive change layer at the bottom of the first opening should be greater than the thickness of the resistive change layer at the sidewalls of the first opening.

[0043] Refer to Figure 4As shown, a second interlayer dielectric layer 160 covering the first interlayer dielectric layer 150 and the memory cells 140 is formed on the surface of the first interlayer dielectric layer 150. The second interlayer dielectric layer 160 in the first region 101 includes a second opening 161 exposing the top electrode 143, and the second interlayer dielectric layer 160 in the second region 102 includes a third opening 162 penetrating through the second interlayer dielectric layer 160, the first interlayer dielectric layer 150, and the mask layer 130.

[0044] In some embodiments of the present application, the second opening 161 and the third opening 162 may be formed separately or simultaneously.

[0045] Reference Figure 5 As shown, a second metal layer 170 electrically connecting the top electrode 143 is formed in the second opening 161, and at the same time, a second metal layer 170 electrically connecting the first metal layer 120 in the second region 102 is also formed in the third opening 162. The second metal layer 170 and the first metal layer 120 in the second region 102 constitute the metal interconnect structure of the logic region.

[0046] In some embodiments of the present application, the material of the second metal layer 170 includes tungsten.

[0047] In the technical solution of the present application, reference Figure 2 and Figure 3 As shown, the memory cells are formed by first forming a first interlayer dielectric layer having a first opening, and then filling a resistive change layer and a top electrode in the first opening, instead of depositing the resistive change layer and the top electrode materials and then etching to form the resistive change layer and the top electrode, directly avoiding the etching process precision problem of the resistive change layer and the top electrode.

[0048] In the technical solution of the present application, both the first interlayer dielectric layer and the second interlayer dielectric layer are directly deposited on a flat surface. Therefore, void defects will not be generated in the first interlayer dielectric layer and the second interlayer dielectric layer, and the quality of the first interlayer dielectric layer and the second interlayer dielectric layer is guaranteed.

[0049] The present application provides a method for forming a semiconductor structure, which can avoid the problem of poor etching precision and improve the quality of the interlayer dielectric layer.

[0050] The present application also provides a semiconductor structure, reference Figure 5As shown, it includes: a substrate, in which a first metal layer 120 is formed; a mask layer 130 is formed on the surfaces of the substrate and the first metal layer 120; a bottom electrode 141 is formed in the mask layer 130, passing through the mask layer 130 and electrically connecting to the first metal layer 120; a first interlayer dielectric layer 150 is located on the surfaces of the mask layer 130 and the bottom electrode 141, and the first interlayer dielectric layer 150 includes a first opening exposing the bottom electrode 141; a resistive change layer 142 and a top electrode 143 are sequentially located at the bottom and sidewalls of the first opening, and the bottom electrode 141, the resistive change layer 142, and the top electrode 143 constitute a memory cell 140; a second interlayer dielectric layer 160 covers the first interlayer dielectric layer 150 and the memory cell 140, and the second interlayer dielectric layer 160 includes a second opening exposing the top electrode 143; a second metal layer 170 is located in the second opening and electrically connects to the top electrode 143.

[0051] In some embodiments of the present application, the substrate includes a semiconductor substrate 100 and a dielectric layer 110 on the surface of the semiconductor substrate 100, and the first metal layer 120 is located in the dielectric layer 110. The semiconductor substrate 100 may include active devices formed in the front-end semiconductor process.

[0052] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.

[0053] In some embodiments of the present application, the semiconductor substrate 100 includes a first region 101 and a second region 102. Among them, the first region 101 is used to form memory cells, and the second region 102 is used to form metal interconnect structures.

[0054] In some embodiments of the present application, the material of the dielectric layer 110 includes silicon oxide, etc. The dielectric layer 110 is used to form part of the metal interconnect structures in the back-end process. Among them, the metal interconnect structure is composed of several metal layers and vias, and the first metal layer 120 is any one of the metal layers in the back-end process metal interconnect structure.

[0055] In some embodiments of the present application, the number of the first metal layers 120 can be arbitrary. Here, in the present application, only two first metal layers 120 in the first region 101 and one first metal layer 120 in the second region 102 are taken as examples. The first metal layers 120 in the first region 101 are set according to the number of memory cells.

[0056] Continue to refer to Figure 5 As shown, a mask layer 130 is formed on the surface of the substrate (specifically, the dielectric layer 110) and the first metal layer 120, and a plurality of bottom electrodes 141 are formed in the mask layer 130 in the first region 101, penetrating through the mask layer 130 and electrically connecting to the first metal layer 120 in the first region 101 respectively.

[0057] In some embodiments of the present application, the material of the mask layer 130 includes silicon nitride.

[0058] In some embodiments of the present application, the material of the bottom electrode 141 includes titanium nitride.

[0059] Refer to Figure 2 and Figure 5 As shown, a first interlayer dielectric layer 150 is formed on the surfaces of the mask layer 130 and the bottom electrode 141. The first interlayer dielectric layer 150 includes a first opening 151 that exposes the bottom electrode 141.

[0060] In some embodiments of the present application, the material of the first interlayer dielectric layer 150 includes silicon oxide.

[0061] In some embodiments of the present application, the first opening 151 partially or completely exposes the bottom electrode 141. That is to say, the width of the first opening 151 can be greater than or equal to the width of the bottom electrode 141 to completely expose the bottom electrode 141; the width of the first opening 151 can also be less than the width of the bottom electrode 141 to partially expose the bottom electrode 141.

[0062] Continue to refer to Figure 5 As shown, a resistive switching layer 142 and a top electrode 143 are sequentially formed at the bottom and sidewalls of the first opening 151. The bottom electrode 141, the resistive switching layer 142, and the top electrode 143 constitute a memory cell 140.

[0063] In some embodiments of the present application, the material of the resistive switching layer 142 includes HfO2 and Ta2O5. The thickness of the resistive switching layer 142 is 1 to 10 nanometers.

[0064] In some embodiments of the present application, the material of the top electrode 143 includes TiN, TaN, W, Ti, Ta, Al, Ir, Cu, etc. The thickness of the top electrode 143 is less than or equal to 100 nanometers.

[0065] In some embodiments of the present application, an oxygen transport layer (OEL) may also be formed at the bottom and sidewalls of the resistive change layer 142 (SWL) between the resistive change layer 142 and the bottom electrode 141. The material of the OEL layer includes Ta, TaOx, TaN, TaOxNy, TiOx, etc., where x and y are any positive integers. The thickness of the OEL layer is less than or equal to 50 nanometers.

[0066] Continue to refer to Figure 5 As shown, in some embodiments of the present application, the thickness of the resistive change layer 142 at the bottom of the first opening 151 is greater than the thickness of the resistive change layer 142 on the sidewall of the first opening 151.

[0067] In some embodiments of the present application, the ratio of the thickness of the resistive change layer 142 at the bottom of the first opening 151 to the thickness of the resistive change layer 142 on the sidewall of the first opening 151 is 1:(0.1 - 1) (excluding 1).

[0068] The memory cell 140 in the technical solution of the present application mainly includes a bottom electrode 141, a resistive change layer 142, and a top electrode 143 stacked in sequence. Therefore, the main part for realizing the function of the memory cell 140 is a structure stacked in the longitudinal direction. Therefore, the part of the resistive change layer located at the bottom of the first opening is the main part, and the part of the resistive change layer located on the sidewall of the first opening is the secondary part. Therefore, the thickness of the resistive change layer at the bottom of the first opening should be greater than the thickness of the resistive change layer on the sidewall of the first opening.

[0069] Continue to refer to Figure 5 As shown, a second interlayer dielectric layer 160 covering the first interlayer dielectric layer 150 and the memory cell 140 is formed on the surface of the first interlayer dielectric layer 150. The second interlayer dielectric layer 160 in the first region 101 includes a second opening 161 exposing the top electrode 143, and the second interlayer dielectric layer 160 in the second region 102 includes a third opening 162 penetrating through the second interlayer dielectric layer 160, the first interlayer dielectric layer 150, and the mask layer 130.

[0070] Continue to refer to Figure 5 As shown, a second metal layer 170 electrically connecting to the top electrode 143 is formed in the second opening 161, and a second metal layer 170 electrically connecting to the first metal layer 120 in the second region 102 is formed in the third opening 162. The second metal layer 170 and the first metal layer 120 in the second region 102 constitute the metal interconnect structure in the logic region.

[0071] In some embodiments of the present application, the material of the second metal layer 170 includes tungsten.

[0072] In the technical solution of the present application, a first interlayer dielectric layer having a first opening is first formed, and then a resistive change layer and a top electrode are filled in the first opening to form a memory cell, instead of depositing a resistive change layer and a top electrode material and then etching to form a resistive change layer and a top electrode, directly avoiding the etching process precision problem of the resistive change layer and the top electrode.

[0073] In the technical solution of the present application, both the first interlayer dielectric layer and the second interlayer dielectric layer are directly deposited on a flat surface. Therefore, void defects will not be generated in the first interlayer dielectric layer and the second interlayer dielectric layer, and the quality of the first interlayer dielectric layer and the second interlayer dielectric layer is guaranteed.

[0074] The present application provides a semiconductor structure and a method for forming the same, which can avoid the problem of poor etching precision and improve the quality of the interlayer dielectric layer.

[0075] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0076] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0077] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recorded features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.

[0078] It should also be understood that although terms such as first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0079] In addition, the specification of the present application describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Thus, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, a first metal layer is formed in the substrate, a mask layer is formed on the surfaces of the substrate and the first metal layer, and a bottom electrode penetrating the mask layer and electrically connecting the first metal layer is formed in the mask layer; Forming a first interlayer dielectric layer on the surfaces of the mask layer and the bottom electrode, and the first interlayer dielectric layer includes a first opening exposing the bottom electrode; Successively forming a resistive change layer and a top electrode at the bottom and sidewalls of the first opening, and the bottom electrode, the resistive change layer and the top electrode constitute a memory cell; Forming a second interlayer dielectric layer on the surface of the first interlayer dielectric layer to cover the first interlayer dielectric layer and the memory cell, and the second interlayer dielectric layer includes a second opening exposing the top electrode; Forming a second metal layer in the second opening to electrically connect the top electrode.

2. The method for forming a semiconductor structure according to claim 1, wherein The substrate includes a semiconductor substrate and a dielectric layer on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

3. The method for forming a semiconductor structure according to claim 1, wherein, The first opening partially or completely exposes the bottom electrode.

4. The method for forming a semiconductor structure according to claim 1, wherein The thickness of the resistive change layer at the bottom of the first opening is greater than the thickness of the resistive change layer at the sidewall of the first opening.

5. The method for forming a semiconductor structure according to claim 4, wherein The ratio of the thickness of the resistive change layer at the bottom of the first opening to the thickness of the resistive change layer at the sidewall of the first opening is 1:(0.1 - 1).

6. A semiconductor structure, characterized in that, Including: A substrate, a first metal layer is formed in the substrate, a mask layer is formed on the surfaces of the substrate and the first metal layer, and a bottom electrode penetrating the mask layer and electrically connecting the first metal layer is formed in the mask layer; A first interlayer dielectric layer, located on the surfaces of the mask layer and the bottom electrode, and the first interlayer dielectric layer includes a first opening exposing the bottom electrode; A resistive change layer and a top electrode successively located at the bottom and sidewalls of the first opening, and the bottom electrode, the resistive change layer and the top electrode constitute a memory cell; A second interlayer dielectric layer, covering the first interlayer dielectric layer and the memory cell, and the second interlayer dielectric layer includes a second opening exposing the top electrode; A second metal layer, located in the second opening to electrically connect the top electrode.

7. The semiconductor structure according to claim 6, wherein The substrate includes a semiconductor substrate and a dielectric layer on the surface of the semiconductor substrate, and the first metal layer is located in the dielectric layer.

8. The semiconductor structure according to claim 6, wherein, The first opening partially or completely exposes the bottom electrode.

9. The semiconductor structure according to claim 6, wherein The thickness of the resistive change layer at the bottom of the first opening is greater than the thickness of the resistive change layer at the sidewall of the first opening.

10. The semiconductor structure according to claim 9, wherein, The ratio of the thickness of the resistive change layer at the bottom of the first opening to the thickness of the resistive change layer at the sidewall of the first opening is 1:(0.1 - 1).

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