Manufacturing method of MIM capacitor
By first etching the lower plate metal layer and etching part of the inter-plate dielectric layer in the MIM capacitor production, the photoresist layer problem caused by uneven thickness of the intermediate dielectric layer is solved, and the reliability of the capacitor and the yield of the wafer edge are improved.
Patent Information
- Application Number
- CN202510397035.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-31
- Publication Date
- 2025-07-01
AI Technical Summary
During the production process of MIM capacitors, the thickness unevenness of the intermediate dielectric layer causes the window of the photoresist layer to tilt or collapse, affecting the reliability of the capacitor and the wafer edge yield.
First etch the patterned lower plate metal layer to form open holes, and then etch the inter-plate dielectric layer with a thickness of part to ensure that the intermediate dielectric layer is not side-exposed, and avoid the formation of an anti-reflective film and photoresist layer, and directly form the upper plate.
Improves the reliability of MIM capacitors and wafer edge yield to ensure wafer flatness.
Smart Images
Figure CN120239286A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and particularly relates to a method for manufacturing a MIM capacitor. Background Art
[0002] In semiconductor integrated circuits, capacitors are essential components in analog chips and radio frequency chips, and the accuracy of capacitors often directly affects the performance of the entire chip. In view of this, integrating metal-insulator-metal (MIM) capacitors in the back-end process of integrated circuits has become a common choice for high-performance analog and radio frequency chips.
[0003] Figure 1 As a positive example of the formation of a MIM capacitor, as Figure 1 shown, the MIM capacitor structure includes a lower electrode 01 located above the wafer substrate. An intermediate dielectric layer 02 and an upper electrode 03 are sequentially formed on the lower electrode 01. In the manufacturing process, a part of the thickness of the intermediate dielectric layer on the right side is etched away, and the remaining thickness of the intermediate dielectric layer is retained to prevent the final dielectric layer of the capacitor from being undercut. Figure 2 As a negative example of the formation of a MIM capacitor, as Figure 2 shown, a part of the intermediate dielectric layer 02 with the full thickness on the right side is etched away by a plurality of methods. There is an undercut phenomenon during the etching process, and a part of the right side surface of the remaining intermediate dielectric layer is etched away, thus affecting the reliability of the capacitor. On the basis of Figure 1 , then Figure 3 shown, an anti-reflection film 04 covering the upper electrode 03 and the remaining intermediate dielectric layer 02 is formed, and a photoresist layer 05 covering the anti-reflection film 04 is formed.
[0004] To prevent undercut, it is necessary to retain a part of the thickness of the intermediate dielectric layer 02 on the right side. The material of the intermediate dielectric layer 02 is silicon nitride, but the thickness uniformity of the remaining intermediate dielectric layer (silicon nitride) on the right side is poor, which ultimately leads to the window C pattern in the upper photoresist layer 05 being prone to tilt or collapse. Subsequently, as Figure 4 shown, using the photoresist layer 05 as a mask, the anti-reflection film 04, the remaining intermediate dielectric layer 02, and the lower electrode 01 exposed by the etched window C are etched, and the lower electrode 01 is patterned to form a plurality of openings K. The window C pattern in the photoresist layer 05 is prone to tilt or collapse, resulting in poor flatness of the wafer after etching, especially the unevenness of the wafer edge, causing a low yield at the wafer edge. Summary of the Invention
[0005] The object of the present invention is to provide a manufacturing method of a MIM capacitor. First, the patterned lower electrode metal layer is etched to form openings, thereby forming the lower electrode of the capacitor; subsequently, a part of the thickness of the interlayer dielectric layer is etched, and the remaining thickness of the interlayer dielectric layer prevents poor reliability caused by side etching of the intermediate dielectric layer of the capacitor; at the same time, it is ensured that the wafer where the MIM capacitor is located is flat, and the wafer edge is also flat, improving the yield of the wafer edge.
[0006] The present invention provides a manufacturing method of a MIM capacitor, including:
[0007] Step S1: Provide a substrate, where the substrate includes a capacitor region and a peripheral region; sequentially form a first dielectric layer, a lower electrode metal layer, and an anti-reflection film layer on the substrate; etch the anti-reflection film layer and the lower electrode metal layer to form openings and expose the first dielectric layer; the lower electrode metal layer remaining in the capacitor region after etching serves as the lower electrode of the capacitor.
[0008] Step S2: Form a second dielectric layer filling the openings.
[0009] Step S3: Form an interlayer dielectric layer, where the interlayer dielectric layer covers the second dielectric layer and the lower electrode metal layer.
[0010] Step S4: Form an upper electrode metal layer covering the interlayer dielectric layer.
[0011] Step S5: Form a mask layer on the surface of the upper electrode metal layer, where the mask layer only covers the area corresponding to the upper electrode of the capacitor; using the mask layer as a mask, etch all the exposed thickness of the upper electrode metal layer and a part of the thickness of the interlayer dielectric layer; the remaining upper electrode metal layer after etching serves as the upper electrode.
[0012] Further, in step S1, a plurality of the openings are etched to separate the lower electrode metal layers located in the capacitor region and the peripheral region and form preset metal lines for the lower electrode metal layer located in the peripheral region.
[0013] Further, the lower electrode metal layer includes a Ti and / or TiN bottom thin film, an Al and / or Cu intermediate thin film, and a Ti and / or TiN top thin film from bottom to top.
[0014] Further, in step S2, it specifically includes:
[0015] Form a second dielectric layer material layer, where the second dielectric layer material layer covers the anti-reflection film layer and fills the openings.
[0016] Perform a chemical mechanical polishing process until the upper surface of the lower electrode metal layer is exposed, polish away the anti-reflection film layer and the second dielectric layer material layer that is higher than the lower electrode metal layer, and the remaining second dielectric layer material layer serves as the second dielectric layer.
[0017] Further, in step S3, the inter-plate dielectric layer is formed by any one of chemical vapor deposition, physical vapor deposition, or atomic layer deposition.
[0018] Further, in step S3, the material of the inter-plate dielectric layer includes at least one of silicon nitride, silicon oxynitride, HFO2, ZrO, Al2O3, and ZrO.
[0019] Further, in step S4, the material of the upper electrode metal layer includes at least one of copper, aluminum, tungsten, Ti, and TiN.
[0020] Further, in step S5, the upper electrode is located in the capacitor region; and the width of the upper electrode is less than or equal to the width of the capacitor region.
[0021] Further, in step S5, the thickness of the remaining inter-plate dielectric layer after etching is 1 / 5 to 2 / 3 of the initial thickness of the inter-plate dielectric layer.
[0022] Further, in step S1, the etching process uses dry etching, and the dry etching includes any one of reactive ion etching, ion beam etching, and plasma etching.
[0023] Compared with the prior art, the present invention has the following beneficial effects:
[0024] The present invention provides a method for manufacturing a MIM capacitor, including: step S1, providing a substrate, the substrate including a capacitor region and a peripheral region; sequentially forming a first dielectric layer, a lower electrode metal layer, and an anti-reflection film layer on the substrate; etching the anti-reflection film layer and the lower electrode metal layer to form an opening and expose the first dielectric layer; step S2, forming a second dielectric layer to fill the opening; step S3, forming an inter-plate dielectric layer, the inter-plate dielectric layer covering the second dielectric layer and the lower electrode metal layer; step S4, forming an upper electrode metal layer covering the inter-plate dielectric layer; step S5, forming a mask layer on the surface of the upper electrode metal layer, the mask layer only covering the region corresponding to the upper electrode of the capacitor; using the mask layer as a mask, etching the exposed entire thickness of the upper electrode metal layer and a partial thickness of the inter-plate dielectric layer; etching the remaining upper electrode metal layer to serve as the upper electrode.
[0025] The present invention first etches the patterned lower electrode metal layer to form an opening, thereby forming the lower electrode of the capacitor; subsequently, a part of the thickness of the inter-plate dielectric layer is etched, and the remaining thickness of the inter-plate dielectric layer prevents poor reliability caused by side etching of the intermediate dielectric layer of the capacitor; while ensuring the reliability of the capacitor with the remaining thickness of the inter-plate dielectric layer, since the lower electrode metal layer has been patterned to form the lower electrode previously, even if there is still a problem of uneven thickness in the remaining thickness of the inter-plate dielectric layer, there is no longer a need to form an anti-reflection film and a photoresist layer to pattern the lower electrode metal layer later, avoiding the tilt or collapse of the photoresist layer caused by the uneven thickness of the remaining thickness of the inter-plate dielectric layer. In this way, after completing the step of forming the upper electrode, the fabrication of the MIM capacitor is completed, ensuring that the wafer where the MIM capacitor is located is flat and the wafer edge is also flat, improving the yield of the wafer edge. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figures 1 to 4 Schematic diagrams of the steps of a method for fabricating a MIM capacitor.
[0027] Figure 5 Schematic flow diagram of the method for fabricating a MIM capacitor according to an embodiment of the present invention.
[0028] Figures 6 to 10 Schematic diagrams of the steps of the method for fabricating a MIM capacitor according to an embodiment of the present invention.
[0029] Among them, the reference numerals are as follows:
[0030] 01 - lower electrode; 02 - intermediate dielectric layer; 03 - upper electrode; 04 - anti-reflection film; 05 - photoresist layer; C - window; K - opening;
[0031] 10 - first dielectric layer; 20 - lower electrode metal layer; 21 - bottom thin film; 22 - intermediate thin film; 23 - top thin film; A - anti-reflection film layer; I - capacitor region; II - peripheral region; B - second dielectric layer material layer; D - second dielectric layer; 30 - inter-plate dielectric layer; 40 - upper electrode metal layer; 50 - mask layer; 41 - upper electrode; 31 - remaining inter-plate dielectric layer. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0032] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.
[0033] For ease of description, some embodiments of the present application may use spatial relative terms such as "above", "below", "top", "bottom", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the respective drawings of the embodiments. It should be understood that, in addition to the orientations described in the drawings, spatial relative terms are also intended to include different orientations during the use or operation of the device. For example, if the device in the drawing is flipped, an element or component described as "below" or "beneath" other elements or components will subsequently be positioned "above" or "over" the other elements or components. The terms "first", "second", etc. in the following text are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence. It is to be understood that these terms may be replaced where appropriate.
[0034] An embodiment of the present invention provides a method for manufacturing a MIM capacitor, as Figure 5 shown, including:
[0035] Step S1: Provide a substrate, the substrate including a capacitor region and a peripheral region; sequentially form a first dielectric layer, a lower electrode metal layer, and an antireflection film layer on the substrate; etch the antireflection film layer and the lower electrode metal layer to form an opening and expose the first dielectric layer; the lower electrode metal layer remaining in the capacitor region after etching serves as the lower electrode of the capacitor;
[0036] Step S2: Form a second dielectric layer to fill the opening;
[0037] Step S3: Form an inter-plate dielectric layer, the inter-plate dielectric layer covering the second dielectric layer and the lower electrode metal layer;
[0038] Step S4: Form an upper electrode metal layer covering the inter-plate dielectric layer;
[0039] Step S5: Form a mask layer on the surface of the upper electrode metal layer, the mask layer only covering the region corresponding to the upper electrode of the capacitor; using the mask layer as a mask, etch the entire thickness of the exposed upper electrode metal layer and a partial thickness of the inter-plate dielectric layer; the remaining upper electrode metal layer after etching serves as the upper electrode.
[0040] The following combines Figures 6 to 10 to introduce in detail each step of the method for manufacturing a semiconductor device according to an embodiment of the present invention.
[0041] Step S1: As Figure 6As shown, a substrate (not shown) is provided, which includes a capacitor region I and a peripheral region II; a first dielectric layer 10, a lower plate metal layer 20, and an anti-reflection film layer A are sequentially formed on the substrate; the lower plate metal layer 20 is etched and patterned to form an opening (gap) in the lower plate metal layer 20, so that the lower plate metal layers 20 in the capacitor region I and the peripheral region II are spaced apart and the lower plate metal layer 20 in the peripheral region II forms a preset metal line; the lower plate metal layer 20 remaining in the capacitor region I after etching serves as the lower plate of the capacitor.
[0042] Exemplarily, the substrate can be at least one of the materials mentioned below: single crystal silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc. An isolation structure (not shown) is also formed in the substrate, and the isolation structure is a shallow trench isolation (STI) structure or a local oxidation of silicon (LOCOS) isolation structure. The isolation structure divides the substrate into different active regions, and various semiconductor devices, such as NMOS and PMOS, etc., can be formed in the active regions.
[0043] The forming method of the lower plate metal layer 20 can be one of chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, laser ablation deposition (LAD), and selective epitaxial growth (SEG). The material of the lower plate includes at least one of copper, aluminum, tungsten, TiAl, and TiN, as well as other suitable metal materials. In one example, the lower plate is, for example, an Al thin film or a Cu thin film. In another example, the lower plate is, for example, a bottom Ti and / or TiN thin film 21, an Al and / or Cu intermediate thin film 22, and a top Ti and / or TiN thin film 23 from bottom to top.
[0044] An anti-reflection film layer A covering the lower plate metal layer 20 is formed. The material of the anti-reflection film layer A is, for example, silicon oxynitride (SiON). The deposition method of the anti-reflection film layer A can be selected from chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, etc. A photoresist layer (not shown) with a defined opening pattern is formed on the anti-reflection film layer A by photolithography process. The photoresist layer can be a photoresist formed by spin coating process, and then formed through processes such as exposure, development, and cleaning. Then, using this photoresist layer as a mask, the anti-reflection film layer A and the lower plate metal layer 20 are etched in different parts respectively until the first dielectric layer 10 is exposed, forming openings (gaps) in the lower plate metal layer 20, separating the lower plate metal layer 20 in the capacitor region I and the peripheral region II, and forming a preset metal line for the lower plate metal layer 20 in the peripheral region; the lower plate metal layer 20 remaining in the capacitor region I after etching serves as the lower plate of the capacitor. Dry etching can be used, and dry etching includes but is not limited to: reactive ion etching (RIE), ion beam etching, and plasma etching.
[0045] Step S2: Form a second dielectric layer, and the second dielectric layer fills the opening. Specifically, as Figure 7 shown, a second dielectric layer material layer B is formed. The second dielectric layer material layer B covers the anti-reflection film layer A and fills the opening. The deposition method of the second dielectric layer material layer B can be selected from chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, etc. In the present invention, chemical vapor deposition (CVD) method is preferably used, and the material of the second dielectric layer includes but is not limited to silicon dioxide (SiO2).
[0046] As Figure 8 shown, a chemical mechanical polishing process is performed until the upper surface of the lower plate metal layer 20 is exposed. The anti-reflection film layer A and the second dielectric layer material layer B higher than the lower plate metal layer 20 are polished away, and the remaining second dielectric layer material layer serves as the second dielectric layer D.
[0047] Step S3: As Figure 9 shown, an inter-plate dielectric layer 30 is formed. The inter-plate dielectric layer 30 covers the second dielectric layer D and the etched lower plate metal layer 20. The deposition method of the inter-plate dielectric layer 30 can be selected from chemical vapor deposition (CVD) method, physical vapor deposition (PVD) method, atomic layer deposition (ALD) method, etc. The material of the inter-plate dielectric layer 30 includes at least one of silicon nitride (Si3N4), silicon oxynitride (SiON), HFO2, ZrO, Al2O3, and ZrO, as well as other suitable materials.
[0048] Step S4: Form the upper electrode metal layer 40 covering the inter-plate dielectric layer 30. The forming method of the upper electrode metal layer 40 is the same as that of the lower electrode metal layer 20, which will not be elaborated here. The material of the upper electrode metal layer 40 can be selected from at least one of copper, aluminum, tungsten, Ti, and TiN, as well as other suitable metal materials. In one example, the upper electrode metal layer 40 is, for example, a Ti and / or TiN thin film.
[0049] Step S5: As Figure 9 and Figure 10 shown, form a mask layer 50 on the surface of the upper electrode metal layer 40. The mask layer 50 only covers the area corresponding to the upper electrode 41 of the capacitor; the mask layer 50 exposes the area outside the upper electrode 41. Using the mask layer 50 as a mask, etch the entire thickness of the upper electrode metal layer 40 and a partial thickness of the inter-plate dielectric layer 30 exposed by the mask layer 50 to form the upper electrode 41 and the remaining inter-plate dielectric layer 31; etch the remaining upper electrode metal layer as the upper electrode 41; the upper electrode 41 is located in the capacitor region I and the width of the upper electrode 41 is less than or equal to the width of the capacitor region I.
[0050] In the present invention, only a partial thickness of the inter-plate dielectric layer 30 exposed by the mask layer 50 is etched. If the entire thickness of the inter-plate dielectric layer exposed by the mask layer is etched, during the dry etching process, the sidewalls of the remaining inter-plate dielectric layer will be etched and undercut, forming a concave sidewall shape (as Figure 2 shown), which affects the reliability of the capacitor.
[0051] In summary, the present invention provides a method for manufacturing a MIM capacitor, including: Step S1: Provide a substrate, the substrate includes a capacitor region and a peripheral region; sequentially form a first dielectric layer, a lower electrode metal layer, and an anti-reflection film layer on the substrate; etch the anti-reflection film layer and the lower electrode metal layer to form an opening and expose the first dielectric layer; Step S2: Form a second dielectric layer filling the opening; Step S3: Form an inter-plate dielectric layer, the inter-plate dielectric layer covering the second dielectric layer and the lower electrode metal layer; Step S4: Form an upper electrode metal layer covering the inter-plate dielectric layer; Step S5: Form a mask layer on the surface of the upper electrode metal layer, the mask layer only covering the area corresponding to the upper electrode of the capacitor; using the mask layer as a mask, etch the entire thickness of the exposed upper electrode metal layer and a partial thickness of the inter-plate dielectric layer; etch the remaining upper electrode metal layer as the upper electrode.
[0052] In the present invention, the patterned lower plate metal layer is first etched to form an opening, thereby forming the lower plate of the capacitor; subsequently, a part of the thickness of the inter-plate dielectric layer is etched, and the remaining thickness of the inter-plate dielectric layer prevents poor reliability caused by side etching of the intermediate dielectric layer of the capacitor; while ensuring the reliability of the capacitor with the remaining thickness of the inter-plate dielectric layer, since the lower plate metal layer has been patterned to form the lower plate previously, even if there is still a problem of uneven thickness in the remaining thickness of the inter-plate dielectric layer, there is no need to form an anti-reflection film and a photoresist layer to pattern the lower plate metal layer later, avoiding the tilt or collapse of the photoresist layer caused by the uneven thickness of the remaining thickness of the inter-plate dielectric layer. In this way, after completing the step of forming the upper plate, the fabrication of the MIM capacitor is completed, ensuring that the wafer where the MIM capacitor is located is flat and the wafer edge is also flat, improving the yield of the wafer edge.
[0053] The various embodiments in this specification are described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the methods disclosed in the embodiments, since they correspond to the devices disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description in the method part.
[0054] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the rights of the present invention in any way. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.
Claims
1. A method for manufacturing a MIM capacitor, characterized in that: include: Step S1, providing a substrate, wherein the substrate includes a capacitor region and a peripheral region; forming a first dielectric layer, a lower plate metal layer and an anti-reflection film layer on the substrate in sequence; Etching the anti-reflection film layer and the lower plate metal layer to form an opening and expose the first dielectric layer; The lower plate metal layer remaining in the capacitor area after etching serves as the lower plate of the capacitor; Step S2, forming a second dielectric layer filling the opening; Step S3, forming an inter-plate dielectric layer, wherein the inter-plate dielectric layer covers the second dielectric layer and the lower plate metal layer; Step S4, forming an upper plate metal layer covering the inter-plate dielectric layer; Step S5, forming a mask layer located on the surface of the upper electrode plate metal layer, wherein the mask layer only covers the area corresponding to the upper electrode plate of the capacitor; Using the mask layer as a mask, etching the exposed upper plate metal layer of the entire thickness and the inter-plate dielectric layer of a partial thickness; The remaining upper electrode plate metal layer is etched to form the upper electrode plate.
2. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S1, a plurality of openings are formed by etching, so that the lower electrode metal layer located in the capacitor region and the lower electrode metal layer located in the peripheral region are separated and the lower electrode metal layer located in the peripheral region forms a preset metal line.
3. The method for manufacturing a MIM capacitor according to claim 1, wherein: The lower plate metal layer includes, from bottom to top, a Ti and / or TiN bottom film, an Al and / or Cu middle film, and a Ti and / or TiN top film.
4. The method for manufacturing a MIM capacitor according to claim 1, wherein: Step S2 specifically includes: forming a second dielectric material layer, wherein the second dielectric material layer covers the anti-reflection film layer and fills the opening; A chemical mechanical polishing process is performed to polish until the upper surface of the lower plate metal layer is exposed, and the anti-reflection film layer and the second dielectric layer material layer higher than the lower plate metal layer are polished away, and the remaining second dielectric layer material layer is used as the second dielectric layer.
5. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S3, the inter-plate dielectric layer is formed by any one of chemical vapor deposition, physical vapor deposition or atomic layer deposition.
6. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S3, the material of the inter-plate dielectric layer includes at least one of silicon nitride, silicon oxynitride, HFO2, ZrO, Al2O3 and ZrO.
7. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S4, the material of the upper plate metal layer includes at least one of copper, aluminum, tungsten, Ti and TiN.
8. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S5, the upper electrode plate is located in the capacitor region; and the width of the upper electrode plate is less than or equal to the width of the capacitor region.
9. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S5, the thickness of the inter-board dielectric layer remaining after etching is 1 / 5 to 2 / 3 of the initial thickness of the inter-board dielectric layer.
10. The method for manufacturing a MIM capacitor according to claim 1, wherein: In step S1, the etching process adopts dry etching, and the dry etching includes: any one of reactive ion etching, ion beam etching and plasma etching.