Semiconductor device and manufacturing method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. The semiconductor device comprises a semiconductor body which comprises a first surface and a second surface which are oppositely arranged; the semiconductor body further comprises n epitaxial regions, and the first epitaxial region, the second epitaxial region,..., and the nth epitaxial region are sequentially arranged in the direction from the first surface to the second surface. The semiconductor body further comprises (n-1) well regions, the first well region, the second well region,..., and the (n-1)-th well region are sequentially arranged in the direction from the first surface to the second surface, and the i-th well region and the i-th epitaxial region are arranged on the same layer and are adjacent to each other; the first surface of the semiconductor body is provided with a groove, and the groove at least penetrates to the interior of the (n-1) th well region; the well region and the epitaxial region are different in conduction type; the cathode is positioned on the second surface; the anode structure is located in the first surface and the groove. According to the invention, electric leakage caused by large damage to the semiconductor device is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in the fields of power electronics, automotive, aerospace, etc. due to their excellent high-temperature performance, chemical stability, and electronic characteristics.

[0003] In the prior art, a Schottky diode forms a well region by injecting with a high-energy ion implanter or by injecting at an inclined angle. The ion implantation with too high energy will cause great damage to the semiconductor device, thereby affecting the characteristics of the semiconductor device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle to avoid large damage to the semiconductor device resulting in leakage.

[0005] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes:

[0006] A semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes n epitaxial regions, where n is an integer greater than or equal to 3, and along the direction from the first surface to the second surface, the first epitaxial region, the second epitaxial region,... the nth epitaxial region are arranged in sequence;

[0007] The semiconductor body further includes n - 1 well regions, and along the direction from the first surface to the second surface, the first well region, the second well region,... the (n - 1)th well region are arranged in sequence. The ith well region and the ith epitaxial region are in the same layer and adjacent to each other; where i is an integer greater than or equal to 1 and less than or equal to n - 1;

[0008] A trench is provided on the first surface of the semiconductor body, and the trench penetrates at least into the interior of the (n - 1)th well region;

[0009] The conductivity types of the well regions and the epitaxial regions are different;

[0010] A cathode, located on the second surface;

[0011] An anode structure, located on the first surface and in the trench.

[0012] Further, the ion concentrations of the first epitaxial region to the (n - 1)th epitaxial region are all greater than the ion concentration of the nth epitaxial region.

[0013] Further, the ion concentrations of the first epitaxial region to the (n - 1)th epitaxial region gradually decrease.

[0014] Further, the sizes of the first well region to the (n - 1)-th well region gradually decrease in a direction parallel to the first surface.

[0015] Further, the sizes of the first well region to the (n - 2)-th well region are the same in a direction parallel to the first surface, and the size of the (n - 1)-th well region in a direction parallel to the first surface is smaller than that of the (n - 2)-th well region in a direction parallel to the first surface.

[0016] Further, the size range of the first well region to the (n - 2)-th well region in a direction parallel to the first surface is 0.4 - 0.6 μm.

[0017] Further, the anode structure includes a Schottky contact layer and an anode; the Schottky contact layer covers the first surface and the trench, and the anode is disposed on a side of the Schottky contact layer away from the semiconductor body.

[0018] Further, the semiconductor body includes 3 epitaxial regions and 2 well regions.

[0019] Further, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0020] According to another aspect of the present invention, a manufacturing method of a semiconductor device is provided, and the manufacturing method of the semiconductor device includes:

[0021] Providing a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body further includes n epitaxial regions, where n is an integer greater than or equal to 3, and in a direction from the first surface to the second surface, the first epitaxial region, the second epitaxial region,... the n-th epitaxial region are arranged in sequence; the semiconductor body further includes n - 1 well regions, and in a direction from the first surface to the second surface, the first well region, the second well region... the (n - 1)-th well region are arranged in sequence, and the i-th well region and the i-th epitaxial region are arranged in the same layer and adjacent to each other; where i is an integer greater than or equal to 1 and less than or equal to n - 1; forming a trench in the first surface of the semiconductor body, and the trench at least penetrates into the interior of the (n - 1)-th well region; the conductive types of the well region and the epitaxial region are different;

[0022] Forming a cathode on the second surface;

[0023] Forming an anode structure on the first surface and in the trench.

[0024] Further, providing the semiconductor body includes:

[0025] Providing a substrate;

[0026] Sequentially disposing the n-th epitaxial region and the (n - 1)-th epitaxial region on a side of the substrate away from the second surface;

[0027] Ion implant the (n - 1)th epitaxial region to form the (n - 1)th well region;

[0028] Sequentially dispose the (n - 2)th epitaxial region to the first epitaxial region on the side of the (n - 1)th epitaxial region away from the substrate. After each epitaxial region is formed, ion implant the epitaxial region to form a well region, so as to form the (n - 2)th well region to the first well region, and the (n - 2)th epitaxial region to the first epitaxial region;

[0029] Form a trench.

[0030] Further, after each epitaxial region is formed, ion implanting the epitaxial region to form a well region includes:

[0031] Form a first mask layer on the surface of the epitaxial region; wherein, the first mask layer includes a first through hole;

[0032] Ion implant the epitaxial region through the first through hole to form a well region;

[0033] Forming a trench includes:

[0034] Form a second mask layer on the surface of the first mask layer used for forming the first well region; wherein, the second mask layer includes a second through hole;

[0035] Etch the first well region to the (n - 1)th well region through the second through hole to form a trench.

[0036] Further, the thickness range of the second mask layer is 0.4 - 0.6 μm.

[0037] Further, forming an anode structure on the first surface and in the trench includes:

[0038] Form a first metal layer on the first surface and in the trench;

[0039] Form a second metal layer on the side of the first metal layer away from the semiconductor body;

[0040] Perform Schottky annealing treatment on the first metal layer and the second metal layer to form a Schottky contact layer and an anode.

[0041] According to another aspect of the present invention, there is provided a power module, which includes a substrate and at least one of the above semiconductor devices, and the substrate is used to carry the semiconductor device.

[0042] According to another aspect of the present invention, there is provided a power conversion circuit, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0043] The power conversion circuit includes a circuit board and at least one of the above semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0044] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit. The power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load.

[0045] In the technical solution of the embodiment of the present invention, by setting n epitaxial regions and n - 1 well regions, the i-th well region and the i-th epitaxial region are arranged on the same layer and adjacent to each other. During the process of forming the well regions, it is necessary to first form the (n - 1)-th epitaxial layer and the n-th epitaxial layer on the substrate, then perform ion implantation on the (n - 1)-th epitaxial layer to form the (n - 1)-th well region, and sequentially form (n - 2) epitaxial layers and (n - 2) well regions. Each time, only one relatively thin epitaxial region needs to be subjected to ion implantation. Compared with the prior art in which a well region surrounding a trench is formed by injecting ions through a high-energy ion implanter or a well region surrounding a trench is formed by injecting at an inclined angle, the equipment capability requirements for the ion implanter are lower, avoiding the phenomenon of large damage to semiconductor devices caused by high-energy ion implantation and resulting in leakage. Moreover, a trench is formed on the first surface of the semiconductor body, and the trench at least penetrates into the interior of the (n - 1)-th well region. In the reverse bias state, compared with a planar junction barrier Schottky diode, a thicker depletion region can be formed between two adjacent trenches, improving the breakdown voltage of the semiconductor device, and thus playing a role in protecting the semiconductor device.

[0046] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0048] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0049] Figure 2 is a flowchart of a manufacturing method of a semiconductor device provided according to an embodiment of the present invention;

[0050] Figure 3 is a corresponding cross-sectional view of the manufacturing method steps of a semiconductor device provided according to an embodiment of the present invention;

[0051] Figure 4It is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0052] Figures 5 - 12 It is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order other than those illustrated or described here. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0055] An embodiment of the present invention provides a semiconductor device, Figure 1 It is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention. Refer to Figure 1, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further includes n epitaxial regions 110, where n is an integer greater than or equal to 3, and along the direction from the first surface 101 to the second surface 102, the first epitaxial region 10, the second epitaxial region 20,... the nth epitaxial region are arranged in sequence; the semiconductor body 100 further includes n - 1 well regions 103, and along the direction from the first surface 101 to the second surface 102, the first well region 11, the second well region 12,... the (n - 1)th well region are arranged in sequence, and the ith well region and the ith epitaxial region are arranged in the same layer and adjacent to each other; where i is an integer greater than or equal to 1 and less than or equal to n - 1; a trench 104 is provided on the first surface 101 of the semiconductor body 100, and the trench 104 penetrates at least into the interior of the (n - 1)th well region; the conductive types of the well region 103 and the epitaxial region 110 are different; a cathode 120 is located on the second surface 102; an anode structure 130 is located on the first surface 101 and in the trench 104.

[0056] Specifically, in the embodiment of the present invention, the semiconductor device is a trench-type junction barrier Schottky diode, and the semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. The epitaxial region 110 is an N+ epitaxial region, and the N-type doping ions in the N+ epitaxial region may be phosphorus (P) ions or nitrogen (N) ions, and the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. As Figure 1 shown, the semiconductor body 100 may further include a substrate 105, and the epitaxial region 110 is a semiconductor layer formed on the basis of the substrate 105 through multiple epitaxial processes, and the epitaxial processes include chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE) and other processes. The semiconductor body 100 includes n - 1 well regions 103, and the adjacent well regions 103 are in contact with each other. The trench 104 penetrating at least into the interior of the (n - 1)th well region can be understood as the trench 104 needs to penetrate through the first well region 11 to the (n - 2)th well region and penetrate into part of the (n - 1)th well region.

[0057] Exemplarily, such as Figure 1As shown, the semiconductor device may only include three epitaxial regions 110 and two well regions 103, namely the first epitaxial region 10, the second epitaxial region 20, the third epitaxial region 30, the first well region 11, and the second well region 12. In the embodiment of the present invention, the semiconductor device including three epitaxial regions 110 and two well regions 103 is taken as an example for description, and the specific description is as follows: During the process of manufacturing the semiconductor device, after the second epitaxial layer 20 and the third epitaxial layer 30 are formed on the substrate 105, ion implantation is performed on the second epitaxial layer 20 to form the second well region 12, and the first epitaxial layer 10 and the first well region 11 are sequentially formed. During the process of forming the well region, ion implantation only needs to be performed on one relatively thin epitaxial region each time, and at this time, the equipment capacity requirement for the ion implanter is relatively low.

[0058] In the technical solution of the embodiment of the present invention, by setting n epitaxial regions 110 and n - 1 well regions 103, the i-th well region and the i-th epitaxial region are arranged on the same layer and adjacent to each other. During the process of forming the well region, after the (n - 1)-th epitaxial layer and the n-th epitaxial layer are formed on the substrate 105, ion implantation is performed on the (n - 1)-th epitaxial layer to form the (n - 1)-th well region, and (n - 2) epitaxial layers and (n - 2) well regions are sequentially formed. Ion implantation only needs to be performed on one relatively thin epitaxial region each time. Compared with the prior art in which a well region surrounding a trench is formed by injecting with a high-energy ion implanter or a well region surrounding a trench is formed by injecting at an inclined angle, the equipment capacity requirement for the ion implanter is relatively low, and the phenomenon of large damage to the semiconductor device caused by high-energy ion implantation and thus leakage is avoided. And a trench 104 is formed on the first surface 101 of the semiconductor body 100, and the trench 104 at least penetrates into the interior of the (n - 1)-th well region. In the reverse bias state, compared with the planar junction barrier Schottky diode, a thicker depletion region can be formed between two adjacent trenches 104, improving the breakdown voltage of the semiconductor device, and thus playing a role in protecting the semiconductor device.

[0059] In other alternative embodiments of the present invention, the ion concentrations of the first epitaxial region 10 to the (n - 1)-th epitaxial region are all greater than the ion concentration of the n-th epitaxial region.

[0060] Specifically, since lateral depletion occurs between adjacent well regions 103, and by increasing the ion concentrations of the first epitaxial region 10 to the (n - 1)-th epitaxial region so that the ion concentrations of the first epitaxial region 10 to the (n - 1)-th epitaxial region are all greater than the ion concentration of the n-th epitaxial region, the on-resistance of the semiconductor device is reduced, and thus the forward conduction characteristics of the semiconductor device are optimized.

[0061] In other alternative embodiments of the present invention, the ion concentrations of the first epitaxial region 10 to the (n - 1)-th epitaxial region gradually decrease.

[0062] Specifically, in the direction from the second surface 102 to the first surface 101, the ion concentration of the epitaxial layer gradually increases, further reducing the on-resistance of the semiconductor device and further optimizing the forward conduction characteristics of the semiconductor device. And the ion concentration of the (n - 1)th epitaxial region is set to be less than that of the first epitaxial region to the (n - 2)th epitaxial region. In the reverse bias state, it is easier to form a depletion region between two adjacent (n - 1)th well regions, further increasing the breakdown voltage of the semiconductor device.

[0063] In other alternative embodiments of the present invention, the sizes of the first well region 11 to the (n - 1)th well region in the direction parallel to the first surface 101 gradually decrease.

[0064] Specifically, if the ion concentrations of the first epitaxial region 10 to the (n - 1)th epitaxial region gradually decrease, and the sizes of the first well region 11 to the (n - 1)th well region in the direction parallel to the first surface 101 are set to gradually decrease, under the condition of reducing the on-resistance of the semiconductor device, it is easier to form a depletion region between two adjacent well regions with higher concentrations in the reverse bias state, further improving the avalanche breakdown resistance of the semiconductor device.

[0065] In other alternative embodiments of the present invention, the sizes of the first well region 11 to the (n - 2)th well region in the direction parallel to the first surface 101 are the same, and the size of the (n - 1)th well region in the direction parallel to the first surface 101 is less than that of the (n - 2)th well region in the direction parallel to the first surface 101.

[0066] Specifically, setting the sizes of the first well region 11 to the (n - 2)th well region in the direction parallel to the first surface 101 to be the same simplifies the manufacturing process under the condition of reducing the on-resistance of the semiconductor device.

[0067] In other alternative embodiments of the present invention, the size range of the first well region to the (n - 2)th well region in the direction parallel to the first surface is 0.4 - 0.6 μm.

[0068] Specifically, setting a smaller well region size can ensure a larger-sized epitaxial region between two adjacent well regions, optimizing the forward conduction characteristics of the semiconductor device; at the same time, in the reverse bias state, it can ensure that the depletion region formed covers the area between two adjacent well regions, increasing the breakdown voltage of the semiconductor device, thereby playing a role in protecting the semiconductor device.

[0069] In other alternative embodiments of the present invention, the anode structure 130 includes a Schottky contact layer 131 and an anode 132; the Schottky contact layer 131 covers the first surface 101 and the trench 104, and the anode 132 is disposed on the side of the Schottky contact layer 131 away from the semiconductor body 100.

[0070] Specifically, a metal deposition layer is formed on the first surface 101 and the trench 104 by titanium metal deposition treatment or titanium nitride deposition treatment. Then, an anode 132 is formed on the side of the metal deposition layer away from the semiconductor body 100. The anode 132 can be made of metal aluminum. Finally, a Schottky contact layer 131 is formed through Schottky annealing treatment, improving the reliability and stability of the semiconductor device.

[0071] In other alternative embodiments of the present invention, the semiconductor body 100 includes three epitaxial regions 110 and two well regions 103, simplifying the process steps while avoiding the phenomenon of large damage to the semiconductor device caused by high-energy ion implantation and thus leakage.

[0072] In other alternative embodiments of the present invention, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0073] Among them, when the semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. When the semiconductor body 100 includes a gallium nitride semiconductor body, the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0074] Specifically, a silicon carbide MOSFET semiconductor device or a gallium nitride MOSFET semiconductor device has the advantages of high breakdown voltage, low on-resistance, and high frequency, which can further improve the performance of the semiconductor device.

[0075] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 2 It is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 3 It is a corresponding cross-sectional view of the steps of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figure 2 and Figure 3 , the method for manufacturing a semiconductor device includes:

[0076] S110. Provide a semiconductor body. The semiconductor body includes a first surface and a second surface that are oppositely arranged; the semiconductor body further includes n epitaxial regions, where n is an integer greater than or equal to 3. Along the direction from the first surface to the second surface, the first epitaxial region, the second epitaxial region,..., the nth epitaxial region are arranged in sequence; the semiconductor body further includes n - 1 well regions. Along the direction from the first surface to the second surface, the first well region, the second well region,..., the (n - 1)th well region are arranged in sequence. The ith well region and the ith epitaxial region are in the same layer and adjacent to each other; where i is an integer greater than or equal to 1 and less than or equal to n - 1; form a trench on the first surface of the semiconductor body, and the trench penetrates at least into the interior of the (n - 1)th well region; the conductivity types of the well regions and the epitaxial regions are different.

[0077] Specifically, referring to Figure 3 , the semiconductor body 100 includes a first surface 101 and a second surface 102 which are oppositely arranged; the semiconductor body 100 further includes n epitaxial regions 110, where n is an integer greater than or equal to 3, and along the direction from the first surface 101 to the second surface 102, the first epitaxial region 10, the second epitaxial region 20... the nth epitaxial region are arranged in sequence; the semiconductor body 100 further includes n - 1 well regions 103, and along the direction from the first surface 101 to the second surface 102, the first well region 11, the second well region 12... the (n - 1)th well region are arranged in sequence, and the ith well region and the ith epitaxial region are on the same layer and adjacent to each other; where i is an integer greater than or equal to 1 and less than or equal to n - 1; the first surface 101 of the semiconductor body 100 further includes a trench 104, and the trench 104 penetrates at least into the interior of the (n - 1)th well region; the conductive types of the well region 103 and the epitaxial region 110 are different; the cathode 120 is located on the second surface 102; the anode structure 130 is located on the first surface 101 and in the trench 104. Among them, the trench 104 is formed on the first surface 101 through photolithography and etching processes.

[0078] The semiconductor device is a trench - type junction barrier Schottky diode, and the semiconductor body 100 may include a third - generation wide - bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. The epitaxial region 110 is an N+ epitaxial region, and the N - type doping ions in the N+ epitaxial region may be phosphorus (P) ions or nitrogen (N) ions, and the well region 103 is a P - well region, and the P - type doping ions in the P - well region may be aluminum (Al) ions or boron (B) ions. As Figure 1 shown, the semiconductor body 100 may further include a substrate 105, and the epitaxial region 110 is a semiconductor layer formed on the basis of the substrate 105 through multiple epitaxial processes, and the epitaxial processes include chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE) and other processes. The semiconductor body 100 includes n - 1 well regions 103, and the adjacent well regions 103 are in contact with each other.

[0079] S120. Form a cathode on the second surface.

[0080] Specifically, referring to Figure 1 , a cathode is formed on the second surface 102 of the semiconductor body 100.

[0081] S130. Form an anode structure on the first surface and in the trench.

[0082] Specifically, referring to Figure 1, a first metal layer is formed on the first surface of the semiconductor body 100 and within the trench 104, a second metal layer is formed on a side of the first metal layer away from the semiconductor body 100, and a Schottky annealing treatment is performed on the first metal layer and the second metal layer to form a Schottky contact layer 131 and an anode 132. The Schottky contact layer 131 and the anode 132 constitute the anode structure 130.

[0083] In the technical solution of the embodiment of the present invention, by providing n epitaxial regions 110 and n - 1 well regions 103, the i-th well region and the i-th epitaxial region are arranged on the same layer and adjacent to each other. During the process of forming the well region, after forming the (n - 1)-th epitaxial layer and the n-th epitaxial layer on the substrate 105, ion implantation is performed on the (n - 1)-th epitaxial layer to form the (n - 1)-th well region, and then (n - 2) epitaxial layers and (n - 2) well regions are formed in sequence. Each time, only one relatively thin epitaxial region needs to be subjected to ion implantation. Compared with the prior art in which a well region surrounding the trench is formed by injecting through a high-energy ion implanter or a well region surrounding the trench is formed by injecting at an inclined angle, the equipment capability requirement for the ion implanter is lower, and the phenomenon of large damage to the semiconductor device caused by high-energy ion implantation and thus leakage is avoided. Moreover, a trench 104 is formed on the first surface 101 of the semiconductor body 100, and the trench 104 at least penetrates into the interior of the (n - 1)-th well region. In the reverse bias state, compared with the planar junction barrier Schottky diode, a thicker depletion region can be formed between two adjacent trenches 104, improving the breakdown voltage of the semiconductor device, and thus playing a role in protecting the semiconductor device.

[0084] The embodiment of the present invention provides another manufacturing method of a semiconductor device. Figure 4 is a flowchart of another manufacturing method of a semiconductor device provided according to the embodiment of the present invention. Figures 5 - 12 is a cross-sectional view corresponding to each step of another manufacturing method of a semiconductor device provided according to the embodiment of the present invention. Refer to Figures 4 - 12 , the manufacturing method of the semiconductor device includes:

[0085] S211, providing a substrate.

[0086] Specifically, as Figure 5 shown, a substrate 105 is provided, and the semiconductor material of the substrate 105 can be silicon carbide or gallium nitride.

[0087] S212, sequentially disposing the n-th epitaxial region and the (n - 1)-th epitaxial region on a side of the substrate away from the second surface.

[0088] Specifically, the n-th epitaxial region and the (n - 1)-th epitaxial region are respectively formed on one side of the substrate 105 through two epitaxial processes, and the doping concentration of the (n - 1)-th epitaxial region is greater than that of the n-th epitaxial region. Exemplarily, as Figure 6As shown, if the semiconductor device only includes 3 epitaxial regions 110 and 2 well regions 103, the second epitaxial layer 20 and the third epitaxial layer 30 are respectively formed on one side of the substrate 105 through two epitaxial processes, and the doping concentration of the second epitaxial region 20 is greater than that of the third epitaxial region 30. Among them, the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0089] S213. Perform ion implantation on the (n - 1)th epitaxial region to form the (n - 1)th well region.

[0090] Specifically, a first mask layer 200 is formed on the surface of the (n - 1)th epitaxial region. Among them, the first mask layer 200 includes a first through hole 201; and the (n - 1)th well region is formed by performing ion implantation on the (n - 1)th epitaxial region through the first through hole 201. Exemplarily, as Figure 7 shown, applying the hard mask (HM) process, a first mask layer 200 is formed on the surface of the second epitaxial region 20 away from the third epitaxial region 30. The first mask layer 200 can also be deposited with SiO2 by plasma enhanced chemical vapor deposition (PECVD). The first mask layer 200 is patterned through the photolithography process. The photolithography process is an important step in the semiconductor device manufacturing process. This step uses exposure and development to engrave geometric graphic structures on the photoresist layer, and then transfers the pattern of the photoresist layer to the first mask layer 200 through the etching process to achieve the patterning of the first mask layer 200, as Figure 7 shown, the first through hole 201 is formed through the photolithography process. The first through hole 201 penetrates the first mask layer 200. The second well region 12 is formed by P-type doping ion implantation at the first through hole 201. The second well region 12 can be formed on the surface of the second epitaxial region 20 away from the third epitaxial region 30 through processes such as ion implantation, ion diffusion, or vapor deposition. Refer to Figure 8 , the first mask layer 200 made of SiO2 material can be etched off by applying a hydrofluoric acid solution.

[0091] S214. The (n - 2)th epitaxial region to the first epitaxial region are sequentially arranged on the side of the (n - 1)th epitaxial region away from the substrate. After each epitaxial region is formed, ion implantation is performed on the epitaxial region to form a well region, so as to form the (n - 2)th well region to the first well region, and the (n - 2)th epitaxial region to the first epitaxial region.

[0092] Specifically, the (n - 2)-th epitaxial region is formed on the side of the (n - 1)-th epitaxial region away from the substrate by epitaxial process. After the (n - 2)-th epitaxial region is formed, according to the manufacturing method described in step S213, the (n - 2)-th well region is formed on the surface of the (n - 2)-th epitaxial region away from the n-th epitaxial region by processes such as ion implantation, ion diffusion or vapor deposition. And so on, to form the (n - 2)-th well region to the first well region 11, and the (n - 2)-th epitaxial region to the first epitaxial region 10. Exemplarily, as Figure 9 shown, if the semiconductor device only includes 3 epitaxial regions 110 and 2 well regions 103, at this time, only the first well region 11 and the first epitaxial region 10 need to be formed according to the manufacturing method described in step S213. As Figure 10 shown, after the first well region 11 is fabricated, it is not necessary to etch away the first mask layer 200 made of SiO2 material with hydrofluoric acid solution.

[0093] S215. Form a trench.

[0094] Specifically, a second mask layer 300 is formed on the surface of the first mask layer 200 used for forming the first well region 11. Wherein, the second mask layer 300 includes a second through hole 301. The first well region 11 to the (n - 1)-th well region are etched through the second through hole 301 to form a trench. Exemplarily, as Figure 11 shown, in the embodiment of the present invention, the second mask layer 300 is formed on the bottom and side walls of the first through hole 201 of the first mask layer 200 and on the surface of the first mask layer 200 away from the semiconductor body 100. Wherein, the thickness of the deposited second mask layer 300 can be between 0.4 μm and 0.6 μm. The material of the second mask layer 300 can be the same as that of the first mask layer 200, or different from that of the first mask layer 200. Exemplarily, the materials of the second mask layer 300 and the first mask layer 200 are both silicon dioxide or silicon nitride, or the material of the second mask layer 300 and the material of the first mask layer 200 are silicon dioxide and silicon nitride respectively. The second mask layer 300 is patterned by photolithography. As Figure 12 shown, the second through hole 301 is formed by photolithography. The second through hole 301 penetrates through the second mask layer 300, and then a trench 104 is formed on the first surface 101 by etching process. Referring to Figure 3 , if the materials of the second mask layer 300 and the first mask layer 200 are both silicon dioxide, the first mask layer 200 and the second mask layer 300 made of SiO2 material can be etched away with hydrofluoric acid solution.

[0095] S220. Form a cathode on the second surface.

[0096] S231. Form a first metal layer on the first surface and in the trench.

[0097] Specifically, referring to Figure 1 , a first metal layer is deposited on the first surface of the semiconductor body 100 and in the trench 104. The material of the first metal layer includes titanium nitride or titanium, etc., and the embodiments of the present invention do not limit this.

[0098] S232. A second metal layer is formed on the side of the first metal layer away from the semiconductor body.

[0099] Specifically, referring to Figure 1 , a second metal layer is formed on the side of the first metal layer away from the semiconductor body 100, where the material of the first metal layer includes aluminum.

[0100] S233. The first metal layer and the second metal layer are subjected to Schottky annealing treatment to form a Schottky contact layer and an anode.

[0101] Specifically, referring to Figure 1 , the first metal layer and the second metal layer are subjected to Schottky annealing treatment to form a Schottky contact layer 131 and an anode 132. Among them, the Schottky annealing treatment can be understood as a metal heat treatment process in which the metal is slowly heated to a certain temperature, held for a sufficient time, and then cooled at an appropriate speed.

[0102] The embodiments of the present invention provide a power module, which includes a substrate and at least one semiconductor device according to any embodiment of the present invention, and the substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device according to any embodiment of the present invention will not be elaborated here.

[0103] The embodiments of the present invention provide a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0104] Therefore, the beneficial effects of the power conversion circuit including the semiconductor device according to any embodiment of the present invention will not be elaborated here.

[0105] The embodiments of the present invention further provide a vehicle, which includes a load and the above-mentioned power conversion circuit. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0106] Therefore, the beneficial effects of the vehicle including the power conversion circuit according to any embodiment of the present invention will not be elaborated here.

[0107] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and no limitations are imposed herein.

[0108] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising n epitaxial regions, wherein n is an integer greater than or equal to 3, and along a direction from the first surface to the second surface, a first epitaxial region, a second epitaxial region, ..., an nth epitaxial region are arranged in sequence; The semiconductor body further includes n-1 well regions, and along the direction pointing from the first surface to the second surface, the first well region, the second well region ... the n-1th well region are arranged in sequence, and the i-th well region and the i-th epitaxial region are arranged in the same layer and adjacently; wherein i is an integer greater than or equal to 1 and less than or equal to n-1; A groove is provided on the first surface of the semiconductor body, and the groove at least penetrates into the interior of the n-1th well region; the well region and the epitaxial region have different conductivity types; a cathode, located on the second surface; The anode structure is located on the first surface and in the groove.

2. The semiconductor device according to claim 1, wherein: The ion concentrations of the first epitaxial region to the n-1th epitaxial region are all greater than the ion concentration of the nth epitaxial region.

3. The semiconductor device according to claim 2, characterized in that The ion concentration from the first epitaxial region to the n-1th epitaxial region gradually decreases.

4. The semiconductor device according to claim 1, wherein: The sizes of the first well region to the (n-1)th well region gradually decrease along a direction parallel to the first surface.

5. The semiconductor device according to claim 1, wherein: The sizes of the first well region to the n-2th well region along the direction parallel to the first surface are the same, and the size of the n-1th well region along the direction parallel to the first surface is smaller than the size of the n-2th well region along the direction parallel to the first surface.

6. The semiconductor device according to claim 5, characterized in that The size range of the first well region to the n-2 th well region along the direction parallel to the first surface is 0.4-0.6 μm.

7. The semiconductor device according to claim 1, wherein: The anode structure includes a Schottky contact layer and an anode; the Schottky contact layer covers the first surface and the groove, and the anode is arranged on a side of the Schottky contact layer away from the semiconductor body.

8. The semiconductor device according to claim 1, wherein: The semiconductor body includes three epitaxial regions and two well regions.

9. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

10. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising n epitaxial regions, wherein n is an integer greater than or equal to 3, and along the direction from the first surface to the second surface, the first epitaxial region, the second epitaxial region, ... the nth epitaxial region are arranged in sequence; the semiconductor body further comprising n-1 well regions, along the direction from the first surface to the second surface, the first well region, the second well region, ... the n-1th well region are arranged in sequence, and the i-th well region and the i-th epitaxial region are arranged in the same layer and adjacently; wherein i is an integer greater than or equal to 1 and less than or equal to n-1; a groove is formed on the first surface of the semiconductor body, and the groove at least penetrates into the inside of the n-1th well region; the well region and the epitaxial region have different conductivity types; forming a cathode on the second surface; An anode structure is formed on the first surface and in the trench.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that: The semiconductor body provided includes: providing a substrate; sequentially disposing an nth epitaxial region and an n-1th epitaxial region on a side of the substrate away from the second surface; Performing ion implantation on the n-1th epitaxial region to form the n-1th well region; The n-2th epitaxial region to the first epitaxial region are sequentially arranged on the side of the n-1th epitaxial region away from the substrate, and after each epitaxial region is formed, ion implantation is performed on the epitaxial region to form a well region, so as to form the n-2th well region to the first well region, and the n-2th epitaxial region to the first epitaxial region; The groove is formed.

12. The method for manufacturing a semiconductor device according to claim 10, wherein: After each epitaxial region is formed, ion implantation is performed on the epitaxial region to form a well region, comprising: Forming a first mask layer on the surface of the epitaxial region; wherein the first mask layer includes a first through hole; Performing ion implantation into the epitaxial region through the first through hole to form a well region; Forming the groove comprises: Forming a second mask layer on the surface of the first mask layer used to form the first well region; wherein the second mask layer includes a second through hole; The first well region to the n-1th well region are etched through the second through hole to form the groove.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that: The thickness of the second mask layer is in the range of 0.4-0.6 μm.

14. The method for manufacturing a semiconductor device according to claim 10, characterized in that: Forming an anode structure on the first surface and in the groove includes: forming a first metal layer on the first surface and in the groove; forming a second metal layer on a side of the first metal layer away from the semiconductor body; The first metal layer and the second metal layer are subjected to Schottky annealing treatment to form a Schottky contact layer and an anode.

15. A power module, characterized in that: The invention comprises a substrate and at least one semiconductor device according to any one of claims 1 to 9, wherein the substrate is used for carrying the semiconductor device.

16. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 9, wherein the semiconductor device is electrically connected to the circuit board.

17. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 16, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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