Method for manufacturing semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device. The manufacturing method of the semiconductor device comprises the following steps: forming a mask pattern on a substrate; performing a first ion implantation for forming a body region and a first impurity region in the substrate by using the mask pattern; forming a first grid electrode and a second grid electrode which are separated from each other on the substrate; performing a first thermal process on the substrate to form the body region and the first impurity region; and forming a contact portion extending from between the first gate and the second gate to the first impurity region.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device. Background Art

[0002] The content described in this section only briefly provides the background art of this embodiment and does not constitute the prior art.

[0003] For a semiconductor device, especially a Super Junction Metal-Oxide-Semiconductor Field-Effect Transistor (SJMOSFET), the effective channel region may affect the threshold voltage characteristics.

[0004] When performing an ion implantation process for a body region for determining an effective channel region and an ion implantation process for an impurity region using different mask patterns, there is a problem that the effective channel region may be asymmetric due to process variations caused by ion implantation, which will affect the threshold voltage characteristics. Summary of the Invention

[0005] An object of the present invention is to provide a method for manufacturing a semiconductor device that reduces the threshold voltage distribution of the semiconductor device.

[0006] The object of the present invention is not limited to the above-mentioned object. Other objects and advantages of the present invention that are not mentioned can be understood in the following description and are more clearly understood through the embodiments of the present invention. And it can be known that the objects and advantages of the present invention can be easily achieved by the solutions and their combinations in the claims of the invention.

[0007] The method for manufacturing a semiconductor device according to an embodiment of the present invention includes the following steps: forming a mask pattern on a substrate; performing a first ion implantation for forming a body region and a first impurity region in the substrate using the above mask pattern; forming a first gate and a second gate spaced apart from each other on the substrate; performing a first thermal process on the substrate to form the body region and the first impurity region; and forming a contact portion extending from between the first gate and the second gate to the first impurity region.

[0008] And, after performing the first thermal process, it further includes a second ion implantation step for forming a second impurity region in the first impurity region.

[0009] And, the first impurity region is formed in the body region, and the second impurity region is formed in the first impurity region.

[0010] Also, the above-described second ion implantation step is performed to form a channel region in a part of the body region that overlaps the above-described first gate and the above-described second gate along a first direction and overlaps the above-described first impurity region and the above-described second impurity region along a second direction, respectively, and the first direction and the second direction are directions that intersect each other.

[0011] Also, the type of the material implanted to form the above-described body region is different from the types of the materials implanted to form the above-described first impurity region and the above-described second impurity region.

[0012] Also, the above-described second ion implantation step is performed using the above-described first gate and the above-described second gate separated from each other as masks.

[0013] Also, the above-described first impurity region is formed within the above-described body region.

[0014] Also, the step of performing the above-described first ion implantation includes the following steps: performing a first implantation process for the above-described body region; and performing a second implantation process for the above-described first impurity region.

[0015] Also, after performing the above-described first implantation process, the above-described second implantation process is performed.

[0016] Also, in the above-described first implantation process, a first type of material is implanted, and in the above-described second implantation process, a second type of material different from the first type is implanted.

[0017] Also, boron is implanted in the above-described first implantation process, and arsenic is implanted in the above-described second implantation process.

[0018] Also, before forming the above-described mask pattern, the following step is further included: forming a buffer insulating film on the above-described substrate.

[0019] Also, after performing the above-described first ion implantation step, the following steps are further included: removing the above-described mask pattern; removing the above-described buffer insulating film; and performing a second thermal process on the above-described substrate.

[0020] Also, the above-described second thermal process is performed to form a gate insulating film on the above-described substrate, a pre-body region within the above-described substrate, and a pre-first impurity region within the above-described substrate.

[0021] Also, after forming the above-described pre-body region and the above-described pre-first impurity region within the above-described substrate, the above-described first gate and the above-described second gate are formed, and the step of performing the above-described first thermal process is performed on the above-described substrate in which the above-described pre-body region and the above-described pre-first impurity region are formed.

[0022] And, the above-described first thermal process is performed to form a channel region in a part of the body region that overlaps the first gate and the second gate along a first direction and overlaps the first impurity region along a second direction, where the first direction and the second direction are intersecting directions.

[0023] The method for manufacturing a semiconductor device according to an embodiment of the present invention includes: a first ion implantation step of implanting different first impurities and second impurities into a substrate; a step of performing a first thermal process to form a pre-body region based on the first impurity and a pre-first impurity region based on the second impurity in the substrate; a step of forming a first gate and a second gate separated from each other on the substrate; a step of performing a second thermal process on the pre-body region and the pre-first impurity region to form a body region and a first impurity region; and a second ion implantation step of forming a second impurity region in the first impurity region.

[0024] And, the above-described first ion implantation step includes the steps of: performing a first implantation process of implanting the first impurity; and after implanting the first impurity, performing a second implantation process of implanting the second impurity.

[0025] And, after performing the above-described first ion implantation step, the method further includes the step of forming a gate insulating film on the substrate by using the above-described first thermal process.

[0026] The method for manufacturing a semiconductor device according to an embodiment of the present invention includes the steps of: forming a buffer insulating film on a substrate; forming a mask pattern on the buffer insulating film; using the mask pattern to implant a first impurity for forming a body region into the substrate; after implanting the first impurity, implanting a second impurity for forming a first impurity region into the substrate; removing the mask pattern and the buffer insulating film; performing a first thermal process on the substrate to form a pre-body region and a pre-first impurity region in the substrate, and forming a gate insulating film on the substrate; forming a first gate and a second gate separated from each other on the gate insulating film; performing a second thermal process on the substrate having the pre-body region and the pre-first impurity region formed thereon to form the body region and the first impurity region; and using the first gate and the second gate as a mask to implant a third impurity into a part of the first impurity region between the first gate and the second gate.

[0027] In the method for manufacturing a semiconductor device of the present invention, the same mask pattern can be used in the ion implantation processes for forming the body region and the impurity region, thereby reducing the distribution of the threshold voltage.

[0028] In addition to the above, the specific effects of the present invention will be described together in the following process of describing the specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flowchart for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention.

[0030] Figure 2 For explaining Figure 1 Figure of step S100.

[0031] Figure 3 And Figure 4 For explaining Figure 1 Figure of step S200.

[0032] Figures 5 to 9 For explaining Figure 1 Figure of step S300.

[0033] Figures 10 to 12 For explaining Figure 1 Figure of step S400.

[0034] Figure 13 For explaining Figure 1 Figure of step S500.

[0035] Figure 14 Figure for explaining the effect of the manufacturing method of the semiconductor device according to the embodiment of the present invention. DETAILED DESCRIPTION

[0036] The terms or words used in this specification and the scope of the invention claimed cannot be construed in a limited sense as general or dictionary meanings. According to the principle that the inventor can define the concepts of terms or words in order to explain his invention by the optimal method, they should be interpreted by the meanings and concepts conforming to the technical idea of the present invention. And, the embodiments described in this specification and the structures shown in the drawings are only one embodiment for implementing the present invention, rather than substituting all the technical ideas of the present invention. Therefore, it should be understood that there can be various equivalent technical solutions, variations and application examples that can replace these at the time of this application.

[0037] The terms such as first, second, A, B, etc. used in this specification and the scope of the invention claimed can be used to explain various structural elements, and the above structural elements are not limited to the above terms. The above terms are only used to distinguish two structural elements. For example, without exceeding the scope of the invention claimed of the present invention, the first structural element can be named the second structural element, and similarly, the second structural element can also be named the first structural element. The terms such as "and / or" include combinations of multiple related recited items or one item among multiple related recited items.

[0038] The terms used in this specification and the scope of the invention claimed are only for describing specific embodiments and are not intended to limit the present invention. Unless clearly indicated in the context, singular expressions include plural expressions. In this application, terms such as "including" or "having" do not preclude the existence or additional possibility of features, numbers, steps, actions, structural elements, components, or combinations thereof described in the specification.

[0039] Unless otherwise defined, the meanings of all terms used herein, including technical or scientific terms, are the same as those commonly understood by those of ordinary skill in the technical field to which the present invention pertains.

[0040] The meanings of terms defined in commonly used dictionaries are the same as those in the context of the related art, and unless clearly defined in this application, they cannot be construed as overly idealized or formal meanings. Also, the various structures, processes, procedures, or methods included in the embodiments of the present invention can be shared within the scope of not being contradictory to each other.

[0041] Hereinafter, with reference to Figures 1 to 14 , a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described.

[0042] Figure 1 FIG. is a flowchart for explaining the method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0043] With reference to Figure 1 , the method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step S100 of forming a mask pattern on a substrate.

[0044] Figure 2 For explaining Figure 1 FIG. is a diagram of step S100.

[0045] With reference to Figure 1 and Figure 2 , the method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step of first forming a buffer insulating film BO on a substrate 100. A filler structure PIL may be formed on the substrate 100.

[0046] A mask pattern MP may be formed on the buffer insulating film BO. The mask pattern MP may include a first mask pattern MP1 and a second mask pattern MP2. The first mask pattern MP1 and the second mask pattern MP2 may be spaced apart from each other and formed on the buffer insulating film BO on the substrate 100. The first mask pattern MP1 and the second mask pattern MP2 may be photoresist.

[0047] Referring again to Figure 1, the method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step S200 of performing a first ion implantation on a substrate. The first ion implantation process may be a step of forming a body region and a first impurity region in the substrate using a mask pattern.

[0048] Figure 3 and Figure 4 is a diagram for explaining Figure 1 step S200.

[0049] Referring to Figure 1 , Figure 3 and Figure 4 , step S200 of performing the first ion implantation in the method for manufacturing a semiconductor device according to an embodiment of the present invention may include a step S201 of performing a first implantation process and a step S203 of performing a second implantation process.

[0050] The first implantation process may implant a first impurity into the substrate 100 to form a body region in the substrate 100. In the first implantation process, a first type of substance may be implanted into the substrate 100 to form the body region. The first implantation process may be performed to form a first impurity implantation region IM1 in which the first type of substance is implanted into the substrate 100. For example, the first type of substance may be a p-type impurity. For example, the first type of substance may be boron.

[0051] The second implantation process may implant a second impurity into the substrate 100 to form a first impurity region in the substrate 100. The second implantation process may be performed after the first implantation process. In the second implantation process, a second type of substance different from the first type may be implanted into the substrate 100 to form the first impurity region. The second implantation process may be performed to form a second impurity implantation region IM2 in which the second type of substance is implanted into the substrate 100. For example, the second type of substance may be an n-type impurity. For example, the second type of substance may be arsenic.

[0052] The first ion implantation step S200 including the first implantation process and the second implantation process may be performed using a first mask pattern MP1 and a second mask pattern MP2. The first impurity and the second impurity may be mainly implanted into the buffer insulating film BO and the substrate 100 portion exposed through the first mask pattern MP1 and the second mask pattern MP2.

[0053] The second impurity implantation region IM2 may be formed on the first impurity implantation region IM1. In the figure, a part of the second impurity implantation region IM2 overlaps with the buffer insulating film BO, but it is not limited thereto. According to the process, the buffer insulating film BO may of course also be formed on the second impurity implantation region IM2 in a non-overlapping manner.

[0054] Referring again to Figure 1, the method for manufacturing a semiconductor device according to an embodiment of the present invention may include step S300 of forming a first gate and a second gate on a substrate. The first gate and the second gate may be formed spaced apart from each other.

[0055] Figures 5 to 9 For explaining Figure 1 Figure of step S300.

[0056] Referring to Figure 5 and Figure 6 , step S300 of forming a first gate and a second gate on substrate 100 may include step S301 of removing a mask pattern ( Figure 4 MP). After performing the first ion implantation step S200, the mask pattern ( Figure 4 MP) may be removed. By removing the mask pattern ( Figure 4 MP), the buffer insulating film BO may be exposed.

[0057] Referring to Figure 5 and Figure 7 , step S300 of forming a first gate and a second gate on substrate 100 may include step S303 of removing the buffer insulating film BO. By removing the buffer insulating film BO, the second impurity implantation region IM2 may be exposed.

[0058] Referring to Figure 5 , Figure 8 and Figure 9 , step S300 of forming a first gate and a second gate on substrate 100 may include step S305 of performing a first thermal process to form a gate insulating film 103, a pre-body region PreBD, and a pre-first impurity region PreIR1.

[0059] The gate insulating film 103 may be formed on the substrate 100. The first thermal process may be performed to form the gate insulating film 103. Due to the first thermal process, the first impurity in the first impurity implantation region IM1 diffuses, and thus a pre-body region PreBD may be formed in the substrate 100. Due to the first thermal process, the second impurity in the second impurity implantation region IM2 diffuses, and thus a pre-first impurity region PreIR1 may be formed in the substrate 100.

[0060] The pre-first impurity region PreIR1 may be formed within the pre-body region PreBD. The pre-first impurity region PreIR1 may be formed by diffusion of the second impurity in such a way as to occupy a part of the pre-body region PreBD.

[0061] In the figure, it is shown that the pre-body region PreBD does not diffuse into the filler structure PIL, but is not limited thereto. Through the first thermal process, the first impurity in the first impurity implantation region IM1 diffuses, and of course, the pre-body region PreBD may also diffuse into the filler structure PIL to be formed.

[0062] After forming the gate insulating film 103, the pre-body region PreBD, and the pre-first impurity region PreIR1 (step S305), the first gate GE1 and the second gate GE2 can be formed on the gate insulating film 103. The first gate GE1 and the second gate GE2 can be formed separately from each other. The first gate GE1 and the second gate GE2 are separated from each other so that a part of the gate insulating film 103 can be exposed. A part of each of the first gate GE1 and the second gate GE2 can overlap with the pre-body region PreBD.

[0063] Referring again to Figure 1 , the method of manufacturing a semiconductor device according to an embodiment of the present invention may include step S400 of forming a body region and a first impurity region.

[0064] Figures 10 to 12 For explaining Figure 1 FIG. for step S400.

[0065] Referring to Figure 10 and Figure 11 , step S400 of forming the body region BD and the first impurity region IR1 may include step S401 of performing a second thermal process on the substrate 100.

[0066] The second thermal process may be performed on the substrate 100 on which the pre-body region PreBD and the pre-first impurity region PreIR1 are formed. Due to the second thermal process, the first impurity in the pre-body region PreBD can be further diffused, thereby forming the body region BD. For example, the body region BD may extend to the filler structure PIL.

[0067] Due to the second thermal process, the second impurity in the pre-first impurity region PreIR1 can be further diffused, thereby forming the first impurity region IR1. The first impurity region IR1 may be formed within the body region BD.

[0068] Due to the difference in the diffusion rates of the first impurity and the second impurity, a difference may occur in the thickness along the first direction D1 of the body region BD and the thickness along the first direction D1 of the first impurity region IR1. The thickness along the first direction D1 of the body region BD may be greater than the thickness along the first direction D1 of the first impurity region IR1.

[0069] Also, due to the difference in the diffusion rates of the first impurity and the second impurity, a difference may occur in the width along the second direction D2 of the body region BD and the width along the second direction D2 of the first impurity region IR1. The width along the second direction D2 of the body region BD may be greater than the width along the second direction D2 of the first impurity region IR1. The first direction D1 and the second direction D2 may be mutually intersecting directions.

[0070] A main body region BD and a first impurity region IR1 are formed, so that a channel region CH can be formed. The channel region CH can be a partial region of the main body region BD. The channel region CH can be a part of the main body region BD that overlaps with the first gate electrode GE1 and the second gate electrode GE2 along a first direction D1 and overlaps with the first impurity region IR1 along a second direction D2.

[0071] Based on the first impurity region IR1, the channel region CH can be formed in a part of the main body region BD on both sides. Based on the first impurity region IR1, the channel regions CH formed in a part of the main body region BD on both sides can be symmetric to each other.

[0072] Referring to Figure 10 and Figure 12 , the step S400 of forming the main body region BD and the first impurity region IR1 may include a step S403 of performing a second ion implantation.

[0073] The second ion implantation can be performed by using the first gate electrode GE1 and the second gate electrode GE2 as masks. The second ion implantation process can implant a third impurity into a part of the first impurity region IR1 between the first gate electrode GE1 and the second gate electrode GE2. After performing the second thermal process, the second ion implantation process can implant the third impurity in order to form a second impurity region IR2 in the first impurity region IR1. The second impurity in the first ion implantation step for forming the first impurity region IR1 and the third impurity in the second ion implantation step for forming the second impurity region IR2 can be substances of the same type. For example, the second impurity can be arsenic and the third impurity can be phosphorus.

[0074] The second impurity region IR2 can occupy a part of the first impurity region IR1. The second impurity region IR2 can be formed in the first impurity region IR1 between the first gate electrode GE1 and the second gate electrode GE2.

[0075] Referring again to Figure 1 , the manufacturing method of the semiconductor device according to an embodiment of the present invention may include a step S500 of forming a contact portion.

[0076] Figure 13 For explaining Figure 1 the step S500 of

[0077] Referring to Figure 1 and Figure 13 , after performing the second ion implantation for forming the second impurity region IR2, a contact portion CT extending from between the first gate electrode GE1 and the second gate electrode GE2 to the first impurity region IR1 can be formed. The contact portion CT can penetrate the first impurity region IR1 and the second impurity region IR2.

[0078] The interlayer insulating film 105 may be formed on the first gate GE1, the second gate GE2, and the contact portion CT. The interlayer insulating film 105 is formed in a manner capable of covering the first gate GE1, the second gate GE2, and the contact portion CT. A metal layer 107 may be formed on the interlayer insulating film 105.

[0079] The manufacturing method of the semiconductor device according to the embodiment of the present invention may perform a first ion implantation process and a second ion implantation process to additionally implant a third impurity of the same type (for example, an n-type impurity) into the first impurity region IR1, thereby compensating the concentration of the impurity. When the concentration of the impurity is compensated, the resistance can be reduced.

[0080] In the manufacturing method of the semiconductor device according to the embodiment of the present invention, in the first ion implantation step, the first impurity for forming the main figure region and the second impurity for forming the first impurity region are implanted using the same mask pattern MP, whereby the channel region CH can be symmetrically formed. In other words, the widths CH_W1 and CH_W2 of the channel regions CH formed on both sides of the first impurity region IR1 and the second impurity region IR2 can be substantially the same. For example, the widths CH_W1 and CH_W2 of the channel regions CH formed on both sides of the first impurity region IR1 and the second impurity region IR2 may have a difference within a minimum degree of error range. For example, the widths CH_W1 and CH_W2 of the channel regions CH formed on both sides of the first impurity region IR1 and the second impurity region IR2 can be the same.

[0081] Figure 14 It is a diagram for explaining the effect of the manufacturing method of the semiconductor device according to the embodiment of the present invention.

[0082] Refer to Figure 14 , the first graph G1 is a graph showing the distribution of the threshold voltage VTH of the manufacturing method of the conventional semiconductor device, and the second graph G2 is a graph showing the distribution of the threshold voltage VTH of the manufacturing method of the semiconductor device according to the embodiment of the present invention. The x-axis may be the length of the channel region (unit: AU (arbitrary unit)), and the y-axis is VTH (unit: V (voltage)).

[0083] The manufacturing method of the conventional semiconductor device may perform the impurity implantation process for forming the body region and the impurity implantation process for forming the first impurity region separately using different mask patterns.

[0084] Compared with the first graph G1, the change in the threshold voltage VTH of the second graph G2 is small. The manufacturing method of the semiconductor device according to the embodiment of the present invention can reduce the distribution of the threshold voltage VTH to ensure the stability of the semiconductor device.

[0085] The above description only illustratively explains the technical idea of the present invention. As long as those of ordinary skill in the technical field to which the present invention pertains can make various modifications and variations without exceeding the essential characteristics of this embodiment. Therefore, this embodiment is used to illustrate the present invention, rather than to limit the technical idea of this embodiment. The scope of the technical idea of this embodiment is not limited to such an embodiment. The protection scope of this embodiment should be interpreted by the following scope of the invention claimed, and all technical ideas within the equivalent scope should be included in the scope of the invention claimed in this embodiment.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The steps include: forming a mask pattern on a substrate; Using the mask pattern, performing a first ion implantation for forming a body region and a first impurity region in the substrate; forming a first gate and a second gate separated from each other on the substrate; Performing a first thermal process on the substrate to form the body region and the first impurity region; and A contact portion is formed extending from between the first gate and the second gate to the first impurity region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: After performing the first thermal process, a second ion implantation step for forming a second impurity region in the first impurity region is further included.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The first impurity region is formed in the main body region. The second impurity region is formed in the first impurity region.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: performing the second ion implantation step to form a channel region in a portion of the body region that overlaps with the first gate and the second gate along the first direction and overlaps with the first impurity region and the second impurity region along the second direction, The first direction and the second direction are directions intersecting each other.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: The type of substance implanted to form the body region is different from the type of substance implanted to form the first impurity region and the second impurity region.

6. The method for manufacturing a semiconductor device according to claim 2, wherein: The second ion implantation step is performed by using the first gate and the second gate separated from each other as masks.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The first impurity region is formed in the body region.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of performing the first ion implantation comprises the following steps: performing a first implantation process for the body region; and A second implantation process is performed for the first impurity region.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: After performing the first implantation process, the second implantation process is performed.

10. The method for manufacturing a semiconductor device according to claim 8, wherein: In the first injection step, a first type of substance is injected. In the second injection step, a second type of substance different from the first type of substance is injected.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: In the first implantation step, boron is implanted. Arsenic is implanted in the second implantation step.

12. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming the mask pattern, the method further includes forming a buffer insulating film on the substrate.

13. The method for manufacturing a semiconductor device according to claim 12, wherein: After performing the first ion implantation step, the method further includes the following steps: Remove the above mask pattern: removing the buffer insulating film; and A second thermal process is performed on the substrate.

14. The method for manufacturing a semiconductor device according to claim 13, wherein: The second thermal process is performed to form a gate insulating film on the substrate, a pre-body region in the substrate, and a pre-first impurity region in the substrate.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: After forming the pre-body region and the pre-first impurity region in the substrate, forming the first gate and the second gate, The step of performing the first thermal process is performed on the substrate having the pre-body region and the pre-first impurity region formed thereon.

16. The method for manufacturing a semiconductor device according to claim 1, wherein: performing the first thermal process to form a channel region in a portion of the body region that overlaps with the first gate and the second gate along a first direction and overlaps with the first impurity region along a second direction, The first direction and the second direction are directions intersecting each other.

17. A method for manufacturing a semiconductor device, characterized in that: include: A first ion implantation step of implanting different first impurities and second impurities into the substrate; A step of performing a first thermal process to form a pre-body region based on the first impurity and a pre-first impurity region based on the second impurity in the substrate; The step of forming a first gate and a second gate separated from each other on the substrate; A step of performing a second thermal process on the pre-body region and the pre-first impurity region to form a body region and a first impurity region; and A second ion implantation step of forming a second impurity region in the first impurity region.

18. The method for manufacturing a semiconductor device according to claim 17, wherein: The first ion implantation step comprises the following steps: Performing a first implantation process of implanting the first impurity; and After the first impurity is implanted, a second implantation step of implanting the second impurity is performed.

19. The method for manufacturing a semiconductor device according to claim 17, wherein: After performing the first ion implantation step, the method further includes forming a gate insulating film on the substrate using the first thermal process.

20. A method for manufacturing a semiconductor device, characterized in that: The steps include: forming a buffer insulating film on a substrate; forming a mask pattern on the buffer insulating film; Using the mask pattern to implant a first impurity for forming a main body region into the substrate; After the first impurities are implanted, second impurities for forming the first impurity region are implanted into the substrate; removing the mask pattern and the buffer insulating film; Performing a first thermal process on the substrate to form a pre-body region and a pre-first impurity region in the substrate, and forming a gate insulating film on the substrate; forming a first gate and a second gate separated from each other on the gate insulating film; Performing a second thermal process on the substrate having the pre-body region and the pre-first impurity region formed thereon to form the body region and the first impurity region; and Using the first gate and the second gate as masks, a third impurity is implanted into a portion of the first impurity region between the first gate and the second gate.

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