Semiconductor device and manufacturing method thereof, power module, power conversion circuit and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a semiconductor device, a power module, a power conversion circuit and a vehicle. The manufacturing method of the semiconductor device comprises the steps that a semiconductor body is provided, the semiconductor body comprises a first surface and a second surface which are oppositely arranged, and the semiconductor body is provided with a gate groove; forming an insulating layer and a grid electrode in the grid electrode groove, namely forming a first dielectric layer in the grid electrode groove and the first surface, and removing at least part of the first dielectric layer so as to reserve the first dielectric layer with a set thickness at the bottom of the grid electrode groove; a second dielectric layer is formed on the side wall of the gate trench, the thickness of the second dielectric layer is smaller than that of the reserved first dielectric layer at the bottom of the gate trench, and the insulating layer comprises the second dielectric layer and the reserved first dielectric layer; and forming a gate on one side of the insulating layer away from the gate trench. According to the invention, the bearing capacity of the insulating layer at the bottom of the gate trench is improved, the conduction characteristic of the semiconductor device is not affected, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Semiconductor devices can be divided into trench-type semiconductor devices and planar semiconductor devices. Among them, trench-type semiconductor devices have a smaller on-resistance and a higher integration degree compared with planar semiconductor devices.

[0003] However, due to its unique "U" - shaped structure, the trench-type semiconductor device has a problem of electric field concentration at the bottom of the gate trench, which causes the insulating layer at the bottom of the gate trench to be easily broken down in advance, affecting the reliability of the trench-type semiconductor device. Summary of the Invention

[0004] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit, and a vehicle, which improve the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, do not affect the on - characteristics of the semiconductor device, and improve the reliability of the semiconductor device.

[0005] According to one aspect of the present invention, a manufacturing method of a semiconductor device is provided. The manufacturing method includes:

[0006] Providing a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged oppositely, and the semiconductor body is provided with a gate trench extending from the first surface into the semiconductor body;

[0007] Forming an insulating layer and a gate in the gate trench, including:

[0008] Forming a first dielectric layer on the gate trench and the first surface, and removing at least a part of it to retain a first dielectric layer with a set thickness at the bottom of the gate trench;

[0009] Forming a second dielectric layer on the sidewall of the gate trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer retained at the bottom of the gate trench, and the insulating layer includes the second dielectric layer and the retained first dielectric layer;

[0010] Forming a gate on a side of the insulating layer away from the gate trench.

[0011] Optionally, the forming a first dielectric layer on the gate trench and the first surface includes:

[0012] Forming a spin coating layer on the gate trench and the first surface by using a coating process;

[0013] Under set conditions, the spin-coated layer is annealed to form the first dielectric layer.

[0014] Optionally, the material of the spin-coated layer includes spin-on glass, and the spin-on glass includes silicon element and oxygen element;

[0015] The material of the first dielectric layer includes silicon dioxide.

[0016] Optionally, the set conditions include a set temperature, nitrogen at a first concentration, and oxygen at a second concentration, and the first concentration is greater than the second concentration;

[0017] The set temperature is 450°C to 600°C.

[0018] Optionally, before forming the spin-coated layer in the gate trench and on the first surface by using a coating process, it includes:

[0019] Forming a third dielectric layer on the bottom and sidewalls of the gate trench; wherein, the material of the third dielectric layer is the same as that of the first dielectric layer.

[0020] Optionally, forming the second dielectric layer on the sidewalls of the gate trench includes:

[0021] Oxidizing the sidewalls of the gate trench to form the second dielectric layer.

[0022] Optionally, the set thickness is 2000 Å to 3000 Å;

[0023] The thickness of the second dielectric layer is 500 Å to 800 Å.

[0024] Optionally, providing the semiconductor body includes:

[0025] Providing a silicon carbide semiconductor body or providing a gallium nitride semiconductor body.

[0026] According to another aspect of the present invention, a semiconductor device is provided, and the semiconductor device is made by using the manufacturing method of the semiconductor device provided in any embodiment of the present invention;

[0027] The semiconductor device includes:

[0028] A semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body;

[0029] A gate structure, the gate structure includes the insulating layer and a gate, the insulating layer includes a first dielectric layer located at the bottom of the gate trench and a second dielectric layer located on the sidewalls of the gate trench, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; the gate is located on a side of the insulating layer away from the gate trench.

[0030] According to another aspect of the present invention, there is provided a power module, the power module includes a substrate and at least one semiconductor device provided in any embodiment of the present invention, and the substrate is used to carry the semiconductor device.

[0031] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction;

[0032] The power conversion circuit includes a circuit board and at least one semiconductor device provided in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0033] According to another aspect of the present invention, there is provided a vehicle, the vehicle includes a load and a power conversion circuit provided in any embodiment of the present invention, and the power conversion circuit is used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input it to the load.

[0034] An embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing method includes first providing a semiconductor body, the semiconductor body includes a gate trench, and further includes a first surface and a second surface arranged opposite to each other. Then, a first dielectric layer is formed on the first surface of the semiconductor body and in the gate trench, and at least part of the first dielectric layer is removed to retain a first dielectric layer with a set thickness at the bottom of the gate trench. Then, a second dielectric layer is formed on the sidewalls of the gate trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer retained at the bottom of the gate trench, and the insulating layer includes the second dielectric layer and the retained first dielectric layer. Finally, a gate is formed on a side of the insulating layer away from the gate trench to manufacture a semiconductor device. The method for manufacturing a semiconductor device provided by the embodiment of the present invention can make the bottom thickness of the manufactured insulating layer greater than its sidewall thickness, can increase the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, solves the problem that the insulating layer is easily broken down due to the electric field concentration at the bottom of the trench-type semiconductor device, and at the same time, the insulating layer located on the sidewalls of the gate trench is relatively thin and does not affect the conduction characteristics of the semiconductor device. In summary, the method for manufacturing a semiconductor device provided by the embodiment of the present invention improves the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, does not affect the conduction characteristics of the semiconductor device, and improves the reliability of the semiconductor device.

[0035] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become readily understood from the following description. Description of the Drawings

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 is a schematic flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0038] Figure 2 is a schematic structural diagram of a semiconductor body according to an embodiment of the present invention;

[0039] Figure 3 is a schematic structural diagram before removing the first dielectric layer after its formation;

[0040] Figure 4 is a schematic structural diagram of retaining a first dielectric layer with a set thickness at the bottom of the gate trench;

[0041] Figure 5 is a schematic structural diagram after forming the second dielectric layer;

[0042] Figure 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0043] Figure 7 is a schematic flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0044] Figure 8 is a schematic structural diagram after forming a spin coating layer;

[0045] Figure 9 is a schematic flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0046] Figure 10 is a schematic structural diagram after forming the third dielectric layer;

[0047] Figure 11 is another schematic structural diagram after forming a spin coating layer;

[0048] Figure 12 is another schematic structural diagram after forming the first dielectric layer;

[0049] Figure 13 Another structural schematic diagram for retaining a first dielectric layer with a set thickness at the bottom of the gate trench;

[0050] Figure 14 Another structural schematic diagram after forming the second dielectric layer;

[0051] Figure 15 Another structural schematic diagram of a semiconductor device provided by an embodiment of the present invention;

[0052] Figure 16 Another structural schematic diagram of a semiconductor device provided according to an embodiment of the present invention. Detailed implementation manners

[0053] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0054] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such used data can be interchanged under appropriate circumstances so that the embodiments of the present invention described here can be implemented in an order different from those illustrated or described here. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0055] After research and analysis by the inventor, it is found that the reason for the premature breakdown of the insulating layer at the bottom of the gate trench of the trench-type semiconductor device is as follows: In the existing manufacturing method of the trench-type semiconductor device, the insulating layer is usually formed by high-temperature oxidation. However, due to the different crystal phases of the bottom and sidewalls of the gate trench, the growth rate of the insulating layer on the sidewalls is faster, and finally an insulating layer with a thick sidewall and a thin bottom is formed, resulting in the problem that the electric field is concentrated at the bottom of the gate trench and the insulating layer at the bottom of the gate trench is easily prematurely broken down.

[0056] An embodiment of the present invention provides a method for manufacturing a semiconductor device, which can form an insulating layer with a thick bottom and a thin sidewall, increasing the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, without affecting the conduction characteristics of the semiconductor device, and improving the reliability of the semiconductor device.

[0057] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figure 1 , the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0058] S110. Provide a semiconductor body.

[0059] Among them, Figure 2 is a schematic structural diagram of a semiconductor body according to an embodiment of the present invention. Referring to Figure 2 , the semiconductor body 110 provided in this embodiment includes a first surface S1 and a second surface S2 that are oppositely arranged. The semiconductor body 110 is provided with a gate trench 101, and the gate trench 101 extends from the first surface S1 into the semiconductor body 110.

[0060] Specifically, the semiconductor body 110 may include a substrate 111 and an epitaxial layer 112 located on one side of the substrate 111. The epitaxial layer 112 may include one or more gate trenches 101 distributed at intervals.

[0061] S120. Form a first dielectric layer in the gate trench and on the first surface, and remove at least a part thereof to retain a set thickness of the first dielectric layer at the bottom of the gate trench.

[0062] Specifically, Figure 3 is a schematic structural diagram before removing the first dielectric layer after formation. Referring to Figure 3 , the first dielectric layer 130 fills the gate trench and covers the first surface S1. The first dielectric layer 130 can be formed in the gate trench and on the first surface S1 by a deposition process, or a spin-coated layer can be first formed in the gate trench and on the first surface S1, and then the spin-coated layer is annealed to form the first dielectric layer 130. Figure 4 is a schematic structural diagram of retaining a set thickness of the first dielectric layer at the bottom of the gate trench. Referring to Figure 4 , the first dielectric layer on the first surface S1 and a part of the first dielectric layer 130 in the gate trench 101 can be removed, so that a set thickness of the first dielectric layer 130 is retained at the bottom of the gate trench 101. At least a part of the first dielectric layer 130 can be removed by a wet etching method. After removing at least a part of the first dielectric layer 130, the sidewall of the gate trench 101 is exposed, and the surface of the first dielectric layer 130 retained in the gate trench 101 away from the bottom of the gate trench 101 can be flush.

[0063] S130. Form a second dielectric layer on the sidewalls of the gate trench.

[0064] Among them, Figure 5 is a schematic structural diagram after the second dielectric layer is formed. Refer to Figure 5 , the thickness of the second dielectric layer 140 is less than the thickness of the remaining first dielectric layer 130 at the bottom of the gate trench 101. The insulating layer 150 includes the second dielectric layer 140 and the remaining first dielectric layer 130.

[0065] Specifically, the thickness of the second dielectric layer 140 refers to the thickness of the second dielectric layer 140 in the direction perpendicular to the depth of the gate trench 101. The thickness of the remaining first dielectric layer 130 at the bottom of the gate trench 101 refers to the thickness of the remaining first dielectric layer 130 in the gate trench 101 in the direction parallel to the depth of the gate trench 101. The material of the first dielectric layer 130 can be the same as the material of the second dielectric layer 140, and both the first dielectric layer 130 and the second dielectric layer 140 have insulating functions.

[0066] S140. Form a gate on the side of the insulating layer away from the gate trench.

[0067] Specifically, Figure 6 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention. Refer to Figure 6 , the gate 161 fills the remaining area of the gate trench. The material of the gate 161 can include polysilicon or metal. The surface of the gate 161 away from the bottom of the gate trench can be flush with the first surface S1 or lower than the first surface S1.

[0068] This embodiment provides a method for manufacturing a semiconductor device. The manufacturing method includes first providing a semiconductor body, which includes a gate trench and also includes a first surface and a second surface that are oppositely arranged. Then, a first dielectric layer is formed on the first surface and in the gate trench of the semiconductor body, and at least part of the first dielectric layer is removed to retain a set thickness of the first dielectric layer at the bottom of the gate trench. Next, a second dielectric layer is formed on the sidewalls of the gate trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer retained at the bottom of the gate trench, and the insulating layer includes the second dielectric layer and the retained first dielectric layer. Finally, a gate is formed on the side of the insulating layer away from the gate trench to fabricate a semiconductor device. The method for manufacturing a semiconductor device provided in this embodiment can make the bottom thickness of the fabricated insulating layer greater than its sidewall thickness, which can increase the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, solve the problem that the insulating layer is easily broken down due to the concentration of the electric field at the bottom of the trench-type semiconductor device, and at the same time, the insulating layer located on the sidewalls of the gate trench is relatively thin and will not affect the conduction characteristics of the semiconductor device. In summary, the method for manufacturing a semiconductor device provided in this embodiment improves the pressure-bearing capacity of the insulating layer at the bottom of the gate trench, does not affect the conduction characteristics of the semiconductor device, and improves the reliability of the semiconductor device.

[0069] Figure 7 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Referring to Figure 7 , the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0070] S310. Provide a semiconductor body.

[0071] Among them, the content of step S310 is the same as the content of step S110. For the description of step S310, please refer to the description of step S110, which will not be repeated here.

[0072] S320. Form a spin coating layer on the gate trench and the first surface by using a coating process.

[0073] Among them, Figure 8 is a schematic structural diagram after the spin coating layer is formed. Referring to Figure 8 , the spin coating layer 120 fills the gate trench and covers the first surface S1. The side of the spin coating layer 120 away from the semiconductor body can be flush. The spin coating layer 120 can be in direct contact with the sidewalls and the bottom of the gate trench. The physical state of the spin coating layer 120 can be molten or similar to a colloidal state. Using the coating process can make the surface of the spin coating layer 120 away from the semiconductor body 110 smooth, flat, and bubble-free, thereby improving the quality of the spin coating layer 120. In addition, in this embodiment, the spin coating layer 120 is formed by using the coating process, and the manufacturing method is simple, which can improve the production capacity of the semiconductor device.

[0074] S330. Under set conditions, anneal the spin-coated layer to form a first dielectric layer.

[0075] Specifically, with continued reference to Figure 8 and Figure 3 , annealing the spin-coated layer 120 under set conditions can form a first dielectric layer 130. The shape, thickness, position, etc. of the first dielectric layer 130 can correspond to those of the spin-coated layer 120. Exemplarily, if the side of the spin-coated layer 120 away from the semiconductor body is flush, then the side of the first dielectric layer 130 away from the semiconductor body is also flush.

[0076] In the manufacturing method of the semiconductor device provided in this embodiment, first, a spin-coated layer is formed by a coating process, and then the spin-coated layer is annealed to form a first dielectric layer. There is no need to use a chemical vapor deposition (CVD) process to form the first dielectric layer. Therefore, there is no need to use CVD equipment, which can reduce the manufacturing cost of the insulating layer and thus reduce the manufacturing cost of the semiconductor device.

[0077] S340. Remove at least part of the first dielectric layer to retain a set thickness of the first dielectric layer at the bottom of the gate trench.

[0078] Among them, the content in step S340 can be the same as the content of removing at least part of the first dielectric layer in step S120. For the description of step S340, please refer to the description of step S120, which will not be elaborated here.

[0079] S350. Form a second dielectric layer on the sidewall of the gate trench.

[0080] Among them, the content of step S350 is the same as the content of step S130. For the description of step S350, please refer to the description of step S130, which will not be elaborated here.

[0081] S360. Form a gate on the side of the insulating layer away from the gate trench.

[0082] Among them, the content of step S360 is the same as the content of step S140. For the description of step S360, please refer to the description of step S140, which will not be elaborated here.

[0083] Optionally, the material of the spin-coated layer includes spin-on glass (SOG), and spin-on glass includes silicon and oxygen elements; the material of the first dielectric layer includes silicon dioxide.

[0084] Specifically, the material of the insulating layer in this embodiment includes silicon dioxide. When the spin-on glass includes silicon and oxygen elements, annealing the spin-coated layer under set conditions can form a first dielectric layer including silicon dioxide.

[0085] Optionally, the setting conditions include a set temperature, nitrogen at a first concentration, and oxygen at a second concentration, and the first concentration is greater than the second concentration; the set temperature is 450°C to 600°C.

[0086] Specifically, after spin-on glass is coated in the gate trench and on the first surface of the semiconductor body, the spin-on glass is annealed under the conditions of a set temperature of 450°C to 600°C, high-concentration nitrogen, and low-concentration oxygen, and a first dielectric layer including silicon dioxide can be formed. The set temperature can specifically be 450°C, 480°C, 500°C, 550°C, 580°C, 600°C, etc.

[0087] Optionally, Figure 9 is a schematic flow chart of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Refer to Figure 9 , the method for manufacturing a semiconductor device provided in this embodiment includes the following steps:

[0088] S210. Provide a semiconductor body.

[0089] Among them, the content of step S210 is the same as that of step S110. For the description of step S210, please refer to the description of step S110, which will not be repeated here.

[0090] S220. Form a third dielectric layer on the bottom and side walls of the gate trench.

[0091] Among them, the material of the third dielectric layer is the same as that of the first dielectric layer.

[0092] Specifically, Figure 10 is a schematic structural diagram after the third dielectric layer is formed. Refer to Figure 10 , the third dielectric layer 160 can be formed by using a low-pressure tetraethyl orthosilicate (LPTEOS) process at a low temperature. The third dielectric layer 160 does not fill the gate trench 101. Forming the third dielectric layer 160 before forming the spin-on layer is to avoid unnecessary damage to the side walls and bottom of the gate trench caused by the spin-on layer, thereby improving the reliability of the finally formed semiconductor device.

[0093] S230. Use a coating process to form a spin-on layer in the gate trench and on the first surface.

[0094] Specifically, Figure 11 is another schematic structural diagram after the spin-on layer is formed. Refer to Figure 11 , the spin-on layer 120 fills the gate trench and covers the third dielectric layer 160.

[0095] It should be noted that the method of forming the spin-coated layer in step S230 may be the same as the method of forming the spin-coated layer in step S320.

[0096] S240. Anneal the spin-coated layer under set conditions to form the first dielectric layer.

[0097] Specifically, Figure 12 is another structural schematic diagram after forming the first dielectric layer. Refer to Figure 12 , the spin-coated layer can be spin-coated glass. Under the conditions of a set temperature of 450°C to 600°C, high-concentration nitrogen, and low-concentration oxygen, the spin-coated glass can be annealed to form the first dielectric layer 130. The formed first dielectric layer 130 fills the gate trench and covers the third dielectric layer 160.

[0098] It should be noted that the method of forming the first dielectric layer in step S240 may be the same as the method of forming the first dielectric layer in step S330.

[0099] S250. Remove at least part of the first dielectric layer to retain a set thickness of the first dielectric layer at the bottom of the gate trench.

[0100] Specifically, Figure 13 is another structural schematic diagram for retaining a set thickness of the first dielectric layer at the bottom of the gate trench. Refer to Figure 13 , while removing at least part of the first dielectric layer 130, the third dielectric layer 160 on the sidewall of the gate trench 101 will also be removed. Finally, the surface of the remaining first dielectric layer 130 away from the bottom of the gate trench 101 is flush with the surface of the third dielectric layer 160 away from the bottom of the gate trench 101.

[0101] S260. Form a second dielectric layer on the sidewall of the gate trench.

[0102] Specifically, Figure 14 is another structural schematic diagram after forming the second dielectric layer. Refer to Figure 14 , the thickness of the second dielectric layer 140 is less than the thickness of the first dielectric layer 130 retained at the bottom of the gate trench 101. The insulating layer 150 includes the second dielectric layer 140 in the gate trench 101, the retained first dielectric layer 130, and the retained third dielectric layer 160. The materials of the first dielectric layer 130, the second dielectric layer 140, and the third dielectric layer 160 can be the same.

[0103] S270. Form a gate on the side of the insulating layer away from the gate trench.

[0104] Among them, Figure 15 is another structural schematic diagram of a semiconductor device provided by an embodiment of the present invention. Refer to Figure 15 , the gate 161 fills the remaining area of the gate trench.

[0105] The content of step S270 is the same as that of step S140. For the description of step S270, please refer to the description of step S140, which will not be repeated here.

[0106] Optionally, a second dielectric layer is formed on the sidewall of the gate trench, including: oxidizing the sidewall of the gate trench to form the second dielectric layer.

[0107] Specifically, forming the second dielectric layer by oxidation can simplify the formation process of the second dielectric layer, reduce the cost of forming the second dielectric layer, and thus reduce the manufacturing cost of the insulating layer.

[0108] Optionally, the set thickness is 2000 Å to 3000 Å; the thickness of the second dielectric layer is 500 Å to 800 Å. Such a setting can further increase the pressure-bearing capacity of the insulating layer at the bottom of the gate trench and further improve the reliability of the semiconductor device.

[0109] Specifically, the set thickness can be specifically 2000 Å, 2200 Å, 2300 Å, 2500 Å, 2800 Å, etc., and the thickness of the second dielectric layer can be specifically 500 Å, 550 Å, 600 Å, 650 Å, 700 Å, 750 Å, etc.

[0110] It should be noted that when the insulating layer 150 includes the second dielectric layer 140, the reserved first dielectric layer 130, and the reserved third dielectric layer 160 in the gate trench 101, the sum of the thickness of the reserved first dielectric layer 130 and the reserved third dielectric layer 160 in the gate trench 101 can be greater than 2000 Å and less than or equal to 3000.1 Å.

[0111] Optionally, a semiconductor body is provided, including: providing a silicon carbide semiconductor body or providing a gallium nitride semiconductor body.

[0112] Specifically, when the semiconductor body includes a silicon carbide semiconductor body, a silicon carbide metal oxide semiconductor field effect transistor (MOSFET) semiconductor device can be formed. When the semiconductor body includes a gallium nitride semiconductor body, a gallium nitride MOSFET semiconductor device can be formed. The silicon carbide MOSFET semiconductor device or the gallium nitride MOSFET semiconductor device has the advantages of high breakdown voltage, low on-resistance, and high frequency, and can further improve the performance of the semiconductor device.

[0113] Figure 16It is a schematic structural diagram of another semiconductor device provided by an embodiment of the present invention. The semiconductor device provided by the embodiment of the present invention is fabricated by using the manufacturing method of the semiconductor device provided by any embodiment of the present invention. Refer to Figure 16 , the semiconductor device provided by this embodiment includes: a semiconductor body 110 and a gate structure. Among them, the outer semiconductor body 110 includes a first surface S1 and a second surface S2 arranged opposite to each other. The semiconductor body 110 is provided with a gate trench that extends from the first surface S1 into the semiconductor body 110; the gate structure includes an insulating layer 150 and a gate 161. The insulating layer 150 includes a first dielectric layer 130 located at the bottom of the gate trench and a second dielectric layer 140 located on the sidewall of the gate trench. The thickness of the second dielectric layer 140 is less than the thickness of the first dielectric layer 130; the gate 161 is located on the side of the insulating layer 150 away from the gate trench.

[0114] In the semiconductor device provided by this embodiment, the thickness of the insulating layer at the bottom of the gate trench is greater than the thickness of the insulating layer on the sidewall of the gate trench, which can prevent the insulating layer at the bottom of the gate trench from being prematurely broken down, and is beneficial to improving the reliability of the semiconductor device.

[0115] Optionally, continue to refer to Figure 16 , the semiconductor body 110 further includes a well region 180 and a first region 170. The first region 170 is disposed on the first surface S1, and the well region 180 is disposed on the side of the first region 170 away from the first surface S1.

[0116] Specifically, the semiconductor device in this embodiment further includes a second region 190. The active region of the semiconductor device may include the first region 170 and the second region 190, or may only include the first region 170. The semiconductor device further includes a first conductive layer 191 electrically connected to the gate 161 and a second conductive layer 192 electrically connected to the active region. The semiconductor device may further include a drain; the drain may be located on the second surface S2.

[0117] It should be noted that Figures 2 - 6 , Figure 8 and Figures 10 - 16 only exemplarily show that the semiconductor device includes two gate trenches, but it is not a limitation to the present invention. The semiconductor device provided by the embodiment of the present invention may also include one gate trench or more than two gate trenches.

[0118] The embodiment of the present invention provides a power module, which includes a substrate and at least one semiconductor device described in any embodiment of the present invention. The substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the semiconductor device described in any embodiment of the present invention are included in this power module, and will not be elaborated here.

[0119] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board. Therefore, the beneficial effects of the power conversion circuit including the semiconductor device described in any embodiment of the present invention will not be elaborated herein.

[0120] An embodiment of the present invention further provides a vehicle, which includes a load and a power conversion circuit according to any embodiment of the present invention. The power conversion circuit is used to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current, and then input it to the load. Therefore, the beneficial effects of the vehicle including the power conversion circuit described in any embodiment of the present invention will not be elaborated herein.

[0121] It should be understood that various forms of the processes shown above can be used, and steps can be reordered, added, or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitations are imposed herein.

[0122] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub - combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body is provided with a gate trench, wherein the gate trench extends from the first surface into the semiconductor body; An insulating layer and a gate are formed in the gate trench, comprising: forming a first dielectric layer in the gate trench and the first surface, and removing at least a portion thereof to retain the first dielectric layer of a set thickness at the bottom of the gate trench; forming a second dielectric layer on the sidewall of the gate trench, wherein the thickness of the second dielectric layer is less than the thickness of the first dielectric layer retained at the bottom of the gate trench, and the insulating layer includes the second dielectric layer and the retained first dielectric layer; A gate is formed on a side of the insulating layer away from the gate trench.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a first dielectric layer in the gate trench and the first surface comprises: Forming a spin-on layer on the gate groove and the first surface by a coating process; Under set conditions, the spin-on layer is annealed to form the first dielectric layer.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The material of the spin-on-coat layer includes spin-on-glass, and the spin-on-glass includes silicon and oxygen; The material of the first dielectric layer includes silicon dioxide.

4. The method for manufacturing a semiconductor device according to claim 2, wherein: The set conditions include a set temperature, a first concentration of nitrogen and a second concentration of oxygen, and the first concentration is greater than the second concentration; The set temperature is 450°C to 600°C.

5. The method for manufacturing a semiconductor device according to claim 2, wherein: Before forming a spin-on coating layer in the gate trench and on the first surface by using a coating process, the method comprises: A third dielectric layer is formed at the bottom and sidewalls of the gate trench; wherein the material of the third dielectric layer is the same as that of the first dielectric layer.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a second dielectric layer on the sidewall of the gate trench comprises: The sidewalls of the gate trench are oxidized to form a second dielectric layer.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The set thickness is 2000A to 3000A; The thickness of the second dielectric layer is 500 Å to 800 Å.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: The semiconductor body is provided, comprising: A silicon carbide semiconductor body is provided or a gallium nitride semiconductor body is provided.

9. A semiconductor device, characterized in that: Made by the method for making a semiconductor device according to any one of claims 1 to 8; The semiconductor device comprises: A semiconductor body, wherein the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body is provided with a gate trench, and the gate trench extends from the first surface into the semiconductor body; A gate structure, wherein the gate structure includes the insulating layer and the gate, the insulating layer includes a first dielectric layer located at the bottom of the gate trench and a second dielectric layer located at the sidewall of the gate trench, the thickness of the second dielectric layer is less than the thickness of the first dielectric layer; the gate is located on a side of the insulating layer away from the gate trench.

10. A power module, characterized in that: The method comprises a substrate and at least one semiconductor device according to claim 9, wherein the substrate is used for carrying the semiconductor device.

11. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device as claimed in claim 9, wherein the semiconductor device is electrically connected to the circuit board.

12. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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