Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The performance of a semiconductor device is improved by reducing the operating voltage of a ferroelectric memory equipped with a ferroelectric film. On a semiconductor substrate, a laminate including a paraelectric film (which is an insulating film) and a ferroelectric film made of three or more ferroelectric layers on the insulating film is formed, and a metal film and a gate electrode are formed on the ferroelectric film. By discretely placing impurity particles between the ferroelectric layers in contact with each other, the crystallinity of the ferroelectric film is enhanced.

Description

[0001] Cross - Reference to Related Applications

[0002] The disclosure of Japanese Patent Application No. 2023-223662, including the specification, drawings, and abstract, filed on December 28, 2023, is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION

[0003] The present invention relates to a semiconductor device and a method for manufacturing the same, and particularly to a semiconductor device equipped with a ferroelectric memory cell and a method for manufacturing the same.

[0004] In recent years, ferroelectric memory cells using a ferroelectric film have been developed as semiconductor memory elements that operate at low voltages. A ferroelectric memory cell is a non-volatile memory cell that changes between a write state and an erase state by controlling the polarization direction of a ferroelectric material. Japanese Patent Laid-Open No. 2019-201172 (Patent Document 1) discloses the structure and manufacturing method of a ferroelectric memory cell. SUMMARY OF THE INVENTION

[0005] Hafnium-based Hf 0.5 Zr 0.5 O2 (HZO) is widely known as a ferroelectric film. However, there is a problem that it is difficult to reduce the operating voltage of a ferroelectric memory cell using an existing HZO film structure.

[0006] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings.

[0007] Typical embodiments in the embodiments disclosed in this application will be briefly described as follows.

[0008] A semiconductor device according to an embodiment includes a ferroelectric memory cell equipped with a paraelectric film and a ferroelectric film sequentially provided on a semiconductor substrate, and the ferroelectric film is a laminate including three or more ferroelectric layers.

[0009] A method for manufacturing a semiconductor device according to an embodiment involves sequentially forming a paraelectric film, a laminate structure, and a metal film on a semiconductor substrate, and then performing heat treatment. The laminate structure is formed by repeating at least three times the step of forming an amorphous layer and discretely providing impurity particles on the surface of the amorphous layer. In the heat treatment step, each amorphous layer in the amorphous layer crystallizes in the horizontal direction to form a ferroelectric laminate film.

[0010] According to an embodiment, the performance of a semiconductor device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a cross-sectional view showing a main part of the semiconductor device in the first embodiment.

[0012] Figure 2 It is a cross-sectional view of the semiconductor device in the first embodiment.

[0013] Figure 3 It is a table showing the operating conditions of the semiconductor device in the first embodiment.

[0014] Figure 4 It is a cross-sectional view during the manufacturing process of the semiconductor device in the first embodiment.

[0015] Figure 5 It is Figure 4 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0016] Figure 6 It is Figure 5 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0017] Figure 7 It is Figure 6 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0018] Figure 8 It is Figure 7 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0019] Figure 9 It is Figure 8 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0020] Figure 10 It is Figure 9 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0021] Figure 11 It is Figure 10 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0022] Figure 12 It is Figure 11 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0023] Figure 13 It is Figure 12 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0024] Figure 14 It is Figure 13 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0025] Figure 15 It is Figure 14 a cross-sectional view during the manufacturing process of the semiconductor device after that.

[0026] Figure 16 is a perspective view showing a two-dimensional crystallization pattern of an amorphous layer.

[0027] Figure 17 is a cross-sectional view showing a two-dimensional crystallization pattern of an amorphous layer.

[0028] Figure 18 is a cross-sectional view explaining the film thickness range of an amorphous layer where two-dimensional nucleation is dominant.

[0029] Figure 19 is a graph showing the relationship between the radius of a crystal and the driving energy of the crystal.

[0030] Figure 20 is a table showing the experimental results for exploring methods for reducing the surface energy σ2.

[0031] Figure 21 is a schematic diagram showing the arrangement of impurity particles in the first embodiment.

[0032] Figure 22 is a graph showing the writing characteristics of the semiconductor device in the first embodiment.

[0033] Figure 23 is a graph showing the erasing characteristics of the semiconductor device in the first embodiment.

[0034] Figure 24 is a graph showing the X-ray diffraction results on the ferroelectric film in the first embodiment.

[0035] Figure 25 is a graph showing the intensity of rectangular bodies in the ferroelectric film in the first embodiment.

[0036] Figure 26 is a flowchart showing the manufacturing process of the semiconductor device in the second embodiment.

[0037] Figure 27 is a cross-sectional view during the manufacturing process of the semiconductor device in the second embodiment.

[0038] Figure 28 is a flowchart showing the manufacturing process of the semiconductor device in the third embodiment.

[0039] Figure 29 is a cross-sectional view showing a three-dimensional crystallization pattern of an amorphous layer.

[0040] Figure 30 is a cross-sectional view showing the main part of the semiconductor device in the comparative example.

[0041] Figure 31 is a graph showing the writing characteristics of the semiconductor device in the comparative example.

[0042] Figure 32 It is a graph showing the erasure characteristics of the semiconductor device in the comparative example. Detailed implementation

[0043] In the following embodiments, when necessary for convenience, it is divided into multiple sections or embodiments, but unless otherwise specified, they are independent of each other, and one section or embodiment among them is related to modification examples, details, supplementary explanations, etc. of a part or all of another section or embodiment. Additionally, in the following embodiments, the number of elements, etc. (including quantity, number, amount, range, etc.) is not limited to the mentioned number, except in cases where it is specifically specified or is clearly limited to a specific number in principle, and it can be equal to or the mentioned number, or it can be equal to or the mentioned number.

[0044] Furthermore, in the following embodiments, constituent elements (including element steps, etc.) are not necessarily essential except in cases where it is specifically specified, cases where it is considered obviously necessary in principle, etc. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is assumed that these shapes, etc. are substantially approximate or similar to these shapes, etc., except in cases where they are specifically specified and cases where it is considered obvious in principle, etc. This also applies to the above numerical values and ranges.

[0045] Hereinafter, the embodiments will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, components having the same function are denoted by the same reference numerals, and their repeated description is omitted. Additionally, in the following embodiments, the description of the same or similar parts is not repeated in principle except when it is particularly necessary.

[0046] Additionally, hereinafter, the direction along the main surface of the semiconductor substrate may be referred to as the planar direction, and the direction perpendicular to the main surface of the semiconductor substrate may be referred to as the thickness direction.

[0047] (First Embodiment)

[0048] (Outline of the First Embodiment)

[0049] Figure 1 A schematic cross-sectional view showing the main part of the semiconductor device of this embodiment is shown. Figure 1 It mainly shows the stacked structure between the semiconductor substrate of the ferroelectric memory cell and the gate electrode. As Figure 1As shown, the semiconductor device of this embodiment has a semiconductor substrate SB. The semiconductor substrate SB includes a first main surface as the upper surface and a second main surface on the opposite side of the first main surface. On the first main surface of the semiconductor substrate SB, an insulating film IF1 as a paraelectric film, a ferroelectric film FEF including a plurality of ferroelectric layers, a metal film MF, and a gate electrode GE are sequentially stacked.

[0050] The ferroelectric film FEF includes a plurality of ferroelectric layers FE1, FE2, FE3, and FE4 stacked in order upward from the semiconductor substrate SB. That is, the ferroelectric film FEF includes a stacked layer including three or more ferroelectric layers stacked in order from the semiconductor substrate SB side. Between the ferroelectric layers FE1 and FE2, between the ferroelectric layers FE2 and FE3, and between the ferroelectric layers FE3 and FE4, impurity particles GR are discretely present.

[0051] Next, it will be explained how having three or more ferroelectric layers in the ferroelectric film enhances the crystallinity of the ferroelectric film of the ferroelectric memory cell, thereby reducing the operating voltage of the ferroelectric memory cell.

[0052] (Semiconductor device structure)

[0053] Figure 2 The specific structure of the ferroelectric memory cell of the semiconductor device of this embodiment is shown. Figure 2 The shown ferroelectric memory cell has a semiconductor substrate SB, which has a first main surface and a second main surface. The semiconductor substrate SB is made of, for example, p-type single crystal silicon (Si) with a resistivity of about 1 to 10 Ω·cm. A p-type well region PW reaching a predetermined depth from the first main surface side to the second main surface side is formed in the semiconductor substrate SB. A plurality of element isolation regions STI reaching a predetermined depth toward the second main surface side are formed on the first main surface of the semiconductor substrate SB. The plurality of element isolation regions STI are formed by embedding an insulating film (such as a silicon oxide film) into grooves formed in the semiconductor substrate SB.

[0054] In this embodiment, as the ferroelectric memory cell, a memory cell of a so-called MFIS (Metal Ferroelectric Insulator Semiconductor) structure in which a ferroelectric film FEF is applied to a transistor structure is exemplified.

[0055] On the semiconductor substrate SB including the well region PW, the insulating film IF1 is formed as a paraelectric film. The insulating film IF1 is, for example, a silicon oxide (SiO2) film or a silicon oxynitride (Si3NO4) film with a thickness of 2 nm or less. The insulating film IF1 is a film provided to stabilize the interface between the semiconductor substrate SB and the ferroelectric film FEF or to prevent electrons from entering the ferroelectric film FEF from the semiconductor substrate SB when a voltage is applied to the gate electrode GE during the operation of the ferroelectric memory cell.

[0056] A ferroelectric film FEF is formed on an insulating film IF1. The ferroelectric film FEF has impurity particles GR present between ferroelectric layers FE1, FE2, FE3, and FE4, which are stacked in sequence from the semiconductor substrate SB side.

[0057] Each of the ferroelectric layers FE1 to FE4 is made of a metal oxide film and is a high dielectric constant layer having a dielectric constant higher than, for example, that of a silicon nitride film. In addition, the thickness of each of the ferroelectric layers FE1 to FE4 is, for example, 0.5 nm or more and 2 nm or less. The thickness of the ferroelectric film FEF is, for example, 6 nm or more and 20 nm or less.

[0058] Moreover, each of the ferroelectric layers FE1 to FE4 is an insulating layer composed of a material that exhibits dielectric polarization when an electric field is applied and retains the polarization even after the electric field is removed, that is, a ferroelectric. That is, even when no electric field is applied, polarization is maintained in the ferroelectric layers FE1 to FE4 (ferroelectric film FEF). A ferroelectric is a material in which electric dipoles are aligned even without an external electric field, and the electric field can change the direction of the dipoles.

[0059] In addition, each of the ferroelectric layers FE1 to FE4 needs to be a tetragonal crystal. In other words, the film mainly includes crystals other than tetragonal crystals, that is, a paraelectric film. Therefore, in a ferroelectric memory cell, it is necessary to form as many tetragonal crystals including the ferroelectric layers FE1 to FE4 as possible to increase the remanent polarization of the ferroelectric film FEF, improve the performance as a ferroelectric, and reduce the driving power of the ferroelectric memory cell. That is, it is necessary to enhance the crystallinity of the ferroelectric layers FE1 to FE4.

[0060] Each of the ferroelectric layers FE1 to FE4 is an insulating film (HZO film) made of a material including a metal oxide and a first element. The metal oxide is, for example, hafnium oxide (HfO) or gallium oxide (GaO). The first element is zirconium (Zr), silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb).

[0061] Impurity particles GR are formed between the ferroelectric layers FE1 and FE2 as part of the ferroelectric film FEF. As described later, the impurity particles GR serve as nuclei for the crystal growth of the ferroelectric layers FE1 to FE4 from the amorphous state to the tetragonal crystal during the manufacturing process of the ferroelectric film FEF. Therefore, the impurity particles GR are separated from each other and are discretely arranged. In other words, the impurity particles GR are not formed as a continuous film like the ferroelectric layers FE1 to FE4, but are discontinuously arranged in the direction along the first main surface of the semiconductor substrate SB. If each of the impurity particles GR in the impurity particles GR is connected to form a film, their function as crystal nuclei of the impurity particles GR will be reduced.

[0062] The impurity particles GR include a second element different from oxygen and the first element. The second element is silicon (Si), aluminum (Al), carbon (C), nitrogen (N), hydrogen (H), or oxygen (O). Specifically, the impurity particles GR are aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, oxygen, or a mixture or compound thereof. In this embodiment, each of the impurity particles GR in the impurity particles GR includes, for example, one atom, a compound, or an aggregate of 2 to 4 atoms. Here, the case where the impurity particles GR are AlN (aluminum nitride) particles is mainly described.

[0063] Moreover, during the manufacturing process of the ferroelectric film FEF, the impurity particles GR may combine with the materials included in the ferroelectric layers FE1, FE2, FE3, or FE4 near the interface between the upper ferroelectric layer and the lower ferroelectric layer. That is, the impurity particles GR may ultimately be a compound combined with aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, or oxygen and hafnium or the above-mentioned first element.

[0064] The surface density of the impurity particles GR is in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 Moreover, the volume density of the impurity particles GR is in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 The average distance between the impurity particles GR in the plan view is between 2.5 nm and 11 nm.

[0065] A metal film MF is formed on the ferroelectric film FEF. The metal film MF is, for example, a conductive film formed of a titanium nitride film, a tantalum nitride film, or a tungsten film. The thickness of the metal film MF is, for example, between 2 nm and 10 nm. The metal film MF serves as a capping film provided during the manufacturing process of the ferroelectric film FEF to apply stress to the ferroelectric layers FE1 to FE4 and control the crystal orientation of each of the ferroelectric layers FE1 to FE4. Therefore, after the ferroelectric film FEF is formed, if each of the ferroelectric layers FE1 to FE4 can exist as an orthorhombic crystal, the metal film MF can be removed. However, removing the metal film MF may cause a change in the crystal orientation of each of the ferroelectric layers FE1 to FE4, so it is preferably left. If the metal film MF is left, it can also be used as a part of the gate electrode GE mentioned later.

[0066] A gate electrode GE is formed on the metal film MF. The gate electrode GE is, for example, a conductive film made of a polysilicon film doped with n-type impurities. As the material constituting the gate electrode GE, a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a laminated film appropriately laminated with these metal films, can also be used instead of the polysilicon film.

[0067] Sidewall spacers SW are formed on both sides of the gate electrode GE. The sidewall spacers SW are formed of a laminated film of, for example, a silicon oxide film and a silicon nitride film.

[0068] In the well region PW below the sidewall spacers SW, an extension region EX is formed as a low-concentration n-type impurity region. Further, in the well region PW aligned with the sidewall spacers SW, a diffusion region D1 is formed, which is an n-type impurity region having a higher concentration than the extension region EX. The extension region EX and the diffusion region D1 are interconnected and respectively constitute a part of the source region or a part of the drain region of the ferroelectric memory cell.

[0069] The ferroelectric memory cell includes at least an insulating film IF1, a ferroelectric film FEF, a gate electrode GE, and a pair of diffusion regions D1 that constitute a part of the source region or a part of the drain region.

[0070] On the gate electrode GE and the diffusion region D1, a silicide layer SI including, for example, cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel platinum silicide (NiPtSi) is formed. The silicide layer SI is mainly formed to reduce the contact resistance with a plug PG mentioned later.

[0071] An interlayer insulating film IL1 is formed on the ferroelectric memory cell. The interlayer insulating film IL1 is, for example, a silicon oxide film. In the interlayer insulating film IL1, a plurality of contact holes are formed, and a plurality of plugs PG are formed in these contact holes. The plug PG includes a barrier metal film made of, for example, a titanium film, a titanium nitride film, or a laminated film of these films, and the conductive film mainly includes tungsten. The plug PG is electrically connected to the diffusion region D1 through the silicide layer SI. Although not shown, there is also a plug PG in the interlayer insulating film IL1 that is electrically connected to the gate electrode GE.

[0072] Further, although not shown, a plurality of wirings are formed on the plug PG. For example, another interlayer insulating film is formed on the interlayer insulating film IL1, and grooves for wiring are formed in this interlayer insulating film. Then, a first layer of the wiring connected to the plug PG is formed by embedding a conductive film mainly including copper in these grooves for wiring.

[0073] (Operation of the ferroelectric memory cell)

[0074] Next, an example of the operation of the ferroelectric memory cell will be described with reference to Figure 3 An example of the operation of the ferroelectric memory cell will be described.

[0075] Figure 3 is a table showing an example of the voltages applied to respective parts of a selected memory cell during "write", "erase", and "read" operations. Figure 3The table in Figure 2 shows the voltages applied to each part during each of these operations. Specifically, the table includes the voltage Vd applied to the drain region (one diffusion region D1) of the ferroelectric memory cell shown in Figure 3 , the voltage Vg applied to the gate electrode GE, the current Vs applied to the source region (another diffusion region D1), and the voltage Vb applied to the well region PW. Note that

[0076] In this embodiment, "write" is defined as the state where the polarization of the ferroelectric film FEF is upward, resulting in a relatively high threshold voltage of the ferroelectric memory cell. On the contrary, "erase" is defined as the state where the polarization of the ferroelectric film FEF is downward, resulting in a relatively low threshold voltage of the ferroelectric memory cell.

[0077] The write operation is performed by applying a negative voltage to the gate electrode GE. That is, voltages such as those shown in the "write" column in Figure 3 are applied to each part of the selected memory cell to be written. Thus, the polarization of the ferroelectric film FEF becomes upward, the threshold voltage of the ferroelectric memory cell increases, and the ferroelectric film FEF enters the write state.

[0078] The erase operation is performed by applying a positive voltage to the gate electrode GE. That is, voltages such as those shown in the "erase" column in Figure 3 are applied to each part of the selected memory cell to be erased. This causes the polarization of the ferroelectric film FEF to become downward, the threshold voltage of the ferroelectric memory cell decreases, and the ferroelectric film FEF enters the erase state.

[0079] During the read operation, voltages such as those shown in the "read" column in Figure 3 are applied to each part of the selected memory cell to be read. By setting the voltage Vg applied to the gate electrode GE to a value between the threshold voltage of the ferroelectric film FEF in the write state and the threshold voltage of the ferroelectric film FEF in the erase state, the write and erase states can be distinguished.

[0080] (Manufacturing process of semiconductor device)

[0081] The following uses Figures 4 to 15 to describe the manufacturing method of the semiconductor device according to this embodiment. Figures 4 to 15 Each of the drawings in

[0082] Figure 4 shows a cross-sectional view of the region where the ferroelectric memory cell is formed.

[0083] First, a semiconductor substrate SB made of single-crystalline silicon is prepared, into which p-type impurities are introduced. Next, trenches are formed in the semiconductor substrate SB using a photolithography and etching process. Then, an insulating film such as a silicon oxide film is formed to fill the trenches, and thereafter, the insulating film outside the trenches is removed by a chemical mechanical polishing (CMP) method, thereby forming an element isolation region STI made of the remaining insulating film in the trenches.

[0084] Next, a p-type well region PW is formed by introducing impurities into the semiconductor substrate SB using a photolithography and ion implantation method.

[0085] Figure 5 The process of forming the insulating film IF1 is shown.

[0086] On the semiconductor substrate SB, an insulating film IF1 made of, for example, silicon oxide or silicon oxynitride is formed by performing a heat treatment in an atmosphere including oxygen, for example. The thickness of the insulating film IF1 is, for example, 1 nm or less.

[0087] Figure 6 The process of forming the amorphous layer AM1 is shown.

[0088] On the insulating film IF1, an amorphous layer (amorphous film) AM1 is formed, for example, by an atomic layer deposition (ALD) method. The thickness of the amorphous layer AM1 is, for example, 0.5 nm to 2 nm. The amorphous layer AM1 is a film made of a material including hafnium (Hf), oxygen (O), and a first element such as zirconium (Zr). Moreover, the first element can be replaced with silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb).

[0089] Figure 7 The process of forming the impurity particles GR is shown.

[0090] Transfer the semiconductor wafer from the ALD apparatus used in the process of forming the amorphous layer AM1 in Figure 6 to another apparatus, and perform the process in Figure 7 . In this embodiment, impurity particles GR are formed on the amorphous layer AM1 by a sputtering method. The impurity particles GR are separated from each other. In other words, the impurity particles GR are not formed as a continuous film like the amorphous layer AM1, but are formed discretely. That is, the impurity particles GR do not cover the entire amorphous layer AM1, but are scattered on the amorphous layer AM1. Therefore, a part of the amorphous layer AM1 is covered with the impurity particles GR, while other parts of the amorphous layer AM1 are exposed from the impurity particles GR. Moreover, some of the impurity particles GR are deposited on the upper surface of the amorphous layer AM1, but impurity particles GR are also introduced near the upper surface inside the amorphous layer AM1. For this reason, the impurity particles GR serve as crystal nuclei in the process of crystallizing the amorphous layer AM1 and other layers described later.

[0091] In addition, the impurity particles GR are aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, oxygen, or any mixture or compound thereof. In this embodiment, for the sake of explanation, an exemplary case where the second element is aluminum is illustrated. Here, the impurity particles GR include aluminum nitride (AlN).

[0092] Moreover, although the impurity particles GR can be formed by chemical vapor deposition (CVD) method instead of sputtering, they are preferably formed by separating them from each other as mentioned above. Therefore, the formation method of the impurity particles GR is preferably performed by sputtering. Additionally, the surface density of the impurity particles GR on the upper surface of the amorphous layer AM1 is in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 . This allows precise control of the grain size radius of the impurity particles GR, for example, in the range of 0.1 nm to 1 nm. Here, the surface density of the impurity particles GR is set to, for example, 1×10 13 / cm 2 .

[0093] In addition, in order to prevent the impurity particles GR from diffusing excessively into the amorphous layer AM1, the above-mentioned sputtering method is preferably performed in a temperature range of 1 degree Celsius or higher and 150 degrees Celsius or lower.

[0094] As mentioned above, the second element constituting the impurity particles GR can be an element other than aluminum, and in this case, the formation method of the impurity particles GR can also be performed using ion implantation instead of sputtering. When the ion implantation method is used, the dose of the impurity particles GR is set in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 .

[0095] Figure 8 Illustrates the formation process of the amorphous layer AM2.

[0096] On top of the impurity particles GR and the amorphous layer AM1, an amorphous layer (amorphous film) AM2 is formed, for example, by the ALD method. Through this process, the impurity particles GR are covered by the amorphous layer AM2. The thickness of the amorphous layer AM2 is, for example, 0.5 nm to 2 nm. The amorphous layer AM2 includes the same material as the amorphous layer AM1, for example, a film made of a material including hafnium (Hf), oxygen (O), and zirconium (Zr) as the first element. Moreover, the first element can be silicon (Si), germanium (Ge), yttrium (Y), lanthanum (La), or ytterbium (Yb) instead of zirconium.

[0097] Figure 9 Shows the formation process of the amorphous layers AM3 and AM4 and the impurity particles GR.

[0098] By repeating the processes described by Figure 7 and 8 Impurity particles GR, amorphous layer AM3, impurity particles GR, and amorphous layer AM4 are sequentially formed over amorphous layer AM2. Thus, a laminated structure including amorphous layers AM1, AM2, AM3, and AM4 stacked in sequence is formed on insulating film IF1. In other words, the laminated structure is formed by sequentially repeating the process of forming amorphous layers and impurity particles three or more times. Between amorphous layers AM1 and AM2, AM2 and AM3, and AM3 and AM4, impurity particles GR are discretely arranged in a direction along the first main surface of semiconductor substrate SB. The film thickness of each of amorphous layers AM1 to AM4 is, for example, 2 nm.

[0099] Figure 10 The process of forming metal film MF is illustrated.

[0100] Over amorphous layer AM4, a metal film MF made of, for example, titanium nitride, tantalum nitride, or tungsten is formed using, for example, a CVD or sputtering method. The thickness of metal film MF is, for example, between 2 nm and 10 nm. Metal film MF is provided mainly to apply stress to amorphous layers AM1 to AM4.

[0101] Figure 11 The process of forming ferroelectric layers FE1, FE2, FE3, and FE4 and ferroelectric film FEF is shown.

[0102] When metal film MF is formed over amorphous layer AM4, heat treatment (annealing) is performed. This causes amorphous layer AM1 to crystallize to form tetragonal crystal ferroelectric layer FE1, and causes amorphous layer AM2 to crystallize to form ferroelectric layer FE2, which is also tetragonal crystal. Similarly, this heat treatment causes amorphous layer AM3 to crystallize to form ferroelectric layer FE3, and causes amorphous layer AM4 to crystallize to form ferroelectric layer FE4, both of which are tetragonal crystals. This heat treatment is performed at a temperature of 500 to 700 degrees Celsius by, for example, an RTA (rapid thermal annealing) method. Through this heat treatment, the stacked structure including multiple amorphous layers crystallizes to form ferroelectric film FEF.

[0103] In this embodiment, impurity particles GR are formed as multiple crystal grains between stacked amorphous layers. These crystal grains serve as crystal nuclei during the crystallization process. Through the above heat treatment, some of the crystal grains that are impurity particles GR combine with the substances included in amorphous layers AM1 and AM2 to form a compound. That is, after the heat treatment, impurity particles GR are considered to be a compound formed by a combination of aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen, or oxygen and hafnium or the above first element. The manner in which the amorphous layers crystallize (crystal growth) around these crystal nuclei due to the heat treatment will be described later.

[0104] Figure 12 The step of forming the conductive film FG is shown.

[0105] Above the metal film MF, a conductive film FG made of polysilicon into which an n-type impurity is introduced is formed, for example, by a CVD method. As mentioned above, if the ferroelectric film FEF can be sufficiently maintained as a tetragonal crystal, the metal film MF can be removed before forming the conductive film FG.

[0106] Figure 13 The process of forming the gate electrode GE is shown.

[0107] The conductive film FG is patterned by a photolithography and etching process. This forms the gate electrode GE made of the conductive film FG. Subsequently, by performing an etching process, the metal film MF, the ferroelectric film FEF, and the insulating film IF1 not covered by the gate electrode GE are removed. Here, an example is given in which the metal film MF remains under the gate electrode GE (conductive film FG), and thus the metal film MF serves as a part of the gate electrode GE.

[0108] Figure 14 The process of forming the extension region EX is shown.

[0109] An n-type impurity region, that is, the extension region EX, is formed at a position aligned with the gate electrode GE within the well region PW by photolithography and ion implantation. The extension region EX constitutes a part of the source region or the drain region of the ferroelectric memory cell.

[0110] Figure 15 The process of forming the sidewall spacer SW, the diffusion region D1, and the silicide layer SI is shown.

[0111] First, a silicon oxide film and a silicon nitride film are sequentially formed above the gate electrode GE, for example, by CVD. Next, the silicon nitride film is anisotropically etched. Then, the silicon oxide film formed on the upper surface of the gate electrode GE is removed. Thus, the sidewall spacer SW including a laminated film of silicon oxide and silicon nitride is formed on the side surface of the gate electrode GE.

[0112] Next, a diffusion region D1 as an n-type impurity region is formed at a position aligned with the sidewall spacer SW within the well region PW by photolithography and ion implantation. The diffusion region D1 has a higher impurity concentration than the extension region EX, is connected to the extension region EX, and constitutes a part of the source region or the drain region of the ferroelectric memory cell.

[0113] Next, a low-resistance silicide layer SI is formed on the upper surfaces of the diffusion region D1 and the gate electrode GE by a self-aligned silicide technique.

[0114] The silicide layer SI can be formed specifically as follows: First, a metal film for forming the silicide layer S1 is formed on the semiconductor substrate SB to cover the diffusion region D1 and the gate electrode GE. The metal film includes, for example, cobalt, nickel, or a nickel-platinum alloy. Next, a first heat treatment at about 300 to 400 degrees Celsius is applied to the semiconductor substrate SB, and then a second heat treatment at about 600 to 700 degrees Celsius is applied to cause the materials included in the diffusion region D1 and the gate electrode GE to react with the metal film. Thus, a silicide layer SI including cobalt silicide (CoSi2), nickel silicide (NiSi), or nickel-platinum silicide (NiPtSi) is formed on the upper surfaces of the diffusion region D1 and the gate electrode GE. Subsequently, the unreacted metal film is removed.

[0115] In addition, if a metal film such as a titanium nitride film, an aluminum film, or a tungsten film, or a laminated film obtained by appropriately laminating these films is used as the material constituting the gate electrode GE, then after Figure 15 the process, a polysilicon film used as the material of the gate electrode GE can be replaced with the above metal film or the above laminated film by using a so-called post-gate process.

[0116] Accordingly, a ferroelectric memory cell having an MFIS structure is formed. That is, the ferroelectric memory cell includes at least an insulating film IF1, a ferroelectric film FEF, a gate electrode GE, and a pair of diffusion regions D1 that constitute a part of the source region or a part of the drain region.

[0117] Subsequently, the structure shown in Figure 2 is obtained through the following steps.

[0118] First, an interlayer insulating film IL1 made of, for example, silicon oxide is formed above the ferroelectric memory cell by, for example, a CVD method. Next, using a photolithography and etching process, a plurality of contact holes are formed in the interlayer insulating film IL1. Then, a barrier metal film including, for example, a titanium film, a titanium nitride film, or a laminated film of these films is formed in these plurality of contact holes, and a conductive film mainly including tungsten is formed on the barrier metal film. Next, by removing, for example, the barrier metal film and the conductive film outside the contact holes by a CMP method, a plug PG is formed in the contact holes. The plug PG is electrically connected to the diffusion region D1 through the silicide layer SI. Although not shown in the drawings, there is also a plug PG that is electrically connected to the gate electrode GE.

[0119] (Crystal Growth)

[0120] The ferroelectric memory cell operates at a relatively low voltage and is characterized by low power consumption. However, in a structure composed of two ferroelectric layers, it is difficult to form a ferroelectric memory cell that operates at a lower voltage, for example, less than 4V. The difficulty in forming such a low-voltage ferroelectric memory cell is due to the crystallization of the ferroelectric layer occurring through isotropic crystal growth (3D nucleation).

[0121] Figure 29 shows the crystal growth mode in the ferroelectric layer as a comparative example. As Figure 29 shown, in the comparative barrier, the ferroelectric film is formed by crystallizing only two stacked amorphous layers AM1 and AM2. The film thickness of each of the amorphous layers AM1 and AM2 is, for example, 3 nm. Impurity particles GR are spaced apart and arranged between the amorphous layers AM1 and AM2. When these amorphous layers AM1 and AM2 are heat-treated, each of them crystallizes three-dimensionally around the impurity particle GR serving as the crystal nucleus CR3. In other words, the crystal nucleus CR3 expands spherically. Each crystal nucleus CR3 grows within each of the amorphous layers AM1 and AM2 with the impurity particle GR between them as the center.

[0122] However, in this case, when the grown crystal nuclei CR3 collide, the crystal growth temporarily stops. Therefore, gaps that cannot be crystallized are formed between the crystals, and amorphous regions (non-crystallized regions) are left in these gaps. Therefore, the crystal density showing ferroelectricity within the ferroelectric film becomes low. That is, due to the poor crystallinity of the ferroelectric film, it is difficult to reduce the operating voltage of the ferroelectric memory cell equipped with such a ferroelectric film.

[0123] In contrast, the crystallization process in the present embodiment (i.e., Figure 11 the heat treatment process described in Figure 16 and 17 ) suppresses the formation of the above-mentioned gaps and improves the crystallinity of the ferroelectric film by causing crystal growth in the horizontal direction (i.e., two-dimensionally) in the amorphous layer around the impurity particle GR, as Figure 16 is a perspective view explaining the crystallization mode of the amorphous layer, and Figure 17 is a cross-sectional view explaining the crystallization mode of the amorphous layer. Note that, for clarity, the hatching of the amorphous layer is omitted in Figure 17 .

[0124] Here, the crystal nucleus CR2 expands in a disk shape with the impurity particle GR as the center, and its thickness basically does not exceed the film thickness of each of the amorphous layers AM1 to AM4. The crystal nucleus CR2 expands only in the horizontal direction (lateral direction) within each of the amorphous layers, and when it collides with another crystal nucleus CR2, the crystal growth temporarily stops. Therefore, compared with the comparative example, the formation of the above-mentioned gaps can be suppressed.

[0125] In this embodiment, although the existence of three-dimensional grown crystals can be imagined, two-dimensional nucleation dominates throughout the ferroelectric film. To ensure that two-dimensional nucleation dominates crystal growth, the surface energy of the horizontal plane of the grains in each amorphous layer in the amorphous layer is made lower than the surface energy of the vertical plane of the grains, and the film thickness of each amorphous layer in the amorphous layer is controlled within a certain range (here, below 2 nm). This makes it possible to expect epitaxial crystal growth. To reduce the surface energy of the horizontal plane of the grains in each amorphous layer in the amorphous layer compared to the surface energy of the vertical plane of the grains in each amorphous layer in the amorphous layer, it is sufficient to discretely control the arrangement of impurity particles GR according to at least one of the following two conditions. That is, the surface density of the impurity particles GR is in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 . In addition, the volume density of the impurity particles GR is in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 . Additionally, the average distance between the impurity particles GR in the plan view is 2.5 nm or more and 11 nm or less. As in the comparative example of Figure 29 , there is a risk that three-dimensional nuclear growth is dominated only by two amorphous layers. Therefore, in this embodiment, three or more amorphous layers are formed.

[0126] Next, use Figure 18 to explain the film thickness range of the amorphous layer in which two-dimensional nuclear growth dominates. In Figure 18 , the three-dimensional growth crystal nucleus CR3 is shown on the left, and the two-dimensional growth crystal nucleus CR2 is shown on the right. The boundary between the amorphous layers AM1 and AM2 is shown by a dashed line. In this embodiment in which the crystal nucleus CR2 grows two-dimensionally, amorphous layers AM3 and AM4 (not shown) are also provided above.

[0127] Figure 18 The "n - 1 layer" shown on the right side of refers to the bottom surface of the first amorphous layer AM1, the "n layer" refers to the bottom surface of the second amorphous layer AM2, and the "n + 1 layer" refers to the upper surface of the second amorphous layer AM1 (or the bottom surface of the third amorphous layer AM3). d represents the thickness of each amorphous layer in the amorphous layer. σ1 is the surface energy within the n layer of the amorphous layer (unit: J / m 2 ), and σ2 is the surface energy of each layer interface (unit: J / m 2 ). Here, if the driving force for crystallization (unit: J / m 2) If it is ΔG, the critical growth radius Rc(3D) of the three-dimensional growth crystal nucleus CR3 is expressed as Rc(3D) = 2σ1 / ΔG>d. In addition, the critical growth radius Rc(2D) of the two-dimensional growth crystal nucleus CR2 is expressed as Rc(2D) = dσ1 / (dΔG - 2σ2).

[0128] The relationship between the radius of the crystal and the driving energy of the crystal is shown by Figure 19 the curve graph shown. Figure 19 In the curve graph of, the horizontal axis is the radius of the crystal, and the vertical axis is the Gibbs free energy (driving energy) of the crystal. In Figure 19 , the curve graph during the formation of three-dimensional nucleus growth (crystal nucleus CR3) is shown by a dashed line, and the curve graph during the formation of two-dimensional nucleus growth (crystal nucleus CR2) is shown by a solid line. As Figure 19 shown, the critical growth radius Rc(2D) of the two-dimensional growth crystal nucleus CR2 is less than the critical growth radius Rc(3D) of the three-dimensional growth crystal nucleus CR3. In other words, when both crystal nuclei CR3 and CR2 start to crystallize and their radii gradually increase, the crystallization of crystal nucleus CR2 starts while its radius is still small, and when the crystallization is completed, crystal nucleus CR2 becomes larger and dominates crystal nucleus CR3. σ2 represents wettability, and its value depends on the amount of added impurity particles GR and the surface treatment of the amorphous layer.

[0129] Figure 20 The table in shows the experimental results of the inventor's exploration of methods to reduce the surface energy σ2. In these experiments, aluminum nitride was used as the impurity particles, but a mixture of silicon and aluminum can also be used instead. Here, the aluminum nitride impurity particles are discretely added to the upper surface of the amorphous layer, and the doping is carried out in the range of 1×10 12 / cm 2 to 1×10 13 / cm 2 . In addition, the volume density of the impurity particles is in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 , and the average distance between the impurity particles in the plan view is between 2.5 nm and 11 nm. In Examples 1 to 4 and Comparative Examples 1 and 2 shown in the table, the film thickness of the amorphous layer is set from the lattice constant of the crystal material (0.5 nm or more) to the surface tension determined by the material properties (2 nm or more). However, some examples or comparative examples are carried out under conditions that deviate from these upper and lower limits.

[0130] In this experiment, crystal peak intensities of 600 or higher were rated excellent (double circles), 400 or higher but less than 600 were rated qualified (circles), and less than 400 were rated unqualified. Thus, Comparative Examples 1 and 2 were rated unqualified. The reason for the unqualified rating of Comparative Example 1 was considered to be that the amount of aluminum nitride added exceeded the upper limit and the lower limit of the spacing of the aluminum nitride. The reason for the non - compliance of Comparative Example 2 was considered to be that the film thickness d exceeded the upper limit. The low crystal peak intensity of Example 4 was considered to be due to the amount of aluminum nitride added exceeding the upper limit. Therefore, it is desirable to set the surface density of the impurity particles at 1×10 12 / cm 2 to 1×10 13 / cm 2 in the range, the volume density in the range of 1×10 18 / cm 3 to 1×10 21 / cm 3 and the average distance between the impurity particles in the plan view is between 2.5 nm and 11 nm.

[0131] Figure 21 shows the arrangement of the impurity particles. In the Figure 21 perspective view, the bottom surface nb of the n - layer ferroelectric layer and the bottom surface n1b of the (n + 1) - layer ferroelectric layer are shown as rectangular regions respectively. Within these surfaces, the impurity particles GR are discretely arranged. Here, the point (position) of a specific impurity particle GR on the bottom surface nb of the n - layer is denoted as a, and the points (positions) of two specific impurity particles GR on the bottom surface n1b of the (n + 1) - layer are denoted as b and c respectively. Also, the point (position) directly above the position a on the bottom surface n1b of the (n + 1) - layer is denoted as o. The amount of the added impurity particles GR is D. The distance between the impurity particles GR is R, and the thickness of the amorphous layer (i.e., the distance between the bottom surface nb of the n - layer ferroelectric layer and the bottom surface n1b of the (n + 1) - layer ferroelectric layer) is t.

[0132] At this time, t is the distance between the point a and the point o. Also, the distance between the point o and the point b is x1, the distance between the point o and the point c is x2, the distance between the point a and the point b is 1a, and the distance between the point a and the point c is 1b. At this time, x1 + x2≈2R, and R≈(Dπ) -1 / 2 , where π is the pi constant. In this embodiment, by setting x1≤x2, it is ensured that for the arrangement of the impurity particles GR, t≤2R and t≤1a≤1b. Although the points b and c are offset from directly above the point a in Figure 21 , even if the point b is directly above the point a, this condition is still satisfied. To satisfy this condition, in this embodiment, the surface density of the impurity particles GR is set at 1×10 12 / cm 2 to 1×1013 / cm 2 within the range of, and the volume density is set to be between 1×10 18 / cm 3 and 1×10 21 / cm 3 .

[0133] In addition, the average distance between impurity particles in the plan view is set to be not less than 2.5 nm and not more than 11 nm. Additionally, the range of t is set to be not less than 0.5 nm and not more than 2 nm.

[0134] (Effect of the first embodiment)

[0135] Figure 30 shows a cross-sectional view of the main part of a ferroelectric memory cell as a comparative example. As Figure 30 shown, the ferroelectric film FEFa of the ferroelectric memory cell in the comparative example is a laminate, and the ferroelectric layers constituting the laminate are only ferroelectric layers FE1 and FE2. Impurity particles GR are arranged between ferroelectric layers FE1 and FE2. Within the ferroelectric film FEFa, as explained using Figure 29 , crystals grow three-dimensionally around the impurity particles GR.

[0136] In Figure 31 's graph shows the write characteristics of the ferroelectric memory cell in such a comparative example, and Figure 32 's graph shows the erase characteristics. In Figure 22 's graph shows the write characteristics of the main part of the ferroelectric memory cell in this embodiment, and Figure 23 's graph shows the erase characteristics. Figure 22 , 23 , 31, and 32, the horizontal axes respectively represent the time when a voltage is applied to the ferroelectric memory cell, and the vertical axes represent the threshold voltage of the ferroelectric memory cell. In Figure 22 and 31 , the graph when -4V is applied to the gate electrode is shown as a black circle graph, the graph when -3V is applied is shown as a triangle circle graph, and the graph when -2V is applied is shown as a square circle graph. In Figure 23 and 32 , the graph when +4V is applied to the gate electrode is shown as a black circle graph, the graph when +3V is applied is shown as a triangle circle graph, and the graph when +2V is applied is shown as a square circle graph.

[0137] From Figure 31 it can be seen that in the write operation of the ferroelectric memory cell in the comparative example, when -4V to -2V is applied to the gate electrode, the threshold voltage shows almost no difference in any case, indicating that the on and off of the current flow in the device does not occur. Similarly, fromFigure 32 It can be seen that in the erasing operation of the ferroelectric memory cell of the comparative example, when a voltage of +4V to +2V is applied to the gate electrode, there is almost no difference in the threshold voltage in any case, indicating that the on and off of the current flow in the device do not occur. Therefore, the ferroelectric memory cell of the comparative example cannot be driven at a low voltage below 4V.

[0138] In contrast, as Figure 22 shown, during the writing operation of the ferroelectric memory cell of the present embodiment, by applying -4V or -3V to the gate electrode, the threshold voltage increases and writing is performed. Also, as Figure 23 shown, during the erasing operation of the ferroelectric memory cell of the present embodiment, by applying +4V to +2V to the gate electrode, the threshold voltage decreases and erasing is performed. That is, in the present embodiment, compared with the comparative example, the operating voltage of the ferroelectric memory cell can be reduced. Specifically, the memory operating voltage in the ferroelectric memory cell (semiconductor element) is reduced to below 4V. This is an effect resulting from the improvement in the crystallinity of the ferroelectric film in the present embodiment.

[0139] By suppressing the memory operating voltage, there is no need to modulate the power supply voltage for memory operation. Therefore, a semiconductor device equipped with a circuit that performs writing and erasing operations in the ferroelectric memory cell without modulating the power supply voltage supplied to the ferroelectric memory cell can be realized.

[0140] Figure 24 The results of X-ray diffraction in the ferroelectric film are shown. Figure 24 In the graph shown, the horizontal axis represents the angle (the incident angle of the X-ray beam), and the vertical axis represents the scattering intensity of the X-ray. By irradiating the ferroelectric film of the present embodiment with an X-ray beam and measuring its scattering intensity, it is found that the orthorhombic phase (o(111)) exists predominantly compared with the monoclinic phase (m(111)). The predominant presence of the orthorhombic phase increases the remanent polarization of the ferroelectric film, improves the performance as a ferroelectric body, and reduces the driving power of the ferroelectric memory cell.

[0141] Figure 25 The crystallization peak intensity of the orthorhombic phase (111) is shown in the graph. Figure 25 The horizontal axis represents the addition amount (dose) of aluminum nitride as impurity particles, and the vertical axis represents the crystallization peak intensity (physical intensity). As shown in the comparative example in Figure 30 , the graph indicated by the white circles plots the case where the ferroelectric layer is formed of only two layers. The graph indicated by the black circles plots the case where the ferroelectric layer is formed of four layers, as in the present embodiment. From Figure 25 it can be seen that compared with the comparative example, when more than two ferroelectric layers are formed, the crystal peak intensity of the orthorhombic phase of the ferroelectric film increases.

[0142] Therefore, in the present embodiment, the ferroelectricity of the ferroelectric film FEF (see Figure 2 ) is improved, and a ferroelectric memory cell capable of operating at a low voltage can be realized. In other words, the performance of the semiconductor device can be improved.

[0143] (Second Embodiment)

[0144] In the first embodiment, impurity particles are discretely arranged, and more than three ferroelectric (amorphous) layers are provided. In the first embodiment, impurity particles are used as nuclei for two-dimensional crystal growth. In contrast, even if three or more amorphous layers are provided and the surface (upper surface) of each amorphous layer is hydrophilized, the crystal can grow two-dimensionally. Hereinafter, in this embodiment, a method for two-dimensional crystal growth by hydrophilizing the surface of the amorphous layer without arranging a plurality of impurity particles will be described.

[0145] Figure 26 The process flow until heat treatment is illustrated in the method for manufacturing a semiconductor device according to this embodiment after forming an insulating film IF1, amorphous layers AM1, AM2, AM3, and AM4, and a metal film MF on a semiconductor substrate. The film formation process in this series of processes is similar to the process described using Figure 5 、 8 、9, 10, and 11, but impurity particles GR are not added. However, after forming each of the amorphous layers AM1, AM2, and AM3, the surface of each amorphous layer in the amorphous layer is hydrophilized.

[0146] That is, as Figure 26 shows, the formation of the insulating film IF1 (step S10), the formation of the amorphous layer AM1 (step S11), the hydrophilization treatment of the surface of the amorphous layer AM1 (step S12), and the formation of the amorphous layer AM2 (step S13) are performed. Subsequently, the hydrophilization of the surface of the amorphous layer AM2 (step S14), the formation of the amorphous layer AM3 (step S15), the hydrophilization treatment of the surface of the amorphous layer AM3 (step S16), and the formation of the amorphous layer AM4 (step S17) are performed. Then, the formation of the metal film MF (step S18) and crystallization by heat treatment (step S19) are performed. The thickness of each of the insulating film IF1, amorphous layers AM1 to AM4, and metal film MF and the temperature conditions of the heat treatment are the same as those in the first embodiment. This forms a stacked structure including the amorphous layers AM1 to AM4. Here, the stacked structure is formed by sequentially repeating the formation process of the amorphous layer and hydrophilization more than three times.

[0147] Subsequently, by performing the process described using Figure 12 and 13 , the structure shown in Figure 27 is obtained. As Figure 27As shown, the ferroelectric film FEF includes four ferroelectric layers FE1 to FE4, and no impurity particles are formed between the overlapping ferroelectric layers. The surfaces (upper surfaces) of the ferroelectric layers FE1 to FE3 are hydrophilized.

[0148] The hydrophilization in step S12 increases the wettability of the surface of the amorphous layer AM1. That is, it reduces the surface energy of the amorphous layer AM1. Similarly, the hydrophilization in step S14 reduces the surface energy of the amorphous layer AM2, and the hydrophilization in step S16 reduces the surface energy of the amorphous layer AM3. The surface energy of the hydrophilized amorphous layer is lower than that of the amorphous layer before hydrophilization. In other words, the contact angle of the hydrophilized amorphous layer is smaller than that of the amorphous layer before hydrophilization. In this way, the interface between the amorphous layers overlapping in the thickness direction is hydrophilized, promoting two-dimensional nucleation, that is, crystal growth in the horizontal direction during the crystallization process in step S19. After obtaining Figure 27 the structure shown, by performing the process described using Figure 14 and 15 a ferroelectric memory cell of the semiconductor device of this embodiment is formed.

[0149] The hydrophilization treatment specifically refers to the process performed on the surface of the amorphous layer, involving O2 plasma treatment, O3 treatment, APM (ammonia-hydrogen peroxide mixture) cleaning, HPM (hydrochloric acid-hydrogen peroxide mixture) cleaning, water rinsing, UV (ultraviolet) treatment, exposure to the atmosphere, or a combination thereof. For example, the hydrophilization treatment can be performed by sequentially cleaning the semiconductor substrate on which the amorphous layer has been formed with a mixed solution of sulfuric acid and hydrogen peroxide water, and then rinsing with pure water. In addition, by treating the semiconductor substrate on which the amorphous layer has been formed with hydrofluoric acid and then rinsing with flowing pure water, the hydrophilization treatment can be performed by attaching hydroxyl groups to the surface to be hydrophilized.

[0150] Additionally, the hydrophilization treatment can be performed by thermally oxidizing the amorphous layer including silicon to form a silicon oxide film on the surface of the amorphous layer, or by reacting the amorphous layer with ammonia to form a silicon nitride film on the surface of the amorphous layer. Moreover, the hydrophilization treatment can be performed by immersing the semiconductor substrate on which the amorphous layer has been formed in a solution of H2SO4:H2O2 = 1:4. Moreover, the hydrophilization treatment can be performed by cleaning the semiconductor substrate on which the amorphous layer has been formed with nitric acid and hydrogen peroxide.

[0151] Furthermore, the hydrophilization treatment can be performed by ashing the surface of the semiconductor substrate on which the amorphous layer has been formed with oxygen plasma and then immersing it in water. Additionally, the hydrophilization treatment can be performed by treating the semiconductor substrate on which the amorphous layer has been formed with ozone using ultraviolet light. Moreover, the hydrophilization treatment can be performed by treating the semiconductor substrate on which the amorphous layer has been formed with a surface treatment liquid selected from organic solvents including hydroxyl groups and aqueous solutions with a pH of 1 to 10.

[0152] The method of hydrophilic treatment is not limited to these, and can also be carried out by irradiating the amorphous layer with energy rays or using a dry process such as RIE (Reactive Ion Etching).

[0153] In this embodiment, by stacking more than three amorphous layers and performing hydrophilic treatment on the interfaces between the overlapping amorphous layers, crystals can grow two-dimensionally within each of the amorphous layers in the amorphous layer during subsequent heat treatment. Therefore, the crystallinity of the ferroelectric film can be enhanced, thereby improving the performance of the semiconductor device.

[0154] (Third Embodiment)

[0155] The above-described first embodiment and second embodiment can be combined with each other. This embodiment relates to discretely forming impurity particles on the upper surface of the amorphous layer after forming the amorphous layer, and performing hydrophilic treatment on the surface of the amorphous layer.

[0156] Figure 28 Illustrated is the process until heat treatment after forming an insulating film IF1, amorphous layers AM1, AM2, AM3, and AM4, and a metal film MF on a semiconductor substrate in the manufacturing method of the semiconductor device of this embodiment. Except for using Figures 5 to 11 the processes described, this series of processes further includes forming amorphous layers AM1, AM2, and AM3, then performing hydrophilic treatment and forming impurity particles.

[0157] That is, as Figure 28 shown, the formation of the insulating film IF1 (step S20), the formation of the amorphous layer AM1 (step S21), the hydrophilic treatment of the surface of the amorphous layer AM1 (step S22), the formation of impurity particles (step S23), and the formation of the amorphous layer AM2 (step S24) are performed. Subsequently, the hydrophilic treatment of the surface of the amorphous layer AM2 (step S25), the formation of impurity particles (step S26), the formation of the amorphous layer AM3 (step S27), the hydrophilic treatment of the surface of the amorphous layer AM3 (step S28), the formation of impurity particles (process S29), and the formation of the amorphous layer AM4 (step S30) are performed. Thereafter, the formation of the metal film MF (step S31) and crystallization by heat treatment (step S32) are performed. The film thicknesses of the insulating film IF1, the amorphous layers AM1 to AM4, and the metal film MF, and the temperature conditions of the heat treatment are the same as those in the first embodiment. Therefore, a laminated structure including the amorphous layers AM1 to AM4 is formed. Here, the laminated structure is formed by repeating the process of forming the amorphous layer, the hydrophilic treatment, and the process of forming impurity particles more than three times in sequence.

[0158] The hydrophilic treatment in step S22 and the formation process of impurity particles in step S23 respectively increase the wettability of the surface of the amorphous layer AM1. That is, they reduce the surface energy of the amorphous layer AM1. Similarly, the hydrophilic treatment in step S25 and the formation process of impurity particles in step S26 respectively reduce the surface energy of the amorphous layer AM2, and the hydrophilic treatment in step S28 and the formation process of impurity particles in step S29 respectively reduce the surface energy of the amorphous layer AM3. In this way, the interface between the amorphous layers overlapping in the thickness direction is hydrophilized, and the impurity particles are used as nuclei to promote the two-dimensional nucleation of crystals during the crystallization process in step S29. After the heat treatment in step S32, a ferroelectric memory cell serving as a semiconductor device of this embodiment is formed by performing the process described using Figures 12 to 15 the process described forms a ferroelectric memory cell as the semiconductor device of this embodiment.

[0159] In this embodiment, more than three amorphous layers are stacked, and after placing impurity particles on the surface of the amorphous layer, a hydrophilic treatment is performed on the interface between the overlapping amorphous layers. Therefore, compared with Embodiments 1 and 2, the two-dimensional growth of crystals in each amorphous layer can be promoted more during the subsequent heat treatment. Therefore, the crystallinity of the ferroelectric film can be enhanced, thereby improving the performance of the semiconductor device.

[0160] Although the present invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its gist.

[0161] For example, similar to the first embodiment, in the second and third embodiments, controlling the thickness of the amorphous layer is very important for promoting the two-dimensional growth of crystals in the ferroelectric film.

[0162] In addition, some of the content described in the embodiments is listed below.

[0163] (Appendix 1)

[0164] A semiconductor device includes:

[0165] The semiconductor element includes

[0166] a paraelectric film formed on a semiconductor substrate, and

[0167] a laminated film formed on the paraelectric film, wherein

[0168] the laminated film includes a plurality of ferroelectric layers stacked in three or more layers, and

[0169] the semiconductor element is a memory element having a plurality of ferroelectric layers, and

[0170] the memory operation voltage on the semiconductor element is 4V or lower.

[0171] (Appendix 2)

[0172] The semiconductor device according to Appendix 1 further includes:

[0173] A circuit that performs a write operation and an erase operation in the semiconductor element without modulating the power supply voltage.

Claims

1. A semiconductor device, comprising: A paraelectric film is formed on a semiconductor substrate, and A laminate film is formed on the paraelectric film, wherein The laminated film includes a plurality of ferroelectric layers laminated in three or more layers.

2. The semiconductor device according to claim 1, wherein Each of the surfaces of the plurality of ferroelectric layers has impurity particles discretely.

3. The semiconductor device according to claim 1, wherein The thickness of each of the plurality of ferroelectric layers is greater than or equal to 0.5 nm and less than or equal to 2 nm.

4. The semiconductor device according to claim 1, wherein The thickness of the laminate film is 6 nm or more and 20 nm or less.

5. The semiconductor device according to claim 1, wherein Each of the plurality of ferroelectric layers is made of a material including a metal oxide and a first element, The metal oxide is hafnium oxide or gallium oxide, and The first element is any one of zirconium, silicon, germanium, yttrium, lanthanum or ytterbium.

6. The semiconductor device according to claim 2, wherein The paraelectric film is a silicon oxide film or a silicon oxynitride film.

7. The semiconductor device according to claim 2, wherein The impurity particles are any one or a combination of aluminum nitride, silicon, aluminum, carbon, nitrogen, hydrogen or oxygen.

8. The semiconductor device according to claim 2, wherein The surface density of the impurity particles is 1×10 12 / cm 2 Above and 1×10 13 / cm 2 the following.

9. The semiconductor device according to claim 2, wherein The volume density of the impurity particles is 1×10 18 / cm 3 Above and 1×10 21 / cm 3 the following.

10. The semiconductor device according to claim 2, wherein An average distance between each of the impurity particles in a plan view is 2.5 nm or more and 11 nm or less.

11. The semiconductor device according to claim 1, wherein Each of the surfaces of the plurality of ferroelectric layers is hydrophilized.

12. The semiconductor device according to claim 11, wherein The surface energy of the ferroelectric layer after being hydrophilized is equal to the surface energy of the ferroelectric layer before being hydrophilized.

13. A method for manufacturing a semiconductor device, comprising: (a) forming a paraelectric film on a semiconductor substrate, (b) forming a laminate structure on the paraelectric film, (c) forming a metal film on the laminate structure, and (d) after step (c), performing a heat treatment, wherein The step (d) is a laminated structure forming step by repeating the following steps at least three times in sequence, (b1) forming an amorphous layer including a material including a metal oxide and a first element, (b2) discretely providing impurity particles on a surface of the amorphous layer, and The step (d) is a ferroelectric laminate film forming step by crystallizing the amorphous layer of the laminate structure in a horizontal direction.

14. The method for manufacturing a semiconductor device according to claim 13, wherein The thickness of each of the amorphous layers of the laminated structure is 0.5 nm or more and 2 nm or less.

15. The method for manufacturing a semiconductor device according to claim 13, wherein The metal oxide is hafnium oxide or gallium oxide, and The first element is any one of zirconium, silicon, germanium, yttrium, lanthanum or ytterbium.

16. The method for manufacturing the semiconductor device according to claim 13, wherein The surface density of the impurity particles provided in step (b2) is 1×10 12 / cm 2 Above and 1×10 13 / cm 2 the following.

17. The method for manufacturing a semiconductor device according to claim 13, wherein An average distance between each of the impurity particles in a plan view is 2.5 nm or more and 11 nm or less.

18. A method for manufacturing a semiconductor device, comprising: (a) forming a paraelectric film on a semiconductor substrate, (b) forming a laminate structure on the paraelectric film, (c) forming a metal film on the laminate structure, and (d) after step (c), performing a heat treatment, wherein in The step (b) is a laminated structure forming step by repeating the following steps in this order at least three times, (b1) forming an amorphous layer including a material including a metal oxide and a first element, (b2) hydrophilizing a surface of the amorphous layer, and The step (d) is a ferroelectric laminate film forming step by crystallizing the amorphous layer of the laminate structure in a horizontal direction.

19. The method for manufacturing a semiconductor device according to claim 18, wherein In the step (b2), the surface energy of the amorphous layer after being hydrophilized is equal to the surface energy of the amorphous layer before being hydrophilized.

20. The method for manufacturing a semiconductor device according to claim 18, wherein In the step (b2), the contact angle of the amorphous layer after being hydrophilized is the same as the contact angle of the amorphous layer before being hydrophilized.

21. The method for manufacturing a semiconductor device according to claim 18, wherein The hydrophilization performed in the step (b2) is any one or a combination of O2 plasma treatment, O3 treatment, APM cleaning, HPM cleaning, water washing treatment, UV treatment, exposure to the atmosphere.

22. The method for manufacturing a semiconductor device according to claim 18, wherein The thickness of each of the amorphous layers of the laminated structure is 0.5 nm or more and 2 nm or less.

23. The method for manufacturing a semiconductor device according to claim 18, wherein The metal oxide is hafnium oxide or gallium oxide, and The first element is any one of zirconium, silicon, germanium, yttrium, lanthanum or ytterbium.

24. The method for manufacturing the semiconductor device according to claim 18, wherein the step (d) further comprises: (b3) After the step (b2), impurity particles are discretely provided on the surface of the amorphous layer.

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