Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle, and the semiconductor device comprises a semiconductor body, a first region which is of a first conduction type and is located on a first surface, a well region which is located on one side of the first region far away from the first surface, and a buried layer region which is located on one side of the well region far away from the first surface, the second region penetrates through the first region and the well region from the first surface and is contacted with the buried layer region; the first surface is provided with a gate trench, and the gate trench extends into the semiconductor body from the first surface; the first insulating layer is located on the bottom surface and the side surface of the gate trench; the channel mobility corresponding to the crystal orientation, close to the surface of the first insulating layer, of the well region is greater than the channel mobility corresponding to the (0001) crystal surface; and the trench gate is positioned on one side, far away from the semiconductor body, of the first insulating layer in the gate trench. According to the invention, the bottom of the gate trench is prevented from being broken down, and the anti-breakdown capability and the mobility of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN) are widely used in fields such as power electronics, automotive, and aerospace due to their excellent high-temperature performance, chemical stability, and electronic characteristics.

[0003] In the prior art, the bottom of the gate trench of a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is easily broken down. Summary of the Invention

[0004] The present invention provides a semiconductor device and manufacturing method, a power module, a power conversion circuit, and a vehicle to avoid breakdown of the bottom of the gate trench and improve the breakdown resistance and mobility of the semiconductor device.

[0005] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes:

[0006] A semiconductor body including a first surface and a second surface disposed opposite to each other; the semiconductor body further includes a well region, a first region, a second region, and a buried layer region. The first region is of a first conductivity type and is located on the first surface. The well region is of a second conductivity type and is located on a side of the first region away from the first surface. The buried layer region is of a second conductivity type and is located on a side of the well region away from the first surface. The second region is of a second conductivity type and penetrates the first region and the well region from the first surface to contact the buried layer region. A gate trench is provided on the first surface and extends from the first surface into the semiconductor body. The semiconductor body further includes a first insulating layer located on the bottom surface and side surface of the gate trench. The channel mobility corresponding to the crystal orientation of the well region near the surface of the first insulating layer is greater than the channel mobility corresponding to the (0001) crystal plane;

[0007] A trench gate located on a side of the first insulating layer away from the semiconductor body within the gate trench; in a first direction, the vertical distance between the buried layer region and the second surface is less than the vertical distance between the bottom of the trench gate and the second surface. The direction from the first surface to the second surface is the first direction;

[0008] A drain located on the second surface;

[0009] A source located on the first surface and in contact with the first region and the second region.

[0010] Further, the size of the second region in the second direction is smaller than the size of the buried layer region in the second direction, and the second direction is perpendicular to the first direction;

[0011] The doping concentration of the second region is greater than that of the well region, and the doping concentration of the buried layer region is greater than that of the well region.

[0012] Further, the semiconductor body includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer; the conduction types of the first epitaxial layer, the second epitaxial layer, and the third epitaxial layer are all the first conduction type;

[0013] The second epitaxial layer is located on the side of the first epitaxial layer away from the second surface;

[0014] The third epitaxial layer is located on the side of the second epitaxial layer away from the second surface;

[0015] The buried layer region is located in the second epitaxial layer, the well region and the first region are located in the third epitaxial layer, and the second region penetrates through the first region, the well region, and a part of the third epitaxial layer from the first surface to contact the buried layer region;

[0016] The doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

[0017] Further, the doping concentration of the third epitaxial layer is greater than or equal to that of the second epitaxial layer.

[0018] Further, the surface of the well region close to the first insulating layer includes a crystal plane or a crystal plane.

[0019] Further, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0020] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device includes:

[0021] Providing a semiconductor body, the semiconductor body including a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region, a first region, a second region, and a buried layer region. The first region is set to the first conduction type and is located on the first surface. The well region is set to the second conduction type and is located on the side of the first region away from the first surface. The buried layer region is set to the second conduction type and is located on the side of the well region away from the first surface. The second region is set to the second conduction type and penetrates through the first region, the well region, and a part of the semiconductor body from the first surface to contact the buried layer region; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; the semiconductor body further includes a first insulating layer, and the first insulating layer is located on the bottom surface and the side surface of the gate trench; the channel mobility corresponding to the crystal orientation of the surface of the well region close to the first insulating layer is greater than the channel mobility corresponding to the (0001) crystal plane;

[0022] A trench gate is formed on a side of the first insulating layer away from the semiconductor body within the gate trench; in a first direction, a vertical distance between the buried layer region and the second surface is less than a vertical distance between the bottom of the trench gate and the second surface; a direction from the first surface to the second surface is the first direction;

[0023] A drain is formed on the second surface;

[0024] A source is formed on the first surface in contact with the first region and the second region.

[0025] Further, providing the semiconductor body includes:

[0026] Forming a first epitaxial layer;

[0027] Forming a second epitaxial layer on a side of the first epitaxial layer away from the second surface; a doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer;

[0028] Forming a buried layer region on a side of the second epitaxial layer away from the first epitaxial layer; wherein, the buried layer region is located within the second epitaxial layer;

[0029] Forming a third epitaxial layer on a side of the second epitaxial layer away from the second surface;

[0030] Forming a well region in the third epitaxial layer;

[0031] Forming a gate trench on the first surface, and the gate trench extends from the first surface into the semiconductor body;

[0032] Forming a first region in the third epitaxial layer;

[0033] Forming a second region, and the second region penetrates through the first region, the well region and a part of the second epitaxial layer from the first surface to contact the buried layer region.

[0034] Further, providing the semiconductor body includes:

[0035] Forming a well region within the semiconductor body; forming a gate trench on the first surface, and a surface of the well region located on the sidewall of the gate trench includes crystal plane or crystal plane.

[0036] Further, providing the semiconductor body includes:

[0037] Providing a semiconductor body including a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0038] According to another aspect of the present invention, there is provided a power module, which includes a substrate and at least one of the above semiconductor devices, and the substrate is used to carry the semiconductor devices.

[0039] According to another aspect of the present invention, there is provided a power conversion circuit for one or more of current conversion, voltage conversion, and power factor correction;

[0040] The power conversion circuit includes a circuit board and at least one of the above semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0041] According to another aspect of the present invention, there is provided a vehicle, which includes a load and the above power conversion circuit. The power conversion circuit is configured to convert alternating current to direct current, convert alternating current to alternating current, convert direct current to direct current, or convert direct current to alternating current and then input it to the load.

[0042] In the technical solution of the embodiment of the present invention, a buried layer region having the same conductivity type as the well region is provided on the side of the well region away from the first surface, and in the first direction, the vertical distance between the buried layer region and the second surface is less than the vertical distance between the bottom of the trench gate and the second surface, so that in the reverse bias state, the semiconductor device provided by the embodiment of the present invention forms a depletion layer by using the buried layer region and the semiconductor body of the first conductivity type, improves the electric field distribution at the bottom of the gate trench, avoids breakdown of the gate trench, and improves its breakdown resistance. At the same time, compared with the design of using a vertical gate trench in the prior art, the channel mobility corresponding to the crystal orientation of the well region close to the surface of the first insulating layer is greater than the channel mobility corresponding to the (0001) crystal plane, thereby improving the mobility of the semiconductor device provided by the embodiment of the present invention.

[0043] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0045] Figure 1 is a schematic structural diagram of a semiconductor device provided by an embodiment of the present invention;

[0046] Figure 2 is a flowchart of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0047] Figures 3 - 4 is a cross-sectional view corresponding to each step of a manufacturing method of a semiconductor device provided by an embodiment of the present invention;

[0048] Figure 5 is a flowchart of another method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0049] Figures 6 - 16 is a cross-sectional view corresponding to each step of another method for manufacturing a semiconductor device according to an embodiment of the present invention. Detailed implementation manners

[0050] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0052] An embodiment of the present invention provides a semiconductor device, Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention, referring to Figure 1, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 which are oppositely arranged; the semiconductor body 100 further includes a well region 103, a first region 104, a second region 105 and a buried layer region 106. The first region 104 is set to a first conduction type and is located on the first surface 101. The well region 103 is set to a second conduction type and is located on the side of the first region 104 away from the first surface 101. The buried layer region 106 is set to a second conduction type and is located on the side of the well region 103 away from the first surface 101. The second region 105 is set to a second conduction type and penetrates through the first region 104 and the well region 103 from the first surface 101 to contact the buried layer region 106; a gate trench 110 is provided on the first surface 101, and the gate trench 110 extends from the first surface 101 into the semiconductor body 100; the semiconductor body 100 further includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and the side surface of the gate trench 110; the channel mobility corresponding to the crystal orientation of the well region 103 near the surface of the first insulating layer 107 is greater than the channel mobility corresponding to the (0001) crystal plane; a trench gate 200 is located on the side of the first insulating layer 107 away from the semiconductor body 100 within the gate trench 110; in the first direction X, the vertical distance between the buried layer region 106 and the second surface 102 is less than the vertical distance between the bottom of the trench gate 200 and the second surface 102; the direction from the first surface 101 to the second surface 102 is the first direction X; a drain 300 is located on the second surface 102; a source 400 is located on the first surface 101 and is in contact with the first region 104 and the second region 105.

[0053] In the embodiments of the present invention, the semiconductor device includes, but is not limited to, an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide-bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conduction type is N-type and the second conduction type is P-type. For a P-type MOSFET, the first conduction type is P-type and the second conduction type is N-type.

[0054] Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions. The well region 103 is a P-well region, and the second region 105 and the buried layer region 106 are P+ doped regions. The P-type doping ions in the P-well region and the P+ doped regions may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 through processes such as ion implantation, ion diffusion, or vapor deposition. As Figure 1As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. The epitaxial layer 20 includes a first epitaxial layer 21, a second epitaxial layer 22, and a third epitaxial layer 23. The buried layer region 106 is located in the second epitaxial layer 22, and the well region 103 and the second region 105 are located in the third epitaxial layer 23. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. Among them, the epitaxial layer 20 is a semiconductor layer formed on the basis of the substrate 10 through an epitaxial process. The epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE). The first insulating layer 107 may be a gate oxide layer.

[0055] In the technical solution of the embodiment of the present invention, a buried layer region 106 having the same conductivity type as the well region 103 is provided on the side of the well region 103 away from the first surface 101. And in the first direction X, the vertical distance between the buried layer region 106 and the second surface 102 is less than the vertical distance between the bottom of the trench gate 200 and the second surface 102. So that in the reverse bias state, the semiconductor device provided by the embodiment of the present invention forms a depletion layer by using the buried layer region 106 and the semiconductor body 100 of the first conductivity type, which improves the electric field distribution at the bottom of the gate trench 110, avoids the breakdown of the bottom of the gate trench 110, and improves its breakdown resistance. At the same time, compared with the design of using a vertical gate trench in the prior art, the channel mobility corresponding to the crystal orientation of the well region 103 close to the surface of the first insulating layer 107 is greater than the channel mobility corresponding to the (0001) crystal plane, thereby improving the mobility of the semiconductor device provided by the embodiment of the present invention.

[0056] Exemplarily, as Figure 1 shown, the source electrode 400 is located on the first surface 101 and is a planar source electrode. In other alternative embodiments of the present invention, a trench-type source electrode may also be included, that is, a source trench may also be provided on the first surface 101, and a source insulating layer and a source conductive filling layer are provided in the source trench. The source electrode 400 covers the source insulating layer and the source conductive filling layer.

[0057] In other alternative embodiments of the present invention, the doping concentration of the second region 105 is greater than that of the well region 103, and the doping concentration of the buried layer region 106 is greater than that of the well region 103. The second region 105 connects the first region 104 and the buried layer region 106. While achieving good ohmic contact, the size of the second region 105 in the second direction Y is smaller than the size of the buried layer region 106 in the second direction Y. The second direction Y is perpendicular to the first direction X, avoiding occupying too much area in the well region 103 to avoid reducing the breakdown voltage capability.

[0058] In other alternative embodiments of the present invention, the semiconductor body 100 includes a first epitaxial layer 21, a second epitaxial layer 22, and a third epitaxial layer 23; the conduction types of the first epitaxial layer 21, the second epitaxial layer 22, and the third epitaxial layer 23 are all of a first conduction type; the second epitaxial layer 22 is located on a side of the first epitaxial layer 21 away from the second surface 102; the third epitaxial layer 23 is located on a side of the second epitaxial layer 22 away from the second surface 102; the buried layer region 106 is located in the second epitaxial layer 22, the well region 103 and the first region 104 are located in the third epitaxial layer 23, and the second region 105 contacts the buried layer region 106 by penetrating the first region 104, the well region 103, and a part of the third epitaxial layer 23 from the first surface 101; the doping concentration of the second epitaxial layer 22 is greater than that of the first epitaxial layer 21.

[0059] The semiconductor body 100 provided in the embodiments of the present invention is formed by multiple epitaxial designs. Compared with directly using high-energy P-type ion implantation in the prior art, the difficulty of single ion implantation is reduced, the electrical parameters of the semiconductor body 100 are more stable, and the instability of the electrical parameters in the surrounding area due to ion scattering during high-energy P-type ion implantation is avoided, which seriously affects the on-resistance and threshold voltage. Moreover, the doping concentration of the second epitaxial layer 22 is set to be greater than that of the first epitaxial layer 21, and the region where the second epitaxial layer 22 is located forms a current spreading layer, reducing the on-resistance of the semiconductor device.

[0060] In other alternative embodiments of the present invention, the doping concentration of the third epitaxial layer 23 is greater than or equal to that of the second epitaxial layer 22, which can further reduce the on-resistance of the semiconductor device.

[0061] In other alternative embodiments of the present invention, the surface of the well region 103 close to the first insulating layer 107 includes crystal planes or crystal planes, which can form a conduction channel along the direction or direction in the semiconductor body 100, improving the mobility of the semiconductor device provided in the embodiments of the present invention.

[0062] In other alternative embodiments of the present invention, the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0063] Among them, when the semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. When the semiconductor body 100 includes a gallium nitride semiconductor body, the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0064] A silicon carbide MOSFET semiconductor device or a gallium nitride MOSFET semiconductor device has the advantages of high breakdown voltage, low on-resistance, and high frequency, and can further improve the performance of semiconductor devices.

[0065] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 2 It is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 3 - 4 It is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Refer to Figures 1 - 4 , the method for manufacturing a semiconductor device includes:

[0066] S110. Provide a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other; the semiconductor body further includes a well region, a first region, a second region, and a buried layer region. The first region is set to a first conductivity type and is located on the first surface. The well region is set to a second conductivity type and is located on the side of the first region away from the first surface. The buried layer region is set to a second conductivity type and is located on the side of the well region away from the first surface. The second region is set to a second conductivity type and penetrates through the first region, the well region, and a part of the semiconductor body from the first surface to contact the buried layer region; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; the semiconductor body further includes a first insulating layer, and the first insulating layer is located on the bottom surface and the side surface of the gate trench. The channel mobility corresponding to the crystal orientation of the well region near the surface of the first insulating layer is greater than the channel mobility corresponding to the (0001) crystal plane.

[0067] Refer to Figure 3 , the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 further includes a well region 103, a first region 104, a second region 105, and a buried layer region 106. The first region 104 is set to a first conductivity type and is located on the first surface 101. The well region 103 is set to a second conductivity type and is located on the side of the first region 104 away from the first surface 101. The buried layer region 106 is set to a second conductivity type and is located on the side of the well region 103 away from the first surface 101. The second region 105 is set to a second conductivity type and penetrates through the first region 104, the well region 103, and a part of the semiconductor body 100 from the first surface 101 to contact the buried layer region 106; a gate trench 110 is provided on the first surface 101, and the gate trench 110 extends from the first surface 101 into the semiconductor body 100; the semiconductor body 100 further includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and the side surface of the gate trench 110.

[0068] Wherein, through a photolithography and etching process, a gate trench 110 is formed on the first surface 101.

[0069] For an N-type MOSFET, the first region 104 is an N+-doped region. The N-type doping ions in the N+-doped region can be phosphorus (P) ions or nitrogen (N) ions. The well region 103 is a P-well region, and the second region 105 and the buried layer region 106 are P+-doped regions. The P-type doping ions in the P-well region and the P+-doped regions can be aluminum (Al) ions or boron (B) ions. The first region 104 can be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or chemical vapor deposition.

[0070] S120. Form a trench gate on the side of the first insulating layer away from the semiconductor body within the gate trench; in the first direction, the vertical distance between the buried layer region and the second surface is less than the vertical distance between the bottom of the trench gate and the second surface; the direction from the first surface to the second surface is the first direction.

[0071] As Figure 4 shown, a trench gate 200 is formed on the side of the first insulating layer 107 away from the semiconductor body 100 within the gate trench 110.

[0072] S130. Form a drain on the second surface.

[0073] Refer to Figure 1 , a drain 300 is formed on the second surface 102 of the semiconductor body 100.

[0074] S140. Form a source on the first surface in contact with the first region and the second region.

[0075] As Figure 1 shown, a source 400 is formed on the first surface 101 in contact with the first region 104 and the second region 105, and a metal gate 210 is formed on the side of the trench gate 200 away from the semiconductor body 100. An interlayer insulating layer 500 is provided between the metal gate 210 and the source 400, and the interlayer insulating layer 500 is used to insulate and separate the metal gate 210 and the source 400.

[0076] In the technical solution of the embodiment of the present invention, a buried layer region 106 having the same conductivity type as the well region 103 is provided on the side of the well region 103 away from the first surface 101, and in the first direction X, the vertical distance between the buried layer region 106 and the second surface 102 is less than the vertical distance between the bottom of the trench gate 200 and the second surface 102. For the semiconductor device provided by the embodiment of the present invention, in the reverse bias state, a depletion layer is formed by using the buried layer region 106 and the semiconductor body 100 of the first conductivity type, improving the electric field distribution at the bottom of the gate trench 110, avoiding breakdown at the bottom of the gate trench 110, and improving its breakdown resistance. At the same time, compared with the design of using a vertical gate trench in the prior art, the channel mobility corresponding to the crystal orientation of the well region 103 close to the surface of the first insulating layer 107 is greater than the channel mobility corresponding to the (0001) crystal plane, thereby improving the mobility of the semiconductor device provided by the embodiment of the present invention.

[0077] Figure 5 is a flowchart of another manufacturing method of a semiconductor device provided by an embodiment of the present invention. Figures 6 - 16 is a cross-sectional view corresponding to each step of another manufacturing method of a semiconductor device provided by an embodiment of the present invention. Refer to Figures 5 - 16 , and providing a semiconductor body includes:

[0078] S211. Form a first epitaxial layer.

[0079] Refer to Figure 6 , and a first epitaxial layer 21 is formed on one side of the substrate 10 through a single epitaxial process. Among them, the epitaxial process includes processes such as chemical vapor epitaxial growth (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0080] S212. Form a second epitaxial layer on the side of the first epitaxial layer away from the second surface; the doping concentration of the second epitaxial layer is greater than that of the first epitaxial layer.

[0081] Refer to Figure 7 , and a second epitaxial layer 22 is formed on the side of the first epitaxial layer 21 away from the substrate 10 through another epitaxial process, and the doping concentration of the second epitaxial layer 22 is greater than that of the first epitaxial layer 21.

[0082] S213. Form a buried layer region on the side of the second epitaxial layer away from the first epitaxial layer; wherein, the buried layer region is located within the second epitaxial layer.

[0083] Refer to Figure 8, applying the hard mask (HM) process, a first mask layer 600 is formed on the surface of the second epitaxial layer 22 away from the first epitaxial layer 21. The first mask layer 600 can also be deposited by plasma enhanced chemical vapor deposition (PECVD) of SiO2. The first mask layer 600 is patterned by photolithography. Photolithography is an important step in the semiconductor device manufacturing process. In this step, geometric graphic structures are engraved on the photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the first mask layer 600 through an etching process to achieve patterning of the first mask layer 600, such as Figure 7 shown, a via 601 is formed by photolithography. The via 601 penetrates the first mask layer 600. A buried layer region 106 is formed by ion implantation of ions of the second conductivity type at the via 601. The buried layer region 106 can be formed on the surface of the second epitaxial layer 22 away from the first epitaxial layer 21 by processes such as ion implantation, ion diffusion, or vapor deposition. Refer to Figure 9 , the first mask layer 600 made of SiO2 material can be etched away using a hydrofluoric acid solution.

[0084] S214. A third epitaxial layer is formed on one side of the second epitaxial layer away from the second surface.

[0085] Refer to Figure 10 , a third epitaxial layer 23 is formed on the side of the second epitaxial layer 22 away from the substrate 10 by another epitaxial process.

[0086] S215. A well region is formed in the third epitaxial layer.

[0087] Refer to Figure 11 , a well region 103 is formed by ion implantation of ions of the second conductivity type on the side of the third epitaxial layer 23 away from the second epitaxial layer 22. There is a part of the third epitaxial layer 23 between the well region 103 and the buried layer region 106, and the ion concentration in the well region 103 is less than that in the buried layer region 106.

[0088] S216. A gate trench is formed on the first surface, and the gate trench extends from the first surface into the semiconductor body.

[0089] Refer to Figure 12, SiO2 is deposited on the first surface 101 of the semiconductor body 100 by HM process or PECVD to form a second mask layer 700, and the second mask layer 700 covers the well region 103. The second mask layer 700 is patterned by photolithography process. A geometric structure is depicted on the photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the second mask layer 700 by etching process, so as to achieve patterning of the second mask layer 700, as shown in FIG. Figure 12 As shown, a first through hole 701 is formed by a photolithography process, and the first through hole 701 penetrates the second mask layer 700, and then a gate trench 110 is formed on the first surface 101 by etching. Figure 13 , a hydrofluoric acid solution may be used to etch away the second mask layer 700 of the SiO2 material.

[0090] Optionally, the surface of the well region 103 located on the side wall of the gate trench 110 includes Crystal face or Crystal face.

[0091] S217, forming a first region in the third epitaxial layer.

[0092] refer to Figure 14 , SiO2 is deposited on the first surface 101 of the semiconductor body 100 by HM process or PECVD to form a third mask layer, and the third mask layer covers the well region 103 and the gate trench 110. The third mask layer is patterned by photolithography process. A geometric structure is depicted on the photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the third mask layer by etching process, that is, the third mask layer near the first surface 101 of the well region 103 is etched away to achieve patterning of the third mask layer, and a first conductive type ion implantation is performed on one side of the well region 103 near the first surface 101 to form a first region 104, and then the third mask layer 700 of SiO2 material can be etched away by hydrofluoric acid solution.

[0093] S218, forming a second region, wherein the second region extends from the first surface through the first region, the well region and a portion of the second epitaxial layer and contacts the buried layer region.

[0094] refer to Figure 15 , SiO2 is deposited on the first surface 101 of the semiconductor body 100 by HM process or PECVD to form a fourth mask layer 800, and the fourth mask layer 800 covers the first region 104 and the gate trench 110. The fourth mask layer 800 is patterned by photolithography process. A geometric structure is depicted on the photoresist layer by exposure and development, and then the pattern of the photoresist layer is transferred to the fourth mask layer 800 by etching process, so as to achieve patterning of the fourth mask layer 800, as shown in FIG. Figure 15As shown, a second via 801 is formed by a photolithography process. The second via 801 penetrates through the fourth mask layer 800. Then, a second region 105 is formed by implanting ions of a first conductivity type at the second via 801. Among them, the doping concentration of the second region 105 is greater than that of the well region 103. Refer to Figure 16 , a hydrofluoric acid solution can be used to etch away the second mask layer 700 made of SiO2 material.

[0095] S220. A trench gate is formed on the side of the first insulating layer away from the semiconductor body within the gate trench; in a first direction, the vertical distance between the buried layer region and the second surface is less than the vertical distance between the bottom of the trench gate and the second surface; the direction from the first surface to the second surface is the first direction.

[0096] As Figure 4 shown, a trench gate 200 is formed on the side of the first insulating layer 107 away from the semiconductor body 100 within the gate trench 110.

[0097] S230. A drain is formed on the second surface.

[0098] Refer to Figure 1 , a drain 300 is formed on the second surface 102 of the semiconductor body 100.

[0099] S240. A source is formed on the first surface in contact with the first region and the second region.

[0100] As Figure 1 shown, a source 400 is formed on the first surface 101 in contact with the first region 104 and the second region 105, and a metal gate 210 is formed on the side of the trench gate 200 away from the semiconductor body 100. An interlayer insulating layer 500 is provided between the metal gate 210 and the source 400. The interlayer insulating layer 500 is used to insulate and separate the metal gate 210 and the source 400.

[0101] An embodiment of the present invention provides a power module, including a substrate and at least one semiconductor device according to any embodiment of the present invention. The substrate is used to carry the semiconductor device. Therefore, the beneficial effects of the power module including the semiconductor device according to any embodiment of the present invention will not be elaborated here.

[0102] An embodiment of the present invention provides a power conversion circuit. The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device according to any embodiment of the present invention. The semiconductor device is electrically connected to the circuit board.

[0103] Therefore, the beneficial effects of the power conversion circuit including the semiconductor device according to any embodiment of the present invention will not be elaborated here.

[0104] An embodiment of the present invention further provides a vehicle, which includes a load and the above-mentioned power conversion circuit. The power conversion circuit is configured to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current, and then input it to the load.

[0105] Therefore, the vehicle includes the beneficial effects of the power conversion circuit package described in any embodiment of the present invention, which will not be elaborated herein.

[0106] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0107] The above specific embodiments do not constitute a limitation to the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprises a well region, a first region, a second region and a buried region, the first region being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first region away from the first surface, the buried region being set to a second conductivity type and being located on a side of the well region away from the first surface, the second region being set to a second conductivity type and being in contact with the buried region through the first surface and the well region; a gate trench being set on the first surface, and the gate trench extending from the first surface into the semiconductor body; the semiconductor body further comprises a first insulating layer, the first insulating layer being located on the bottom and side surfaces of the gate trench; a channel mobility corresponding to a crystal orientation of the well region close to the surface of the first insulating layer is greater than a channel mobility corresponding to a (0001) crystal plane; A trench gate is located in the gate trench on a side of the first insulating layer away from the semiconductor body; In a first direction, a vertical distance between the buried layer region and the second surface is smaller than a vertical distance between the bottom of the trench gate and the second surface; a direction from the first surface to the second surface is the first direction; a drain electrode, located on the second surface; The source is located on the first surface and is in contact with the first region and the second region.

2. The semiconductor device according to claim 1, wherein: The size of the second region in the second direction is smaller than the size of the buried layer region in the second direction, and the second direction is perpendicular to the first direction; The doping concentration of the second region is greater than the doping concentration of the well region, and the doping concentration of the buried layer region is greater than the doping concentration of the well region.

3. The semiconductor device according to claim 1, wherein: The semiconductor body comprises a first epitaxial layer, a second epitaxial layer and a third epitaxial layer; the conductivity types of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all the first conductivity type; The second epitaxial layer is located on a side of the first epitaxial layer away from the second surface; The third epitaxial layer is located on a side of the second epitaxial layer away from the second surface; The buried region is located in the second epitaxial layer, the well region and the first region are located in the third epitaxial layer, and the second region is connected to the buried region by the first surface, through the first region, the well region and part of the third epitaxial layer; The doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer.

4. The semiconductor device according to claim 3, characterized in that The doping concentration of the third epitaxial layer is greater than or equal to the doping concentration of the second epitaxial layer.

5. The semiconductor device according to claim 1, wherein: The surface of the well region close to the first insulating layer includes Crystal face or Crystal face.

6. The semiconductor device according to claim 1, wherein: The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

7. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a well region, a first area, a second area and a buried area, the first area being set to a first conductivity type and being located on the first surface, the well region being set to a second conductivity type and being located on a side of the first area away from the first surface, the buried area being set to a second conductivity type and being located on a side of the well region away from the first surface, the second area being set to a second conductivity type and being in contact with the buried area from the first surface through the first area, the well region and a part of the semiconductor body; a gate trench being set on the first surface, and the gate trench extending from the first surface into the semiconductor body; the semiconductor body further comprising a first insulating layer, the first insulating layer being located on the bottom and side surfaces of the gate trench; the channel mobility corresponding to the crystal orientation of the well region close to the surface of the first insulating layer is greater than the channel mobility corresponding to the (0001) crystal plane; Forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; In a first direction, a vertical distance between the buried layer region and the second surface is smaller than a vertical distance between the bottom of the trench gate and the second surface; a direction from the first surface to the second surface is the first direction; forming a drain electrode on the second surface; A source electrode is formed on the first surface in contact with the first region and the second region.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The semiconductor body provided includes: forming a first epitaxial layer; forming a second epitaxial layer on a side of the first epitaxial layer away from the second surface; the doping concentration of the second epitaxial layer is greater than the doping concentration of the first epitaxial layer; forming a buried layer region on a side of the second epitaxial layer away from the first epitaxial layer; wherein the buried layer region is located in the second epitaxial layer; forming a third epitaxial layer on a side of the second epitaxial layer away from the second surface; forming a well region in the third epitaxial layer; forming a gate trench on the first surface, wherein the gate trench extends from the first surface into the semiconductor body; forming a first region in the third epitaxial layer; A second region is formed, where the second region extends from the first surface through the first region, the well region and a portion of the second epitaxial layer and contacts the buried layer region.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The semiconductor body provided includes: forming a well region in the semiconductor body; A gate trench is formed on the first surface, and a surface of the well region located on a sidewall of the gate trench includes Crystal face or Crystal face.

10. The method for manufacturing a semiconductor device according to claim 7, characterized in that: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

11. A power module, characterized in that: It comprises a substrate and the semiconductor device according to any one of claims 1 to 6, wherein the substrate is used to carry the semiconductor device.

12. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one semiconductor device according to any one of claims 1 to 6, wherein the semiconductor device is electrically connected to the circuit board.

13. A vehicle, characterized in that: It includes a load and a power conversion circuit as claimed in claim 11, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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