A hybrid high-voltage LDMOS device and its preparation method

Abstract

The present invention relates to the technical field of semiconductor high-voltage devices, and in particular to a hybrid high-voltage LDMOS device and a method for preparing the same. The hybrid high-voltage LDMOS device of the present invention provides a shallow trench isolation region within an N-type drift region, and provides a thick oxide layer on the surface of a P-type drift region and the N-type drift region. The shallow trench isolation layer and the thick oxide layer on the surface of the field plate are mixed, so that the shallow trench isolation region and the thick oxide layer work together to affect the electric field between the source and the drain, significantly improving the longitudinal electric field distribution. The hybrid high-voltage LDMOS device achieves a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and has lower on-resistance and longer hot carrier injection lifetime than pure shallow trench isolation and pure oxide layer structures, thereby solving the problem of short hot carrier injection effect lifetime in pure oxide layer structures.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor high-voltage devices, and in particular to a hybrid high-voltage LDMOS device and a preparation method thereof. Background Art

[0002] The performance optimization of high-voltage laterally diffused metal oxide semiconductor (HV-LDMOS) devices must focus on three core indicators: high breakdown voltage (BVD), low on-resistance (Rdson), and long hot carrier injection (HCI) lifetime. The breakdown voltage determines the device's withstand voltage at high voltages, the on-resistance directly affects energy efficiency and heat generation, and the HCI lifetime is related to long-term reliability. Currently, for high-voltage LDMOS operating voltages above 20V, mainstream designs fall into two categories:

[0003] The first is a field-plate structure based on shallow trench isolation (STI). This structure introduces a deep trench oxide layer in the drift region for isolation. Combined with field-plate technology, it optimizes the surface electric field distribution, improving breakdown voltage and hot carrier injection lifetime. This makes it suitable for applications with stringent reliability requirements, such as industrial power supplies and automotive electronics. However, its high lateral resistance results in a high on-resistance (Rdson), making it difficult to meet the requirements of low-power applications.

[0004] The second type is a field plate structure based on a thick oxide layer (RESURF Oxide, ROX) on the semiconductor silicon surface. This structure utilizes ROX technology and the charge balance effect to reduce the peak electric field on the field plate surface, thereby increasing the breakdown voltage. It also laterally expands the depletion region to reduce the current path resistance, thereby significantly reducing the on-resistance. However, the ROX structure has a short hot carrier injection lifetime, making it difficult to meet the requirements of products with high lifetime requirements.

[0005] Therefore, how to design a high-voltage LDMOS device with both low on-resistance and long hot carrier injection lifetime has become a technical problem that needs to be solved urgently in this field. Summary of the Invention

[0006] The present invention aims to provide a hybrid high-voltage LDMOS device and a preparation method thereof to solve the technical problems of large on-resistance and short hot carrier injection lifetime of the existing field plate structure, so that the high-voltage LDMOS device has both low on-resistance and long hot carrier injection lifetime.

[0007] To achieve the above-mentioned object, the present invention provides, in a first aspect, a hybrid high-voltage LDMOS device, comprising a substrate, a P-type drift region, a P-type body region, a high-concentration P-type doped region, an N-type drift region, a shallow trench isolation region, a thick oxide layer, a source, a gate, and a drain, wherein: the P-type drift region is located on one side of the substrate surface, the N-type drift region is located on the other side of the substrate surface, and the P-type drift region is connected to the N-type drift region; the P-type body region is located inside the P-type drift region; the high-concentration P-type doped region and the source are located inside the P-type body region; the high-concentration P-type doped region and the source are connected; and the drain is located inside the N-type drift region;

[0008] The shallow trench isolation region is located inside the N-type drift region, and the shallow trench isolation region is located between the source and the drain;

[0009] The thick oxide layer is located on the surface of the P-type drift region and the N-type drift region;

[0010] The gate is located on the surface of the P-type drift region and the thick oxide layer.

[0011] The hybrid high-voltage LDMOS device has a shallow trench isolation region within the N-type drift region, and a thick oxide layer on the surface of the P-type drift region and the N-type drift region. This hybrid combines the shallow trench isolation layer with the thick oxide layer on the surface of the field plate, allowing the shallow trench isolation region and the thick oxide layer to work together to influence the electric field between the source and drain, significantly improving the longitudinal electric field distribution. This allows the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure. Furthermore, compared to pure shallow trench isolation and pure oxide layer structures, the hybrid high-voltage LDMOS device has lower on-resistance and longer hot carrier injection lifetime, thereby resolving the short lifetime of the hot carrier injection effect associated with a pure oxide layer structure.

[0012] It should be noted that if a shallow trench isolation region and a thick oxide layer are simply combined on a high-voltage LDMOS device, the etching process may affect the boundary between the shallow trench isolation region and the thick oxide layer, causing the shallow trench isolation region to be concave or the thick oxide layer to be thinned, resulting in a weak point in the breakdown voltage at this location.

[0013] In order to solve the above technical problem, preferably, the shallow trench isolation region is located directly below the middle of the thick oxide layer.

[0014] The above-described embodiment places the shallow trench isolation region directly beneath the thick oxide layer, allowing the top of the shallow trench isolation region and the bottom of the thick oxide layer to completely overlap, forming a hybrid drain oxide structure. This avoids the problem of a weak point in breakdown voltage caused by the boundary between the shallow trench isolation region and the thick oxide layer. Furthermore, placing the shallow trench isolation region directly below the middle of the thick oxide layer can improve the mixed electric field generated by the two. Compared to placing the shallow trench isolation region below the boundary of the thick oxide layer, it has a higher breakdown voltage and lower on-resistance, which is beneficial for applications that meet low power consumption requirements and high life requirements.

[0015] Preferably, the boundary of the gate is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly below the gate.

[0016] The above embodiment further optimizes the relative positions of the shallow trench isolation region, the thick oxide layer, and the gate, thereby achieving a higher breakdown voltage and lower on-resistance. Specifically, the gate boundary is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly below the gate. That is, the shallow trench isolation region is not only located directly below the middle of the thick oxide layer, but also directly below the gate, and the shallow trench isolation region boundary is close to the vertical axis of the gate boundary in space.

[0017] A second aspect of the present invention provides a method for preparing a hybrid high-voltage LDMOS, which is suitable for preparing a hybrid high-voltage LDMOS device according to any one of the first aspects of the present invention, and comprises the following steps:

[0018] Determine a substrate, and then form an N-type drift region on one side of the substrate surface, wherein a shallow trench isolation region is provided inside the N-type drift region, and form a P-type drift region on the other side of the substrate surface;

[0019] forming a thick oxide layer on surfaces of the P-type drift region and the N-type drift region;

[0020] Injecting P-type impurities into the P-type drift region to form a P-type body region;

[0021] forming a gate on the surface of the P-type drift region and the thick oxide layer;

[0022] Implanting high-concentration N-type impurities into the P-type body region and the N-type drift region respectively to form a source located inside the P-type body region and a drain located inside the N-type drift region;

[0023] High-concentration P-type impurities are injected into the P-type body region to form a high-concentration P-type doping region.

[0024] Preferably, the determining of the substrate, further forming an N-type drift region on one side of the substrate surface, wherein a shallow trench isolation region is provided inside the N-type drift region, and forming a P-type drift region on the other side of the substrate surface, comprises:

[0025] growing an epitaxial layer on the surface of the substrate;

[0026] forming a shallow trench isolation region in an active region of the epitaxial layer;

[0027] Implanting N-type impurities into one side of the epitaxial layer to form an N-type drift region surrounding the shallow trench isolation region;

[0028] P-type impurities are implanted into the other side of the epitaxial layer to form a P-type drift region.

[0029] Preferably, forming a thick oxide layer on the surface of the P-type drift region and the N-type drift region includes:

[0030] Depositing a first oxide layer on surfaces of the P-type drift region and the N-type drift region;

[0031] performing photolithography on the first oxide layer to form a thick oxide layer pattern;

[0032] The first oxide structure is etched based on the thick oxide layer pattern, thereby forming the thick oxide layer.

[0033] Preferably, the step of injecting P-type impurities into the P-type drift region to form a P-type body region comprises:

[0034] performing photolithography on the P-type drift region to form a P-type body doping pattern;

[0035] P-type impurities are injected into the P-type drift region based on the P-type body doping pattern, thereby forming a P-type body region in the P-type drift region.

[0036] Preferably, forming a gate on the surface of the P-type drift region and the thick oxide layer includes:

[0037] growing a second oxide layer on the surface of the P-type drift region and the thick oxide layer;

[0038] depositing a polysilicon layer on the surface of the second oxide layer;

[0039] The second oxide layer and the polysilicon layer are etched to form the gate.

[0040] Preferably, the step of respectively injecting high-concentration N-type impurities into the P-type body region and the N-type drift region to form a source located inside the P-type body region and a drain located inside the N-type drift region comprises:

[0041] performing photolithography on the P-type body region and the N-type drift region respectively to form a source doping pattern and a drain doping pattern;

[0042] Injecting high-concentration N-type impurities into the P-type body region based on the source doping pattern, thereby forming a source in the P-type body region;

[0043] High-concentration N-type impurities are implanted into the N-type drift region based on the drain doping pattern, thereby forming a drain in the N-type drift region.

[0044] Preferably, the step of injecting high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doped region comprises:

[0045] Performing photolithography on the P-type body region to form a high-concentration P-type doping pattern;

[0046] P-type impurities are injected into the P-type drift region based on the high-concentration P-type doping pattern, thereby forming a high-concentration P-type doping region in the P-type drift region.

[0047] A hybrid high-voltage LDMOS device and a method for manufacturing the same provided by the present invention have at least the following advantages over the prior art:

[0048] First, the hybrid high-voltage LDMOS device provides a shallow trench isolation region within the N-type drift region while providing a thick oxide layer on the surface of the P-type drift region and the N-type drift region. This hybrid combines the shallow trench isolation layer with the thick oxide layer on the field plate surface, so that the shallow trench isolation region and the thick oxide layer work together to affect the electric field between the source and the drain, significantly improving the longitudinal electric field distribution. This enables the hybrid high-voltage LDMOS device to achieve a breakdown voltage that is superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure. In addition, the hybrid high-voltage LDMOS device has a lower on-resistance and a longer hot carrier injection lifetime than pure shallow trench isolation and pure oxide layer structures, thereby solving the problem of a short hot carrier injection effect lifetime in a pure oxide layer structure.

[0049] Secondly, the hybrid high-voltage LDMOS device places the shallow trench isolation region directly beneath the thick oxide layer, allowing the top of the shallow trench isolation region and the bottom of the thick oxide layer to completely overlap, forming a hybrid drain oxide structure. This avoids the problem of a weak point in breakdown voltage caused by the boundary between the shallow trench isolation region and the thick oxide layer. Furthermore, placing the shallow trench isolation region directly below the middle of the thick oxide layer can improve the mixed electric field generated by the two. Compared with placing the shallow trench isolation region below the boundary of the thick oxide layer, it has a higher breakdown voltage and lower on-resistance, which is beneficial for applications that meet low power consumption requirements and high life requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 Schematic diagram of a pure STI field plate structure provided by an embodiment of the present invention;

[0051] Figure 2Schematic diagram of a pure ROX field plate structure provided by an embodiment of the present invention;

[0052] Figure 3 This is a structural diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0053] Figure 4 is a structural diagram of another hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0054] Figure 5a Schematic diagram of the electric field of a pure STI field plate structure provided by an embodiment of the present invention;

[0055] Figure 5b Schematic diagram of the electric field of a pure ROX field plate structure provided by an embodiment of the present invention;

[0056] Figure 5c Schematic diagram of an electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0057] Figure 6a 1 is a schematic diagram of a shallow trench isolation region provided by an embodiment of the present invention, in which the region is located at the lower left of a thick oxide layer;

[0058] Figure 6b Schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0059] Figure 7a This is a schematic diagram of a shallow trench isolation region located directly below the middle of a thick oxide layer provided by an embodiment of the present invention;

[0060] Figure 7b Schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0061] Figure 8a 1 is a schematic diagram of a shallow trench isolation region located at the lower right side of a thick oxide layer provided by an embodiment of the present invention;

[0062] Figure 8b Schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0063] Figure 9a This is a schematic diagram of a shallow trench isolation region close to the left side of a gate boundary provided by an embodiment of the present invention;

[0064] Figure 9b Schematic diagram of an electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0065] Figure 10a 1 is a schematic diagram of a shallow trench isolation region located below a gate boundary provided by an embodiment of the present invention;

[0066] Figure 10b Schematic diagram of an electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0067] Figure 11a This is a schematic diagram of a shallow trench isolation region close to the right side of a gate boundary provided by an embodiment of the present invention;

[0068] Figure 11b Schematic diagram of an electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0069] Figure 12 is a schematic diagram of the depth of a shallow trench isolation region provided by an embodiment of the present invention;

[0070] Figure 13a This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 0.2 μm provided by an embodiment of the present invention;

[0071] Figure 13b This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 0.3 μm provided by an embodiment of the present invention;

[0072] Figure 13c This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 0.35 μm provided by an embodiment of the present invention;

[0073] Figure 14 Schematic diagram of the width of a shallow trench isolation region provided by an embodiment of the present invention;

[0074] Figure 15a This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 0.5 μm provided by an embodiment of the present invention;

[0075] Figure 15b This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 0.75 μm provided by an embodiment of the present invention;

[0076] Figure 15c This is a schematic diagram of an electric field in a shallow trench isolation region with a depth of 1.0 μm provided by an embodiment of the present invention;

[0077] Figure 16 This is a structural diagram of the intermediate process of preparing a first hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0078] Figure 17 This is a structural diagram of the intermediate process of preparing a second hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0079] Figure 18 This is a structural diagram of the intermediate process of preparing a third hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0080] Figure 19 This is a structural diagram of the intermediate process of preparing a fourth hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0081] Figure 20 This is a structural diagram of the intermediate process of manufacturing a fifth hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0082] Figure 21 This is a structural diagram of an intermediate process for preparing a sixth hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0083] Figure 22 This is a structural diagram of the intermediate process of preparing the seventh hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0084] Figure 23 This is a structural diagram of an intermediate process for preparing an eighth hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0085] Figure 24 This is a structural diagram of an intermediate process for preparing a ninth hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0086] Figure 25 This is a schematic structural diagram of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention;

[0087] Among them: 1. Substrate; 11. N-type buried layer; 12. Epitaxial layer; 2. P-type drift region; 21. P-type body region; 211. High-concentration P-type doped region; 3. N-type drift region; 4. Shallow trench isolation region; 5. Thick oxide layer; 51. First oxide layer; 6. Source; 7. Gate; 71. Second oxide layer; 8. Drain. DETAILED DESCRIPTION

[0088] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments. It should be noted that the following detailed descriptions are all exemplary descriptions and are intended to provide further detailed descriptions of the present invention. Unless otherwise defined, all technical and scientific terms used herein have the same meanings as those generally understood by those skilled in the art to which this application belongs; the terms used herein in the specification of the application are only for the purpose of describing specific embodiments and are not intended to limit this application; the terms "including" and "having" in the specification and claims of this application and the description of the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of this application or the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order.

[0089] The performance optimization of high-voltage laterally diffused metal oxide semiconductor (HV-LDMOS) devices must focus on three core indicators: high breakdown voltage (BVD), low on-resistance (Rdson), and long hot carrier injection (HCI) lifetime. The breakdown voltage determines the device's withstand voltage at high voltages, the on-resistance directly affects energy efficiency and heat generation, and the HCI lifetime is related to long-term reliability. Currently, for high-voltage LDMOS operating voltages above 20V, mainstream designs fall into two categories:

[0090] See also Figure 1 The first type is a field-plate structure based on shallow trench isolation (STI). This structure introduces a deep trench oxide layer in the drift region for isolation. Combined with field-plate technology, it optimizes the surface electric field distribution, improving breakdown voltage and hot carrier injection lifetime. This makes it suitable for applications with stringent reliability requirements, such as industrial power supplies and automotive electronics. However, its high lateral resistance results in a high on-resistance (Rdson), making it difficult to meet the requirements of low-power applications.

[0091] See also Figure 2 The second type is a field plate structure based on a thick oxide layer (RESURF Oxide, ROX) on the semiconductor silicon surface. This structure utilizes ROX technology and the charge balance effect to reduce the peak electric field on the field plate surface, thereby increasing the breakdown voltage. It also laterally expands the depletion region to reduce the current path resistance, thereby significantly reducing the on-resistance. However, the ROX structure has a short hot carrier injection lifetime, making it difficult to meet the requirements of products with high lifetime requirements.

[0092] Therefore, how to design a high-voltage LDMOS device with both low on-resistance and long hot carrier injection lifetime has become a technical problem that needs to be solved urgently in this field.

[0093] See also Figure 3 In order to solve the above technical problems, a first aspect of an embodiment of the present invention provides a hybrid high-voltage LDMOS device, comprising a substrate 1, a P-type drift region 2, a P-type body region 21, a high-concentration P-type doping region 211, an N-type drift region 3, a shallow trench isolation region 4, a thick oxide layer 5, a source 6, a gate 7, and a drain 8, wherein: the P-type drift region 2 is located on one side of the surface of the substrate 1, the N-type drift region 3 is located on the other side of the surface of the substrate 1, and the P-type drift region 2 and the N-type drift region 3 are connected; the P-type body region 21 is located inside the P-type drift region 2; the high-concentration P-type doping region 211 and the source 6 are located inside the P-type body region 21; the high-concentration P-type doping region 211 and the source 6 are connected; and the drain 8 is located inside the N-type drift region 3;

[0094] The shallow trench isolation region 4 is located inside the N-type drift region 3 , and the shallow trench isolation region 4 is located between the source 6 and the drain 8 ;

[0095] The thick oxide layer 5 is located on the surface of the P-type drift region 2 and the N-type drift region 3;

[0096] The gate 7 is located on the surface of the P-type drift region 2 and the thick oxide layer 5 .

[0097] It should be noted that if the shallow trench isolation region 4 and the thick oxide layer 5 are simply combined on the high-voltage LDMOS device, the etching process may affect the junction of the shallow trench isolation region 4 and the thick oxide layer 5, resulting in a depression of the shallow trench isolation region 4 or a thinning of the thick oxide layer 5, resulting in a weak point of breakdown voltage at this location.

[0098] See also Figure 4 In order to solve the above technical problems, preferably, the shallow trench isolation region 4 is located directly below the middle of the thick oxide layer 5; further, the boundary of the gate 7 is aligned with the center of the thick oxide layer 5, and the shallow trench isolation region 4 is located directly below the gate 7.

[0099] In the above embodiment, the shallow trench isolation region 4 is positioned directly below the middle of the thick oxide layer 5. The shallow trench isolation region 4 is also located directly below the gate 7 and close to the vertical axis of the gate 7 boundary in space. This arrangement allows the top of the shallow trench isolation region 4 and the bottom of the thick oxide layer 5 to completely overlap, forming a hybrid drain 8 oxidation structure. This avoids the problem of a weak point in breakdown voltage created by the boundary between the shallow trench isolation region 4 and the thick oxide layer 5. Furthermore, positioning the shallow trench isolation region 4 directly below the middle of the thick oxide layer 5 improves the mixed electric field generated by the two. Compared to positioning the shallow trench isolation region 4 below the boundary of the thick oxide layer 5, it achieves a higher breakdown voltage and lower on-resistance, which is beneficial for applications in products with low power consumption requirements and high lifespan requirements.

[0100] To illustrate the technical effect of this embodiment, first, see Figure 6a to Figure 8b , where ss represents the distance from the high-concentration N-type impurity region in the P-type body region to the shallow trench isolation region. Figure 6a The figure shows the shallow trench isolation region 4 being located directly below the thick oxide layer 5 and close to the left edge of the thick oxide layer 5. Figure 6b The heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm); Figure 7a The shallow trench isolation region 4 is shown to be located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5. Figure 7bThe heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm); Figure 8a The figure shows the shallow trench isolation region 4 being located directly below the thick oxide layer 5 and close to the right edge of the thick oxide layer 5. Figure 8b The heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm).

[0101] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Figure 6a to Figure 8b It can be seen that Figure 7b The electric field peak range shown is smaller, and the overall electric field size is smaller than that of Figure 6b and Figure 8b The lower the value, the more uniform the electric field distribution. Figure 7b The reduction of the peak electric field and the improvement of its uniformity directly increase the threshold of the field plate breakdown voltage, while the large range of low electric field intensity areas effectively improves the carrier mobility between the source and drain and reduces the field plate on-resistance; that is, Figure 7a and Figure 7b When the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5 , the field plate electric field distribution is optimal, and both a higher breakdown voltage and a lower on-resistance can be achieved.

[0102] It should also be noted that in the experimental data corresponding to this embodiment, Figure 6b The corresponding ratio of breakdown voltage (V) to on-resistance (Ω) is 0.325. Figure 7b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.383. Figure 8b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.299, demonstrating that the hybrid high-voltage LDMOS device can achieve both high breakdown voltage and low on-resistance when the shallow trench isolation region 4 is located directly below and in the middle of the thick oxide layer 5.

[0103] Furthermore, based on the fact that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, see Figure 9a to Figure 11b At this time, the boundary of the gate 7 is aligned with the center of the thick oxide layer 5. Figure 9a The figure shows the situation where the shallow trench isolation region 4 is close to the left side of the gate 7 boundary. Figure 9b The heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm); Figure 10aThe shallow trench isolation region 4 is shown to be located directly below the gate 7 boundary. Figure 10b The heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm); Figure 11a The figure shows the situation where the shallow trench isolation region 4 is close to the right side of the gate 7 boundary. Figure 11b The heat map shows the magnitude and distribution of the electric field strength of the field plate at this time (Electric Field), with the unit being volts per centimeter (V / cm).

[0104] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Figure 9a to Figure 11b It can be seen that Figure 9b The overall electric field magnitude shown is compared to Figure 10b and Figure 11b The lower the value, the wider the range of low peak electric field distribution, and the more uniform the electric field distribution. Figure 9b The improvement of the low-peak electric field distribution and uniformity in a wide range directly increases the threshold of the field plate breakdown voltage, and the wide range of low-peak electric field distribution area effectively improves the carrier mobility between the source and drain and reduces the field plate on-resistance; that is, Figure 9a and Figure 9b As shown, based on the shallow trench isolation region 4 being located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, the field plate electric field distribution is optimal when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, which can achieve both higher breakdown voltage and lower on-resistance.

[0105] It also needs to be explained. Figure 9b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.403. Figure 10b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.383. Figure 11b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.294, demonstrating that the hybrid high-voltage LDMOS device can achieve both high breakdown voltage and low on-resistance when the shallow trench isolation region 4 is located directly below and in the middle of the thick oxide layer 5 and is close to the left side of the gate 7 boundary.

[0106] Furthermore, based on the fact that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5 and close to the left side of the gate 7 boundary, the depth and width of the shallow trench isolation region 4 are further explored. Figure 12 , Figure 12 Middle D STI Indicates the depth of the shallow trench isolation region 4. Figure 14 , Figure 14 Middle WSTI represents the width of the shallow trench isolation region 4.

[0107] See also Figure 13a to Figure 13c , Figure 13a The magnitude and distribution of the electric field strength of the field plate when the shallow trench isolation region 4 is 0.2 μm deep based on the above is shown in a thermal diagram (Electric Field), with the unit being volts per centimeter (V / cm); Figure 13b The magnitude and distribution of the electric field strength of the field plate when the depth of the shallow trench isolation region 4 is 0.3 μm based on the above is represented by a thermal diagram (ElectricField), with the unit being volts per centimeter (V / cm); Figure 13c A heat map is used to represent the magnitude and distribution of the electric field strength of the field plate when the depth of the shallow trench isolation region 4 is 0.35 μm based on the above, with the unit being volts per centimeter (V / cm).

[0108] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Figure 13a to Figure 13c It can be seen that Figure 13b The overall electric field magnitude shown is compared to Figure 13a and Figure 13c The lower the value, the wider the range of low peak electric field distribution, and the more uniform the electric field distribution. Figure 13b The improvement of the low-peak electric field distribution and uniformity in a wide range directly increases the threshold of the field plate breakdown voltage, and the wide range of low-peak electric field distribution area effectively improves the carrier mobility between the source and drain and reduces the field plate on-resistance; that is, Figure 13b As shown, on the basis that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the field plate electric field distribution is optimal when the shallow trench isolation region 4 is 0.3um deep, which can achieve both higher breakdown voltage and lower on-resistance.

[0109] It also needs to be explained. Figure 13a The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.260. Figure 13b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.429. Figure 13c The corresponding ratio of breakdown voltage (V) to on-resistance (Ω) is 0.403, which proves that when the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, and when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the shallow trench isolation region 4 with a depth of 0.3 μm can achieve both a higher breakdown voltage and a lower on-resistance.

[0110] Further, see Figure 15a to Figure 15c, Figure 15a to Figure 15c Based on setting the shallow trench isolation region 4 to be located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, and when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the optimal width of the shallow trench isolation region 4 is further tested based on the depth of the shallow trench isolation region 4 being 0.3um. Figure 15a The magnitude and distribution of the electric field strength of the field plate when the width of the shallow trench isolation region 4 is 0.5 μm based on the above is represented by a thermal diagram (Electric Field), with the unit being volts per centimeter (V / cm); Figure 15b The magnitude and distribution of the electric field strength of the field plate when the width of the shallow trench isolation region 4 is 0.75 μm based on the above is shown in a thermal diagram (Electric Field), with the unit being volts per centimeter (V / cm); Figure 15c A heat map is used to represent the magnitude and distribution of the electric field strength of the field plate when the width of the shallow trench isolation region 4 is 1.0 μm based on the above, with the unit being volts per centimeter (V / cm).

[0111] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Figure 15a to Figure 15c It can be seen that Figure 15c The overall electric field magnitude shown is compared to Figure 15a and Figure 15b The lower the value, the wider the range of low peak electric field distribution, and the more uniform the electric field distribution. Figure 15c The improvement of the low-peak electric field distribution and uniformity in a wide range directly increases the threshold of the field plate breakdown voltage, and the wide range of low-peak electric field distribution area effectively improves the carrier mobility between the source and drain and reduces the field plate on-resistance; that is, Figure 15c As shown, on the basis that the shallow trench isolation region 4 is located directly below the thick oxide layer 5 and in the middle of the thick oxide layer 5, when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, the field plate electric field distribution is optimal when the shallow trench isolation region 4 has a depth of 0.3um and a width of 1.0um, which can achieve both a higher breakdown voltage and a lower on-resistance.

[0112] It also needs to be explained. Figure 15a The corresponding ratio of breakdown voltage (V) to on-resistance (Ω) is 0.375. Figure 15b The corresponding breakdown voltage (V) to on-resistance (Ω) ratio is 0.429. Figure 15cThe corresponding ratio of breakdown voltage (V) to on-resistance (Ω) is 0.484, demonstrating that the hybrid high-voltage LDMOS device can achieve both high breakdown voltage and low on-resistance when the shallow trench isolation region 4 is located directly below and in the middle of the thick oxide layer 5, and when the shallow trench isolation region 4 is close to the left side of the gate 7 boundary, and the shallow trench isolation region 4 has a depth of 0.3 μm and a width of 1.0 μm.

[0113] See also Figure 5a to Figure 5c , Figure 5a This is a schematic diagram of the electric field of a pure STI field plate structure provided by an embodiment of the present invention, showing the magnitude and distribution of the field plate electric field strength (Electric Field) in units of volts per centimeter (V / cm) using a heat map. Figure 5b This is a schematic diagram of the electric field of a pure ROX field plate structure provided by an embodiment of the present invention, showing the magnitude and distribution of the electric field strength of the field plate at this time as a thermal diagram (Electric Field), with the unit being volts per centimeter (V / cm); Figure 5c FIG. 1 is a schematic diagram of the electric field of a hybrid high-voltage LDMOS device provided by an embodiment of the present invention, showing the magnitude and distribution of the field plate electric field strength (Electric Field) at this time using a heat map, with the unit being volts per centimeter (V / cm).

[0114] Since the field plate breakdown voltage is determined by the uniformity of the electric field distribution and the peak electric field strength, and the field plate on-resistance is related to the carrier mobility between the source and drain, the cross-sectional area and length of the current path between the source and drain. Figure 5a to Figure 5c It can be seen that Figure 5c The overall electric field magnitude shown is compared to Figure 5a and Figure 5b The lower the value, the wider the range of low peak electric field distribution, and the more uniform the electric field distribution. Figure 5c The improvement of the low-peak electric field distribution and uniformity in a wide range directly increases the threshold of the field plate breakdown voltage, and the wide range of low-peak electric field distribution area effectively improves the carrier mobility between the source and drain and reduces the field plate on-resistance; that is, Figure 5c The hybrid high-voltage LDMOS device can achieve both higher breakdown voltage and lower on-resistance compared to a pure STI field plate structure or a pure ROX field plate structure.

[0115] It also needs to be explained. Figure 5a The ratio of breakdown voltage (V) to on-resistance (Ω) of the pure STI field plate structure shown is 0.379. Figure 5b The breakdown voltage (V) to on-resistance (Ω) ratio of the pure ROX field plate structure shown is 0.242. Figure 5cThe ratio of breakdown voltage (V) to on-resistance (Ω) of the hybrid high-voltage LDMOS device is 0.484, demonstrating that the hybrid high-voltage LDMOS device can achieve both higher breakdown voltage and lower on-resistance compared to pure STI field-plate structures or pure ROX field-plate structures.

[0116] It can be seen that the hybrid high-voltage LDMOS device provides a shallow trench isolation region 4 inside the N-type drift region 3, and provides a thick oxide layer 5 on the surface of the P-type drift region 2 and the N-type drift region 3. The shallow trench isolation layer and the thick oxide layer 5 on the surface of the field plate are mixed, so that the shallow trench isolation region 4 and the thick oxide layer 5 work together to affect the electric field between the source 6 and the drain 8, significantly improving the longitudinal electric field distribution. As a result, the hybrid high-voltage LDMOS device achieves a breakdown voltage that is superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and has a lower on-resistance and a longer hot carrier injection lifetime compared to pure shallow trench isolation and pure oxide layer structures, thereby solving the problem of short hot carrier injection effect lifetime based on the pure oxide layer structure.

[0117] A second aspect of an embodiment of the present invention provides a method for preparing a hybrid high-voltage LDMOS, which is suitable for preparing a hybrid high-voltage LDMOS device according to any one of the first aspects of the present invention, and comprises the following steps:

[0118] Determine a substrate 1, and then form an N-type drift region 3 on one side of the surface of the substrate 1, wherein a shallow trench isolation region 4 is provided inside the N-type drift region 3, and form a P-type drift region 2 on the other side of the surface of the substrate 1;

[0119] forming a thick oxide layer 5 on the surfaces of the P-type drift region 2 and the N-type drift region 3;

[0120] Injecting P-type impurities into the P-type drift region 2 to form a P-type body region 21;

[0121] forming a gate 7 on the surface of the P-type drift region 2 and the thick oxide layer 5;

[0122] Implanting high-concentration N-type impurities into the P-type body region 21 and the N-type drift region 3 respectively to form a source 6 located inside the P-type body region 21 and a drain 8 located inside the N-type drift region 3;

[0123] High-concentration P-type impurities are implanted into the P-type body region 21 to form a high-concentration P-type doping region 211 .

[0124] See also Figures 16 to 19 Preferably, the substrate 1 is determined, and an N-type drift region 3 is formed on one side of the surface of the substrate 1, a shallow trench isolation region 4 is provided inside the N-type drift region 3, and a P-type drift region 2 is formed on the other side of the surface of the substrate 1, including:

[0125] Determine a substrate 1, and implant an N-type buried layer 11 on the surface of the substrate 1;

[0126] Growing an epitaxial layer 12 on the surface of the N-type buried layer 11;

[0127] forming a shallow trench isolation region 4 in the active region of the epitaxial layer 12;

[0128] Injecting N-type impurities into one side of the epitaxial layer 12 to form an N-type drift region 3 surrounding the shallow trench isolation region 4;

[0129] P-type impurities are implanted into the other side of the epitaxial layer 12 to form a P-type drift region 2 .

[0130] See also Figures 19 to 21 Preferably, the forming of the thick oxide layer 5 on the surface of the P-type drift region 2 and the N-type drift region 3 includes:

[0131] Depositing a first oxide layer 51 on the surfaces of the P-type drift region 2 and the N-type drift region 3;

[0132] performing photolithography on the first oxide layer 51 to form a thick oxide layer pattern;

[0133] The first oxide structure is etched based on the thick oxide layer pattern, thereby forming the thick oxide layer 5 .

[0134] See also Figure 21-22 Preferably, the step of injecting P-type impurities into the P-type drift region 2 to form the P-type body region 21 includes:

[0135] Performing photolithography on the P-type drift region 2 to form a P-type body doping pattern;

[0136] P-type impurities are injected into the P-type drift region 2 based on the P-type body doping pattern, thereby forming a P-type body region 21 in the P-type drift region 2 .

[0137] See also Figures 22 to 24 Preferably, the forming of the gate 7 on the surface of the P-type drift region 2 and the thick oxide layer 5 includes:

[0138] Growing a second oxide layer 71 on the surface of the P-type drift region 2 and the thick oxide layer 5;

[0139] Depositing a polysilicon layer on the surface of the second oxide layer 71;

[0140] The second oxide layer 71 and the polysilicon layer are etched to form the gate 7 .

[0141] See also Figure 24-25Preferably, the step of respectively injecting high-concentration N-type impurities into the P-type body region 21 and the N-type drift region 3 to form a source 6 located inside the P-type body region 21 and a drain 8 located inside the N-type drift region 3 includes:

[0142] Performing photolithography on the P-type body region 21 and the N-type drift region 3 to form a source doping pattern and a drain doping pattern respectively;

[0143] Injecting high-concentration N-type impurities into the P-type body region 21 based on the source doping pattern, thereby forming a source 6 in the P-type body region 21;

[0144] High-concentration N-type impurities are implanted into the N-type drift region 3 based on the drain doping pattern, thereby forming a drain 8 in the N-type drift region 3 .

[0145] See also Figure 24-25 Preferably, the step of injecting high-concentration P-type impurities into the P-type body region 21 to form a high-concentration P-type doping region 211 includes:

[0146] Performing photolithography on the P-type body region 21 to form a high-concentration P-type doping pattern;

[0147] P-type impurities are injected into the P-type drift region 2 based on the high-concentration P-type doping pattern, thereby forming a high-concentration P-type doping region 211 in the P-type drift region 2 .

[0148] A hybrid high-voltage LDMOS device and a method for manufacturing the same provided by the present invention have at least the following advantages over the prior art:

[0149] First, the hybrid high-voltage LDMOS device provides a shallow trench isolation region 4 within the N-type drift region 3 while providing a thick oxide layer 5 on the surface of the P-type drift region 2 and the N-type drift region 3. This hybrid high-voltage LDMOS device combines the shallow trench isolation layer and the thick oxide layer 5 on the field plate surface, thereby allowing the shallow trench isolation region 4 and the thick oxide layer 5 to work together to affect the electric field between the source 6 and the drain 8, significantly improving the longitudinal electric field distribution. This allows the hybrid high-voltage LDMOS device to achieve a breakdown voltage superior to that of a pure shallow trench isolation field plate structure or a pure oxide layer field plate structure, and has lower on-resistance and longer hot carrier injection lifetime than pure shallow trench isolation and pure oxide layer structures, thereby solving the problem of short hot carrier injection effect lifetime in pure oxide layer structures.

[0150] Secondly, the hybrid high-voltage LDMOS device places the shallow trench isolation region 4 directly beneath the thick oxide layer 5, allowing the top of the shallow trench isolation region 4 and the bottom of the thick oxide layer 5 to completely overlap, forming a hybrid drain 8 oxide structure. This avoids the problem of a weak point in breakdown voltage caused by the boundary between the shallow trench isolation region 4 and the thick oxide layer 5. Furthermore, placing the shallow trench isolation region 4 directly below the middle of the thick oxide layer 5 improves the mixed electric field generated by the two. Compared to placing the shallow trench isolation region 4 below the boundary of the thick oxide layer 5, it achieves a higher breakdown voltage and lower on-resistance, which is beneficial for applications that meet low power consumption requirements and high lifespan requirements.

[0151] Those skilled in the art will appreciate that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the above-mentioned embodiments. In particular, any reference to memory, database, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The databases involved in the various embodiments provided herein may include at least one of a relational database and a non-relational database. Non-relational databases may include, but are not limited to, distributed databases based on blockchains. The processors involved in the various embodiments provided herein may be, but are not limited to, general-purpose processors, central processing units (CPUs), graphics processing units (GPUs), digital signal processors (DSPs), programmable logic devices (PLDs), data processing logic devices based on quantum computing, and the like.

[0152] The "embodiment" mentioned in this document means that the specific features, structures or characteristics described in conjunction with the embodiment may be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0153] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present application. It should be noted that a person of ordinary skill in the art may make several improvements and substitutions without departing from the scope of the present application, and such improvements and substitutions should also be considered within the scope of protection of the present invention. Therefore, the scope of protection of the present application shall be determined by the appended claims.

Claims

1. A hybrid high-voltage LDMOS device, characterized in that: The present invention comprises a substrate, a P-type drift region, a P-type body region, a high-concentration P-type doped region, an N-type drift region, a shallow trench isolation region, a thick oxide layer, a source, a gate, and a drain, wherein: the P-type drift region is located on one side of the substrate surface, the N-type drift region is located on the other side of the substrate surface, the P-type drift region is connected to the N-type drift region; the P-type body region is located inside the P-type drift region; the high-concentration P-type doped region and the source are located inside the P-type body region; the high-concentration P-type doped region and the source are connected; and the drain is located inside the N-type drift region. The shallow trench isolation region is located inside the N-type drift region, and the shallow trench isolation region is located between the source and the drain; The thick oxide layer is located on the surface of the P-type drift region and the N-type drift region; The gate is located on the surface of the P-type drift region and the thick oxide layer; The shallow trench isolation region is located directly below the middle portion of the thick oxide layer; The boundary of the gate is aligned with the center of the thick oxide layer, and the shallow trench isolation region is located directly under the gate.

2. A method for preparing a hybrid high-voltage LDMOS, characterized in that: Suitable for preparing a hybrid high-voltage LDMOS device as claimed in claim 1, comprising the following steps: Determine a substrate, and then form an N-type drift region on one side of the substrate surface, wherein a shallow trench isolation region is provided inside the N-type drift region, and form a P-type drift region on the other side of the substrate surface; forming a thick oxide layer on surfaces of the P-type drift region and the N-type drift region; Injecting P-type impurities into the P-type drift region to form a P-type body region; forming a gate on the surface of the P-type drift region and the thick oxide layer; Implanting high-concentration N-type impurities into the P-type body region and the N-type drift region respectively to form a source located inside the P-type body region and a drain located inside the N-type drift region; High-concentration P-type impurities are injected into the P-type body region to form a high-concentration P-type doping region.

3. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The method further comprises: forming an N-type drift region on one side of the substrate surface, wherein a shallow trench isolation region is provided inside the N-type drift region, and forming a P-type drift region on the other side of the substrate surface; growing an epitaxial layer on the surface of the substrate; forming a shallow trench isolation region in an active region of the epitaxial layer; Implanting N-type impurities into one side of the epitaxial layer to form an N-type drift region surrounding the shallow trench isolation region; P-type impurities are implanted into the other side of the epitaxial layer to form a P-type drift region.

4. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The forming of a thick oxide layer on the surface of the P-type drift region and the N-type drift region includes: Depositing a first oxide layer on surfaces of the P-type drift region and the N-type drift region; performing photolithography on the first oxide layer to form a thick oxide layer pattern; The first oxide layer is etched based on the thick oxide layer pattern, thereby forming the thick oxide layer.

5. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The step of injecting P-type impurities into the P-type drift region to form a P-type body region includes: performing photolithography on the P-type drift region to form a P-type body doping pattern; P-type impurities are injected into the P-type drift region based on the P-type body doping pattern, thereby forming a P-type body region in the P-type drift region.

6. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The forming of a gate on the surface of the P-type drift region and the thick oxide layer includes: growing a second oxide layer on the surface of the P-type drift region and the thick oxide layer; depositing a polysilicon layer on the surface of the second oxide layer; The second oxide layer and the polysilicon layer are etched to form the gate.

7. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The step of respectively injecting high-concentration N-type impurities into the P-type body region and the N-type drift region to form a source located inside the P-type body region and a drain located inside the N-type drift region comprises: performing photolithography on the P-type body region and the N-type drift region respectively to form a source doping pattern and a drain doping pattern; Injecting high-concentration N-type impurities into the P-type body region based on the source doping pattern, thereby forming a source in the P-type body region; High-concentration N-type impurities are implanted into the N-type drift region based on the drain doping pattern, thereby forming a drain in the N-type drift region.

8. The method for preparing a hybrid high-voltage LDMOS according to claim 2, wherein: The step of injecting high-concentration P-type impurities into the P-type body region to form a high-concentration P-type doped region comprises: Performing photolithography on the P-type body region to form a high-concentration P-type doping pattern; P-type impurities are injected into the P-type drift region based on the high-concentration P-type doping pattern, thereby forming a high-concentration P-type doping region in the P-type drift region.

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