Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof, and the method comprises the steps: providing a substrate, forming a plurality of gate structures on the substrate, and forming a preprocessing groove in the substrate between two adjacent gate structures; forming an expansion layer on the inner wall of the pretreatment groove; etching to remove the part, located at the bottom of the pretreatment groove, in the expansion layer, so that the residual expansion layer covers the side wall of the pretreatment groove, and etching the substrate below the pretreatment groove to form an initial groove based on the pretreatment groove; etching the part, which is not covered by the expansion layer, in the initial groove and forming a sigma groove; removing the residual expansion layer; an epitaxial layer is formed in the sigma groove, the epitaxial layer comprises a buffer layer, a middle layer and a cap layer which are sequentially stacked from bottom to top, and the buffer layer completely covers the inner wall of the sigma groove. The diffusion of elements in the intermediate layer into the substrate is reduced or avoided, so that the short-channel effect of the semiconductor device is reduced or even avoided.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technologies, and particularly to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In a general epitaxy process (Epitaxy, EPI), an epitaxial layer usually includes a buffer layer, an intermediate layer, and a capping layer. Among them, the buffer layer is formed on the inner wall of a trench in a substrate, the intermediate layer is formed on the buffer layer and fills the trench, and the capping layer is formed on the intermediate layer and is higher than the substrate on both sides of the trench.

[0003] However, during the actual epitaxy process, the buffer layer included in the epitaxial layer in the top corner region of the epitaxial trench may not completely cover the inner wall of the trench, that is, the buffer layer does not completely enclose the intermediate layer, so that the intermediate layer cannot be isolated from the substrate through the buffer layer. This will cause elements (such as boron elements) in the intermediate layer to diffuse into the channel region in the substrate, and in severe cases, it may even cause short channel effects (Short Channel Effects, SCE) in the semiconductor device. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and a manufacturing method thereof to reduce or avoid the risk of diffusion of the epitaxial layer, and at the same time reduce or avoid the short channel effect of the semiconductor device.

[0005] This application provides a manufacturing method of a semiconductor device, including:

[0006] Providing a substrate, on which a plurality of spaced-apart gate structures are formed, and forming a pre-treatment trench in the substrate between two adjacent gate structures;

[0007] Forming an expansion layer on the inner wall of the pre-treatment trench;

[0008] Etching and removing a part of the expansion layer located at the bottom of the pre-treatment trench, so that the remaining expansion layer covers the side wall of the pre-treatment trench, and etching a part of the substrate below the pre-treatment trench to form an initial trench based on the pre-treatment trench;

[0009] Etching a part of the initial trench that is not covered by the expansion layer and forming a sigma trench;

[0010] Removing the remaining expansion layer;

[0011] Forming an epitaxial layer in the sigma trench, the epitaxial layer includes a buffer layer, an intermediate layer, and a capping layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0012] In one embodiment, the buffer layer includes a first buffer layer close to the substrate side and a second buffer layer close to the intermediate layer side.

[0013] In one embodiment, the material of the first buffer layer includes a germanium-silicon material, the materials of the second buffer layer and the intermediate layer include a germanium-silicon-boron material, the germanium element content in the intermediate layer is higher than that in the second buffer layer, and the material of the capping layer includes boron silicide.

[0014] In one embodiment, a first wet etching process is used to etch the portion of the initial trench that does not cover the extended layer to form the sigma trench, and the etchant used in the first wet etching process includes THMA.

[0015] In one embodiment, a second wet etching process is used to remove the remaining extended layer, and the etchant used in the second wet etching process includes DHF.

[0016] In one embodiment, an ISSG growth process is used to form the extended layer on the inner wall of the pre-treatment trench.

[0017] In one embodiment, the depth range of the pre-treatment trench includes 5 Å to 20 Å.

[0018] In one embodiment, the material of the extended layer includes silicon oxide.

[0019] Correspondingly, the present application further provides a semiconductor device manufactured by using the manufacturing method of the semiconductor device as described above.

[0020] In one embodiment, the semiconductor device includes:

[0021] A substrate, in which a sigma trench is provided;

[0022] A plurality of mutually spaced gate structures located on the substrate, and two adjacent gate structures are located on the substrate on both sides of the sigma trench;

[0023] An epitaxial layer located in the sigma trench, the epitaxial layer includes a buffer layer, an intermediate layer and a capping layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0024] The unexpected effects of this application are as follows: By forming a pre-treatment trench and an extension layer covering the sidewalls of the pre-treatment trench, and forming an initial trench based on the pre-treatment trench to utilize the extension layer to protect the sidewalls it covers during subsequent etching processes; by forming a sigma trench based on the initial trench and removing the extension layer, the width of the sigma trench on the side closer to the gate structure is increased, providing process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; by making the buffer layer completely cover the inner wall of the sigma trench, the diffusion of elements in the intermediate layer in the epitaxial layer into the substrate is reduced or avoided, thereby reducing and even avoiding the short-channel effect of semiconductor devices. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 It is a schematic structural diagram of a semiconductor device in the related art.

[0027] Figure 2 is Figure 1 a schematic TEM structure diagram corresponding to the semiconductor device shown.

[0028] Figure 3 It is a flowchart of a manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0029] Figure 4 It is a schematic structural diagram corresponding to the step of providing a substrate in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0030] Figure 5 It is a schematic structural diagram corresponding to the step of forming a pre-treatment trench in the substrate between two adjacent gate structures in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0031] Figure 6 It is a schematic structural diagram corresponding to the step of forming an extension layer on the inner wall of the pre-treatment trench in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0032] Figure 7 It is a schematic structural diagram corresponding to the step of etching the extension layer and the substrate under the pre-treatment trench to form an initial trench in the manufacturing method of a semiconductor device provided by one embodiment of the present application.

[0033] Figure 8 The structural schematic diagram corresponding to the step of etching the part of the initial trench that is not covered by the extension layer and forming a sigma trench in the manufacturing method of the semiconductor device provided by one embodiment of the present application.

[0034] Figure 9 The structural schematic diagram corresponding to the step of removing the extension layer in the manufacturing method of the semiconductor device provided by one embodiment of the present application.

[0035] Figure 10 The structural schematic diagram corresponding to the step of forming an epitaxial layer in the sigma trench in the manufacturing method of the semiconductor device provided by one embodiment of the present application.

[0036] Figure 11 is Figure 10 The enlarged structural schematic diagram corresponding to the part of the epitaxial layer shown in the top corner region of the sigma trench.

[0037] Wherein, the reference numerals include: 100 - substrate; 101 - epitaxial trench; 110 - gate structure; 120 - germanium-silicon-boron epitaxial layer; 200 - substrate; 201 - pre-treatment trench; 202 - initial trench; 203 - sigma trench; 210 - gate structure; 211 - gate dielectric layer; 212 - gate; 213 - gate sidewall; 220 - extension layer; 230 - epitaxial layer; 231 - buffer layer; 231a - first buffer layer; 231b - second buffer layer; 232 - intermediate layer; 233 - capping layer; A - top corner region. Detailed implementation manners

[0038] To facilitate the understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the present application belongs. The terms used in the description of the present application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present application, the first element, component, region, layer, doping type, or portion discussed below may be referred to as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for instance, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0041] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "below" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0042] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / having" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0043] Figure 1 It is a schematic structural diagram of an epitaxial layer formed by an epitaxial process in a semiconductor device. Refer to Figure 1 , multiple spaced-apart gate structures 110 are formed on a substrate 100 of a semiconductor device, an epitaxial trench 101 is provided in the substrate 100 between two adjacent gate structures 110, and a germanium-silicon-boron epitaxial layer 120 is formed in the epitaxial trench 101.

[0044] In a general semiconductor device, the substrate 100 is usually a silicon (Si) substrate, and the gate structure 110 generally includes a gate dielectric layer (not labeled in the figure) formed on the substrate 100, a gate electrode (not labeled in the figure) formed on the gate dielectric layer, and sidewalls (not labeled in the figure) covering the sidewalls of the gate electrode. Optionally, the gate electrode can be a metal gate electrode or a polysilicon gate electrode, the material of the gate dielectric layer includes silicon oxide, and the sidewalls can be a silicon oxide layer, a silicon nitride layer, or a stacked structure composed of a combination of the two. For example, the sidewalls can be an ONO stacked structure formed by stacking a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0045] Continue to refer to Figure 1 , the epitaxial trench 101 is a sigma (Sigma) trench, and the germanium-silicon-boron epitaxial layer 120 includes an L1 layer, an L2 layer, and an L3 layer stacked in sequence in a direction away from the surface of the substrate 100. Optionally, the L1 layer includes an L1-1 layer on the side close to the substrate 100 and an L1-2 layer on the side close to the L2 layer. Among them, the L1-1 layer is a germanium-silicon material layer (SiGe Layer), that is, the L1-1 layer does not contain boron element; both the L1-2 layer and the L2 layer are germanium-silicon-boron material layers (SiGeB Layer), and the content of germanium (Ge) in the L2 layer is higher than that in the L1-2 layer to increase the stress in the L2 layer; the L3 layer is a silicon boride layer (SiB Layer).

[0046] However, refer to Figure 1 and Figure 2 , in an actual epitaxial process, in the epitaxial layer 120 formed at the top corner of the epitaxial trench 101 (that is, the part circled by the dotted line in Figure 1 and Figure 2 ), the L1 layer (that is, the stacked structure formed by combining the L1-1 layer and the L1-2 layer) may not completely cover the substrate 100, so that the L1 layer does not enclose the L2 layer, resulting in the boron element in the L2 layer being easily diffused into the channel (Channel, not shown in the figure) in the substrate 100, thereby causing the short-channel effect (Short-Channel Effects, SCE) of the semiconductor device.

[0047] To solve the above problems, the present application provides a semiconductor device and a manufacturing method thereof to reduce or avoid the risk of diffusion of the epitaxial layer and at the same time reduce or avoid the short-channel effect of the semiconductor device.

[0048] Figure 3 A flowchart of a method for manufacturing a semiconductor device provided by one embodiment of the present application. Refer to Figure 3 , a method for manufacturing a semiconductor device provided by one embodiment of the present application includes the following steps S01 to step S06.

[0049] Step S01: Provide a substrate, on which a plurality of spaced-apart gate structures are formed, and form a pre-treatment trench in the substrate between two adjacent gate structures.

[0050] Step S02: Form an expansion layer on the inner wall of the pre-treatment trench.

[0051] Step S03: Etch and remove the part of the expansion layer located at the bottom of the pre-treatment trench, so that the remaining expansion layer covers the side wall of the pre-treatment trench, and etch a part of the substrate below the pre-treatment trench to form an initial trench based on the pre-treatment trench.

[0052] It should be noted that by forming the pre-treatment trench in step S01 and the expansion layer in step S02, and forming the initial trench based on the pre-treatment trench in step S03, it is to make the remaining expansion layer cover the side wall of the pre-treatment trench (it can also be understood that the remaining expansion layer covers the part of the side wall of the initial trench close to the gate structure), providing a process basis for subsequent process steps.

[0053] Step S04: Etch the part of the initial trench not covered by the expansion layer and form a sigma trench.

[0054] Step S05: Remove the remaining expansion layer.

[0055] It should be noted that after removing the remaining expansion layer, the width of the sigma trench on the side close to the gate structure increases, providing a process space for the subsequently formed epitaxial layer.

[0056] Step S06: Form an epitaxial layer in the sigma trench, the epitaxial layer includes a buffer layer, an intermediate layer and a cap layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

[0057] In the method for manufacturing a semiconductor device as described above, by forming a pre-treatment trench and an extension layer covering the sidewalls of the pre-treatment trench, and forming an initial trench based on the pre-treatment trench, the extension layer is used to protect the sidewalls it covers during subsequent etching processes; by forming a sigma trench based on the initial trench and removing the extension layer, the width of the sigma trench near the gate structure side is increased, providing a process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; by completely covering the inner wall of the sigma trench with the buffer layer, the diffusion of elements in the intermediate layer in the epitaxial layer into the substrate is reduced or avoided, thereby reducing and even avoiding the short-channel effect of the semiconductor device.

[0058] Figures 4 to 11 The following is a schematic structural diagram corresponding to some process steps in the method for manufacturing a semiconductor device provided in one embodiment of the present application. Hereinafter, in conjunction with Figure 4 and Figure 11 the specific details of steps S01 to S06 in the method for manufacturing a semiconductor device provided in one embodiment to be provided in the present application will be described in detail.

[0059] First, refer to Figure 4 and Figure 5 and perform step S01 to provide a substrate 200. A plurality of spaced-apart gate structures 210 are formed on the substrate 200, and pre-treatment trenches 201 are formed in the substrate 200 between two adjacent gate structures 210. Optionally, the material of the substrate 200 includes silicon material (Si).

[0060] Continue to refer to Figure 4 In one embodiment, the gate structure 210 includes a gate dielectric layer 211, a gate 212, and a gate sidewall 213. Among them, the gate dielectric layer 211 is formed on the substrate 200, the gate 212 is formed on the gate dielectric layer 211, and the gate sidewall 213 covers the sidewalls of the gate 212 and the sidewalls of the gate dielectric layer 211. Exemplarily, the gate 212 is a metal gate or a polysilicon gate, the material of the gate dielectric layer 211 includes silicon oxide, and the gate sidewall 213 can be a laminated structure composed of a silicon oxide layer, a silicon nitride layer, or a combination of the two. For example, the gate sidewall 213 can be an ONO laminated structure stacked by a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer.

[0061] Refer to Figure 5 In one embodiment, a dry etching process is used to etch the substrate 200 between two adjacent gate structures 210 to form the pre-treatment trenches 201. Optionally, the depth range of the pre-treatment trenches 201 includes 5 Å to 20 Å.

[0062] It should be emphasized that the depth of the pre-treatment trench 201 is relatively shallow compared to the overall thickness of the substrate 200, and the depth of the pre-treatment trench 201 is usually set within the thickness range of a few angstroms to dozens of angstroms to ensure that the formation of the pre-treatment trench 201 will not have a great negative impact on subsequent process steps, thereby reducing or avoiding affecting the yield of semiconductor devices.

[0063] Next, referring to Figure 6 , perform step S02 to form an expansion layer 220 on the inner wall of the pre-treatment trench 201. In one embodiment, an in-situ steam generation (ISSG) process is used to form the expansion layer 220 on the inner wall of the pre-treatment trench 201. Optionally, the material of the expansion layer 220 includes silicon oxide.

[0064] In other embodiments of the present application, other commonly used process methods can also be used to form the expansion layer according to actual process requirements. For example, a thermal oxidation growth process can be used to form the expansion layer on the inner wall of the pre-treatment trench, or other commonly used process methods can be used to form the expansion layer. In addition, the well-known common knowledge in the art is not elaborated in this application.

[0065] Subsequently, referring to Figure 7 , perform step S03 to etch away the part of the expansion layer 220 located at the bottom of the pre-treatment trench 201, so that the remaining expansion layer 220 covers the side wall of the pre-treatment trench 201, and etch a part of the substrate 200 below the pre-treatment trench 201 to form an initial trench 202 based on the pre-treatment trench 201.

[0066] It should be noted that during the formation of the initial trench 202, a dry etching process is used to etch away the part of the expansion layer 220 located at the bottom of the pre-treatment trench 201, and continue to etch the substrate 200 below the pre-treatment trench 201 to form the initial trench 202. Among them, the surface of the remaining expansion layer 220 on the side away from the side wall is flush with the part of the side wall of the initial trench 202 that is not covered by the expansion layer 220 to ensure the smooth progress of subsequent process steps.

[0067] Next, referring to Figure 8 , perform step S04 to etch the part of the initial trench 202 that is not covered by the expansion layer 220 and form a sigma trench 203. In one embodiment, a first wet etching process is used to etch the part of the initial trench 202 that is not covered by the expansion layer 220 to form the sigma trench 203. Optionally, the etchant used in the first wet etching process includes tetramethylammonium hydroxide (THMA).

[0068] It should be emphasized that referring to Figure 8 , the sigma trench 203 is formed based on the initial trench 202. Therefore, the sigma trench 203 formed here includes the entire trench starting from the surface of the substrate 200 (it can also be understood that the sigma trench 203 includes not only the polygonal trench area under the extended layer 220, but also the rectangular trench area at the position of the extended layer 220).

[0069] Subsequently, referring to Figure 9 , step S05 is performed to remove the remaining extended layer 220. In one embodiment, the remaining extended layer 220 is removed by a second wet etching process. Optionally, the etchant used in the second wet etching process includes DHF (i.e., a mixed solution composed of hydrofluoric acid and deionized water).

[0070] It should be noted that during the second wet etching process, the gate sidewall in the gate structure 210 (i.e., Figure 4 the gate sidewall 213 in ) can protect the gate dielectric layer 211 to avoid damage to the gate dielectric layer 211 during the second wet etching process, thereby ensuring the normal operation of the semiconductor device.

[0071] Continuing to refer to Figure 8 and Figure 9 , it needs to be further emphasized that after removing the remaining extended layer 220, the sigma trench 203 includes the entire trench area in the substrate 200 under the gate structure 210 (it can also be understood that the sigma trench 203 includes not only Figure 9 the rectangular trench area in the substrate 200 between two adjacent gate structures 210 in , but also the polygonal trench area below the rectangular trench area).

[0072] Next, referring to Figure 10 and Figure 11 , step S06 is performed to form an epitaxial layer 230 in the sigma trench 203. The epitaxial layer 230 includes a buffer layer 231, an intermediate layer 232, and a cap layer 233 stacked in sequence from bottom to top, and the buffer layer 231 completely covers the inner wall of the sigma trench 203.

[0073] Continuing to refer to Figure 10 and Figure 11, in one embodiment, the buffer layer 231 includes a first buffer layer 231a close to the substrate 200 side and a second buffer layer 231b close to the intermediate layer 232 side. In one embodiment, the material of the first buffer layer 231a includes a germanium-silicon material, such as germanium silicide (SiGe), the materials of the second buffer layer 231b and the intermediate layer 232 include a germanium-silicon-boron material (SiGeB), and the content of germanium (Ge) in the intermediate layer 232 is higher than that in the second buffer layer 231b to increase the pressure of the intermediate layer 232. The material of the capping layer 233 includes a silicon-boron material, such as boron silicide (SiB). In other embodiments of the present application, the specific material of the epitaxial layer 230 and the elements and their contents included in each film layer of the epitaxial layer 230 can be set according to actual process requirements, and the present application does not limit this.

[0074] Referring to Figure 11 , in the top corner region A of the sigma trench 203, the buffer layer 231 completely covers the inner wall of the sigma trench 203, thereby completely isolating the substrate 200 and the intermediate layer 232. It can be seen that in the epitaxial layer manufactured by using the manufacturing method of the semiconductor device improved in one embodiment of the present application, since the buffer layer completely isolates the substrate and the intermediate layer, the boron element in the intermediate layer will not diffuse into the trench in the substrate, thereby reducing or avoiding the risk of element diffusion in the epitaxial layer, and further reducing or even avoiding the short-channel effect caused by the diffusion of elements in the epitaxial layer into the channel, improving the performance and stability of the semiconductor device.

[0075] Correspondingly, one embodiment of the present application further provides a semiconductor device manufactured by using the manufacturing method of the semiconductor device as described above. Continuing to refer to Figure 10 and Figure 11 , in one embodiment, the semiconductor device includes a substrate 200 and a plurality of mutually spaced gate structures 210 located on the substrate 200; wherein, a sigma trench 203 is provided in the substrate 200, and two adjacent gate structures 210 are located on the substrate 200 on both sides of the sigma trench 203, and an epitaxial layer 230 is provided in the sigma trench. The epitaxial layer 230 includes a buffer layer 231, an intermediate layer 232, and a capping layer 233 stacked in sequence from bottom to top, and the buffer layer 231 completely covers the inner wall of the sigma trench 203.

[0076] Referring to Figure 11, in the top corner region A of the sigma trench 203, the buffer layer 231 completely covers the inner wall of the sigma trench 203, thereby completely isolating the substrate 200 from the intermediate layer 232. It can be seen that in the semiconductor structure as described above, by using the buffer layer 231 to completely isolate the substrate 200 from the intermediate layer 232, it is ensured that the boron element in the intermediate layer 232 will not diffuse into the trenches (such as the sigma trench 203) in the substrate 200, thereby reducing or avoiding the risk of element diffusion in the epitaxial layer 230, and further reducing or even avoiding the short-channel effect caused by element diffusion into the channel in the epitaxial layer 230, improving the performance and stability of the semiconductor device.

[0077] Refer to Figure 4 and Figure 10 , in one embodiment, the gate structure 210 includes a gate dielectric layer 211, a gate 212, and a gate sidewall 213. Among them, the gate dielectric layer 211 is formed on the substrate 200, the gate 212 is formed on the gate dielectric layer 211, and the gate sidewall 213 covers the sidewalls of the gate 212 and the sidewalls of the gate dielectric layer 211. Exemplarily, the material of the substrate 200 includes silicon material (Si), the gate 212 is a metal gate or a polysilicon gate, the material of the gate dielectric layer 211 includes silicon oxide, and the gate sidewall 213 can be a stacked structure composed of a silicon oxide layer, a silicon nitride layer, or a combination of the two. For example, the gate sidewall 213 can be an ONO stacked structure composed of a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked together.

[0078] Continue to refer to Figure 10 , in one embodiment, the material of the first buffer layer 231a includes a germanium-silicon material, such as germanium silicide (SiGe), the materials of the second buffer layer 231b and the intermediate layer 232 include a germanium-silicon-boron material (SiGeB), and the germanium (Ge) content in the intermediate layer 232 is higher than the germanium content in the second buffer layer 231b to increase the pressure of the intermediate layer 232. The material of the capping layer 233 includes a silicon-boron material, such as boron silicide (SiB). In other embodiments of the present application, the specific material of the epitaxial layer 230 and the elements and their contents respectively included in each film layer in the epitaxial layer 230 can be set according to actual process requirements, and the present application does not limit this.

[0079] The unexpected effects of the present application are as follows: By forming a pre-treatment trench and an extension layer covering the sidewalls of the pre-treatment trench, and forming an initial trench based on the pre-treatment trench, the sidewalls covered by the extension layer can be protected during subsequent etching processes; By forming a sigma trench based on the initial trench and removing the extension layer, the width of the sigma trench near the gate structure side is increased, providing a process space for the subsequently formed epitaxial layer, which is beneficial to improving the thickness and uniformity of the buffer layer included in the epitaxial layer; By making the buffer layer completely cover the inner wall of the sigma trench, the diffusion of elements in the intermediate layer within the epitaxial layer into the substrate can be reduced or avoided, thereby reducing and even avoiding the short-channel effect of semiconductor devices.

[0080] In the description of this specification, the description referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0081] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0082] The above-described embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that, Comprising: Providing a substrate, on which a plurality of spaced-apart gate structures are formed, and a pre-treatment trench is formed in the substrate between two adjacent gate structures; Forming an extension layer on the inner wall of the pre-treatment trench; Etching away a part of the extension layer located at the bottom of the pre-treatment trench, so that the remaining extension layer covers the side wall of the pre-treatment trench, and etching a part of the substrate below the pre-treatment trench to form an initial trench based on the pre-treatment trench; Etching a part of the initial trench not covered by the extension layer to form a sigma trench; Removing the remaining extension layer; Forming an epitaxial layer in the sigma trench, the epitaxial layer including a buffer layer, an intermediate layer and a capping layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

2. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The buffer layer includes a first buffer layer on the side close to the substrate and a second buffer layer on the side close to the intermediate layer.

3. The manufacturing method of the semiconductor device according to claim 2, wherein, The material of the first buffer layer includes a germanium-silicon material, the materials of the second buffer layer and the intermediate layer include a germanium-silicon-boron material, and the germanium element content in the intermediate layer is higher than that in the second buffer layer, and the material of the capping layer includes boron silicide.

4. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Using a first wet etching process to etch a part of the initial trench not covered by the extension layer to form the sigma trench, and the etching agent used in the first wet etching process includes THMA.

5. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Using a second wet etching process to remove the remaining extension layer, and the etching agent used in the second wet etching process includes DHF.

6. The manufacturing method of the semiconductor device according to claim 1, characterized in that, Using an ISSG growth process to form the extension layer on the inner wall of the pre-treatment trench.

7. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The depth range of the pre-treatment trench includes 5 Å to 20 Å.

8. The manufacturing method of the semiconductor device according to claim 1, characterized in that, The material of the extension layer includes silicon oxide.

9. A semiconductor device, characterized in that, Manufactured by using the manufacturing method of the semiconductor device according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, wherein, Comprising: A substrate, in which a sigma trench is provided; A plurality of spaced-apart gate structures, located on the substrate, and two adjacent gate structures are located on the substrate on both sides of the sigma trench; An epitaxial layer, located in the sigma trench, the epitaxial layer including a buffer layer, an intermediate layer and a capping layer stacked in sequence from bottom to top, and the buffer layer completely covers the inner wall of the sigma trench.

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