Semiconductor element arrangement structure

Abstract

The invention discloses a semiconductor element arrangement structure which comprises a carrier, an adhesive layer, a plurality of first semiconductor elements and a plurality of second semiconductor elements. The carrier has an upper surface, and the adhesive layer is located on the upper surface. The plurality of first semiconductor elements are located on a first element region of the adhesive layer, the plurality of second semiconductor elements are located on a second element region of the adhesive layer, and the first element region is adjacent to the second element region. Wherein any two adjacent first semiconductor elements in the plurality of first semiconductor elements have a first spacing, any two adjacent first semiconductor elements and second semiconductor elements in the plurality of first semiconductor elements and the plurality of second semiconductor elements have a second spacing, and the first spacing is greater than the second spacing.

Description

Technical Field

[0001] The present invention relates to a semiconductor element arrangement structure, and particularly to a semiconductor element arrangement structure in which semiconductor elements are arranged on a substrate or a carrier plate and a manufacturing method thereof. Background Art

[0002] Semiconductor elements such as light-emitting diodes (LEDs) have advantages such as low power consumption, low generated heat energy, long working life, shock resistance, small volume, fast response speed, and good optoelectronic characteristics (such as stable emission wavelength). Therefore, they are widely used in electronic devices such as household appliances, device indicators, and displays.

[0003] When light-emitting diode elements are continuously miniaturized, for example: less than 100 μm, 50 μm, or 30 μm, in order to apply the miniaturized light-emitting diode elements to a display, it is necessary to transfer a large number of light-emitting diode elements between different substrates, which is the so-called mass transfer. How to perform mass transfer with high efficiency and make the transfer result have high precision, high yield, and low cost is the goal that the industry is striving for.

[0004] A high-speed transfer method is to divide a light-emitting diode element arrangement structure into multiple light-emitting diode element regions, and each light-emitting diode element region contains multiple light-emitting diode elements. When transferring, taking the light-emitting diode element region as the minimum transfer unit, all the light-emitting diode elements in one or more light-emitting diode element regions are transferred at one time. Summary of the Invention

[0005] The present invention discloses a semiconductor element arrangement structure, including: a carrier having an upper surface; an adhesive layer located on the upper surface; a plurality of first semiconductor elements located on a first element region of the adhesive layer; a plurality of second semiconductor elements located on a second element region of the adhesive layer, and the first element region is adjacent to the second element region. Wherein, any two adjacent first semiconductor elements among the plurality of first semiconductor elements have a first spacing; any two adjacent first semiconductor elements and second semiconductor elements among the plurality of first semiconductor elements and the plurality of second semiconductor elements have a second spacing, and the first spacing is greater than the second spacing. Description of the Drawings

[0006] Figure 1A It is a top view of a light-emitting diode element wafer according to an embodiment of the present invention;

[0007] Figure 1B It is a cross-sectional view of the aforementioned light-emitting diode element wafer at line AA';

[0008] Figure 2ATop view of a light-emitting diode element carrier structure according to an embodiment of the present invention;

[0009] Figure 2B Cross-sectional view of the above-mentioned light-emitting diode element carrier structure at line BB';

[0010] Figure 3A Cross-sectional view of a regional laser transfer manufacturing process for a light-emitting diode element wafer 100 according to an embodiment of the present invention;

[0011] Figure 3B Simulation diagram of the laser transfer manufacturing process at region R of the above cross-sectional view;

[0012] Figure 3C Top view of a partial light-emitting diode element carrier structure according to an embodiment of the present invention;

[0013] Figure 3D Schematic diagram of the air flow field at line CC' of the above top view;

[0014] Figure 4A Top view of a light-emitting diode element wafer according to another embodiment of the present invention;

[0015] Figure 4B Top view of a light-emitting diode element carrier structure according to another embodiment of the present invention;

[0016] Figures 5A - 5C Flow chart of a regional transfer manufacturing process according to an embodiment of the present invention.

[0017] Symbol description

[0018] 1... Light-emitting diode element

[0019] 10, 40... Substrate

[0020] 10', 40'... Carrier board

[0021] 10a, 10a', 40a... Upper surface

[0022] 12... Semiconductor stack

[0023] 18... Transparent conductive layer

[0024] 20... Temporary carrier board

[0025] 25... First electrode

[0026] 35... Second electrode

[0027] 50... Insulating layer

[0028] 100, 200, 400... Light-emitting diode element wafers

[0029] 120... Adhesive layer

[0030] 121… First semiconductor layer

[0031] 122… Second semiconductor layer

[0032] 123… Active layer

[0033] 100’, 300, 400’… Light-emitting diode element carrier structure

[0034] 501, 502... Openings

[0035] AA’, BB’, CC’, A’A”, B’B”… Line segments

[0036] D1, D2, D3, D1”, D2”, D3”… Horizontal spacings

[0037] D1’, D2’, D3’, D11, D22, D33… Vertical spacings

[0038] G… Airflow

[0039] ISO, D’… Spacings

[0040] L… Laser beam

[0041] R… Region

[0042] O1, O2, O3, O4, P1, P2, P3, P4, S1, S2, S3, S4, Z1, Z2, Z3, Z4, Z1’, Z2’, Z3’, Z4’… Light-emitting diode element regions Detailed implementation manners

[0043] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art of the present invention can fully understand the spirit of the present invention. The present invention is not limited to the following embodiments, but can be implemented in other forms. In this specification, there are some identical symbols, which represent elements with the same or similar structures, functions, and principles, and can be inferred by those with ordinary knowledge and ability in the industry according to the teachings of this specification. For the sake of simplicity of the specification, the elements with the same symbols will not be restated.

[0044] Please refer to both Figure 1A and Figure 1B . Figure 1A which shows a top view of a semiconductor wafer (Wafer), Figure 1B and is a cross-sectional view of the semiconductor wafer at line segment AA’. Refer to Figure 1B, taking the light-emitting diode element 1 as an example of the semiconductor element, the light-emitting diode element wafer 100 includes a plurality of light-emitting diode elements 1 formed on a substrate 10. A plurality of semiconductor stacks 12 are formed on the upper surface 10a of the substrate 10, and each semiconductor stack 12 includes a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122. In addition, a transparent conductive layer 18, an insulating layer 50, a first electrode 25, and a second electrode 35 can be selectively formed on each semiconductor stack 12 to form the light-emitting diode element 1. Two adjacent light-emitting diode elements 1 are formed on the substrate 10 separated from each other by a pitch ISO. In one embodiment, a plurality of light-emitting diode elements 1 are arranged on the substrate 10 in a two-dimensional matrix.

[0045] The light-emitting diode element wafer 100 includes a plurality of virtual light-emitting diode element regions, such as light-emitting diode element regions Z1 to Z4, and N light-emitting diode elements 1 arranged in a matrix are respectively located on each light-emitting diode element region. In the present invention, the number of the plurality of light-emitting diode elements 1 located on a single light-emitting diode element region is 25 (5×5), and the arrangement, division, area, and number of the regions of the light-emitting diode elements 1 can be designed differently according to requirements.

[0046] Substrate 10

[0047] The substrate 10 can be a growth substrate, including a gallium arsenide (GaAs) substrate for growing aluminum gallium indium phosphide (AlGaInP), a gallium phosphide (GaP) substrate, or a sapphire (Al2O3) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 10 includes an upper surface 10a. In one embodiment, the upper surface 10a is a flat surface. In another embodiment, the substrate 10 can be a patterned substrate, that is, the substrate 10 has a patterned structure (not shown in the figure) on its upper surface 10a, and the patterned structure includes a plurality of protrusions and a plurality of cavities. In one embodiment, the light emitted from the semiconductor stack 12 can be refracted by the patterned structure of the substrate 10, thereby improving the brightness of the light-emitting diode element. In addition, the patterned structure slows down or suppresses the dislocation caused by lattice mismatch between the substrate 10 and the semiconductor stack 12, thereby improving the epitaxial quality of the semiconductor stack 12.

[0048] Semiconductor stack 12

[0049] In one embodiment of the present invention, the method of forming the semiconductor stack 12 on the substrate 10 includes metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0050] The semiconductor stack 12 includes a buffer structure (not shown), a first semiconductor layer 121, an active layer 123, and a second semiconductor layer 122 formed in sequence on a substrate 10. The buffer structure can reduce the above-mentioned lattice mismatch and suppress dislocations, thereby improving the epitaxial quality. The material of the buffer structure includes GaN, AlGaN, or AlN. In one embodiment, the buffer structure includes a plurality of sub-layers (not shown). The sub-layers include the same material or different materials. In one embodiment, the buffer structure includes two sub-layers, wherein the first sub-layer is grown by sputtering or MOCVD, and the second sub-layer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sub-layer. The growth mode of the third sub-layer is MOCVD, and the growth temperature of the second sub-layer is higher or lower than that of the third sub-layer. In one embodiment, the first, second, and third sub-layers include the same material, such as AlN. In another embodiment, the first semiconductor layer 121 and the second semiconductor layer 122 have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer 121 is an n-type semiconductor layer, and the second semiconductor layer 122 is a p-type semiconductor layer. The active layer 123 is formed between the first semiconductor layer 121 and the second semiconductor layer 122. Electrons and holes are combined in the active layer 123 under the drive of current to convert electrical energy into light energy to emit light. The wavelength of the light emitted by the semiconductor stack 12 can be adjusted by changing the material composition of one or more layers in the semiconductor stack 12.

[0051] The material of the semiconductor stack 12 includes Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y)III-V semiconductor material of P, where 0 ≤ x, y ≤ 1; x + y ≤ 1. According to the material of the active layer 123, when the material of the semiconductor stack 12 is of the AlInGaP series, red light with a wavelength between 610 nm and 650 nm or yellow light with a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack 12 is of the InGaN series, blue light with a wavelength between 400 nm and 490 nm or green light with a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack 12 is of the AlGaN series, UV light with a wavelength between 400 nm and 250 nm can be emitted. The active layer 123 can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active layer 123 can be an i-type, p-type, or n-type semiconductor.

[0052] Transparent conductive layer 18

[0053] The transparent conductive layer 18 covers the upper surface of the second semiconductor layer 122 of each light-emitting diode element 1 and is in electrical contact with the second semiconductor layer 122. The transparent conductive layer 18 can be a metal or a transparent conductive material, where the metal can be selected from thin metal layers with light transmittance, and the transparent conductive material is transparent to the light emitted by the active layer 123, including materials such as graphene, indium tin oxide (ITO), aluminum zinc oxide (AZO), gallium zinc oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO). In another embodiment, the light-emitting diode 1 does not have the transparent conductive layer 18. In this structure, the opening 502 exposes a partial area of the second semiconductor layer 122 to contact the second electrode 35.

[0054] Insulating layer 50

[0055] The insulating layer 50 is transparent to the light emitted by the semiconductor stack 12 and can be an insulating layer of a single material or a stack composed of multiple layers of different insulating materials. In one embodiment, the insulating layer 50 is formed by alternately stacking one or more pairs of insulating materials with different refractive indices, and the materials include, for example, silicon oxide, silicon nitride, silicon oxynitride, niobium oxide, hafnium oxide, titanium oxide, magnesium fluoride, aluminum oxide, etc. By selecting and matching insulating materials with different refractive indices and designing their thicknesses, the insulating layer 50 forms a reflective structure, such as a Distributed Bragg Reflector (DBR), for selectively reflecting light of a specific wavelength. The insulating layer 50 can be formed by methods such as Atomic Layer Deposition (ALD), Sputtering, Evaporation, and Spin-Coating. In another embodiment, the insulating layer 50 includes a stack composed of multiple layers of the same insulating material or different insulating materials formed by different forming methods. In this embodiment, the openings 501 and 502 of the insulating layer 50 expose the first semiconductor layer 121 and the transparent conductive layer 18 respectively.

[0056] Electrode

[0057] The electrode includes a first electrode 25 and a second electrode 35. The materials of the electrode include metals, such as metals like chromium (Cr), titanium (Ti), gold (Au), aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), rhodium (Rh), tungsten (W), indium (In), or platinum (Pt), or alloys of the above materials or stacks of the above materials.

[0058] In one embodiment, in a top view (not shown), the size of the light-emitting diode element 1, for example, has a diagonal length of less than 150 μm, and the distance between the first electrode 25 and the second electrode 35 is less than 30 μm. In another embodiment, in a top view (not shown), the size of the light-emitting diode element 1 has a diagonal length of less than 100 μm, and the distance between the first electrode 25 and the second electrode 35 is less than or equal to 25 μm.

[0059] Please also refer to Figure 2A and Figure 2B . Figure 2A A top view showing a semiconductor element carrier structure according to different embodiments of the present application, Figure 2B then it is Figure 2A a cross-sectional view of the line segment BB' in Figure 2B, taking the light-emitting diode element 1 as an example of the semiconductor element, the light-emitting diode element carrier structure 100' includes a plurality of light-emitting diode elements 1 formed on a carrier substrate 10'. The plurality of light-emitting diode elements 1 are arranged on the upper surface 10a' of the carrier substrate 10' at a fixed pitch D' and separated from each other. Among them, for the manufacturing process, structure, and material composition of the light-emitting diode element 1, reference can be made to the relevant paragraphs above.

[0060] In one embodiment, the light-emitting diode elements 1 are arranged on the carrier substrate 10' in a flip mounting manner. In order to increase the stability of the light-emitting diode elements 1 arranged on the carrier substrate 10', a continuous adhesive layer 120 is selectively disposed between the upper surface 10a' of the carrier substrate 10' and the light-emitting diode elements 1. In addition, in another embodiment, the light-emitting diode elements 1 do not have a growth substrate. In one embodiment, a plurality of light-emitting diode elements 1 are arranged on the carrier substrate 10' in a matrix manner. In another embodiment, a plurality of light-emitting diode elements 1 are arranged on the carrier substrate 10' with the first electrode 25 and the second electrode 35 facing away from the carrier substrate 10'.

[0061] As Figure 2A shown, the light-emitting diode element carrier structure 100' includes a plurality of virtual light-emitting diode element regions, such as light-emitting diode element regions Z1' to Z4', and N light-emitting diode elements 1 arranged in a matrix, for example, a 5×5 matrix, respectively located on each light-emitting diode element region. In other embodiments, the arrangement of the light-emitting diode elements 1, the division of the regions, and the area and number of the regions can be designed differently according to requirements.

[0062] Carrier substrate 10'

[0063] The carrier substrate 10' can be a non-epitaxial material or a non-growth substrate, such as a ceramic substrate, a metal substrate, a glass substrate, a quartz substrate, a thermal release tape, a UV release tape, a chemical release tape, a heat-resistant tape, a blue tape, or a tape with a dynamic release layer (DRL). According to one embodiment, the carrier substrate 10' is a substrate that can be penetrated by a laser, so that the light-emitting diode elements 1 can be separated from the carrier substrate 10' through a laser lift-off (LLO) manufacturing process.

[0064] Adhesive layer 120

[0065] The adhesive layer 120 is a continuous layer. The material of the adhesive layer 120 can be a polymer, especially a resin material that can be decomposed by laser heating through a laser ablation (LA) manufacturing process. In one embodiment, it can be a resin material with a laser absorption rate of 60% or more and 100% or less, or 80% or more and 100% or less. For example, the adhesive layer 120 may include polyimide (PI), acrylic resin, epoxy resin (EPO), polybenzoxazole (PBO), polysiloxane, cyclic olefin polymer (COP), or benzocyclobutane (BCB), but is not limited thereto.

[0066] Figure 3A A cross-sectional view schematically showing the regional laser transfer manufacturing process of the light-emitting diode element wafer 100. As shown in the figure, in the light-emitting diode element region Z1 of the light-emitting diode element wafer 100, a plurality of light-emitting diode elements 1 are simultaneously irradiated by a laser beam L and separated from the substrate 10 and move downward, and are adhered to a temporary carrier 20 through a continuous adhesive layer 200. In one embodiment, the number of light-emitting diode elements 1 in a single light-emitting diode element region is 25 (5×5), and the arrangement, division, area, and number of the regions of the light-emitting diode elements 1 can be designed differently according to requirements. Among them, the light-emitting diode element 1 is presented in a simplified structure (detailed elements are omitted), and the structure and material composition of the adhesive layer 200 and the temporary carrier 20 can refer to the relevant paragraphs above.

[0067] Please also refer to Figure 3A and Figure 3B , Figure 3B is Figure 3A the numerical simulation of region R in Figure 3B In x In y Ga (1-x-y)III-V semiconductor material of N, where 0 ≤ x, y ≤ 1; when x + y ≤ 1, the semiconductor stack 12 will decompose to produce nitrogen gas (N2) when irradiated by a laser. At this time, the generated gas will push the light-emitting diode element 1 downward. In addition, a disturbing air flow G that dissipates to both sides of the light-emitting diode element 1 will also be generated at the semiconductor stack 12 irradiated by the laser. According to the simulation, when the intensity of the left disturbing air flow G and the right disturbing air flow G generated on both sides of the light-emitting diode element 1 is the same, the resultant force of each light-emitting diode element 1 receiving the disturbing air flow G in the horizontal direction is approximately zero, so that when the light-emitting diode element 1 is separated from the substrate 10, it can move straight downward toward the temporary carrier 20, and the dropped light-emitting diode adheres to the temporary carrier 20 through the adhesive layer 200. In one embodiment, the object irradiated by the laser is Figure 2A and Figure 2B the light-emitting diode element carrier structure 100' in. When the laser beam L irradiates the adhesive layer 120, depending on the material difference, the adhesive layer 120 does not necessarily generate gas, but a shock wave will still be caused at the adhesive layer 120 due to the heat conduction of the chemical reaction. Similarly, according to the simulation, if the intensity of the left disturbing air flow G and the right disturbing air flow G generated by the shock wave causing the light-emitting diode element 1 is the same, because the resultant force of each light-emitting diode element 1 receiving the disturbing air flow G in the horizontal direction is generally zero, the light-emitting diode element 1 will move straight downward toward the temporary carrier 20 after being separated from the carrier 10'.

[0068] Laser beam L

[0069] When performing the regional transfer manufacturing process, the selected laser beam L light source module can be, for example, an argon fluoride (ArF) excimer laser that emits a wavelength of 193 nm or a krypton fluoride (KrF) excimer laser that emits a wavelength of 248 nm or a diode-pumped solid-state (DPSS) laser that emits a wavelength of 266 nm or a diode-pumped solid-state (DPSS) laser that emits a wavelength of 355 nm. In one embodiment, the laser beam L with a preset cross-sectional size as in Figure 3A can be generated by structures such as a beam shaping optical system, an adjustable aperture, an optical mask... configured in the laser light source module.

[0070] Please also refer to Figure 3C and Figure 3D ,Figure 3C is a top view of the light-emitting diode element carrier structure 300. The light-emitting diode element carrier structure 300 shows that the light-emitting diode elements 1 on the light-emitting diode element wafer 1 are transferred to the temporary carrier 20 via the Figure 3A regional transfer manufacturing process shown in the top view after the transfer. According to Figure 3C shown, Figure 3D shows Figure 3A a schematic diagram of the flow field around the light-emitting diode element 1 in the regional laser transfer manufacturing process in

[0071] Next, please refer to Figure 3A and Figure 3C simultaneously. The light-emitting diode element carrier structure 300 includes a temporary carrier 20, and the transferred light-emitting diode elements 1 are arranged in an array on the temporary carrier 20. The temporary carrier 20 has an upper surface 20a; an adhesive layer 200 is located on the upper surface 20a; a plurality of virtual light-emitting diode element regions S1 to S4 are located on the adhesive layer 200, and the light-emitting diode elements 1 on the plurality of virtual light-emitting diode element regions S1 to S4 respectively come from the light-emitting diode elements 1 on the light-emitting diode element regions Z1 to Z4 on the light-emitting diode element wafer 1. Among them, N light-emitting diode elements 1 arranged in a matrix, for example, a 5×5 matrix, are respectively located on each light-emitting diode element region. In one embodiment, as Figure 3A shown, the light-emitting diode element wafer 1 transfers the light-emitting diode elements 1 to the temporary carrier 20 with the upper surface 10a facing down. For example, in Figure 3A the five light-emitting diode elements 1 in the Z1 region are located at the line CC' in Figure 3C after the laser transfer manufacturing process. In other words, the light-emitting diode elements 1 originally located on the light-emitting diode element regions Z1, Z2, Z3, and Z4 will be transferred to the light-emitting diode element regions S3, S4, S1, and S2 respectively.

[0072] As Figure 3C shown, in the light-emitting diode element carrier structure 300, the light-emitting diode elements 1 arranged in a matrix are respectively located on the light-emitting diode element regions S1 to S4. In addition, in each light-emitting diode element region, the distribution morphologies of the plurality of light-emitting diode elements 1 are generally the same. The spacing between two adjacent light-emitting diode elements 1 increases outward from the central region of the light-emitting diode element region. For example, the spacing between the light-emitting diode element 1 located in the central region of the light-emitting diode element region and the adjacent light-emitting diode element 1 is D1 in the horizontal direction and D1' in the vertical direction; and the spacing between any two adjacent light-emitting diode elements 1 in the outermost two rows or two columns is D2 in the horizontal direction and D2' in the vertical direction. Among them, D2>D1, D2'>D1'.

[0073] Please refer to Figure 3D , when the light-emitting diode element 1 is irradiated by the laser beam L, in one embodiment, the semiconductor stack 12 adjacent to the substrate 10 decomposes and generates gas, for example, nitrogen gas (N2), and an air flow is generated at the interface with the substrate 10. However, since the light-emitting diode element 1 is transferred in units of regions, the air flow field intensities in the boundary region and the central region are not the same. Specifically, in addition to moving downward through the gaps between the light-emitting diode elements 1, the air flow also escapes toward the boundary region. As Figure 3C shown in Figure 3D , the region outside the region S1 is not irradiated by the laser beam L and no gas is generated. Therefore, when the region S1 is irradiated by the laser beam L, in addition to the air flow passing downward through the gaps between several light-emitting diode elements 1, there is also an air flow escaping laterally toward the boundary of the region S1. As Figure 3D shown in Figure 3C , there is more downward air flow in the gap located in the center of the region; there is less downward air flow in the gap between the light-emitting diode elements 1 located at the boundary of the region; the pressure difference caused by the different air flow rates generates a non-zero resultant force in the horizontal direction and an outward horizontal air flow, and the unbalanced pressure pushes the light-emitting diode element 1 to also generate a lateral movement during the downward movement to the temporary carrier 20, thereby changing the spacing between several light-emitting diode elements 1, that is, the spacing between several light-emitting diode elements 1 on the substrate 10 is different from the spacing between them on the temporary carrier 20. For example, as Figure 3C shown in

[0074] shown in Figure 3CAs shown, in each light-emitting diode element region S1 to S4, the pitch between multiple light-emitting diode elements located in a single region increases outward from the center of the region, and in each region, the distribution pattern of the light-emitting diode elements is the same (radially expanding outward). As shown in the figure, the horizontal pitches D1 and D2 and the vertical pitches D1' and D2' between adjacent light-emitting diode elements 1 are greater than the pitch ISO of the original light-emitting diode elements 1 located on the entire light-emitting diode element wafer 100. In addition, the horizontal pitch D3 and the vertical pitch D3' between adjacent light-emitting diode elements 1 located on the boundaries of two adjacent light-emitting diode element regions and within different light-emitting diode element regions are both smaller than the pitch ISO of the original light-emitting diode elements 1 located on the light-emitting diode element wafer 100. In one embodiment, the ranges of D3 and D3' are between 1 μm and 50 μm. In another embodiment, the transferred light-emitting diode element wafer 100 can also be replaced with a light-emitting diode element carrier structure 100'.

[0075] Please refer to Figure 4A , Figure 4A which shows a top view of a semiconductor element wafer (Wafer) of different embodiments of the present application. The semiconductor element is taken as the light-emitting diode element 1 as an example. The light-emitting diode wafer 400 includes a plurality of light-emitting diode elements 1 formed on the upper surface 40a of a substrate 40. The light-emitting diode element wafer 400 includes a plurality of virtual light-emitting diode element regions, such as light-emitting diode element regions O1 to O4, and N light-emitting diode elements 1 arranged in a matrix, such as a 5×5 matrix, are respectively located on each light-emitting diode element region. In other embodiments, the arrangement of the light-emitting diode elements 1, the division of the regions, and the area and number of the regions can be designed differently according to requirements.

[0076] The cross-sectional view of the light-emitting diode wafer 400 at the line A'A'' can be referred to the relevant Figure 1B paragraphs and will not be described again here. The difference between this embodiment and the aforementioned Figure 1A embodiment is that in each light-emitting diode element region O1 to O4, the pitch between multiple light-emitting diode elements located in a single region decreases outward from the center of the region; and in each region, the distribution pattern of the light-emitting diode elements is the same (dense outside and sparse inside).

[0077] In the light-emitting diode element wafer 400, taking the light-emitting diode element region O1 as an example, the pitch between the 5×5 light-emitting diode elements 1 arranged in a matrix in the region shrinks outward from the center of the light-emitting diode element region O1. That is to say, the pitch between the light-emitting diode element 1 at the center of the light-emitting diode element region O1 and the adjacent light-emitting diode element 1 is D1” in the horizontal direction and D11 in the vertical direction; while the pitch between the adjacent light-emitting diode element 1 and the more peripheral light-emitting diode element 1 is D2” in the horizontal direction and D22 in the vertical direction. Among them, D1”>D2”, D11>D22. The same situation also occurs in the light-emitting diode element regions O2 to O4. In addition, in the light-emitting diode element wafer 400, the pitch between adjacent light-emitting diode body elements within the same light-emitting diode element region is smaller than the pitch between adjacent light-emitting diode body elements in different light-emitting diode element regions. That is, D1”>D2”>D3”, D11>D22>D33. In one embodiment, the ranges of D3” and D33 are between 1 μm and 50 μm.

[0078] Please refer to Figure 4B , Figure 4B which shows a top view of a semiconductor element carrier structure according to different embodiments of the present application. Taking the light-emitting diode element 1 as an example, the light-emitting diode element carrier structure 400’ includes a plurality of light-emitting diode elements 1 formed on a carrier plate 40’. Similar to the foregoing light-emitting diode element carrier structure 100’, the light-emitting diode element carrier structure 400’ is divided into a plurality of virtual light-emitting diode element regions, such as light-emitting diode element regions P1 to P4. N light-emitting diode elements 1 arranged in a matrix, such as a 5×5 matrix, are respectively located on the light-emitting diode element regions. In other embodiments, the arrangement, division of regions, area and number of regions of the light-emitting diode elements 1 can be designed differently according to requirements.

[0079] The cross-sectional view of the light-emitting diode element carrier structure 400’ at the line B’B” can be referred to Figure 2B and the relevant paragraphs. The difference between this embodiment and the foregoing light-emitting diode element carrier structure 100’ is that in each of the light-emitting diode element regions P1 to P4, the pitch between the multiple light-emitting diode elements in a single region shrinks outward from the region center; and in each region, the distribution pattern of the light-emitting diode elements is the same (dense outside and sparse inside).

[0080] In the light-emitting diode element carrier structure 400', taking the light-emitting diode element area P1 as an example, the pitch between the 5×5 light-emitting diode elements 1 arranged in a matrix in the area shrinks outward from the center of the light-emitting diode element area P1. That is, the pitch between the light-emitting diode element 1 at the center of the light-emitting diode element area P1 and the adjacent light-emitting diode element 1 in the horizontal direction is D1", and in the vertical direction is D11; while the pitch between the adjacent light-emitting diode elements 1 and the more peripheral light-emitting diode elements 1 in the horizontal direction is D2", and in the vertical direction is D22. Among them, D1">D2", D11>D22. The same situation also occurs in the light-emitting diode element areas P2 to P4. In addition, in the light-emitting diode element carrier structure 400', the pitch between adjacent light-emitting diode body elements within the same light-emitting diode element area is greater than the pitch between adjacent light-emitting diode body elements in different light-emitting diode element areas. That is, D1">D2">D3", D11>D22>D33. In one embodiment, the ranges of D3" and D33 are between 1 μm and 50 μm.

[0081] In one embodiment, when using the aforementioned light-emitting diode element wafer 400 or light-emitting diode element carrier structure 400' to perform the regional laser transfer manufacturing process to transfer the light-emitting diode elements 1 to another carrier, a light-emitting diode element carrier structure with a fixed pitch between each light-emitting diode element 1 similar to that shown can be obtained. Figure 2A Shown is a light-emitting diode element carrier structure with a fixed pitch between each light-emitting diode element 1.

[0082] Figures 5A - 5C FIG. is a process flow diagram of a manufacturing process for transferring a plurality of light-emitting diode elements 1 on an entire light-emitting diode element carrier structure 500 to a temporary carrier 60 through a regional transfer manufacturing process according to another embodiment of the present application. Refer to Figure 5A , which is shown as a cross-sectional view of a light-emitting diode element carrier structure 500. Similar to the aforementioned light-emitting diode element carrier structure 100', the light-emitting diode element carrier structure 500 includes a carrier 50, and a first adhesive sub-layer 221 and a second adhesive sub-layer 222 are respectively located within virtual light-emitting diode element areas Q1 and Q2 on the upper surface 50a' of the carrier 50. In the light-emitting diode element area Q1, a plurality of light-emitting diode elements 1 are respectively arranged on the adhesive sub-layer 221 at a fixed pitch D111; in the light-emitting diode element area Q2, a plurality of light-emitting diode elements 1 are respectively arranged on the adhesive sub-layer 222 at a fixed pitch D111'; and between the light-emitting diode element areas Q1 and Q2, the pitch between adjacent light-emitting diode elements 1 is D222.

[0083] In this embodiment, the difference from the light-emitting diode element carrier structure 100' is that the light-emitting diode elements 1 are arranged on the carrier substrate 50 in a flip-chip manner with a relatively simple structural diagram (omitting detailed elements). In addition, the first adhesive sub-layer 221 and a second adhesive sub-layer 222 within each light-emitting diode element region Q1 and Q2 are separated from each other. In one embodiment, the first adhesive sub-layer 221 and the second adhesive sub-layer 222 have the same composition, which can be achieved by selectively etching a continuous adhesive layer (not shown) located on the upper surface 50a'. In this embodiment, when D111 = D111' = D222, the pitch between adjacent light-emitting diode elements within the same light-emitting diode element region is equal to the pitch between adjacent light-emitting diode elements in different light-emitting diode element regions; when D111 = D111' > D222, the pitch between adjacent light-emitting diode elements within the same light-emitting diode element region is greater than the pitch between adjacent light-emitting diode elements in different light-emitting diode element regions; when D111 = D111' < D222, the pitch between adjacent light-emitting diode elements within the same light-emitting diode element region is less than the pitch between adjacent light-emitting diode elements in different light-emitting diode element regions.

[0084] Reference Figure 5B , the entire light-emitting diode element carrier structure 500 is flipped and then placed on the transfer carrier substrate 60. In the light-emitting diode element region Q1 of the light-emitting diode element carrier structure 500, the adhesive layer 221 is irradiated and etched by the laser beam L and decomposed, and thus a plurality of light-emitting diode elements 1 are detached from the carrier substrate 50 and then adhered to a continuous transfer adhesive layer 150 of the temporary carrier substrate 60. Through the same area transfer manufacturing process, a plurality of light-emitting diode elements 1 on another light-emitting diode element region Q2 can be successively transferred to a continuous transfer adhesive layer 150 of the temporary carrier substrate 60. In one embodiment, the substrate 50 of the light-emitting diode element region Q1 and the light-emitting diode element region Q2 can be two separate sub-substrates (not shown).

[0085] Reference Figure 5C, after removing the substrate 50, a light-emitting diode element carrier structure 600 is formed. It should be noted that during the regional laser transfer, since one side of the light-emitting diode element 1 is adhered to the substrate 50 (the first sub-adhesive layer 221 and the second sub-adhesive layer 222), and the other side is adhered to the transfer substrate 60 (the transfer adhesive layer 150), the spacing between the transferred light-emitting diode elements 1 will be the same as that of the original light-emitting diode element carrier structure 500. That is to say, the light-emitting diode element carrier structure 600 includes a carrier plate 60, and a continuous adhesive layer 150 is continuously located within the virtual light-emitting diode element regions Q1' and Q2' on the upper surface 60a of the carrier plate 60. Within the light-emitting diode element region Q1', a plurality of light-emitting diode elements 1 are arranged on the continuous adhesive layer 150 at a fixed spacing D111 respectively; within the light-emitting diode element region Q2', a plurality of light-emitting diode elements 1 are arranged on the continuous adhesive layer 150 at a fixed spacing D111' respectively; and between the light-emitting diode element regions Q1 and Q2, the spacing between adjacent light-emitting diode elements 1 is D222. In one embodiment, D111 may also not be equal to D111'.

[0086] According to an embodiment of the present invention, the regional laser transfer manufacturing process can be carried out through light-emitting diode element wafers and light-emitting diode element carrier structures with different configurations, and the distribution morphology of a plurality of light-emitting diode elements within (1) a single light-emitting diode element region, (2) the spacing between adjacent light-emitting diode elements within a single light-emitting diode element region, and (3) the spacing between adjacent light-emitting diode elements in different light-emitting diode element regions in different light-emitting diode element carrier structures can be adjusted.

[0087] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A semiconductor device arrangement structure, comprising: a carrier having an upper surface; an adhesive layer disposed on the upper surface; A plurality of first semiconductor elements are located on a first semiconductor element region of the adhesive layer; and A plurality of second semiconductor elements are located on the second semiconductor element region of the adhesive layer; in, The first semiconductor device region is adjacent to the second semiconductor device region; Any two adjacent first semiconductor elements among the plurality of first semiconductor elements have a first spacing, any two adjacent first semiconductor elements and second semiconductor elements among the plurality of first semiconductor elements and the plurality of second semiconductor elements have a second spacing, and the first spacing is greater than the second spacing.

2. The semiconductor device arrangement structure according to claim 1, wherein: The intervals between the plurality of first semiconductor elements are enlarged outward from the center of the first semiconductor element region.

3. The semiconductor device arrangement structure according to claim 1, wherein: The intervals between the plurality of first semiconductor elements decrease from the center of the first semiconductor element region outwards.

4. The semiconductor device arrangement structure according to claim 1, wherein: The semiconductor devices in the first semiconductor device region and the second semiconductor device region have the same distribution morphology.

5. The semiconductor device arrangement structure according to claim 1, wherein: The adhesive layer is a continuous layer.

6. The semiconductor device arrangement structure according to claim 1, wherein: The adhesive layer further includes a first adhesive sublayer and a second adhesive sublayer. The first semiconductor element region is located on the first adhesive sublayer, the second semiconductor element region is located on the second adhesive sublayer, and the first adhesive sublayer and the second adhesive sublayer are separated from each other.

7. The semiconductor device arrangement structure according to claim 1, wherein: The distance between any two adjacent first semiconductor elements is equal to the distance between any two adjacent second semiconductor elements.

8. The semiconductor device arrangement structure according to claim 6, wherein: The first adhesive sub-layer and the second adhesive sub-layer have the same composition.

9. The semiconductor device arrangement structure according to claim 1, wherein: The carrier includes a glass substrate, a sapphire substrate, or a quartz substrate.

10. The semiconductor device arrangement structure according to claim 1, wherein: The second interval is 1 μm to 50 μm.

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