Core grouping in processor

Abstract

In an embodiment, a processor includes a plurality of cores and a control circuit. The control circuitry is to: detect a selection of a deep sleep mode into which a first core of the processor is to enter; in response to detecting the selection of the deep sleep mode, determining whether a total number of cores in a light sleep state is less than a lowest level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the lowest level of the light sleep group, causing the first core to enter the light sleep mode rather than the selected deep sleep mode. Other embodiments are described and claimed.

Description

Technical Field

[0001] Generally, embodiments relate to computer processors. More specifically, embodiments relate to power management in computer processors. Background Art

[0002] Advances in semiconductor processing and logic design have allowed an increase in the amount of logic that may be present on an integrated circuit device. As a result, computer system configurations have evolved from single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and / or complete systems on individual integrated circuits. Additionally, as the density of integrated circuits has increased, the power requirements of computing systems have also increased. As a result, there is a necessary need for energy efficiency and conservation associated with integrated circuits. Brief Description of the Drawings

[0003] Figure 1 is a schematic diagram of an exemplary computing system in accordance with one or more embodiments.

[0004] Figure 2 is a schematic diagram of an exemplary processor having (one or more) cores in accordance with one or more embodiments.

[0005] Figures 3A - 3B is a schematic diagram of an exemplary core architecture in accordance with one or more embodiments.

[0006] Figure 4 is a schematic diagram of an exemplary (one or more) execution unit circuits in accordance with one or more embodiments.

[0007] Figure 5 is a schematic diagram of an exemplary register architecture in accordance with one or more embodiments.

[0008] Figures 6A - 6B is a schematic diagram of an exemplary system in accordance with one or more embodiments.

[0009] Figures 7A - 7B is a schematic diagram of an exemplary core group in accordance with one or more embodiments.

[0010] Figure 8 is a flowchart of an exemplary method in accordance with one or more embodiments.

[0011] Figure 9 is a flowchart of an exemplary method in accordance with one or more embodiments.

[0012] Figure 10 is a schematic diagram of an exemplary software component in accordance with one or more embodiments.

[0013] Figure 11 is a flowchart of an exemplary method in accordance with one or more embodiments.

[0014] Figure 12 Schematic diagram of an exemplary storage medium according to one or more embodiments. Detailed implementation

[0015] Some computer processors may include multiple processing engines or "cores". A core may be capable of operating in one of multiple power or sleep modes. For example, a core may operate in a light sleep mode that provides a relatively high level of functionality but a relatively low level of energy savings. Additionally, a core may operate in a deep sleep mode that provides a relatively low level of functionality but a relatively high level of energy savings. However, the deep sleep mode may require a relatively long latency to restore full functionality (e.g., compared to the light sleep mode). Additionally, in some examples, such a relatively long latency may significantly affect the performance of the processor. Thus, some users may disable the deep sleep mode of the processor to prevent the negative impacts associated with that latency. Therefore, in such examples, the energy consumption of the processor may not be reduced by using the deep sleep state.

[0016] According to one or more embodiments described herein, a processor may group the cores of the processor according to their respective operating modes. For example, cores may be assigned to an active group, a light sleep group, and a deep sleep group. The processor may manage the core groups to attempt to maintain a minimum number of cores in the light sleep mode and maintain at least some cores in the deep sleep group. In this way, the core grouping functionality may reduce the latency of activating cores, while the cores using the deep sleep mode still provide at least some energy savings. Thus, some embodiments may improve the performance and / or energy efficiency of the processor. Details of various embodiments are further described below with reference to Figures 6A - 12 Details of some embodiments are further described below. Additionally, details of an exemplary system and architecture are described below with reference to Figures 1 - 5 An exemplary system and architecture are described.

[0017] Exemplary system and architecture

[0018] Figure 1 —Exemplary computing system

[0019] Figure 1An exemplary computing system is shown. The multiprocessor system 100 is an interface system and includes multiple processors, which include a first processor 170 and a second processor 180 coupled via an interface 150 (e.g., a point-to-point (P-P) interconnect, fabric, and / or bus). In some examples, the first processor 170 and the second processor 180 are homogeneous. In some examples, the first processor 170 and the second processor 180 are heterogeneous. Although the exemplary system 100 is shown as having two processors, the system can have three or more processors, or can be a single-processor system. In some examples, the computing system is implemented in whole or in part using a system-on-chip (SoC) or a multi-chip (or multi-die) module in the same or different package combinations.

[0020] Processors 170 and 180 are shown as including integrated memory controller (IMC) circuits 172 and 182, respectively. Processor 170 also includes interface circuits 176 and 178 and a core set. Similarly, the second processor 180 includes interface circuits 186 and 188 and a core set. The core set generally refers to one or more computing cores, which may or may not be grouped into different clusters, hierarchical groups, or groups of a common core type. The cores can be configured differently to perform different functions and / or instructions at different performance and / or power levels. The processor may also include other blocks, such as memory and other processing unit engines.

[0021] Processors 170, 180 can exchange information via interface circuits 178, 188 using interface 150. IMCs 172 and 182 couple processors 170, 180 to respective memories, namely memory 132 and memory 134, which can be portions of the main memory locally attached to the respective processors.

[0022] Processors 170, 180 can each exchange information with a network interface (NW I / F) 190 via interface circuits 176, 194, 186, 198 using separate interfaces 152, 154. The network interface 190 (e.g., one or more of an interconnect, bus, and / or fabric, and in some examples is a chipset) can optionally exchange information with a coprocessor 138 via an interface circuit 192. In some examples, the coprocessor 138 is a dedicated processor, such as a high-throughput processor, a network or communication processor, a compression engine, a graphics processor, a general-purpose graphics processing unit (GPGPU), a neural network processing unit (NPU), an embedded processor, etc.

[0023] A shared cache (not shown) may be included in either processor 170, 180 or outside both processors, but is connected to the processors via an interface such as a P-P interconnect so that if a processor is in a low power mode, local cache information of either or both processors can be stored in the shared cache.

[0024] Network interface 190 may be coupled to first interface 116 via interface circuit 196. In some examples, first interface 116 may be an interface such as a Peripheral Component Interconnect (PCI) interconnect, a PCI Express interconnect, or another I / O interconnect. In some examples, first interface 116 is coupled to a Power Control Unit (PCU) 117, which may include circuitry, software, and / or firmware for performing power management operations regarding processors 170, 180, and / or coprocessor 138. PCU 117 provides control information to one or more voltage regulators (not shown) to cause the (one or more) voltage regulators to generate appropriate (one or more) regulated voltages. PCU 117 also provides control information to control the generated operating voltages. In various examples, PCU 117 may include various power management logic units (circuits) to perform hardware-based power management. Such power management may be entirely processor-controlled (e.g., controlled by various processor hardware and may be triggered by workload and / or power, thermal, or other processor constraints), and / or power management may be performed in response to an external source (e.g., a platform or power management source or system software).

[0025] PCU 117 is shown as existing as a logic unit separate from processors 170 and / or processor 180. In other cases, PCU 117 may execute on a given one or more cores in the cores (not shown) of processor 170 or 180. In some cases, PCU 117 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic unit configured to execute its own dedicated power management code (sometimes referred to as P-code). In other examples, the power management operations to be performed by PCU 117 may be implemented external to the processor, such as by a separate Power Management Integrated Circuit (PMIC) or another component external to the processor. In other examples, the power management operations to be performed by PCU 117 may be implemented within the BIOS or other system software. Along this line, power management may be performed in conjunction with other power control units that are autonomously or semi-autonomously implemented (e.g., as execution software in a controller or core, cluster, IP block, and / or other parts of the system).

[0026] Various I / O devices 114 may be coupled to the first interface 116 and a bus bridge 118 that couples the first interface 116 to the second interface 120. In some examples, one or more additional processors 115 (such as a coprocessor, a high throughput many integrated core (MIC) processor, a GPGPU, an accelerator (such as a graphics accelerator or a digital signal processing (DSP) unit), a field programmable gate array (FPGA), or any other processor) are coupled to the first interface 116. In some examples, the second interface 120 may be a low pin count (LPC) interface. Various devices may be coupled to the second interface 120, including, for example, a keyboard and / or mouse 122, a communication device 127, and a storage circuit 128. The storage circuit 128 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device (which may include instructions / code and data 130 in some examples and may implement storage ISAB03). Additionally, audio I / O 124 may be coupled to the second interface 120. Note that other architectures besides the point-to-point architecture described above are possible. For example, a system such as the multiprocessor system 100 may implement a multi-point interface or other such architecture instead of a point-to-point architecture.

[0027] Processor cores may be implemented in different ways, for different purposes, and in different processors. For example, implementations of such cores may include: 1) a general-purpose in-order core intended for general-purpose computing; 2) a high-performance general-purpose out-of-order core intended for general-purpose computing; 3) a specialized core intended primarily for graphics and / or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU that includes one or more general-purpose in-order cores intended for general-purpose computing and / or one or more general-purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor that includes one or more specialized cores intended primarily for graphics and / or scientific (throughput) computing. Such different processors result in different computer system architectures, which may include: 1) a coprocessor on a chip separate from the CPU; 2) a coprocessor on a separate die within the same package as the CPU; 3) a coprocessor on the same die as the CPU (in which case such a coprocessor is sometimes referred to as a dedicated logic unit, such as an integrated graphics and / or scientific (throughput) logic unit, or as a specialized core); and 4) a system-on-a-chip (SoC) that may include the CPU described above (sometimes referred to as the (one or more) application core or (one or more) application processor), the coprocessor described above, and additional functionality on the same die. Exemplary core architectures are described next, followed by exemplary processor and computer architectures.

[0028] Figure 2 —Exemplary processor with (one or more) cores

[0029] Figure 2 A block diagram of an exemplary processor and / or SoC 200 that may have one or more cores and an integrated memory controller is shown. The solid-line boxes show processor 200, which has a single core 202(A), a system agent unit circuit 210, and a group of one or more interface controller unit circuits 216, while the optionally added dashed-line boxes show an alternative processor 200, which has multiple cores 202(A)-(N), a group of one or more integrated memory controller unit circuits 214 in the system agent unit circuit 210, a dedicated logic unit 208, and a group of one or more interface controller unit circuits 216. Note that processor 200 can be Figure 1 one of processors 170 or 180 or coprocessors 138 or 115 in

[0030] Accordingly, different embodiments of processor 200 can include: 1) a CPU, where the dedicated logic unit 208 is an integrated graphics and / or scientific (throughput) logic unit (which may include one or more cores, not shown), and cores 202(A)-(N) are one or more general-purpose cores (e.g., general-purpose in-order cores, general-purpose out-of-order cores, or a combination of both); 2) a coprocessor, where cores 202(A)-(N) are a large number of dedicated cores designed primarily for graphics and / or scientific (throughput); and 3) a coprocessor, where cores 202(A)-(N) are a large number of general-purpose in-order cores. Thus, processor 200 can be a general-purpose processor, a coprocessor, or a special-purpose processor, such as a network or communication processor, a compression engine, a graphics processor, a GPGPU (general-purpose graphics processing unit), a high-throughput many integrated core (MIC) coprocessor (including 30 or more cores), an embedded processor, etc. The processor can be implemented on one or more chips. Processor 200 can be part of one or more substrates and / or can be implemented on one or more substrates using any of a variety of process technologies, such as complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).

[0031] The memory hierarchy includes one or more levels of cache unit circuits 204(A)-(N) within cores 202(A)-(N), a group of one or more shared cache unit circuits 206, and an external memory (not shown) coupled to the group of integrated memory controller unit circuits 214. The group of one or more shared cache unit circuits 206 can include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache (e.g., last-level cache (LLC) and / or combinations thereof). Although in some examples, interface network circuit 212 (e.g., a ring interconnect) interfaces with dedicated logic unit 208 (e.g., integrated graphics logic unit), the group of shared cache unit circuits 206, and system agent unit circuit 210, alternative examples use any number of well-known techniques to interface such units. In some examples, coherence is maintained between one or more of the (one or more) shared cache unit circuits 206 and cores 202(A)-(N). In some examples, interface controller unit circuit 216 couples core 202 to one or more other devices 218, such as one or more I / O devices, memory banks, one or more communication devices (e.g., wireless network, wired network, etc.), and the like.

[0032] In some examples, one or more of cores 202(A)-(N) are capable of implementing multithreading. System agent unit circuit 210 includes those components that coordinate and operate cores 202(A)-(N). System agent unit circuit 210 can include, for example, a power control unit (PCU) circuit and / or a display unit circuit (not shown). The PCU can be or can include the logic units and components required to regulate the power states of cores 202(A)-(N) and / or dedicated logic unit 208 (e.g., integrated graphics logic unit). The display unit circuit is used to drive one or more externally connected displays.

[0033] Cores 202(A)-(N) can be homogeneous in terms of instruction set architecture (ISA). Alternatively, cores 202(A)-(N) can be heterogeneous in terms of ISA, i.e., a subset of cores 202(A)-(N) may be capable of executing the ISA, while other cores may be capable of executing only a subset of the ISA or another ISA.

[0034] Figures 3A - 3B — Exemplary core architecture

[0035] Figure 3A is a block diagram showing both an exemplary in-order pipeline and an out-of-order issue / execution pipeline with exemplary register renaming, according to an example. Figure 3Bis a block diagram showing both an exemplary in-order architecture core to be included in a processor and an exemplary out-of-order issue / execution architecture core with register renaming. Figures 3A - 3B The solid boxes in [ ] show the in-order pipeline and in-order core, while the optional added dashed boxes show the out-of-order issue / execution pipeline and core with register renaming. Assuming the in-order aspect is a subset of the out-of-order aspect, the out-of-order aspect will be described.

[0036] In Figure 3A , the processor pipeline 300 includes a fetch stage 302, an optional length decoding stage 304, a decode stage 306, an optional allocation (Alloc) stage 308, an optional rename stage 310, a schedule (also referred to as dispatch or issue) stage 312, an optional register read / memory read stage 314, an execution stage 316, a write-back / memory write stage 318, an optional exception handling stage 322, and an optional commit stage 324. One or more operations may be performed in each of these processor pipeline stages. For example, during the fetch stage 302, one or more instructions are fetched from the instruction memory, and during the decode stage 306, one or more of the fetched instructions may be decoded, an address using a forwarding register port (e.g., a load store unit (LSU) address) may be generated, and branch forwarding (e.g., immediate offset or link register (LR)) may be performed. In one example, the decode stage 306 and the register read / memory read stage 314 may be combined into one pipeline stage. In one example, during the execution stage 316, the decoded instructions may be executed, LSU address / data pipelining to an advanced microcontroller bus (AMB) interface may be performed, multiplication and addition operations may be performed, arithmetic operations with branch results may be performed, etc.

[0037] By way of example, Figure 3BThe out-of-order issue / execution architecture core with exemplary register renaming can implement pipeline 300 in the following manner: 1) The instruction fetch circuit 338 performs the fetch stage 302 and the length decoding stage 304; 2) The decoding circuit 340 performs the decoding stage 306; 3) The rename / allocator unit circuit 352 performs the allocation stage 308 and the rename stage 310; 4) The (one or more) scheduler circuits 356 perform the scheduling stage 312; 5) The (one or more) physical register file circuits 358 and the memory unit circuit 370 perform the register read / memory read stage 314; The (one or more) execution clusters 360 perform the execution stage 316; 6) The memory unit circuit 370 and the (one or more) physical register file circuits 358 perform the write-back / memory write stage 318; 7) Various circuits may be involved in the exception handling stage 322; and 8) The retirement unit circuit 354 and the (one or more) physical register file circuits 358 perform the commit stage 324.

[0038] Figure 3B A processor core 390 is shown, which includes a front-end unit circuit 330 coupled to an execution engine unit circuit 350, and both are coupled to a memory unit circuit 370. The core 390 can be a reduced instruction set architecture computing (RISC) core, a complex instruction set architecture computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type. As another option, the core 390 can be a dedicated core, such as a network or communication core, a compression engine, a coprocessor core, a general-purpose computing graphics processing unit (GPGPU) core, a graphics core, etc.

[0039] The front-end unit circuit 330 may include a branch prediction circuit 332 coupled to an instruction cache circuit 334, the instruction cache circuit 334 being coupled to an instruction translation lookaside buffer (TLB) 336, the instruction translation lookaside buffer 336 being coupled to an instruction fetch circuit 338, and the instruction fetch circuit 338 being coupled to a decode circuit 340. In one example, the instruction cache circuit 334 is included in the memory unit circuit 370 rather than the front-end circuit 330. The decode circuit 340 (or decoder) may decode instructions and generate one or more micro-operations, microcode entry points, microinstructions, other instructions, or other control signals (which are decoded from the original instructions, or otherwise reflect the original instructions, or are derived from the original instructions) as output. The decode circuit 340 may also include an address generation unit (AGU, not shown) circuit. In one example, the AGU generates LSU addresses using forwarded register ports and may further perform branch forwarding (e.g., immediate offset branch forwarding, LR register branch forwarding, etc.). The decode circuit 340 may be implemented using a variety of different mechanisms. Examples of suitable mechanisms include, but are not limited to, lookup tables, hardware implementations, programmable logic arrays (PLAs), microcode read-only memories (ROMs), etc. In one example, the core 390 includes a microcode ROM (not shown) or other medium (e.g., in the decode circuit 340 or otherwise within the front-end circuit 330) that stores microcode for certain macroinstructions. In one example, the decode unit circuit 340 includes a micro-operation (micro-op) or operation cache (not shown) to hold / cache decoded operations, microtags, or micro-operations generated during the decode or other stages of the processor pipeline 300. The decode circuit 340 may be coupled to a rename / allocator unit circuit 352 in the execution engine circuit 350.

[0040] The execution engine circuit 350 includes a rename / allocator unit circuit 352, which is coupled to a retirement unit circuit 354 and a set of one or more scheduler circuits 356. The scheduler circuits 356 represent any number of different schedulers, including reservation stations, a central instruction window, and the like. In some examples, the scheduler circuits 356 may include an arithmetic logic unit (ALU) scheduler / scheduling circuit, an ALU queue, an address generation unit (AGU) scheduler / scheduling circuit, an AGU queue, and the like. The (one or more) scheduler circuits 356 are coupled to the (one or more) physical register file circuits 358. Each of the (one or more) physical register file circuits 358 represents one or more physical register files, where different physical register files store one or more different data types, such as scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points, status (e.g., an instruction pointer that is the address of the next instruction to be executed), and the like. In one example, the (one or more) physical register file circuits 358 include a vector register unit circuit, a write mask register unit circuit, and a scalar register unit circuit. These register units may provide architectural vector registers, vector mask registers, general-purpose registers, and the like. The (one or more) physical register file circuits 358 are coupled to the retirement unit circuit 354 (also referred to as a retirement queue) to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using the (one or more) reorder buffers (ROBs) and the (one or more) retirement register files; using the (one or more) future files, the (one or more) history buffers, and the (one or more) retirement register files; using register mapping and register pools; and so on). The (one or more) execution clusters 360 include a set of one or more execution unit circuits 362 and a set of one or more memory access circuits 364. The execution unit circuits 362 may perform various arithmetic, logical, floating-point, or other types of operations (e.g., shifts, additions, subtractions, multiplications) on various types of data (e.g., scalar integers, scalar floating points, packed integers, packed floating points, vector integers, vector floating points). While some examples may include multiple execution units or execution unit circuits dedicated to a particular function or set of functions, other examples may include only one execution unit circuit or multiple execution units / execution unit circuits that perform all functions.(One or more) scheduler circuits 356, (one or more) physical register file circuits 358, and (one or more) execution clusters 360 are shown as potentially being multiple because some examples create separate pipelines for certain types of data / operations (e.g., scalar integer pipelines, scalar floating point / tight integer / tight floating point / vector integer / vector floating point pipelines, and / or memory access pipelines, each having its own scheduler circuit, (one or more) physical register file circuits, and / or execution cluster, and in the case of a separate memory access pipeline, in some examples only the execution cluster of that pipeline has (one or more) memory access unit circuits 364. It should also be understood that in cases where separate pipelines are used, one or more of these pipelines may be out-of-order issue / execution while the remaining pipelines are in-order.

[0041] In some examples, the execution engine unit circuit 350 may perform load / store unit (LSU) address / data pipelining to an advanced microcontroller bus (AMB) interface (not shown), as well as address phase and write-back, data phase load, store, and branch.

[0042] A set of memory access circuits 364 is coupled to a memory unit circuit 370, which includes a data TLB circuit 372 coupled to a data cache circuit 374, and the data cache circuit 374 is coupled to a level 2 (L2) cache circuit 376. In one example, the memory access circuit 364 may include a load unit circuit, a store address unit circuit, and a store data unit circuit, each of which is coupled to the data TLB circuit 372 in the memory unit circuit 370. An instruction cache circuit 334 is also coupled to the level 2 (L2) cache circuit 376 in the memory unit circuit 370. In one example, the instruction cache 334 and the data cache 374 are combined into a single instruction and data cache (not shown) in the L2 cache circuit 376, a level 3 (L3) cache circuit (not shown), and / or main memory. The L2 cache circuit 376 is coupled to one or more other levels of cache and ultimately to main memory.

[0043] The core 390 may support one or more instruction sets (e.g., x86 instruction set architecture (optionally with some extensions added with newer versions); MIPS instruction set architecture; ARM instruction set architecture (optionally with optional additional extensions such as NEON)), which include the instructions described herein. In one example, the core 390 includes logic for supporting a packed data instruction set architecture extension (e.g., AVX1, AVX2), thereby allowing operations used by many multimedia applications to be performed using packed data.

[0044] Figure 4 — Exemplary execution unit circuit(s)

[0045] Figure 4 illustrates an example of an execution unit circuit(s), such as Figure 3B the execution unit circuit(s) 362 in . As shown, the execution unit circuit 362 may include one or more ALU circuits 401, an optional vector / single instruction multiple data (SIMD) circuit 403, a load / store circuit 405, a branch / jump circuit 407, and / or a floating point unit (FPU) circuit 409. The ALU circuit 401 performs integer arithmetic and / or Boolean operations. The vector / SIMD circuit 403 performs vector / SIMD operations on packed data (e.g., SIMD / vector registers). The load / store circuit 405 performs load and store instructions to load data from memory into registers or store data from registers to memory. The load / store circuit 405 may also generate addresses. The branch / jump circuit 407 depends on the instruction to cause a branch or jump to a memory address. The FPU circuit 409 performs floating point arithmetic. The width of the execution unit circuit(s) 362 varies depending on the example and may be, for example, in the range from 16 bits to 1024 bits. In some examples, two or more smaller execution units are logically combined to form a larger execution unit (e.g., two 128-bit execution units are logically combined to form a 256-bit execution unit).

[0046] Figure 5 — Exemplary register architecture

[0047] Figure 5 is a block diagram of a register architecture 500 according to some examples. As shown, the register architecture 500 includes vector / SIMD registers 510 that vary in width from 128 bits to 1024 bits. In some examples, the vector / SIMD registers 510 are physically 512 bits and only some of the lower bits are used depending on the mapping. For example, in some examples, the vector / SIMD registers 510 are 512-bit ZMM registers: the lower 256 bits are used for YMM registers and the lower 128 bits are used for XMM registers. Thus, there is register coverage. In some examples, the vector length field selects between a maximum length and one or more other shorter lengths, where each such shorter length is half the length of the previous length. Scalar operations are operations performed on the lowest order data element positions in the ZMM / YMM / XMM registers; the higher order data element positions are either held the same as they were before the instruction or are zeroed, depending on the example.

[0048] In some examples, the register architecture 500 includes write mask / predicate registers 515. For example, in some examples, there are 8 write mask / predicate registers (sometimes referred to as k0 through k7), each register being 16 bits, 32 bits, 64 bits, or 128 bits in size. The write mask / predicate registers 515 can allow merging (e.g., allow any set of elements in the destination to be protected from update during the execution of any operation) and / or zeroing (e.g., a zeroing vector mask allows any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given write mask / predicate register 515 corresponds to a data element position in the destination. In other examples, the write mask / predicate registers 515 are scalable and consist of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).

[0049] The register architecture 500 includes a plurality of general-purpose registers 525. These registers can be 16 bits, 32 bits, 64 bits, etc., and can be used for scalar operations. In some examples, these registers are referred to by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.

[0050] In some examples, the register architecture 500 includes a scalar floating-point (FP) register file 545, which is used for scalar floating-point operations on 32 / 64 / 80-bit floating-point data using the x87 instruction set architecture extensions, or as MMX registers to perform operations on 64-bit packed integer data, and to save operands for some operations performed between MMX and XMM registers.

[0051] One or more flag registers 540 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, comparison, and system operations. For example, one or more flag registers 540 can store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, one or more flag registers 540 are referred to as program status and control registers.

[0052] The segment registers 520 include segment points for accessing memory. In some examples, these registers are referred to by the names CS, DS, SS, ES, FS, and GS.

[0053] Machine-specific registers (MSRs) 535 control and report processor performance. Most MSRs 535 handle system-related functions and are not accessible to applications. Machine check registers 560 consist of control, status, and error-reporting MSRs for detecting and reporting hardware errors.

[0054] One or more instruction pointer registers 530 store instruction pointer values. One or more control registers 555 (e.g., CR0 - CR4) determine the operating mode of the processor (e.g., processors 170, 180, 138, 115, and / or 200) and the characteristics of the currently executing task. Debug registers 550 control and allow monitoring of the debug operations of the processor or core.

[0055] Memory (mem) management registers 565 specify the locations of data structures used in protected mode memory management. These registers can include Global Descriptor Table Register (GDTR), Interrupt Descriptor Table Register (IDTR), Task Register, and Local Descriptor Table Register (LDTR) registers.

[0056] Alternative examples can use wider or narrower registers. Additionally, alternative examples can use more, fewer, or different register banks and registers. Register architecture 500 can be used, for example, in a register bank / memory or one or more physical register bank circuits 358 ( Figure 3B as shown in).

[0057] Core grouping in a processor

[0058] Figures 6A - 6B —Exemplary computing system

[0059] Figure 6A FIG. shows a block diagram of an exemplary computing system 600 in accordance with one or more embodiments. In some embodiments, computing system 600 can be all or a part of a computing device. For example, computing system 600 can be a cellular phone, a computer, a server, a network device, a System on Chip (SoC), a controller, a distributed system, etc.

[0060] As Figure 6A shown, computing system 600 can include a processor 610, a memory 620, a storage 630, and a power supply 640. Additionally, although not shown in Figure 6A , computing system 600 can include other components. Power supply 640 can supply power to other components (e.g., processor 610, memory 620, storage 630).

[0061] In one or more embodiments, memory 620 can be implemented using any type of computer memory (e.g., Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Non - Volatile Memory (NVM), a combination of DRAM and NVM, etc.). Storage 630 can store system software 660 (e.g., an operating system, drivers, power management code, etc.).

[0062] In one or more embodiments, the processor 610 may be a hardware processing device (e.g., a central processing unit (CPU), a system-on-chip (SoC), etc.). As shown, the processor 610 may include any number of cores 650A - 650N (also referred to herein as "cores 650" or "processing engines 650"). In some embodiments, the cores 650 may include various types of processing engines and / or other computing resources (e.g., (one or more) graphics processing engines, math processing engines, cryptographic processing engines, network processing engines, memory devices, network devices, storage devices, bus devices, etc.). Additionally, in some embodiments, the cores 650 may include general-purpose hardware processing engines.

[0063] In some embodiments, the core 650 may be capable of operating in one of a plurality of sleep modes. Each sleep mode may correspond to a particular combination of reduced functionality and / or power consumption levels compared to the "awake" or active operating mode. For example, in some embodiments, the core 650 may operate in a "shallow" sleep mode, which means the sleep mode has a relatively low level of energy savings, but it maintains a relatively high level of functionality or may require a relatively short time to resume full functionality. Additionally, the core 650 may operate in a "deep" sleep mode, which means the sleep mode has a relatively high level of energy savings, but maintains a relatively low level of functionality or may require a relatively long time to resume full functionality. Further, in some embodiments, the core 650 may operate in other sleep modes that have functionality and / or energy savings levels that are between those of the shallow and deep sleep modes (e.g., "medium" sleep mode, "medium - shallow" sleep mode, "medium - deep" sleep mode, etc.). In some embodiments, the power states of the core 650 may conform to the Advanced Configuration and Power Interface (ACPI) standard (e.g., version 3.0b released on October 10, 2006). For example, the operating mode of the core 650 may be the C0 state, the shallow sleep mode of the core 650 may be the C1 state, and the deep sleep mode of the core 650 may be a state deeper than the C1 state (e.g., C1E, C6, etc.).

[0064] In one or more embodiments, the system software 660 may include core grouping instructions 670 and a core state structure 675. The core grouping instructions 670 may control the operating modes of the cores 650 (e.g., active mode, shallow sleep mode, deep sleep mode, etc.). Additionally, the core grouping instructions 670 may group the cores 650 according to their respective operating modes and may store these assignments in the core state structure 675. For example, the core grouping instructions 670 may assign the cores 650 among an active group, a shallow sleep group, and a deep sleep group. Some exemplary embodiments of such core groups are discussed below with reference to Figures 7A - 7B Discuss some exemplary embodiments of such core groups.

[0065] In one or more embodiments, the core grouping instruction 670 may allocate cores 650, may manage the core groups to attempt to maintain a minimum number of cores in the shallow sleep mode, and maintain cores in at least some of the deep sleep groups. In this way, the core grouping instruction 670 may reduce the latency of activating cores 650, while the cores 650 using the deep sleep mode still provide at least some power savings. Thus, the core grouping instruction 670 may improve the performance and / or energy efficiency of the processor 610.

[0066] In some embodiments, the core state structure 675 may be a data structure for storing information about the cores 650 and their assigned mode groups. For example, the core state structure 675 may be a table including a plurality of table entries, where each table entry includes an identifier of a different core 650 and an identifier of one of the active group, the shallow sleep group, and the deep sleep group. In other embodiments, the core state structure 675 may be implemented as a bit array, where the bit positions identify the cores 650, and the bit values indicate the corresponding operating modes of each core 650. Other implementations are possible.

[0067] In some embodiments, the core grouping instruction 670 may detect a request for a new active core 650 (e.g., to execute an upcoming processing load), and in response, may cause a particular core 650 in the shallow sleep mode to transition to the active mode. The core grouping instruction 670 may also transfer the particular core 650 from the shallow sleep group to the active group, and may update the core state structure 675 to indicate the transfer.

[0068] In some embodiments, the core grouping instruction 670 may determine whether the number of cores 650 in the shallow sleep group is less than a minimum level. If so, the core grouping instruction 670 may transfer one or more cores from the deep sleep group to the shallow sleep group, such that the number of cores 650 in the shallow sleep group meets or exceeds the minimum level. Additionally, the core grouping instruction 670 may update the core state structure 675 to indicate the transfer. As used herein, the term "shallow group count" may refer to the total number of cores 650 currently assigned to the shallow sleep group.

[0069] In some embodiments, the core grouping instruction 670 may detect that the active core 650 is idle (e.g., after finishing processing a load), and in response, may cause the active core 650 to transition to a shallow sleep mode. The core grouping instruction 670 may also transfer the active core 650 from the active group to the shallow sleep group, and may update the core state structure 675 to indicate the transfer. Alternatively, in some examples, the core grouping instruction 670 may cause the active core 650 to transition to a deep sleep mode, and may transfer the active core 650 to the deep sleep group. The following refers to Figures 8 - 11 discuss some exemplary core grouping methods.

[0070] Note that although Figure 6A illustrates an exemplary embodiment in which the core grouping functionality is implemented as the instruction 670, the embodiments are not limited thereto. For example, now referring to Figure 6B , an exemplary computing system 605 is illustrated, in which the functionality described above with reference to the core grouping instruction 670 and the core state structure 675 is alternatively implemented in the core grouping circuit 680 included in the processor 610. Additionally, although not shown in Figures 6A - 6B , it is contemplated that the above-described core grouping functionality may be implemented in other software and / or hardware of the computing systems 600, 605. Other embodiments are possible.

[0071] Figures 7A - 7B —Exemplary core group

[0072] Figure 7A illustrates a first group 700 of core groups according to one or more embodiments. In some embodiments, the first group 700 may be generated and maintained by the core grouping instruction 670 (shown in Figure 6A ), by the core grouping circuit 680 (shown in Figure 6B ).

[0073] As Figure 7A shown, the first group 700 may include an active group 710, a shallow sleep group 720, and a deep sleep group 730. Additionally, the shallow sleep group 720 may include each core 650 that is currently using the shallow sleep mode (e.g., C1 state), and the deep sleep group 730 may include each core 650 that is currently using the deep sleep mode (e.g., a sleep state deeper than C1, such as C1E, C2, C6, etc.). For example, the core state structure may be a table including a plurality of entries, where each entry includes an identifier of a different core 650 and an identifier of the group 710, 720, 730 to which it is currently assigned.

[0074] In some embodiments, the core 650 in the active group 710 can support the current workload of the processor. Subsequently, when additional workload is expected or scheduled for the processor, the core 650 (or cores 650) can be activated (i.e., transitioned to the active mode) to handle the additional workload. In some embodiments, the activated core 650 can transition from the light sleep mode to the active mode. Additionally, as Figure 7A shown, the core 650 can be transferred 740 from the light sleep group 720 to the active group 710. Further, in some examples, the activated core 650 can transition from the deep sleep mode to the active mode, and the core 650 can be directly transferred 760 from the deep sleep group 730 to the active group 710. For example, if the light sleep group 720 is currently empty, then the activated core 650 can transition from the deep sleep mode to the active mode.

[0075] In some embodiments, when the workload of the processor decreases, the number of cores 650 in the active group 710 can be correspondingly reduced. For example, the core 650 (or cores 650) can transition from the active mode to the light sleep mode, and the core 650 can be transferred 745 from the active group 710 to the light sleep group 720. Further, in some examples, the core 650 can transition from the active mode to the deep sleep mode, and the core 650 can be directly transferred 765 from the active group 710 to the deep sleep group 730. In some embodiments, if a core 650 is predicted to remain idle for a relatively long time (e.g., compared to other cores 650 of the processor), then the core 650 can be selected for transfer 765 (e.g., from the active group 710 to the deep sleep group 730). For example, the predicted idle time of the core 650 can be based on historical information regarding the past active usage (or idle) level of the core 650. Additionally, if a different core 650 is predicted to remain idle for a relatively short time, then the core 650 can be selected for transfer 745 (e.g., from the active group 710 to the light sleep group 720).

[0076] In some embodiments, if the number of cores 650 in the light sleep group 720 drops below a minimum level, at least one action can be performed to increase the number of cores 650 in the light sleep group 720 to reach or exceed the minimum level. For example, if the deep sleep group 630 is not empty, then a core 650 (or cores 650) can be transitioned from the deep sleep mode to the light sleep mode, and the core 650 can be transferred 750 from the deep sleep group 730 to the light sleep group 720. In some embodiments, the minimum level of the light sleep group 720 can be specified by configuration settings, user selection, etc. Additionally, in some embodiments, the minimum level of the light sleep group 720 can be adjusted during operation (e.g., by the core grouping instruction 670) based on system metrics or characteristics (such as the history of active / idle time for each core 650, the wait time to transition to the active mode, the proportion of idle time, etc.).

[0077] In some embodiments, if the light group count (i.e., the number of cores 650 in the light sleep group 720) exceeds a predefined fill level, at least one action can be performed to reduce the number of cores 650 in the light sleep group 720. For example, when the workload of the processor decreases, a core 650 can transition from the active mode to the light sleep mode, thereby increasing the number of cores 650 in the light sleep group 720. Additionally, if the light sleep group 720 reaches a predefined fill capacity (e.g., 80% full, 100% full, etc.), then a core 650 (or cores 650) can be transitioned from the light sleep mode to the deep sleep mode, and the core 650 can be transferred 755 from the light sleep group 720 to the deep sleep group 730. In some embodiments, the predefined fill level of the light sleep group 720 can be specified by configuration settings, user selection, etc. Additionally, in some embodiments, the predefined fill level of the light sleep group 720 can be adjusted during operation (e.g., by the core grouping instruction 670) based on system metrics or characteristics (such as the history of active / idle time for each core 650, the wait time to transition to the active mode, the proportion of idle time, etc.).

[0078] In some embodiments, the use of the light sleep group 720 and the deep sleep group 730 can provide control over the number of cores 650 in the light sleep mode and the deep sleep mode under different operating conditions. For example, some embodiments can allow multiple cores 650 to remain in the light sleep mode to reduce the wait time when the cores 650 are to be activated, while allowing at least some cores 650 to remain in the deep sleep mode to reduce the power consumption of the processor 610. In this way, some embodiments can improve the performance and / or energy efficiency of the processor 610.

[0079] Now refer to Figure 7B, showing a second set 705 of core groups according to one or more embodiments. In some embodiments, the second set 705 may be generated and maintained by core grouping instructions 670 (shown in Figure 6A ), and by core grouping circuitry 680 (shown in Figure 6B ).

[0080] As Figure 7B shown, the second set 705 may include an active group 710, a first shallow sleep group 720A, a second shallow sleep group 720B, and a deep sleep group 730. The active group 710 may include each core 650 that is currently using the active operating mode (e.g., C0 state). Additionally, the first shallow sleep group 720A may include each core 650 that is currently using the first shallow sleep mode (e.g., C1 state), and the second shallow sleep group 720B may include each core 650 that is currently using a second shallow sleep mode deeper than the first shallow sleep mode (e.g., C1E state). Further, the deep sleep group 730 may include each core 650 that is currently using the deep sleep mode (e.g., a sleep state deeper than C1E, such as C2, C6, etc.).

[0081] In some embodiments, when additional workload is expected for the processor or additional workload is scheduled for the processor, a core 650 may transition from the first shallow sleep mode to the active mode, and the core 650 may be transferred 740A from the first shallow sleep group 720A to the active group 710. Additionally, when the workload of the processor decreases, a core 650 may transition from the active mode to the first shallow sleep mode, and the core 650 may be transferred 745A from the active group 710 to the first shallow sleep group 720A.

[0082] In some embodiments, if the number of cores 650 in the first shallow sleep group 720A drops below a first minimum level, a core 650 (or cores 650) may transition from the second shallow sleep mode to the first shallow sleep mode, and the core 650 may be transferred 770 from the second shallow sleep group 720B to the first shallow sleep group 720A. Similarly, if the number of cores 650 in the second shallow sleep group 720B drops below a second minimum level, a core 650 (or cores 650) may transition from the deep sleep mode to the second shallow sleep mode, and the core 650 may be transferred 780 from the deep sleep group 730 to the second shallow sleep group 720B.

[0083] In some embodiments, if the number of cores 650 in the first light sleep group 720A exceeds a first fill level (e.g., 80% full, 100% full, etc.), the core 650 (or cores 650) can transition from the first light sleep mode to the second light sleep mode, and the core 650 can be transferred 775 from the first light sleep group 720A to the second light sleep group 720B. Similarly, if the number of cores 650 in the second light sleep group 720B exceeds a second fill level, the core 650 (or cores 650) can transition from the second light sleep mode to the deep sleep mode, and the core 650 can be transferred 785 from the second light sleep group 720B to the deep sleep group 730.

[0084] Figure 8 - Exemplary method

[0085] Figure 8 FIG. shows a flowchart of an exemplary method 800 for controlling a sleep mode according to one or more embodiments. In various embodiments, the method 800 can be executed by processing logic, which can include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. For example, the method 800 can be executed by the core grouping instructions 670 (shown in Figure 6A ), by the core grouping circuitry 680 (shown in Figure 6B ), etc. In a firmware or software embodiment, the method 800 can be implemented by computer-executable instructions stored in a non-transitory machine-readable medium (e.g., an optical, semiconductor, or magnetic storage device). The machine-readable medium can store data that, if used by at least one machine, causes at least one machine to fabricate at least one integrated circuit to execute the method. For illustrative purposes, the actions involved in the method 800 can be described below with reference to Figures 6A - 7A FIG. However, the scope of the various embodiments discussed herein is not limited thereto. Figures 6A - 7A FIG. shows an example according to one or more embodiments.

[0086] Block 810 can include detecting a first core idle. Block 820 can include selecting a sleep mode for the first core. Decision block 830 can include determining whether the selection is a light sleep mode or a deep sleep mode. If the selection is the light sleep mode, the method 800 can continue at block 840, including causing the first core to enter the light sleep mode. After block 840, the method 800 can be completed.

[0087] For example, with reference to Figure 6A and Figure 7A, the system software 660 (including the core grouping instructions 670) detects that the active core 650A has completed its assigned workload, and then sends an idle signal or message to indicate that the workload has been completed. The system software 660 receives the idle signal and then selects a sleep mode for the core 650A (e.g., based on the expected workload of the core 650A, the past usage / idle history of the core 650A, the workloads and / or states of the other cores 650, etc.). If the selected sleep mode is a light sleep mode, the system software 660 causes the core 650A to transition from the active mode (e.g., C0 state) to the selected light sleep mode (e.g., C1 state). Additionally, the core state structure 675 is updated to indicate that the core 650A has been transferred 745 from the active group 710 to the light sleep group 720.

[0088] Referring again to Figure 8 , if instead it is determined at decision block 830 that the selected mode is the deep sleep mode (e.g., C6 state), the method 800 may continue at decision block 850, including determining whether the light group count is less than a minimum level. If so ("yes"), the method 800 may continue at block 840 (as described above). Otherwise, if the light group count is not less than the minimum level ("no"), the method 800 may continue at block 860, including putting the first core into the deep sleep mode. After block 860, the method 800 may be completed.

[0089] For example, referring to Figure 6A and Figure 7A , the system software 660 (including the core grouping instructions 670) determines that the selected sleep mode is the deep sleep mode, and in response, determines whether the light group count (i.e., the number of cores 650 in the light sleep group 720) is less than a minimum level predefined for the light sleep group 720. If the light group count is less than the minimum level ("yes"), the system software 660 causes the core 650A to transition from the active mode to the light sleep mode (i.e., instead of the selected deep sleep mode), and updates the core state structure 675 to indicate that the core 650A has been transferred 745 from the active group 710 to the light sleep group 720. In other words, if the count of the light sleep group 720 is too low (e.g., below the predefined minimum level), the core 650A is not transferred to the deep sleep group 730 (per the initial selection), but is added to the light sleep group 720, and the count of the light sleep group 720 can thereby be increased to above (or close to) the minimum level. Otherwise, if the light group count is not less than the minimum level, the system software 660 causes the core 650A to transition from the active mode to the deep sleep mode (as initially selected), and updates the core state structure 675 to indicate that the core 650A has been transferred 765 from the active group 710 to the deep sleep group 730.

[0090] Figure 9 — Exemplary method

[0091] Figure 9 FIG. 900 is a flow chart showing an exemplary method for controlling a sleep mode in accordance with one or more embodiments. In various embodiments, method 900 may be executed by processing logic that may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. For example, method 900 may be executed by core group instructions 670 (shown in Figure 6A ), by core group circuitry 680 (shown in Figure 6B ), etc. In a firmware or software embodiment, method 900 may be implemented by computer-executable instructions stored on a non-transitory machine-readable medium (e.g., an optical, semiconductor, or magnetic storage device). The machine-readable medium may store data that, if used by at least one machine, causes at least one machine to fabricate at least one integrated circuit to execute the method. For purposes of illustration, the actions involved in method 900 may be described below with reference to Figures 6A - 7B showing an example in accordance with one or more embodiments. However, the scope of the various embodiments discussed herein is not limited thereto. Figures 6A - 7B Block 910 may include detecting a requirement for a new active core. Decision block 920 may include determining whether any core is currently in a shallow sleep mode. If not ("No"), then method 900 may continue at block 950, including transitioning a core from a deep sleep mode to an active mode. After block 950, method 900 may continue at block 960 (described below). However, if it is determined at decision block 920 that at least one core is currently in a shallow sleep mode ("Yes"), then method 900 may continue at block 930, including transitioning a core from a shallow sleep mode to an active mode.

[0092] For example, referring to

[0093] and Figure 6A system software 660 (including core group instructions 670) detects that the workload of processor 610 is expected to increase and thus requires or demands activation of core 650 to handle the increased workload. If at least one core 650 is currently in a shallow sleep mode (e.g., C1 state), then that core 650 transitions to an active mode (e.g., C0 state) and also transfers 740 from shallow sleep group 720 to active group 710. However, if no core 650 is in a shallow sleep mode, then core 650 transitions from a deep sleep mode to an active mode and also transfers 760 from deep sleep group 730 to active group 710. Figure 7A Referring again to

[0094] and Figure 9, after block 930, method 900 can continue at decision block 940, including determining whether the shallow group count is below a minimum level. If not ("No"), then method 900 can complete. However, if it is determined that the shallow group count is below the minimum level ("Yes"), then method 900 can continue at block 960, including transitioning one or more cores from deep sleep mode to shallow sleep mode. After block 960, method 900 can be completed.

[0095] For example, referring to Figure 6A and Figure 7A , system software 660 (including core grouping instructions 670) determines that the number of cores 650 in the shallow sleep group 720 is below a minimum level, and in response, causes at least one core 650 to transition from deep sleep mode to shallow sleep mode. Additionally, at least one core 650 is transferred 760 from the deep sleep group 730 to the shallow sleep group 720. In this way, the count of the shallow sleep group 720 can be increased to be above (or close to) the minimum level.

[0096] Figure 10 - Exemplary software component

[0097] Figure 10 FIG. 1000 shows an exemplary system of software components in accordance with one or more embodiments. System 1000 can generally correspond to an exemplary implementation of some or all of system software 660 (shown in Figure 6A ).

[0098] As Figure 10 shown, system 1000 can include a scheduler 1020 and an idle framework 1010. The scheduler 1020 can be a software module that assigns workloads or idle periods to processors (e.g., the processor 610 shown in Figure 6A ). The idle framework 1010 can be a (one or more) software component of an operating system to control the idle or sleep mode of the cores of a processor. In some embodiments, the idle framework 1010 can include logical cores 1030, a governor 1040, a platform driver 1050, and a core state structure 1060.

[0099] In some embodiments, the logical cores 1030 can be abstractions representing the cores of a processor. The governor 1040 can select a sleep mode for the logical cores 1030 (e.g., based on historical or recent execution data), and the platform driver 1050 can be a software driver (e.g., an idle driver) for controlling the sleep mode (e.g., idle state) in components of a processor. In some embodiments, the platform driver 1050 can include core grouping logic (e.g., Figure 6AThe core grouping instructions shown in [FIG.]. However, in other embodiments, the core grouping logic may be implemented in any other component of the system 1000 (e.g., in the governor 1040, in the scheduler 1020, etc.).

[0100] In some embodiments, when a core becomes idle, the governor 1040 may determine the sleep mode it should enter. If the governor 1040 selects the light sleep mode (e.g., C1 state), it causes the core to enter the light sleep mode (via the logical core 1030 and the platform driver 1050). However, if the governor 1040 selects the deep sleep mode, the platform driver 1050 may determine whether the light group count is less than the minimum level. If so, the platform driver 1050 will cause the core to enter the light sleep mode (instead of the deep sleep mode selected by the governor 1040). Otherwise, if the light group count is not less than the minimum level, the platform driver 1050 will cause the core to enter the deep sleep mode (as selected by the governor 1040). The change in the mode of the core can be updated in the core state structure 1060.

[0101] In some embodiments, when a core needs to be activated (e.g., to process an upcoming workload), the scheduler 1020 determines whether any core is currently in the light sleep mode. If so, the scheduler 1020 selects the core in the light sleep mode and causes that core to enter the active mode. Otherwise, if it is determined that no core is currently in the light sleep mode, the scheduler 1020 selects the core in the deep sleep mode and causes that core to enter the active mode. The platform driver 1050 then determines whether the light group count is below the minimum level. If so, the platform driver 1050 transitions one or more cores from the deep sleep mode to the light sleep mode. The change in the mode of the core can be updated in the core state structure 1060.

[0102] Figure 11 — Exemplary method

[0103] Figure 11 FIG. shows a flowchart of an exemplary method 1100 for controlling the sleep mode according to one or more embodiments. In various embodiments, the method 1100 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), or a combination thereof. For example, the method 1100 may be executed by the core grouping instructions 670 (shown in Figure 6A ), by the core grouping circuit 680 (in Figure 6Bbe performed, etc. In a firmware or software embodiment, method 1100 may be implemented by computer-executable instructions stored on a non-transitory machine-readable medium (such as an optical, semiconductor, or magnetic storage device). The machine-readable medium may store data that, if used by at least one machine, causes at least one machine to fabricate at least one integrated circuit to perform the method. For purposes of illustration, the actions involved in method 1100 may be described below with reference to Figures 6A - 7B to describe the actions involved in method 1100, Figures 6A - 7B illustrates an example in accordance with one or more embodiments. However, the scope of the various embodiments discussed herein is not limited thereto.

[0104] Block 1110 may include a processor detecting a selection to enter a deep sleep mode for a first core of the processor. Block 1120 may include: in response to detecting the selection to enter the deep sleep mode, the processor determining whether the total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor. Block 1130 may include: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, the processor causing the first core to enter a light sleep mode instead of the selected deep sleep mode.

[0105] For example, referring to Figure 6A and Figure 7A , system software 660 (including core grouping instructions 670) determines that core 650 has selected to enter a deep sleep mode, and in response, determines whether the light group count (i.e., the number of cores 650 in light sleep group 720) is less than a predefined minimum level for light sleep group 720. If the light group count is less than the minimum level, then system software 660 causes core 650A to transition from an active mode to a light sleep mode (i.e., instead of the selected deep sleep mode), and updates core state structure 675 to indicate that core 650A has transferred 745 from active group 710 to light sleep group 720.

[0106] Figure 12 —Exemplary storage medium

[0107] Now referring to Figure 12 , a storage medium 1200 storing executable instructions 1210 is shown. In some embodiments, storage medium 1200 may be a non-transitory machine-readable medium, such as an optical medium, semiconductor, magnetic storage device, etc. Executable instructions 1210 may be executable by a processing device to perform the Figures 8 - 11 method shown in Figures 8 - 11 In addition, at least one machine may use executable instructions 1210 to fabricate at least one integrated circuit to perform the

[0108] The following paragraphs and / or examples relate to additional embodiments.

[0109] In Example 1, the processor may include multiple cores and control circuitry. The control circuitry is configured to: detect a selection of a deep sleep mode for a first core of the processor to enter; in response to detecting the selection of the deep sleep mode, determine whether the total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter a light sleep mode instead of the selected deep sleep mode.

[0110] In Example 2, the subject matter of Example 1 may optionally include: control circuitry configured to: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update a core state structure to indicate that the first core has been transferred from an active group to the light sleep group.

[0111] In Example 3, the subject matter of Examples 1-2 may optionally include: a core state structure configured to identify an allocation of multiple cores to multiple groups, and the multiple groups include an active group, a light sleep group, and a deep sleep group.

[0112] In Example 4, the subject matter of Examples 1-3 may optionally include: control circuitry configured to in response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group, cause the first core to enter the selected deep sleep mode.

[0113] In Example 5, the subject matter of Examples 1-4 may optionally include: control circuitry configured to: detect a selection of a light sleep mode for a second core of the processor to enter; and in response to detecting the selection of the light sleep mode, cause the second core to enter the light sleep mode.

[0114] In Example 6, the subject matter of Examples 1-5 may optionally include: control circuitry configured to: detect a request for a new active core; in response to detecting the request, determine whether any core is currently in the light sleep mode; and in response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to the active mode.

[0115] In Example 7, the subject matter of Examples 1-6 may optionally include: control circuitry configured to: after causing the third core to transition from the light sleep mode to the active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

[0116] In Example 8, the subject matter of Examples 1-7 may optionally include: control circuitry configured to: in response to determining that no core is currently in the light sleep mode, cause a fourth core to transition from the deep sleep mode to the active mode.

[0117] In Example 9, a method may include: detecting, by a processor including a plurality of cores, a selection for a first core of the processor to enter a deep sleep mode; in response to detecting the selection for the deep sleep mode, determining, by the processor, whether a total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, causing, by the processor, the first core to enter a light sleep mode instead of the selected deep sleep mode.

[0118] In Example 10, the subject matter of Example 9 may optionally include: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, updating a core state structure to indicate that the first core is transferred from an active group to the light sleep group.

[0119] In Example 11, the subject matter of Examples 9-10 may optionally include: a core state structure for identifying an allocation of a plurality of cores to a plurality of groups, and the plurality of groups including an active group, a light sleep group, and a deep sleep group.

[0120] In Example 12, the subject matter of Examples 9-11 may optionally include: in response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group, causing the first core to enter the selected deep sleep mode.

[0121] In Example 13, the subject matter of Examples 9-12 may optionally include: detecting a selection for a second core of the processor to enter a light sleep mode; and in response to detecting the selection for the light sleep mode, causing the second core to enter the light sleep mode.

[0122] In Example 14, the subject matter of Examples 9-13 may optionally include: detecting a requirement for a new active core; in response to detecting the requirement, determining whether any core is currently in the light sleep mode; and in response to determining that a third core is currently in the light sleep mode, causing the third core to transition from the light sleep mode to the active mode.

[0123] In Example 15, the subject matter of Examples 9-14 may optionally include: after causing the third core to transition from the light sleep mode to the active mode, determining whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, causing at least one core to transition from the deep sleep mode to the light sleep mode.

[0124] In Example 16, a computing device may include: one or more processors; and a memory storing a plurality of instructions that, when executed by the one or more processors, cause the computing device to perform the method of any one of Examples 9 to 15.

[0125] In Example 17, at least one machine-readable medium can store data thereon, which, if used by at least one machine, causes the at least one machine to perform the method of any one of Examples 9 to 15.

[0126] In Example 18, an electronic device can include a module for performing the method of any one of Examples 9 to 15.

[0127] In Example 20, a system can include: a processor including a plurality of cores; and a memory coupled to the processor. The processor is configured to: detect a selection for a deep sleep mode that a first core of the processor is about to enter; in response to detecting the selection for the deep sleep mode, determine whether the total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter the light sleep mode instead of the selected deep sleep mode.

[0128] In Example 21, the subject matter of Example 20 can optionally include: the processor is configured to: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update a core state structure to indicate that the first core is transferred from an active group to the light sleep group.

[0129] In Example 22, the subject matter of Examples 20-21 can optionally include: a core state structure for identifying an assignment of a plurality of cores to a plurality of groups, and the plurality of groups include an active group, a light sleep group, and a deep sleep group.

[0130] In Example 23, the subject matter of Examples 20-22 can optionally include: the processor is configured to: detect a requirement for a new active core; in response to detecting the requirement, determine whether any core is currently in the light sleep mode; and in response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to the active mode.

[0131] In Example 24, the subject matter of Examples 20-23 can optionally include: the processor is configured to: after causing the third core to transition from the light sleep mode to the active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

[0132] In Example 25, a device may include: a module for detecting a selection of a deep sleep mode to which a first core of a processor is to enter; a module for determining, in response to detecting the selection of the deep sleep mode, whether the total number of cores in a light sleep state is less than the minimum level of a light sleep group of the processor; and a module for causing the first core to enter a light sleep mode instead of the selected deep sleep mode in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group.

[0133] In Example 26, the subject matter of Example 25 may optionally include: a module for updating a core state structure to indicate that the first core is transferred from an active group to a light sleep group in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group.

[0134] In Example 27, the subject matter of Examples 25-26 may optionally include: a core state structure for identifying an allocation of a plurality of cores to a plurality of groups, and the plurality of groups include an active group, a light sleep group, and a deep sleep group.

[0135] In Example 28, the subject matter of Examples 25-27 may optionally include: a module for causing the first core to enter the selected deep sleep mode in response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group.

[0136] In Example 29, the subject matter of Examples 25-28 may optionally include: a module for detecting a selection of a light sleep mode to which a second core of the processor is to enter; and a module for causing the second core to enter the light sleep mode in response to detecting the selection of the light sleep mode.

[0137] In Example 30, the subject matter of Examples 25-29 may optionally include: a module for detecting a requirement for a new active core; a module for determining, in response to detecting the requirement, whether any core is currently in a light sleep mode; and a module for causing a third core to transition from the light sleep mode to an active mode in response to determining that the third core is currently in the light sleep mode.

[0138] In Example 31, the subject matter of Examples 25-30 may optionally include: a module for determining, after causing the third core to transition from the light sleep mode to the active mode, whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and a module for causing at least one core to transition from the deep sleep mode to the light sleep mode in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group.

[0139] In Example 32, a computing device may include: a processor including a plurality of cores, a memory, and a machine-readable storage medium storing instructions. The instructions may be executable by the processor to: detect a selection for a first core of the processor to enter a deep sleep mode; in response to detecting the selection for the deep sleep mode, determine whether a total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter a light sleep mode instead of the selected deep sleep mode.

[0140] In Example 33, the subject matter of Example 32 may optionally include instructions executable by the processor to: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update a core state structure to indicate that the first core is transferred from an active group to the light sleep group.

[0141] In Example 34, the subject matter of Examples 32-33 may optionally include: a core state structure for identifying an allocation of a plurality of cores to a plurality of groups, and the plurality of groups include an active group, a light sleep group, and a deep sleep group.

[0142] In Example 35, the subject matter of Examples 32-34 may optionally include instructions executable by the processor to: in response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group, cause the first core to enter the selected deep sleep mode.

[0143] In Example 36, the subject matter of Examples 32-35 may optionally include instructions executable by the processor to: detect a selection for a second core of the processor to enter a light sleep mode; and in response to detecting the selection for the light sleep mode, cause the second core to enter the light sleep mode.

[0144] In Example 37, the subject matter of Examples 32-36 may optionally include instructions executable by the processor to: detect a requirement for a new active core; in response to detecting the requirement, determine whether any core is currently in the light sleep mode; and in response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to the active mode.

[0145] In Example 38, the subject matter of Examples 32-37 may optionally include instructions executable by the processor to: after causing the third core to transition from the light sleep mode to the active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

[0146] Note that although Figures 6A - 12illustrates various exemplary embodiments, but other variations are possible. For example, it is contemplated that one or more embodiments may be implemented in the exemplary devices and systems described with reference to Figures 1 - 5 Note that the examples shown in Figures 1 - 12 are provided for illustration and are not intended to limit any embodiment. Specifically, while embodiments may be shown in a simplified form for clarity, an embodiment may include any number and / or arrangement of components. For example, it is contemplated that some embodiments may include any number of components in addition to the embodiments shown, and different arrangements of the shown components may occur in certain implementations. Further, it is contemplated that Figures 1 - 12 the various details in the examples shown in

[0147] may be used anywhere in one or more embodiments.

[0148] It should be understood that various combinations of the above examples are possible. Embodiments may be used in many different types of systems. For example, in one embodiment, a communication device may be arranged to perform the various methods and techniques described herein. Of course, the scope of the present invention is not limited to communication devices. Instead, other embodiments may be directed to other types of devices for processing instructions, or one or more machine-readable media including instructions that, when executed on a computing device, cause the device to perform one or more of the methods and techniques described herein.

[0149] While the invention has been described with respect to a limited number of embodiments, those skilled in the art will recognize many modifications and variations therefrom. The appended claims are intended to cover all such modifications and variations that fall within the true spirit and scope of the invention.

Claims

1. A processor, comprising: a plurality of cores; and control circuitry configured to: detect a selection of a deep sleep mode for a first core of the processor to enter; in response to detecting the selection of the deep sleep mode, determine whether a total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter the light sleep mode instead of the selected deep sleep mode.

2. The processor according to claim 1, wherein the control circuitry is configured to: in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update a core state structure to indicate that the first core is transferred from an active group to the light sleep group.

3. The processor according to claim 2, wherein, The core state structure is configured to identify an assignment of the plurality of cores to a plurality of groups, and wherein the plurality of groups include the active group, the light sleep group, and a deep sleep group.

4. The processor according to claim 1, wherein the control circuitry is configured to: in response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group, cause the first core to enter the selected deep sleep mode.

5. The processor according to claim 1, wherein the control circuitry is configured to: detect a selection of the light sleep mode for a second core of the processor to enter; and in response to detecting the selection of the light sleep mode, cause the second core to enter the light sleep mode.

6. The processor according to claim 1, wherein the control circuitry is configured to: detect a request for a new active core; in response to detecting the request, determine whether any core is currently in the light sleep mode; and in response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to an active mode.

7. The processor according to claim 6, wherein the control circuitry is configured to: after causing the third core to transition from the light sleep mode to an active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and in response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

8. The processor according to claim 6, wherein the control circuitry is configured to: in response to determining that no core is currently in the light sleep mode, cause a fourth core to transition from the deep sleep mode to the active mode.

9. A computing device, comprising: a processor including a plurality of cores; a memory; and a machine-readable storage medium storing instructions executable by the processor for: detecting a selection of a deep sleep mode for a first core of the processor to enter; in response to detecting the selection of the deep sleep mode, determining whether a total number of cores in a light sleep state is less than a minimum level of a light sleep group of the processor; and In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter the light sleep mode instead of the selected deep sleep mode.

10. The computing device according to claim 9, comprising instructions executable by the processor for: In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update the core state structure to indicate that the first core is transferred from the active group to the light sleep group.

11. The computing device according to claim 10, wherein, The core state structure is used to identify the allocation of the plurality of cores to a plurality of groups, and wherein the plurality of groups include the active group, the light sleep group, and the deep sleep group.

12. The computing device according to claim 9, comprising instructions executable by the processor for: In response to determining that the total number of cores in the light sleep state is not less than the minimum level of the light sleep group, cause the first core to enter the selected deep sleep mode.

13. The computing device according to claim 9, comprising instructions executable by the processor for: Detect a selection of the light sleep mode to which a second core of the processor is to enter; and In response to detecting the selection of the light sleep mode, cause the second core to enter the light sleep mode.

14. The computing device according to claim 9, comprising instructions executable by the processor for: Detect a requirement for a new active core; In response to detecting the requirement, determine whether any core is currently in the light sleep mode; and In response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to the active mode.

15. The computing device according to claim 14, comprising instructions executable by the processor for: After causing the third core to transition from the light sleep mode to the active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

16. A system, comprising: A processor including a plurality of cores; And A memory coupled to the processor, the processor for: Detect a selection of the deep sleep mode to which a first core of the processor is to enter; In response to detecting the selection of the deep sleep mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group of the processor; And In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause the first core to enter the light sleep mode instead of the selected deep sleep mode.

17. The system according to claim 16, the processor for: In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, update the core state structure to indicate that the first core is transferred from the active group to the light sleep group.

18. The system according to claim 17, wherein The core state structure is used to identify the allocation of the multiple cores to multiple groups, and wherein the multiple groups include the active group, the light sleep group, and the deep sleep group.

19. The system according to claim 16, wherein the processor is configured to: Detect a requirement for a new active core; In response to detecting the requirement, determine whether any core is currently in the light sleep mode; and In response to determining that a third core is currently in the light sleep mode, cause the third core to transition from the light sleep mode to the active mode.

20. The system according to claim 19, wherein the processor is configured to: After causing the third core to transition from the light sleep mode to the active mode, determine whether the total number of cores in the light sleep state is less than the minimum level of the light sleep group; and In response to determining that the total number of cores in the light sleep state is less than the minimum level of the light sleep group, cause at least one core to transition from the deep sleep mode to the light sleep mode.

Images