Method for manufacturing semiconductor device

Abstract

The purpose of the present invention is to form an impurity implantation region with high precision when ion implantation is performed on a SiC substrate. A method for manufacturing a semiconductor device includes: a first step of implanting a first conductivity-type impurity into a SiC substrate; and a second step of implanting a second conductivity type impurity into the SiC substrate. In the thickness direction of the SiC substrate, there is a reduction region in which the concentration of the first conductivity-type impurity continuously decreases as the concentration distribution of the first conductivity-type impurity injected in the first step goes away from the position of a first peak value. In the thickness direction of the SiC substrate, the concentration distribution of the second conductivity-type impurity implanted in the second step has a second peak value. The position of the second peak value overlaps a specific region within the reduced region and having a first conductivity type impurity concentration of 10% or more of the first peak value. The position of the first peak value is a first conductivity type region. At least a portion of the specific region becomes a second conductivity type region.

Description

Technical Field

[0001] (Cross - reference to Related Applications)

[0002] This application is a related application of Japanese Patent Application No. 2023 - 001709 filed on January 10, 2023, claims priority based on this Japanese patent application, and incorporates by reference all the content described in this Japanese patent application as part of the content of this specification.

[0003] The technology disclosed in this specification relates to a method for manufacturing a semiconductor device. Background Art

[0004] In Japanese Unexamined Patent Application Publication No. 2021 - 015978, a technology of ion - implanting impurities into a SiC substrate (i.e., a semiconductor substrate made of silicon carbide) is disclosed. Summary of the Invention

[0005] When ion - implanting into a SiC substrate, the implanted impurities diffuse over a wide range and are implanted. Therefore, it is impossible to form an impurity - implanted region with high precision. In a SiC substrate, it is difficult to cause thermal diffusion of impurities during activation annealing. Therefore, forming an impurity - implanted region with high precision during ion implantation can improve the formation accuracy of p - type or n - type regions. A technology for forming an impurity - implanted region with high precision when ion - implanting into a SiC substrate is proposed in this specification.

[0006] The method for manufacturing a semiconductor device disclosed in this specification includes: a first step of implanting first - conductivity - type impurities into a SiC substrate; and a second step of implanting second - conductivity - type impurities into the SiC substrate. The first step and the second step are carried out under the following conditions: in the thickness direction of the SiC substrate, there is a first peak where the concentration distribution of the first - conductivity - type impurities implanted in the first step is the maximum, and a decreasing region where the concentration of the first - conductivity - type impurities continuously decreases as the distance from the position of the first peak increases. In the thickness direction of the SiC substrate, there is a second peak where the concentration distribution of the second - conductivity - type impurities implanted in the second step is the maximum, and the position of the second peak overlaps with a specific region. The specific region is within the decreasing region and has a first - conductivity - type impurity concentration of 10% or more of the first peak. The position of the first peak becomes a first - conductivity - type region, and at least a part of the specific region becomes a second - conductivity - type region.

[0007] In addition, either the first - conductivity - type region or the second - conductivity - type region is p - type and the other is n - type. That is, when the first - conductivity - type region is p - type, the second - conductivity - type region is n - type, and when the first - conductivity - type region is n - type, the second - conductivity - type region is p - type.

[0008] In addition, the first peak, the second peak, and the decreasing region are determined based on a distribution curve obtained by removing noise generated during the measurement of the impurity concentration.

[0009] Moreover, either the first process or the second process can be carried out first.

[0010] According to this manufacturing method, there is a first peak at which the concentration distribution of the first conductivity type impurity implanted in the first process is maximum, and a decreasing region where the concentration of the first conductivity type impurity continuously decreases as the distance from the position of the first peak increases. The decreasing region is a region where impurities are implanted due to the deviation of the implantation depth during ion implantation. In addition, according to this manufacturing method, the position of the second peak of the concentration distribution of the second conductivity type impurity implanted in the second process overlaps with a specific region having a first conductivity type impurity concentration of 10% or more of the first peak within the decreasing region. At least a part of the specific region becomes a second conductivity type region. Therefore, a first conductivity type region can be formed around the position of the first peak. Thus, according to this manufacturing method, a first conductivity type region can be formed with high precision. Description of the Drawings

[0011] Figure 1 It is an explanatory diagram of the first process of Example 1.

[0012] Figure 2 (a) thereof is a diagram showing the p-type impurity concentration distribution implanted in the first process of Example 1 in a cross section, Figure 2 and (b) thereof is a graph showing the p-type impurity concentration distribution at the position of line A-A.

[0013] Figure 3 It is an explanatory diagram of the first step of the second process of Example 1.

[0014] Figure 4 (a) thereof is a diagram showing the effective p-type impurity concentration distribution after the implementation of the second process of Example 1 in a cross section, Figure 4 and (b) thereof is a graph showing the impurity concentration distribution at the position of line A-A.

[0015] Figure 5 It is an explanatory diagram of the second step of the second process of Example 1.

[0016] Figure 6 It is a cross-sectional view of a MOSFET manufactured by the manufacturing method of Example 1.

[0017] Figure 7 It is an explanatory diagram of the first process of Example 2.

[0018] Figure 8FIG. (a) is a diagram showing the p-type impurity concentration distribution injected in the first step of Example 2 in a cross-section. Figure 8 FIG. (b) is a graph showing the p-type impurity concentration distribution at the position of line A-A.

[0019] Figure 9 It is an explanatory diagram of the second step of Example 2.

[0020] Figure 10 FIG. (a) is a diagram showing the effective p-type impurity concentration distribution after the implementation of the second step of Example 2 in a cross-section. Figure 10 FIG. (b) is a graph showing the impurity concentration distribution at the position of line A-A.

[0021] Figure 11 It is a cross-sectional view of a MOSFET manufactured by the manufacturing method of Example 1.

[0022] Figure 12 It is Figure 11 an explanatory diagram of the manufacturing process of the MOSFET.

[0023] Figure 13 It is Figure 11 an explanatory diagram of the manufacturing process of the MOSFET. Detailed Description of the Invention

[0024] In the manufacturing method of an example disclosed in this specification, it is also possible that the position of the second peak overlaps with the specific region existing at a position shallower than the position of the first peak.

[0025] In the manufacturing method of an example disclosed in this specification, it is also possible that the position of the second peak overlaps with the specific region existing at a position deeper than the position of the first peak.

[0026] In addition, the above-mentioned "shallow" means that the injection distance of the impurity in the first step is short, and the above-mentioned "deep" means that the injection distance of the impurity in the first step is long.

[0027] The manufacturing method of an example disclosed in this specification may also include a step of forming a mask having an opening on the surface of the SiC substrate. In this case, it is also possible that in the first step, a first conductive type impurity is injected into the SiC substrate via the mask, and in the second step, a second conductive type impurity is injected into the SiC substrate via the mask.

[0028] In the case of implantation through a mask, in the first step, the first-conductivity-type impurities also tend to diffuse laterally (i.e., in the direction parallel to the surface of the semiconductor substrate). By performing the second step using the same mask as the first step, the second-conductivity-type impurities can be diffused laterally in the second step. Thus, the formation range of the first-conductivity-type region can also be defined laterally.

[0029] In the manufacturing method according to an example disclosed in this specification, the width of the opening may be 3.5 μm or less.

[0030] In the manufacturing method according to an example disclosed in this specification, the semiconductor device manufactured by the manufacturing method may have an element region and a p-type protection ring that surrounds and extends around the element region. In this case, the first-conductivity-type region formed at the position of the first peak may be the protection ring.

[0031] In the manufacturing method according to an example disclosed in this specification, the semiconductor device manufactured by the manufacturing method may have a superstructure in which a plurality of p-type layers and a plurality of n-type layers are alternately arranged laterally in the drift region. The first-conductivity-type region formed at the position of the first peak may be the p-type layer of the superstructure.

[0032] Example 1

[0033] The manufacturing method of the semiconductor device of Example 1 includes a mask formation step, a first step of implanting p-type impurities into the SiC substrate, and a second step of implanting n-type impurities into the SiC substrate.

[0034] In the mask formation step, as Figure 1 shown, a mask 70 is formed on the upper surface 12a of the SiC substrate 12. The mask 70 has an opening 72. The SiC substrate 12 is made of n-type SiC. The n-type impurity concentration of the SiC substrate 12 is, for example, 1×10 15 cm -3 or so.

[0035] After the mask formation step, the first step is performed. In the first step, as Figure 1 shown, p-type impurities are ion-implanted into the SiC substrate 12 through the mask 70. Therefore, the p-type impurities are implanted into the SiC substrate 12 from the upper surface 12a within the opening 72. Here, the p-type impurities are implanted along the thickness direction of the SiC substrate 12. In addition, here, the p-type impurities are implanted multiple times while changing the acceleration energy. Thus, the p-type impurities are implanted at substantially the same concentration into the depths D1, D2, and D3.

[0036] Figure 2 shows the concentration distribution of the p-type impurities after performing the first step.Figure 2 The (a) of Figure 1 shows the same cross-section as Figure 2 , and the concentration of p-type impurities is represented by the density of the shading. Figure 2 The (b) of Figure 2 shows the concentration distribution of p-type impurities at the position of the A-A line of the (a) of Figure 2 . In addition,

[0037] As described above, in the first process, p-type impurities are implanted into a plurality of depths D1, D2, and D3. Therefore, within the depth range including depths D1, D2, and D3, the p-type impurity concentration is distributed substantially fixed at a relatively high value (for example, 8×10 17 cm -3 ). Hereinafter, the region where the p-type impurity concentration is distributed substantially fixed at a relatively high value is referred to as the main region 50. A peak Pmax of p-type impurities is formed within the main region 50. Above and below the main region 50, there are decreasing regions 52 and 54 where the p-type impurity concentration continuously decreases as it moves away from the main region 50. In addition, Figure 2 In the (b) of

[0038] , the decreasing region 52 of the curve G7 is taken as an example for illustration. The decreasing regions 52 and 54 are regions formed due to the deviation of the implantation depth of p-type impurities in the first process. The decreasing region 52 is formed above the main region 50 (i.e., on the shallower side in the implantation direction of p-type impurities). In the decreasing region 52, the p-type impurity concentration continuously decreases as it moves upward. The decreasing region 54 is formed below the main region 50 (i.e., on the deeper side in the implantation direction of p-type impurities). In the decreasing region 54, the p-type impurity concentration continuously decreases as it moves downward. Figure 2 In addition, an increasing region 56 exists above the decreasing region 52. In the increasing region 56, the p-type impurity concentration is higher than the upper end of the decreasing region 52. The increasing region 56 is a region where p-type impurities scattered and reflected by the mask 70 are implanted. Therefore, as Figure 2 shown by the curve G8 in the (b) of

[0039] , in the absence of the mask 70, the increasing region 56 is not formed. In addition, as Figure 2As shown in (a) thereof, a peripheral region 58 in which p-type impurities are distributed at a low concentration is formed at a position adjacent to the main region 50 in the lateral direction (i.e., the direction orthogonal to the ion implantation direction). The peripheral region 58 is a region into which the p-type impurities scattered and reflected by the mask 70 are implanted.

[0040] As described above, in the first step, p-type impurities are implanted not only into the main region 50 which is the implantation target of the p-type impurities, but also into the reduction regions 52, 54, the increase region 56, and the peripheral region 58 around it.

[0041] After the first step, a second step is performed. In the second step, n-type impurities are implanted into the SiC substrate 12 via the mask 70. Therefore, the n-type impurities are implanted into the SiC substrate 12 from the upper surface 12a within the opening 72. Here, the n-type impurities are implanted along the thickness direction of the SiC substrate 12. The implantation depth and implantation concentration of the n-type impurities in the second step are set corresponding to the p-type impurity concentration distribution formed in the first step. Hereinafter, taking the case where p-type impurities are implanted as in the curve G7 of (b) as an example, the second step will be described. The second step has a first process of implanting n-type impurities into the upper side of the main region 50 and a second process of implanting n-type impurities into the lower side of the main region 50. Figure 2 As shown in (b) thereof, while changing the acceleration energy, n-type impurities are implanted into the upper side of the main region 50 multiple times. Thereby, the n-type impurities are implanted into multiple depths in the region on the upper side of the main region 50.

[0042] In the first process, as Figure 3 shown, while changing the acceleration energy, n-type impurities are implanted into the upper side of the main region 50 multiple times. Thereby, the n-type impurities are implanted into multiple depths in the region on the upper side of the main region 50. Figure 4 The curve G10 of the concentration distribution of the n-type impurities implanted into the SiC substrate 12 in the first process is overlapped with the curve G7 in (b) thereof for representation. In addition, Figure 4 the region 52a in (b) thereof is a region in the reduction region 52 having a p-type impurity concentration higher than 10% of the peak Pmax. In the first process, the n-type impurities are implanted into the depth within the region 52a at least once. In Figure 4In the example shown in (b), n-type impurities are implanted into the reduction region 52 at depths D11, D12, and D13 including depths D12 and D13 within the inclusion region 52a. Here, among depths D11 to D13, the closer the depth is to the main region 50, the higher the concentration of n-type impurities is implanted. That is, at the depth D13 closest to the main region 50, n-type impurities are implanted at the highest concentration, and at the depth D11 farthest from the main region 50, n-type impurities are implanted at the lowest concentration. Therefore, within the reduction region 52, a peak Nmax1 of n-type impurities is formed at the depth D13 within the region 52a. Additionally, here, n-type impurities are also implanted into multiple depths within the increase region 56. Here, within a range above the depth D13, n-type impurities are implanted such that the concentration of n-type impurities is higher than the concentration of p-type impurities.

[0043] In the second process, as Figure 5 shown, while varying the acceleration energy, n-type impurities are implanted multiple times downward of the main region 50. Thereby, n-type impurities are implanted into multiple depths in the region below the main region 50. Figure 4 The curve G11 of the concentration distribution of the n-type impurities implanted into the SiC substrate 12 in the second process is overlapped with the curve G7 in (b) of Figure 4 The region 54a in (b) of Figure 4 is a region in the reduction region 54 having a p-type impurity concentration higher than 10% of the peak Pmax. In the second process, n-type impurities are implanted into the depth within the region 54a at least once. In the example shown in (b) of

[0044] n-type impurities are implanted into the reduction region 52, the reduction region 54, the increase region 56, and the peripheral region 58 as described above in the second step. Figure 4 The curve G13 in (b) of Figure 4As shown in (b), by injecting n-type impurities into the reduction regions 52, 54, and the increase region 56, the effective p-type impurity concentration in these regions becomes low. Figure 4 (a) of shows the same as Figure 5 the distribution of the effective p-type impurity concentration in the cross-section. As Figure 4 shown in (a), by injecting n-type impurities into the peripheral region 58, the effective p-type impurity concentration in the peripheral region 58 becomes low. In the reduction regions 52, 54, the increase region 56, and the peripheral region 58, except near the main region 50, the n-type impurity concentration is higher than the p-type impurity concentration. Therefore, in the main region 50 and its vicinity, the effective p-type impurity concentration becomes positive, and in other regions, the effective p-type impurity concentration becomes negative.

[0045] Next, the SiC substrate 12 is annealed. As a result, the p-type impurities and n-type impurities injected into the SiC substrate 12 are activated. The region where the effective p-type impurity concentration is positive becomes the p-type region 20, and the region where the effective p-type impurity concentration is negative (i.e., the region where the n-type impurity concentration is higher than the p-type impurity concentration) becomes the n-type region 22. That is, in Figure 4 (a), the p-type region 20 is formed in the shaded region, and in Figure 4 (a), the non-shaded region remains as the n-type region 22. As described above, the effective p-type impurity concentration is positive in the main region 50 and its vicinity. Therefore, the p-type region is formed in the main region 50 and its vicinity. The regions 52a, 54a adjacent to the main region 50 become n-type regions in at least a part of them. Therefore, the range where the p-type region is formed can be narrowed. In this way, according to this manufacturing method, the p-type region 20 can be formed in a region narrower than the region where the p-type impurities were injected in the first process.

[0046] Figure 6FIG. 0 shows a specific example of a MOSFET (metal-oxide-semiconductor field effect transistor) as a semiconductor device manufactured by the manufacturing method of Example 1. The SiC substrate 12 has an element region 60 and a peripheral region 61. In the element region 60, a MOSFET structure having an n-type source region 62, a p-type body region 63, a trench gate electrode 64, a bottom p-type region 65, an n-type drift region 66, and an n-type drain region 67 is formed. The trench gate electrode 64 is a gate electrode disposed in a trench and is insulated from the SiC substrate 12 by a gate insulating film. The bottom p-type region 65 is in contact with the bottom surface of the trench. The peripheral region 61 is provided around the element region 60. The drift region 66 is distributed in the peripheral region 61. A plurality of p-type guard rings 68 are provided in the peripheral region 61. Each guard ring 68 is provided inside the drift region 66. When observing the SiC substrate 12 from above, each guard ring 68 has a rectangular ring shape surrounding the periphery of the element region 60. Each guard ring 68 is disposed at the same depth as the bottom p-type region 65. Each guard ring 68 is formed after the formation of the element region 60. In the process of forming each guard ring 68, a mask 70 can be formed on the upper surface 12a of the SiC substrate 12, and a first process (i.e., implantation of p-type impurities) and a second process (i.e., implantation of n-type impurities) can be performed via the mask 70. According to this method, a small-sized guard ring 68 can be formed, and the MOSFET can be miniaturized.

[0047] In addition, in the above-mentioned Example 1, in the second process, n-type impurities were implanted into both the upper side and the lower side of the main region 50. However, in the second process, n-type impurities may be implanted only into either the upper side or the lower side of the main region 50. When n-type impurities are implanted into the upper side of the main region 50 via the mask 70, the reduction region 52 and the increase region 56 can be n-type. When n-type impurities are implanted into the lower side of the main region 50 via the mask 70, the reduction region 54 and the peripheral region 58 can be n-type.

[0048] Furthermore, in the above-mentioned Example 1, the impurity implantation of the first process and the second process was performed via the mask 70. However, the impurity implantation of the first process and the second process may be performed in the absence of a mask. Even with such a structure, a small-sized p-type region can be formed by implanting n-type impurities into the reduction region of the curve G8 in (b) of Figure 2 . However, when p-type impurities are implanted via a mask, there is a problem that p-type impurities are significantly implanted into the increase region 56 and the peripheral region 58. In particular, as Figure 2As shown in (b), when the width of the opening of the mask is 3.5 μm or less, the problem of injecting p-type impurities into the increasing region 56 and the peripheral region 58 occurs more significantly. Therefore, when the width of the opening of the mask is 3.5 μm or less, by using the technology disclosed in this specification, a higher effect can be obtained as an effect of suppressing the expansion of the p-type region.

[0049] Example 2

[0050] In Example 2, the mask formation process was also carried out in the same manner as in Example 1. After that, the first process and the second process were carried out.

[0051] In the first process of Example 2, as Figure 7 shown, p-type impurities were ion-implanted into the SiC substrate 12 via the mask 70. Here, the p-type impurities were implanted multiple times while changing the acceleration energy. Here, different from Example 1, the p-type impurities were implanted at equal intervals in the depth range from the upper surface 12a of the SiC substrate 12 to the depth D100. Here, for each depth, the p-type impurities were implanted at substantially the same concentration.

[0052] Figure 8 shows the concentration distribution of the p-type impurities after the first process. More specifically, Figure 8 (a) represents the same cross-section as Figure 7 , and the concentration of the p-type impurities is represented by the shaded concentration. Figure 8 (b) of Figure 8 shows the concentration distribution of the p-type impurities at the position of the A-A line of (a) of 17 cm -3 . In the depth range from the upper surface 12a to the depth D100, the p-type impurity concentration is distributed substantially fixed at a relatively high value (for example, 8×10 17 cm -3 ). Hereinafter, the region where the p-type impurity concentration is distributed substantially fixed is referred to as the main region 150. A peak Pmax of the p-type impurities is formed within the main region 150. Below the main region 150, there is a decreasing region 154 where the p-type impurity concentration continuously decreases as it moves away from the main region 150. The decreasing region 154 is a region formed due to the deviation of the implantation depth of the p-type impurities in the first process.

[0053] In addition, as Figure 8 (a) shows, in a position adjacent to the main region 150 in the lateral direction (i.e., the direction orthogonal to the ion implantation direction), a peripheral region 158 where the p-type impurities are distributed at a low concentration is formed. The peripheral region 158 is a region where the p-type impurities scattered and reflected by the mask 70 are implanted.

[0054] After the first process, the second process is implemented. In the second process, n-type impurities are ion-implanted into the SiC substrate 12 via a mask 70. The implantation depth and implantation concentration of the n-type impurities in the second process are set corresponding to the p-type impurity concentration distribution formed in the first process. As Figure 9 shown, in the second process, the n-type impurities are implanted multiple times while changing the acceleration energy on the lower side of the main region 150. Thereby, the n-type impurities are implanted to multiple depths in the region on the lower side of the main region 150. Figure 10 (b) of Figure 10 shows the curve G101 of the concentration distribution of the n-type impurities implanted into the SiC substrate 12 in the second process overlapping G100. In addition, Figure 10 (b) of

[0055] the region 154a in Figure 10 (b) is a region that reduces the region 154 having a p-type impurity concentration higher than 10% of the peak Pmax. In the second process, the n-type impurities are implanted into the depth within the region 154a at least once. In Figure 10 (b) of Figure 10 the example shown, the n-type impurities are implanted into the reduction region 154 at depths D121 and D122 including the depth D121 within the region 154a. Here, at the depths D121 and D122, the closer to the depth of the main region 150, the higher the concentration of the n-type impurities is implanted. That is, at the depth D121, the n-type impurities are implanted at a higher concentration than at the depth D122. Therefore, within the reduction region 154, a peak Nmax of the n-type impurities is formed at the depth D121. Here, in the range below the depth D121, the n-type impurities are implanted such that the n-type impurity concentration is higher than the p-type impurity concentration. In addition, when the n-type impurities are implanted in the second process, the n-type impurities are scattered and reflected by the mask 70. The n-type impurities scattered and reflected by the mask 70 are implanted into the peripheral region 158. Figure 9 Figure 10 As described above, in the second process, the n-type impurities are implanted into the reduction region 154 and the peripheral region 158. (b) of Figure 10 the curve G102 shows the effective p-type impurity concentration obtained by subtracting the n-type impurity concentration from the p-type impurity concentration. As Figure 10 (b) of Figure 9 shown, by implanting the n-type impurities into the reduction region 154, the effective p-type impurity concentration in the reduction region 154 becomes lower. Figure 10 (a) of (a) shows the distribution of the effective p-type impurity concentration in the same cross-section as Figure 9 . As Figure 10 (a) of shown, by implanting the n-type impurities into the peripheral region 158, the effective p-type impurity concentration in the peripheral region 158 becomes lower. In the reduction region 154 and the peripheral region 158, except near the main region 150, the n-type impurity concentration is higher than the p-type impurity concentration. Therefore, in the main region 50 and its vicinity, the effective p-type impurity concentration becomes positive, and in other regions, the effective p-type impurity concentration becomes negative.

[0056] Next, the SiC substrate 12 is annealed. As a result, the p-type impurities and n-type impurities implanted into the SiC substrate 12 are activated. The region where the effective p-type impurity concentration is positive becomes the p-type region 120, and the region where the effective p-type impurity concentration is negative (i.e., the region where the n-type impurity concentration is higher than the p-type impurity concentration) becomes the n-type region 122. That is, in Figure 10 (a) of, the p-type region 120 is formed in the shaded region, and in Figure 10 (a) of, the non-shaded region remains as the n-type region 122. As described above, the main region 150 and its vicinity have a positive effective p-type impurity concentration, so the p-type region is formed in the main region 150 and its vicinity. In particular, since at least a part of the region 154a adjacent to the main region 150 becomes the n-type region, the range where the p-type region is formed can be made narrower. Thus, according to this manufacturing method, the p-type region 120 can be formed in a region narrower than the region into which the p-type impurities were implanted in the first process.

[0057] Figure 11 FIG. shows a MOSFET as a specific example of a semiconductor device manufactured by the manufacturing method of Example 2. In the SiC substrate 12, a MOSFET structure having an n-type source region 62, a p-type body region 63, a trench gate electrode 64, a drift region 66, and an n-type drain region 67 is formed. The drift region 66 has a superstructure in which a plurality of p-type regions 66a and a plurality of n-type regions 66b are alternately arranged in the lateral direction. The p-type regions 66a and the n-type regions 66b each have a shape that is long in the thickness direction of the SiC substrate 12. In the manufacturing method of this MOSFET, first, as Figure 12 shown, the drift region 66 is formed on the drain region 67 by epitaxial growth. At this stage, the entire drift region 66 is composed of a low-concentration n-type region. Next, as Figure 13 shown, a mask 70 is formed on the upper surface of the drift region 66, and impurities are implanted through the mask 70 to form a plurality of p-type regions 66a. At this time, by applying the technology of Example 2, the formation range of the p-type regions 66a can be accurately controlled. The n-type regions remaining between the p-type regions 66a become the n-type regions 66b. After that, an epitaxial layer is formed on the drift region 66, and the source region 31, the body region 32, the trench gate electrode 36, etc. are formed in the formed epitaxial layer, thereby completing Figure 10 the MOSFET shown.

[0058] In addition, in the above-described Embodiment 2, the impurity implantation of the first process and the second process was performed via the mask 70. However, the impurity implantation of the first process and the second process may also be performed in the state where the mask is absent. Even with such a structure, a small p-type region can be formed by implanting an n-type impurity into the reduced region 154. However, in the case of implanting a p-type impurity via a mask, there is a problem that the p-type impurity is implanted into the peripheral region 158. In particular, when the width of the opening of the mask is 3.5 μm or less, the problem that the p-type impurity is implanted into the peripheral region 158 occurs more significantly. Therefore, by using the technology disclosed in this specification when the width of the opening of the mask is 3.5 μm or less, a higher effect can be obtained as an effect of suppressing the expansion of the p-type region.

[0059] In addition, in the above-described Embodiments 1 and 2, a p-type impurity was ion-implanted in the first process, and an n-type impurity was ion-implanted in the second process. However, an n-type impurity may also be ion-implanted in the first process, and a p-type impurity may be ion-implanted in the second process.

[0060] In addition, in the above-described Embodiments 1 and 2, the second process was performed after the first process. However, the first process may also be performed after the second process.

[0061] As described above, the embodiments have been described in detail, but these are merely examples and do not limit the claims. The technology described in the claims includes technologies obtained by various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or the drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations recited in the claims at the time of application. In addition, the technology illustrated in this specification or the drawings achieves multiple objects at the same time, and achieving one of the objects itself has technical usefulness.

Claims

1. A method of manufacturing a semiconductor device, characterized in that: It has: A first process of implanting an impurity of a first conductivity type into a SiC substrate (12); And A second process of implanting an impurity of a second conductivity type into the SiC substrate, The first process and the second process are carried out under the following conditions, and the conditions are: · In the thickness direction of the SiC substrate, there is a first peak (Pmax) where the concentration distribution (G7) of the impurity of the first conductivity type implanted in the first process is the maximum value, and a decreasing region (52, 54) where the concentration of the impurity of the first conductivity type continuously decreases as it moves away from the position of the first peak; · In the thickness direction of the SiC substrate, there are second peaks (Nmax1, Nmax2) where the concentration distributions (G10, G11) of the impurity of the second conductivity type implanted in the second process are the maximum values; · The position of the second peak overlaps with a specific region (52a, 54a) that is within the decreasing region and has a concentration of the impurity of the first conductivity type of 10% or more of the first peak; · The position of the first peak becomes a first conductivity type region; And · At least a part of the specific region becomes a second conductivity type region.

2. The manufacturing method according to claim 1, characterized in that: The position of the second peak overlaps with the specific region (52a) existing at a position shallower than the position of the first peak.

3. The manufacturing method according to claim 1, characterized in that: The position of the second peak overlaps with the specific region (54a) existing at a position deeper than the position of the first peak.

4. The manufacturing method according to any one of claims 1 to 3, characterized in that: It further has a process of forming a mask (70) having an opening (72) on the surface of the SiC substrate, In the first process, an impurity of a first conductivity type is implanted into the SiC substrate via the mask, In the second process, an impurity of a second conductivity type is implanted into the SiC substrate via the mask.

5. The manufacturing method according to claim 4, characterized in that: The width of the opening is 3.5 μm or less.

6. The manufacturing method according to claim 4, characterized in that: The semiconductor device manufactured by the manufacturing method has an element region (60) and a p-type protection ring (68) that surrounds and extends around the element region, The first conductivity type region formed at the position of the first peak is the protection ring.

7. The manufacturing method according to claim 4, characterized in that: The semiconductor device manufactured by the manufacturing method has a superstructure in which a plurality of p-type layers (66a) and a plurality of n-type layers (66b) are alternately arranged laterally in a drift region (66), The first conductivity type region formed at the position of the first peak is the p-type layer of the superstructure.

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