SiN gap filling via nucleation suppression

Abstract

The present disclosure generally relates to methods for forming a silicon nitride layer and a silicon nitride structure on a substrate. In one embodiment, the method includes positioning a substrate having at least one feature thereon in a processing chamber; depositing a first silicon layer on the substrate and the at least one feature; nitriding the first silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; selectively inhibiting silicon nucleation on a portion of the first silicon nitride layer to form a inhibited profile; selectively depositing a second silicon layer on the first silicon nitride layer according to the suppressed profile; and nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the first silicon nitride layer.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to fabricating semiconductor components and devices. More specifically, embodiments described herein provide methods for forming a silicon nitride layer on a semiconductor surface. Background Art

[0002] In semiconductor processing, the feature sizes of fabricated devices are continuously decreasing. Often, features used to fabricate devices at these advanced technology nodes include high aspect ratio structures, and it is often necessary to fill trenches between high aspect ratio structures with a gap filling material. Examples of using a gap filling material layer include shallow trench isolation (STI), horizontal interconnects, vias between adjacent metal layers, inter-metal dielectric layer (ILD), pre-metal dielectric (PMD), passivation layers, patterned applications, and the like. As device geometries shrink and the thermal budget decreases, due to the limitations of existing deposition processes, void-free and seamless filling of high aspect ratio spaces becomes increasingly difficult.

[0003] Filling the gaps between such high aspect ratio structures in a reliable manner while avoiding voids or gaps in the filling material is particularly challenging at this scale. Current processes for depositing gap filling materials include Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layered Deposition (ALD), Plasma Enhanced Chemical Vapor Deposition (PECVD), and High Density Plasma Chemical Vapor Deposition (HDP CVD), each of which presents some problems in filling small-sized, high aspect ratio features. Depositing a gap filling material into small and especially high aspect ratio features may result in the formation of slits and voids inside the filled features. Large slits may lead to high resistance, contamination, loss of the filling material, and degradation of the performance of integrated circuits. For example, after the filling process, the slit may extend to the near-field region and then open during the chemical-mechanical planarization process.

[0004] Accordingly, there is a need for improved methods for forming a gap filling material layer in trenches between high aspect ratio structures. Summary of the Invention

[0005] The present disclosure generally relates to methods for forming a silicon nitride layer and a silicon nitride structure on a substrate. In one embodiment, a method for forming a silicon nitride structure on a substrate is provided. The method includes: positioning a substrate having at least one feature thereon in a processing chamber; depositing a first silicon layer on the substrate and the at least one feature; nitriding the first silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; selectively inhibiting silicon nucleation on a portion of the first silicon nitride layer to form an inhibited profile; selectively depositing a second silicon layer on the first silicon nitride layer according to the inhibited profile; and nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the first silicon nitride layer.

[0006] In one embodiment, a method for forming a silicon nitride gap fill is provided. The method includes: positioning a substrate having at least one feature thereon in a processing chamber, the at least one feature extending from a top surface to a bottom surface of the substrate by a depth and having a width defined by a first sidewall and a second sidewall; depositing a first amorphous silicon layer on the substrate and the at least one feature; nitriding the first amorphous silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; selectively oxidizing one or more portions of the first silicon nitride layer disposed on the top surface of the substrate and on the top portions of the first sidewall and the second sidewall near an opening of at least one feature in the substrate surface to form a silicon oxide layer on one or more portions of the substrate and to inhibit silicon nucleation on the oxidized portions of the first silicon nitride layer; selectively depositing a second silicon layer on the remaining unoxidized portions of the first silicon nitride layer on the substrate; and nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the remaining unoxidized portions of the first silicon nitride layer.

[0007] In another embodiment, a method for forming a silicon nitride gap fill is provided. The method includes: positioning a substrate having at least one feature thereon in a processing chamber, the at least one feature extending from a top surface to a bottom surface of the substrate by a depth and having a width defined by a first sidewall and a second sidewall; performing a deposition process to deposit a first amorphous silicon layer on the substrate and the at least one feature; performing a plasma nitriding process on the substrate to convert the first amorphous silicon layer into a first silicon nitride layer; performing a plasma oxidation process to selectively oxidize one or more portions of the first silicon nitride layer on one or more portions of the substrate and the at least one feature; performing a deposition process to selectively deposit a second amorphous silicon layer on the remaining unoxidized portions of the first silicon nitride layer on the substrate; performing a plasma nitriding process on the substrate to convert the second amorphous silicon layer into a second silicon nitride layer disposed directly on the remaining unoxidized portions of the first silicon nitride layer; and repeating the selective plasma oxidation, selective deposition, and plasma nitriding processes in sequence to fill the at least one feature with silicon nitride and form a silicon nitride gap fill. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] To understand in detail the manner in which the above - described features of the present disclosure are utilized, reference may be made to the embodiments for a more particular description of the present disclosure briefly summarized above. Some embodiments are illustrated in the accompanying drawings. However, it will be noted that the drawings only illustrate exemplary embodiments and are thus not considered to limit its scope, and other equally effective embodiments are permitted.

[0009] Figure 1A A schematic illustration of an exemplary processing chamber that can be used to practice Figure 2 the methods depicted in

[0010] Figure 1B is shown in accordance with certain embodiments of the present disclosure; Figure 1A A schematic cross - sectional view of an electrostatic chuck that can be used in the

[0011] Figure 2 devices of Figure 1A is shown in accordance with certain embodiments of the present disclosure;

[0012] Figure 3A Up to Figure 3I A cross - sectional view of a silicon nitride gap fill feature formed by the Figure 2 methods of

[0013] Figure 4 is shown in accordance with certain embodiments of the present disclosure; and

[0014] Figure 5 A flowchart of an embodiment of a method for forming a silicon nitride gap fill in a gap feature in accordance with certain embodiments of the present disclosure.

[0015] For ease of understanding, the same reference numerals have been used, where possible, to identify the same elements common to the figures. It is contemplated that the elements and features of one embodiment may be advantageously incorporated into other embodiments without further recitation. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure generally relate to apparatuses and methods for depositing thin films to form interconnect structures on substrates. Certain details are set forth in the following description and FIGS. 1 through Figure 5 to provide a thorough understanding of the various implementations of the present disclosure. Other details of well - known methods and systems often associated with depositing thin films are not set forth in the following disclosure to avoid unnecessarily obscuring the description of the various implementations.

[0017] The numerous details, components, and other features described herein merely illustrate particular implementations. Thus, other implementations may have other details, components, and features without departing from the spirit or scope of the present disclosure. Additionally, further implementations of the present disclosure may be practiced without several of the details described below.

[0018] Developing thin film materials that can fully and effectively fill high aspect ratio features (trenches between high aspect ratio structures) remains a challenging goal. Thin films deposited by plasma CVD typically exhibit poor conformality, which can result in void formation inside high aspect ratio features. Thin films deposited by thermal CVD typically exhibit conformality higher than 90%. However, current methods of filling high aspect ratio features using thermal CVD typically result in gap formation.

[0019] Compared to silicon nitride thin films deposited using currently known thermal CVD techniques, implementations of the present disclosure improve the gap filling ability of silicon nitride thin films formed in high aspect ratio features. Implementations described herein include suppressing silicon nucleation. In certain embodiments, the method involves selectively suppressing silicon deposition along a portion of a high aspect ratio feature and an adjacent structure (the suppressed profile), followed by selective deposition according to the suppressed profile. Methods of selectively suppressing silicon nucleation may include exposing silicon deposited on the feature to direct or remote plasma. In certain embodiments, the methods described herein may be used for bottom-up filling of vertical features (such as in vias).

[0020] Selective suppression (also referred to as preferential suppression, preferential passivation, selective passivation, differential suppression, or differential passivation) involves suppressing subsequent silicon nucleation on a portion of a feature or structure while not suppressing (or suppressing to a lesser extent) nucleation on the remaining portion of the feature or structure. Once a feature and structure are selectively suppressed, selective deposition according to the suppressed profile is selective because silicon preferentially deposits on the less suppressed and unsuppressed portions of the feature and structure. By leveraging selective silicon suppression and deposition, the methods disclosed herein achieve bottom-up formation of seamless silicon nitride gap fills. In certain embodiments, contrary to high-cost custom precursor gases in other processes, the methods described herein use only relatively low-cost precursor gases such as silane and disilane. Thus, the disclosure described herein provides several advantages over conventional methods and techniques.

[0021] Figure 1AFIG. 132 is a schematic side cross-sectional view of an exemplary processing system 132 suitable for performing a deposition process according to at least one embodiment disclosed herein. Suitable chambers are available from Applied Materials, Inc., located in Santa Clara, Calif. It will be understood that the systems described below are exemplary processing chambers, and other chambers (including chambers from other manufacturers) may be used in or modified to implement embodiments of the present disclosure (e.g., method 200 described below). In some embodiments, the processing system 132 may be configured to deposit a thin film onto a substrate using a chemical vapor deposition (plasma-enhanced and / or thermal) process.

[0022] The processing system 132 includes a processing chamber 100 and a controller 110 coupled to a gas panel 130. The processing chamber 100 generally includes a top wall 124, side walls 101, and a bottom wall 122 that define a processing space 126. A substrate support assembly 146 is provided in the processing space 126 of the processing chamber 100. The substrate support assembly 146 generally includes an electrostatic chuck 150 supported by rods 160. The electrostatic chuck 150 may generally be made of aluminum, ceramic, and other suitable materials. The electrostatic chuck 150 may be moved vertically within the processing chamber 100 using a displacement mechanism (not shown).

[0023] A vacuum pump 102 is coupled to a port formed in the bottom of the processing chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the processing chamber 100. The vacuum pump 102 also evacuates the processed gases and by-products of the process from the processing chamber 100.

[0024] The substrate processing system 132 may further include additional equipment for controlling the chamber pressure, such as valves (e.g., throttle valves and isolation valves) positioned between the processing chamber 100 and the vacuum pump 102 to control the chamber pressure.

[0025] A gas distribution assembly 120 having a plurality of holes 128 is disposed on top of the electrostatic chuck 150 in the top of the processing chamber 100. The holes 128 of the gas distribution assembly 120 are used to introduce process gases into the processing chamber 100. The holes 128 may have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases for different processing requirements. The gas distribution assembly 120 is connected to the gas panel 130, which allows various gases to be supplied to the processing space 126 during processing. A plasma is formed from the process gas mixture exiting the gas distribution assembly 120 to enhance the thermal decomposition of the process gas, resulting in the deposition of material on the surface 191 of the substrate 190.

[0026] The gas distribution assembly 120 and the electrostatic chuck 150 can form a pair of spaced-apart electrodes in the processing space 126. One or more RF power supplies 140 provide a bias potential to the gas distribution assembly 120 via a matching network 138 (which is optional) to facilitate the generation of a plasma between the gas distribution assembly 120 and the electrostatic chuck 150. Alternatively, the RF power supply 140 and the matching network 138 can be coupled to the gas distribution assembly 120, the electrostatic chuck 150, or both the gas distribution assembly 120 and the electrostatic chuck 150, or to an antenna (not shown) disposed outside the processing chamber 100. In some implementations, the RF power supply 140 can generate power at a frequency of 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz. In one implementation, the RF power supply 140 can provide between about 100 watts and about 3,000 watts at a frequency of about 50 kHz to about 13.6 MHz. In another implementation, the RF power supply 140 can provide between about 500 watts and about 1,800 watts at a frequency of about 50 kHz to about 13.6 MHz.

[0027] The controller 110 includes a central processing unit (CPU) 112, a memory 116, and support circuitry 114 for controlling the process sequence and regulating the gas flow from the gas panel 130. The CPU 112 can be any form of general-purpose computer processor that can be used in an industrial setting. Software routines can be stored in the memory 116, such as random access memory, read-only memory, floppy disks, or hard disk drives, or other forms of digital memory. The support circuitry 114 is conventionally coupled to the CPU 112 and can include cache, clock circuits, input / output systems, power supplies, and the like. Bidirectional communication between the controller 110 and the various components of the substrate processing system 132 is handled via several signal cables, collectively referred to as the signal bus 118, some of which are shown in Figure 1A in.

[0028] Figure 1B is depicted in Figure 1A a schematic cross-sectional view of a substrate support assembly 146 used in the processing system of. See Figure 2, the electrostatic chuck 150 may include a heater element 170 adapted to control the temperature of a substrate 190 supported on the upper surface 192 of the electrostatic chuck 150. The heater element 170 may be embedded in the electrostatic chuck 150. The electrostatic chuck 150 may be resistively heated by applying current from a heater power supply 106 to the heater element 170. The heater power supply 106 may be coupled via an RF filter 158. The RF filter 158 may be used to protect the heater power supply 106 from RF energy. The heater element 170 may be made of nickel-chromium wire encapsulated in a nichrome (e.g., ) sheath. The current supplied from the heater power supply 106 is regulated by a controller 110 to control the heat generated by the heater element 170, thus maintaining the substrate 190 and the electrostatic chuck 150 at a substantially constant temperature during film deposition. The supplied current may be adjusted to selectively control the temperature of the electrostatic chuck 150 between about -50 degrees Celsius and about 600 degrees Celsius.

[0029] See Figure 1A , a temperature sensor 172 (such as a thermocouple) may be embedded in the electrostatic chuck 150 to monitor the temperature of the electrostatic chuck 150 in a conventional manner. The measured temperature is used by the controller 110 to control the power supplied to the heater element 170 for maintaining the substrate at a desired temperature.

[0030] The electrostatic chuck 150 includes a clamping electrode 152, which may be a grid of conductive material. The clamping electrode 152 may be embedded in the electrostatic chuck 150. The clamping electrode 152 is coupled to a clamping power supply 154, which, when energized, electrostatically clamps the substrate 190 to the upper surface 192 of the electrostatic chuck 150.

[0031] The clamping electrode 152 may be configured as a monopole or bipolar electrode, or have another suitable arrangement. The clamping electrode 152 may be coupled to the clamping power supply 154 via an RF filter 156, which provides direct current (DC) power to electrostatically secure the substrate 190 to the upper surface 192 of the electrostatic chuck 150. The RF filter 156 prevents the RF power used to form a plasma within the processing chamber 100 from damaging electrical equipment or presenting an electrical hazard outside the chamber. The electrostatic chuck 150 may be made of a ceramic material, such as AlN or Al2O3. Alternatively, the electrostatic chuck 150 may be made of a polymer, such as polyimide, polyetheretherketone (PEEK), polyaryletherketone (PAEK), and the like.

[0032] The power application system 162 is coupled to the substrate support assembly 146. The power application system 162 may include a heater power supply 106, a chucking power supply 154, a first radio frequency (RF) power supply 180, and a second RF power supply 182. Implementations of the power application system 162 may additionally include a controller 110, as well as a sensor device 164 in communication with the controller 110, and both the first RF power supply 180 and the second RF power supply 182.

[0033] The controller 110 may also be used to control the plasma from the process gas by applying RF power from the first RF power supply 180 and the second RF power supply 182 to deposit a material layer on the substrate 190.

[0034] As described above, the electrostatic chuck 150 includes a chucking electrode 152 that may be used in one aspect to hold the substrate 190 while also serving as the first RF electrode. The electrostatic chuck 150 may also include a second RF electrode 166, and together with the chucking electrode 152, may apply RF power to tune the plasma. The first RF power supply 180 may be coupled to the second RF electrode 166, while the second RF power supply 182 may be coupled to the chucking electrode 152. A first matching network and a second matching network may be provided for the first RF power supply 180 and the second RF power supply 182, respectively. The second RF electrode 166 may be a solid metal plate of a conductive material as shown. Alternatively, the second RF electrode 166 may be a grid of conductive material.

[0035] The first RF power supply 180 and the second RF power supply 182 may generate power at the same frequency or at different frequencies. In some implementations, one or both of the first RF power supply 180 and the second RF power supply 182 may independently generate power at a frequency ranging from about 350 KHz to about 100 MHz (e.g., 350 KHz, 2 MHz, 13.56 MHz, 27 MHz, 40 MHz, 60 MHz, or 100 MHz). In some implementations, the first RF power supply 180 may generate power at a frequency of 13.56 MHz, and the second RF power supply 182 may generate power at a frequency of 2 MHz, and vice versa. The RF power from one or both of the first RF power supply 180 and the second RF power supply 182 may be varied to tune the plasma. For example, the sensor device 164 may be used to monitor the RF energy from one or both of the first RF power supply 180 and the second RF power supply 182. Data from the sensor device 164 may be communicated to the controller 110, and the controller 110 may be used to vary the power applied by the first RF power supply 180 and the second RF power supply 182.

[0036] Other deposition chambers may also benefit from the present disclosure and the parameters listed above may vary depending on the particular deposition chamber used to form the amorphous carbon layer. For example, other deposition chambers may have a larger or smaller volume and thus require a larger or smaller gas flow rate compared to the gas flow rates recited for the deposition chambers obtained from Applied Materials, Inc.

[0037] Figure 2 is for use in accordance with certain embodiments described herein using Figure 1A FIG. 200 is a flow chart of an exemplary method for forming a silicon nitride gap fill in the features on a substrate using the processing chamber 100 depicted in FIG. As used in this context, the term "feature" means any intentional surface irregularity. The shape of the feature can be any suitable shape, including but not limited to trenches and cylindrical vias. Suitable examples of features include but are not limited to trenches having a top, two sidewalls, and a bottom and vias having generally cylindrical sidewalls. Other examples of features include but are not limited to pipelines, contact holes, vias, or other feature definitions utilized in semiconductor, solar, or other electronic devices such as high aspect ratio contact plugs. The feature can have any suitable aspect ratio (the ratio of the depth of the feature to the width of the feature). In some embodiments, the aspect ratio is greater than or equal to about 5:1, 10:1, 15:1, 20:1, 25:1, 30:1, 35:1, or 40:1.

[0038] However, those skilled in the art will understand that the described precursors and methods are not limited to gap fill applications and can be used for other films.

[0039] In one embodiment, method 200 begins at operation 202 by positioning a substrate having features (such as substrate 302 shown in FIG. 3) within the interior processing space 126 of processing chamber 100 for processing. In one embodiment, the substrate (e.g., substrate 302) is transferred into processing chamber 100 and onto substrate support assembly 146 by any suitable means (such as through a substrate transfer port (not shown)). Substrate support assembly 146 can be adjusted to a processing position by an actuator (not shown). In one embodiment, substrate support assembly 146 can include an electrostatic chuck 150 for securing substrate 302. Substrate 302 can include one or more materials such as nitrides, oxides, silicon, and / or metals (e.g., tungsten, molybdenum, titanium, etc.). Although Figure 3A a substrate 302 having a single feature is shown for illustrative purposes, those skilled in the art will understand that there can be more than one feature.

[0040] In Figure 3AIn the example shown, substrate 302 has a substrate surface 304 that has at least one feature that forms an opening in the substrate surface 304. In one embodiment, the at least one feature includes a trench 305 that extends a depth D from the substrate surface 304 to a bottom surface 306. The trench 305 has a first sidewall 308 and a second sidewall 310 that define a width W of the trench 305. The opening area formed by the sidewalls 308, 310, and the bottom surface 306 is also referred to as a gap.

[0041] At operation 204, a cycle of a deposition process is performed on substrate 302 in processing chamber 100 to deposit a first amorphous silicon layer 312 on substrate 302. In one embodiment, processing chamber 100 can be a CVD chamber as Figure 1A shown, and the first amorphous silicon layer 312 can be deposited on substrate 302 using a thermal CVD process. The thermal CVD process for depositing the first amorphous silicon layer 312 includes flowing a source precursor gas from gas panel 130 into an interior processing space 126 of chamber 100. In one embodiment, the source precursor gas for forming the first amorphous silicon layer 312 can include silicon precursor gases such as silane, disilane, tetrasilane, and other higher order silanes, dichlorosilane, trichlorosilane, and silicon tetrachloride. The source precursor gas is provided into the processing space 126 through, for example, gas distribution assembly 120 such that the source precursor gas is uniformly distributed in the processing space 126. In one embodiment, the plurality of holes 128 in gas distribution assembly 120 can be radially distributed and the gas flow to each of the plurality of holes 128 can be separately controlled to further promote gas uniformity within the processing space 126.

[0042] The source precursor gas can then be thermally decomposed in the interior processing space 126 to deposit the first amorphous silicon layer 312 on the substrate surface 304 and in the trench 305. To deposit the first amorphous silicon layer 312, during the thermal deposition process, the temperature of substrate support assembly 146 in chamber 100 can be set between about 100 degrees Celsius and about 1,000 degrees Celsius, for example, between about 400 degrees Celsius and about 600 degrees Celsius, and the pressure in the chamber can be between about 10 millitorr and about 760 torr, for example, about 300 torr.

[0043] As Figure 3B shown, the CVD process can deposit the first amorphous silicon layer 312 above the substrate surface 304 and the trench 305, including above the bottom surface 306, and the first and second sidewalls 308, 310. The deposited amorphous silicon layer can have a thickness between about and about .

[0044] In operation 206, an amorphous silicon nitridation process is performed on substrate 302 in chamber 100 to process the first amorphous silicon layer 312 and convert the first amorphous silicon layer 312 into a first silicon nitride layer 314. The nitridation process may include performing a thermal nitridation process or a plasma-based nitridation process. Silicon nitridation performed using plasma processing can process the amorphous silicon layer to form a conformal layer of silicon nitride having a thickness from about to about .

[0045] The plasma-based nitridation process includes flowing a process gas from gas distribution assembly 120, including but not limited to N2, NH3, hydrazine (N2H4), H2, noble gases (He, Ar, Ne, Kr, Xe), or combinations thereof, for generating a plasma. The plasma can be generated in the plasma region between the substrate and electrostatic chuck 150 by using the introduced process gas and applying a first RF bias from one or both of first RF power supply 180 and second RF power supply 182 to the electrostatic chuck. Typically, the RF power can be from about 1 kW to about 10 kW, although other power levels are also contemplated.

[0046] When the plasma is ignited, the nitrogen radical-containing material formed from the nitrogen-containing process gas reacts with substrate 302. Such nitrogen radical-containing material may include N and / or NH, for example, N* and / or NH*. During the nitridation process, the nitrogen radical-containing material saturates on the surface of amorphous silicon layer 312 due to the high material flow rate, such that the diffusion of the reactive material becomes the dominant factor. The diffusion and reaction of the nitrogen radical-containing material convert the amorphous silicon atoms in amorphous silicon layer 312 into SiN, thereby converting the first amorphous silicon layer 312 into a first silicon nitride layer 312, as Figure 3C shown.

[0047] In operation 206, the processing chamber 100 for the nitridation process can be operated at a temperature from about 100 °C to about 1200 °C, such as from about 150 °C to about 650 °C; and / or at a pressure from about 0.025 Torr (25 millitorr (mTorr)) to about 5 Torr, such as from about 0.050 Torr (50 millitorr) to about 2 Torr. However, other temperatures and pressures are contemplated. The RF power can be controlled between about 25 watts and about 2000 watts, such as between about 100 watts and about 800 watts, for example, about 400 watts. The plasma-forming gas (such as N2 gas) can be supplied between about 1000 sccm and about 5000 sccm, such as about 2000 sccm. In another embodiment, the NH3 plasma-forming gas can be supplied between about 500 sccm and about 2000 sccm, such as about 1000 sccm.

[0048] At operation 208, silicon nucleation on portions of the substrate surface 304 and sidewalls 308, 310 near the openings of the trenches 305 is selectively inhibited, while nucleation on portions of the sidewalls 308, 310 inside the trenches 305 and near the bottom surface 306 on the bottom surface 306 is not selectively inhibited. In one embodiment, selective inhibition of portions of features on the substrate 304 can involve exposing the features to an activating material that passivates the feature surfaces. In the present disclosure, portions of the first silicon nitride layer 314 are passivated by exposure to an oxygen-based plasma, where oxygen atoms from the plasma replace nitrogen atoms in the silicon nitride film, thereby oxidizing the silicon nitride (SiN) and forming silicon oxide (SiO).

[0049] At operation 208, the selective inhibition is performed by selectively oxidizing the above-mentioned portions of the substrate surface 304 and the trenches 305. As Figure 3D shown, portions of the first silicon nitride layer 314 along portions of the substrate surface 304 adjacent to the openings of the trenches 305 and portions of the sidewalls 308, 310 near the openings of the trenches 305 are selectively oxidized and converted from SiN to SiO to form a silicon oxide layer 316. For the purposes of the present disclosure, due to the incubation delay of amorphous silicon deposition observed on the oxidized silicon surface during the thermal CVD process, the oxidation of SiN in the first silicon nitride layer 314 selectively inhibits silicon nucleation. Figure 4 The delayed deposition of amorphous silicon on the oxidized silicon surface as compared to an unoxidized silicon surface (such as the SiN layer surface) is shown. This incubation delay on the oxidized silicon surface can subsequently be utilized in a subsequent step to selectively deposit amorphous silicon on the non-inhibited portions of the trenches 305.

[0050] Exemplary plasma-forming gases for the oxygen plasma treatment process that can flow into the processing space 126 of the chamber 100 for operation 208 include oxygen-containing gases such as oxygen (O2), nitrous oxide (N2O), and the like. In certain embodiments, tuning the inhibited profile on the substrate 302 (e.g., the selective oxidation on portions of the substrate surface 304 and sidewalls 308, 310 near the openings of the trenches 305) can involve appropriately customizing and selecting one or more substrate bias powers, plasma powers, processing pressures, gas types, exposure times, and other processing parameters such as the spacing between the substrate support assembly 146 and the gas distribution assembly 120. When appropriately tuned, oxygen radicals from the ignited plasma can contact and react with only portions of the SiN layer deposited on the substrate surface 304 and sidewalls 308, 310 near the openings of the trenches 305, thereby selectively oxidizing and converting only these portions of the first silicon nitride layer 314 to silicon oxide.

[0051] In one embodiment, the processing pressure is controlled between about 0.1 Torr and about 100 Torr (e.g., between about 0.1 Torr and about 80 Torr; between about 1 Torr and about 20 Torr or between about 7 Torr and about 30 Torr). In one implementation, the processing temperature is between about 100 degrees Celsius and about 900 degrees Celsius (e.g., between about 125 degrees Celsius and about 350 degrees Celsius, e.g., between about 200 degrees Celsius and about 300 degrees Celsius, such as between about 164 degrees Celsius and about 340 degrees Celsius). The RF power can be controlled between about 25 watts and about 2000 watts, such as between about 100 watts and about 800 watts, e.g., about 400 watts. The plasma-forming gas (such as O2 gas) can be supplied between about 5 sccm and 200 sccm.

[0052] Once a portion of the first silicon nitride layer 314 along the substrate surface 304 adjacent to the opening of the trench 305 and portions of the sidewalls 308, 310 near the opening of the trench 305 is selectively inhibited by selective oxidation, a thermal CVD process is then performed in operation 210 to selectively deposit a second amorphous silicon layer 318 according to an inhibited profile on the remaining uninhibited / unoxidized portions of the first silicon nitride layer 314. The selective deposition according to the inhibited profile is selective because the thermal CVD process in operation 410 is only performed for (or less than) the duration that amorphous silicon initially and preferentially grows only on the unoxidized silicon surface. In one embodiment, the thermal CVD process is thus performed for between about 1 to 4 minutes, such as between about 2 to 3 minutes. As Figure 3E shown, the selective deposition of amorphous silicon forms a second amorphous silicon layer 318 on only the uninhibited portions of the first silicon nitride layer 314 in the trench 305.

[0053] In operation 212, an amorphous silicon nitridation process similar to the nitridation process performed in operation 206 is performed in the processing chamber 100 to process the second amorphous silicon layer 318 and convert the second amorphous silicon layer 318 into a second silicon nitride layer 320 formed in the trench 305, as Figure 3F shown.

[0054] The selective oxidation, selective deposition, and nitridation processes in operations 208, 210, and 212 can be repeated in sequence to fill the trench 305. In certain embodiments, the number of cycles may depend on the size and depth of the feature being filled. After the second silicon nitride layer 320 is formed in the trench 305, the selective plasma oxidation process is also repeated to enhance the silicon nucleation inhibition of the silicon oxide layer 316. Figure 3G Shown is a third amorphous silicon layer 322 selectively deposited on the second silicon nitride layer 320 and subsequently converted into a third silicon nitride layer 324, as shown in Figure 3H. Figure 3IIllustrated is a silicon nitride gap fill 326 formed in trench 305 after a cycle of repeating operations 208, 210, and 212 a sufficient number of times to completely fill trench 305 with a silicon nitride layer.

[0055] Figure 5 is a flowchart of an embodiment of a method 500 for forming a silicon nitride gap fill in a gap feature according to an embodiment of the present disclosure.

[0056] Method 500 begins at operation 502, where processing is performed by positioning a substrate having a gap feature within an interior processing space 126 of a processing chamber 100. In one embodiment, the substrate is transferred into processing chamber 100 and onto substrate support assembly 146 by any suitable means (such as through a substrate transfer port (not shown)).

[0057] In operation 504, a deposition process is performed in processing chamber 100 to deposit a first conformal amorphous silicon layer on the substrate and the gap feature.

[0058] In operation 506, a nitridation process is performed to convert the first conformal amorphous silicon layer into a first silicon nitride layer. After the nitridation process, the first silicon nitride layer is disposed directly on the substrate and the gap feature.

[0059] In operation 508, a selective inhibition process is performed according to an inhibited profile to selectively inhibit silicon nucleation on the first silicon nitride layer disposed on portions of the substrate and the gap feature. In one embodiment, the inhibited profile of the substrate and the gap feature includes the substrate surface above the opening field of the gap feature and the top of the sidewalls in the gap feature near the opening. Selective inhibition (which may also be referred to as preferential inhibition, preferential passivation, selective passivation, differential inhibition, or differential passivation) involves inhibiting subsequent silicon nucleation on a portion of the substrate and the gap feature while not inhibiting (or inhibiting to a lesser extent) nucleation on the remaining portions of the substrate and the gap feature.

[0060] Selective inhibition can involve selectively exposing a portion of the substrate and the gap feature to an activating material of a plasma according to the inhibited profile. In one embodiment, the substrate and the gap feature are selectively inhibited by selective exposure to a plasma generated from a molecular oxygen-containing gas in the processing chamber. The desired inhibited profile can be formed by appropriately selecting one or more of an inhibition chemical material, a substrate bias power, a plasma power, a processing pressure, an exposure time, and other processing parameters (such as the spacing between the substrate and the showerhead in the processing chamber).

[0061] Once the selective inhibition process is performed, method 400 can continue at operation 510, where a second amorphous silicon layer is selectively deposited according to the inhibited profile. Operation 508 can involve one or more chemical vapor deposition (CVD) and / or atomic layer deposition (ALD) processes, including thermal and plasma-enhanced CVD and / or ALD processes. The deposition is selective because during the deposition process, amorphous silicon preferentially grows on the substrate surface and on the less inhibited and non-inhibited portions of the gap features. The deposition process can be performed for a limited time during which the inhibition of silicon nucleation takes effect. In one embodiment, operation 510 involves selectively depositing amorphous silicon in the bottom or inner portion of the gap features.

[0062] In operation 512, an amorphous silicon nitridation process similar to the nitridation process performed in operation 406 is performed in processing chamber 100 to process the second amorphous silicon layer and convert the second amorphous silicon layer into a second silicon nitride layer. In one embodiment, the second silicon nitride layer formed in operation 512 is disposed above the first silicon nitride layer in the gap features.

[0063] The selective inhibition, selective deposition, and nitridation processes in operations 508, 510, and 512 can be repeated in sequence until the gap features are completely filled with silicon nitride.

[0064] Using the aspects described herein, in certain embodiments, it has been found that by using the cyclic amorphous silicon deposition, nitridation, and selective oxidation processes disclosed herein, features (such as trenches) on a substrate can be seamlessly filled from the bottom up with a layer of SiN to form a SiN gap fill. In one embodiment, the cyclic deposition, nitridation, and oxidation processes disclosed herein can be performed in situ in the same processing chamber 100, thus eliminating the need for substrate transfer and the use of expensive cluster systems. Additionally, since the deposition processes utilized herein only require the deposition of amorphous silicon, compared to other deposition methods that may require costly custom precursors, the present disclosure enables the formation of a completely seamless SiN gap fill using low-cost silicon precursor gases such as silane and disilane.

[0065] Although the foregoing relates to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its basic scope, and its scope is determined by the following claims.

Claims

1. A method for forming a silicon nitride structure, the method comprising: Positioning a substrate having at least one feature thereon in a processing chamber; Depositing a first silicon layer on the substrate and the at least one feature; Nitriding the first silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; Selectively inhibiting silicon nucleation on portions of the first silicon nitride layer to form an inhibited profile; Selectively depositing a second silicon layer on the first silicon nitride layer according to the inhibited profile; And Nitriding the second silicon layer to form a second silicon nitride layer disposed directly on the first silicon nitride layer.

2. The method of claim 1, wherein the at least one feature extends a certain depth from a substrate surface to a bottom surface and has a width defined by a first sidewall and a second sidewall, and the method further comprises: Repeating the selective inhibition, the selective deposition, and the nitriding processes in sequence to fill the at least one feature with silicon nitride and form a silicon nitride gap fill.

3. The method of claim 2, wherein the at least one feature has substantially no gap in the silicon nitride gap fill.

4. The method according to claim 1, wherein depositing the first silicon layer and selectively depositing the second silicon layer comprise: Performing a thermal CVD process and a thermal ALD process.

5. The method according to claim 1, wherein selectively inhibiting silicon nucleation on portions of the first silicon nitride layer comprises: Selectively oxidizing the portion of the first silicon nitride layer to a silicon oxide layer.

6. The method according to claim 4, wherein depositing the first silicon layer and selectively depositing the second silicon layer comprises: Flowing a source-containing precursor gas into an internal processing space of the processing chamber, wherein the source-containing precursor gas is selected from the group consisting of silane, disilane, tetrasilane, and other higher-order silanes, dichlorosilane, trichlorosilane, and silicon tetrachloride, and thermally decomposing the precursor gas in the internal processing space.

7. The method according to claim 1, wherein nitriding the first silicon layer and the second silicon layer comprises: Performing a plasma nitriding process in the processing chamber.

8. The method according to claim 1, wherein selectively depositing the second silicon layer comprises: Performing a thermal CVD process in the processing chamber for a duration less than a SiO incubation delay period, wherein the SiO incubation delay period includes the time period spent depositing amorphous silicon on an oxidized silicon surface first in the thermal CVD process.

9. The method according to claim 1, wherein selectively depositing the second silicon layer comprises: Performing a thermal ALD process in the processing chamber for a duration less than a SiO incubation delay period, wherein the SiO incubation delay period includes the time period spent depositing amorphous silicon on an oxidized silicon surface first in the thermal ALD process.

10. The method of claim 1, wherein the inhibited profile includes inhibiting silicon nucleation on one or more portions of the first silicon nitride layer disposed on the substrate surface and on top of the first sidewall and the second sidewall near an opening of the at least one feature in the substrate surface.

11. The method of claim 1, wherein the first silicon layer comprises an amorphous silicon layer.

12. A method for forming a silicon nitride gap fill, the method comprising: Positioning a substrate having at least one feature thereon in a processing chamber, the at least one feature extending a certain depth from a substrate surface to a bottom surface and having a width defined by a first sidewall and a second sidewall; Depositing a first amorphous silicon layer on the substrate and the at least one feature; Nitriding the first amorphous silicon layer to form a first silicon nitride layer on the substrate and the at least one feature; Selectively oxidize one or more portions of the first silicon nitride layer disposed on the surface of the substrate and on top of the first sidewall and the second sidewall near the opening of the at least one feature in the substrate surface to form a silicon oxide layer on one or more portions of the substrate and inhibit silicon nucleation on the oxidized portion of the first silicon nitride layer; Selectively deposit a second silicon layer on the remaining unoxidized portion of the first silicon nitride layer on the substrate; And Nitridize the second silicon layer to form a second silicon nitride layer disposed directly on the remaining unoxidized portion of the first silicon nitride layer.

13. The method according to claim 12, the method further comprising: Repeat the selective oxidation, the selective deposition, and the nitridation processes in sequence to fill the at least one feature with silicon nitride and form a silicon nitride gap fill, wherein the at least one feature has substantially no gap in the silicon nitride gap fill.

14. The method according to claim 12, wherein depositing the first amorphous silicon layer and selectively depositing the second silicon layer comprises: Perform a thermal CVD process or a thermal ALD process.

15. The method according to claim 12, wherein depositing the first amorphous silicon layer and selectively depositing the second silicon layer comprises: Flow a source precursor gas into an internal processing space of a processing chamber, wherein the source precursor gas is selected from the group consisting of silane and disilane, and thermally decompose the precursor gas in the internal processing space.

16. The method according to claim 12, wherein nitriding the first silicon layer and the second silicon layer comprises: Perform a plasma nitridation process in the processing chamber.

17. The method according to claim 12, wherein selectively depositing the second silicon layer comprises: Perform a CVD process or an ALD process for a duration less than the SiO incubation delay period, wherein the SiO incubation delay period includes the time periods respectively spent on depositing amorphous silicon on an oxidized silicon surface in the CVD process or the ALD process.

18. A method for forming a silicon nitride gap fill, the method comprising: Position a substrate having at least one feature in a processing chamber, the at least one feature extending a certain depth from the substrate surface to the bottom surface and having a width defined by a first sidewall and a second sidewall; Perform a deposition process to deposit a first amorphous silicon layer on the substrate and the at least one feature; Perform a plasma nitridation process on the substrate to convert the first amorphous silicon layer into a first silicon nitride layer; Perform a plasma oxidation process to selectively oxidize one or more portions of the first silicon nitride layer on one or more portions of the substrate and the at least one feature; Perform a deposition process to selectively deposit a second amorphous silicon layer on the remaining unoxidized portion of the first silicon nitride layer on the substrate; Perform the plasma nitridation process on the substrate to convert the second amorphous silicon layer into a second silicon nitride layer disposed directly on the remaining unoxidized portion of the first silicon nitride layer; And Repeat the selective plasma oxidation, the selective deposition, and the plasma nitridation processes in sequence to fill the at least one feature with silicon nitride and form the silicon nitride gap fill.

19. The method of claim 18, wherein the at least one feature has substantially no gap in the silicon nitride gap fill.

20. The method according to claim 18, wherein performing the deposition process to selectively deposit the second amorphous silicon layer comprises: Perform a CVD process or an ALD process for a duration less than the SiO incubation delay period, wherein the SiO incubation delay period includes the time periods respectively spent on depositing amorphous silicon on an oxidized silicon surface in the CVD process or the ALD process.

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