Data processing method and device, electronic equipment and readable storage medium

Abstract

The invention discloses a data processing method and device, electronic equipment and a readable storage medium, and relates to the technical field of computers, and the data processing method comprises the steps that a flash memory interaction module writes a word line to be subjected to disk falling into a preset cache region and performs primary data programming, and the word line serves as a temporary storage word line temporarily stored in the preset cache region; and when a preset number of temporary storage word lines are stored in the preset cache region, selecting an initial word line in the current temporary storage word lines, performing secondary data programming on the initial word line, and placing the initial word line into a disk. And when new to-be-loaded data is obtained again, covering the loaded initial word line by using the new to-be-loaded data. At the moment, a preset number of temporary storage word lines are stored, the initial word line is selected again, secondary data programming is carried out again, and the secondary data programming control of the word line to be subjected to disk falling is transferred to the flash memory interaction module from the flash memory conversion layer. Therefore, the technical problems of heavy communication overhead burden and performance pressure in the data disk dropping process are solved, and the technical effects of reducing the communication and performance burden and improving the flash memory performance are achieved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a data processing method, a data processing device, an electronic device, and a computer-readable storage medium. Background Art

[0002] For storage devices such as solid-state drives and flash drives, their flash architectures may at least include a front-end module, an FTL (Flash Translation Layer), and a back-end module (i.e., a flash interaction module) connected in sequence. When the to-be-written word line is transmitted from the flash translation layer to the logic unit of the flash interaction module, generally, the flash translation layer needs to send requests for primary data programming and secondary data programming to the flash interaction module respectively. Moreover, after receiving the data, the flash translation layer will accumulate the data until it reaches the data length of a flash page (NAND page) before sending it. Thus, it will cause a heavy communication overhead burden due to the pressure of message interaction between modules, and during the period after the flash translation layer completes the first write and before the second write, the context cannot be released, resulting in a gradual increase in the required context data and causing a certain performance pressure. Summary of the Invention

[0003] This application provides a data processing method, a data processing device, an electronic device, and a computer-readable storage medium to at least solve the problems of heavy communication overhead burden and performance pressure in the data disk-writing process in related technologies.

[0004] This application provides a data processing method, which includes: the flash interaction module of the logic unit obtains the to-be-written word line from the flash translation layer; writes the to-be-written word line into a preset buffer area of the flash interaction module, and performs primary data programming on it to be a temporary word line; in response to the preset buffer area having stored a preset number of temporary word lines, selects the initial word line among them for secondary data programming and writes it to the flash particle; uses the new to-be-written data to overwrite the initial word line in the preset buffer area, and performs primary data programming on the new to-be-written data to be a temporary word line; where the initial word line refers to the temporary word line whose writing time is earlier than the writing times of other temporary word lines.

[0005] This application also provides a data processing device, which includes: a flash interaction module for connecting to the flash translation layer and the flash particle; the flash interaction module includes a preset buffer area and a control unit, the preset buffer area is used to temporarily store the to-be-written word line; the control unit is used to implement the steps of any of the above data processing methods.

[0006] This application also provides an electronic device, which includes: a memory for storing a computer program; a processor for implementing the steps of any of the above data processing methods when executing the computer program.

[0007] The present application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any one of the above data processing methods.

[0008] With the present application, since a preset buffer is built in the logic unit to temporarily store the word lines to be written to disk and implement automatic secondary data programming. The control of the secondary data programming of the word lines to be written to disk is transferred from the flash conversion layer to the flash interaction module, thereby reducing the communication burden on the flash conversion layer to request the flash interaction module for secondary data programming. At the same time, the flash interaction module can temporarily store the word lines to be written to disk to release the context, and can reduce the context occupation time to reduce the performance pressure. Therefore, the technical problems of heavy communication overhead and performance pressure during the data write-to-disk process can be solved, achieving the technical effect of reducing the communication and performance burdens to improve the flash performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0010] Figure 1 It is a schematic structural diagram of an embodiment of the application scenario of the data processing method of the present application;

[0011] Figure 2 It is a schematic structural diagram of an embodiment of the back-end module of the present application;

[0012] Figure 3 It is a schematic structural diagram of an embodiment of the data processing device of the present application;

[0013] Figure 4 It is a schematic flowchart of an embodiment of the data processing method of the present application;

[0014] Figure 5 It is a schematic diagram of an embodiment of the data write-to-disk of the present application;

[0015] Figure 6 It is a schematic flowchart of another embodiment of the data write-to-disk of the present application;

[0016] Figure 7 It is a schematic flowchart of an embodiment of the working principle of the preset buffer of the present application;

[0017] Figure 8 It is a schematic structural diagram of an embodiment of the electronic device of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0019] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0020] In order to enable those skilled in the art of the present technology to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the data processing method depends, the specific application environment architecture or specific hardware architecture will be described herein.

[0022] Please refer to Figure 1 , Figure 1 which is a schematic structural diagram of an embodiment of Application Scenario 1 of the data processing method of the present application.

[0023] In one embodiment, with the development of information technology, the generation of a large amount of data at all times has become a common phenomenon in various industries, and the demand for the storage reliability of massive data has also emerged accordingly. The usage of storage devices such as SSD (Solid State Disk or Solid State Drive, solid state drive) in the storage industry has also increased year by year.

[0024] With the development of NAND (flash memory) technology, the mainstream architecture inside SSDs has also been updated and iterated. For example, QLC NAND has the advantage of reducing costs while increasing storage capacity compared to TLC NAND. Among them, QLC (Quad Level Cell) and TLC (Triple Level Cell) are flash memory particles; the difference is that TLC is a three-level cell flash memory, that is, each cell can store three bits of data; QLC is a four-level cell flash memory, that is, each cell can store four bits of data.

[0025] For example, taking the application of SSDs in servers as an example, such asFigure 1 As shown in the example, the terminal 101 communicates with the server 102 via a network, so as to support the terminal 101 to send data to the server 102 via the network.

[0026] The server 102 may at least include a host and a storage device. The storage device may include, for example, Figure 1 the front-end module, flash translation layer, back-end module, and flash memory particles as shown in the example.

[0027] The host obtains data from the terminal 101 and sends it to the front-end module. The front-end module sends the obtained data as the word lines to be written to disk in this application to the flash translation layer. The flash translation layer processes the word lines to be written to disk and sends them to the back-end module. After obtaining the word lines to be written to disk, the back-end module can perform data processing on them. The data processing can refer to the data processing method described later, and sends the processed data to the flash memory particles to achieve data writing to disk.

[0028] Among them, the terminal 101 may be, but is not limited to, various personal computers, laptop computers, smart phones, tablet computers, and portable wearable devices. The server 102 may be implemented by an independent server or a server cluster composed of multiple servers.

[0029] Please refer to Figure 2 , Figure 2 which is a schematic structural diagram of an embodiment of the back-end module of this application.

[0030] In one embodiment, the back-end module may include multiple logical units. Among them, the logical unit may be a LUN (Logic Unit), and the LUN can work independently in the NAND and can be considered as the smallest unit for obtaining status.

[0031] Further, among the multiple logical units included in the back-end module, at least one logical unit can be used to store check data (i.e., Parity described later), and other logical units are used to store the word lines to be written to disk obtained from the outside. As the name implies, the check data can be used to check the word lines to be written to disk stored.

[0032] Among them, the word lines to be written to disk stored can represent the word lines after data programming or the original word lines to be written to disk. Since the word lines to be written to disk can perform data programming within the logical unit, they are uniformly summarized as word lines to be written to disk here without introducing other defined names.

[0033] Such as Figure 2As shown by the example, the backend module may include 32 logical units and operate in a 31 + 1 manner. That is, LUN0 to LUN30 are used to store the word lines to be written to the disk, and LUN31 is used to store the parity data formed based on the data stored in LUN0 to LUN30. Generally speaking, 31 user data can be separately stored in LUN0 to LUN30, and a parity data is calculated from the 31 user data and written to LUN31.

[0034] An embodiment of the present application also provides a data processing device. Please refer to Figure 3 , Figure 3 which is a schematic structural diagram of an embodiment of the data processing device of the present application.

[0035] In one embodiment, the data processing device may include a flash memory interaction module for connecting to a flash translation layer and flash memory particles.

[0036] Among them, the flash memory interaction module may include a preset buffer and a control unit. The preset buffer is used to temporarily store the word lines to be written to the disk; the control unit is used to implement the steps of any of the above data processing methods.

[0037] For the description of the features in the corresponding embodiment of the data processing device, reference may be made to the relevant description of the corresponding embodiment of the data processing method hereinafter, and details will not be repeated here.

[0038] An embodiment of the present application provides a data processing method. The method will be described in detail in combination with the execution process of the data processing method.

[0039] Please refer to Figure 4 , Figure 4 which is a schematic flowchart of an embodiment of the data processing method of the present application.

[0040] S101: The logical unit of the flash memory interaction module obtains the word lines to be written to the disk from the flash translation layer.

[0041] In this embodiment, the word lines to be written to the disk, as the name implies, are the word lines to be written to the storage device. Generally speaking, a word line is an electrical connection line inside a solid-state drive, used to control the read and write operations of flash memory chips. That is to say, in storage devices such as solid-state drives, the word line can connect the control unit and the storage unit (such as flash memory particles, etc.), and realize the read and write operations of flash memory chips through the transmission of control signals. That is, the word line can be responsible for transmitting the instructions of the control unit to the flash memory chips of the storage unit to realize the read and write operations of data. The logical unit of the flash memory interaction module in the storage device can obtain the word lines to be written to the disk from the flash translation layer.

[0042] S102: Write the word lines to be written to the disk into the preset buffer of the logical unit and perform a data programming on them to be used as temporarily stored word lines.

[0043] In this embodiment, a preset buffer can be pre-constructed in at least part of the logical units of the storage device. The data processing logic of at least part of the logical units can be changed to optimize the data writing process to the disk of at least part of the logical units, so as to optimize the performance of the flash memory. For example, a preset buffer can be pre-constructed in each logical unit to temporarily store the word lines to be written to the disk.

[0044] That is, in response to obtaining the data transmitted by the word line to be written to the disk, the flash memory interaction module can control to write the word line to be written to the disk into the preset buffer of the response logical unit, and perform a data programming on the word line to be written to the disk written into the preset buffer, and use it as the temporary word line temporarily stored in the preset buffer. That is to say, the temporary word line is the word line to be written to the disk that has undergone one data programming.

[0045] S103: In response to the preset buffer having stored a preset number of temporary word lines, select the initial word lines among them for secondary data programming and write them to the flash memory particles; wherein, the initial word line refers to the temporary word line whose writing time is earlier than the writing times of other temporary word lines.

[0046] In this embodiment, the number of temporary word lines stored in the preset buffer can be identified. When the preset buffer has stored a preset number of temporary word lines, it can be considered that the temporary word lines can be subjected to secondary data programming at present to write them to the disk.

[0047] To improve the matching with the writing order of the word lines to be written to the disk, the writing times of the temporary word lines stored in the preset buffer can be identified, and the earliest written word line to be written to the disk in the current preset buffer is selected as the initial word line at the current moment, so as to select the earliest written word line to be written to the disk in the current preset buffer for secondary data programming, that is, perform secondary data programming on the initial word line and write it to the flash memory particles.

[0048] Optionally, in this embodiment, the preset number can be preset according to the number of word lines that can be stored in a single layer of the logical unit (i.e., the target number in the following text), and no limitation is made here.

[0049] It should be noted that the word lines to be written to the disk stored in the preset buffer will change as the word lines to be written to the disk are continuously written, and the initial word lines will also change accordingly. The specific change process will be elaborated in detail later and will not be elaborated here first.

[0050] S104: Use the new data to be written to the disk to overwrite the initial word line in the preset buffer, and perform a data programming on the new data to be written to the disk to use it as a temporary word line.

[0051] In this embodiment, in response to the initial word line, secondary data programming is performed and written to the flash memory cell. When the logic unit obtains a new word line to be written, when the flash memory interaction module writes the word line to be written into the preset buffer area of the logic unit, it can use the new word line to be written to overwrite the initial word line that has been written, and perform primary data programming on the new data to be written, so as to be used as a temporary word line temporarily stored in the preset buffer area.

[0052] Meanwhile, since the new data to be written overwrites the initial word line that has been written, and after performing primary data programming, a new temporary word line is formed. At this time, the number of temporary word lines stored in the preset buffer area after this update is the preset number. Triggering the working principle such as step S103 again can identify the initial word line in the current preset buffer area, perform secondary data programming and write it to the disk, and overwrite it when new data to be written is obtained again. In this way, in this embodiment, a cycle of secondary data programming and writing of the initial word line and overwriting by the new data to be written can be triggered, realizing automatic triggering of secondary data programming of the word line to be written, without the need for the flash translation layer to separately request secondary data programming for each data to be written.

[0053] That is to say, since a preset buffer area is built in the flash memory interaction module to temporarily store the word line to be written and realize automatic secondary data programming. The control of secondary data programming of the word line to be written is transferred from the flash translation layer to the flash memory interaction module, which can at least reduce the cumbersome operation of the flash translation layer separately requesting secondary data programming for each word line to be written, thereby reducing the communication burden of the flash translation layer requesting the flash memory interaction module to perform secondary data programming. At the same time, the flash memory interaction module can release the context by temporarily storing the word line to be written, and can reduce the context occupation time to reduce the performance pressure. Therefore, the technical problems of heavy communication overhead and performance pressure in the data writing process can be solved, and the technical effects of reducing communication and performance burdens to improve flash memory performance can be achieved.

[0054] The working principle of data writing to the disk is illustrated by examples below. Please refer to Figure 5 , Figure 5 which is a schematic diagram of an embodiment of data writing to the disk in this application.

[0055] In one embodiment, Figure 5 an example of the data writing form of QLC NAND is given, and the WL (word line) in the block is sequentially stored according to the writing order. Among them, the writing order identifiers of the word lines shown in the figure, such as 0 to 15, 4*N 4 to N + 3, are the writing order identifiers of the word lines, that is, the actual writing order is subtracted by one.

[0056] However, since each Cell in QLC NAND stores 16 voltage ranges, compared with the 8 voltage ranges of TLC, the fineness of data Program is doubled. It is difficult for the NAND production process to achieve one-time writing without affecting the relevant WL. Therefore, in the program process of QLC, it is required that the writing of each WL be divided into two steps. Specifically, please refer to Figure 6 , Figure 6 which is a schematic flow diagram of another embodiment of data disk dropping in this application.

[0057] In one embodiment, first, the first write is performed on WL-0 of the 0th layer in the block (write order identifier 0), and then the first writes of WL-1 / 2 / 3 of the 0th layer are continuously performed (write order identifiers 1 / 2 / 3); after writing all the WLs of the 0th layer, the first write is performed on the first WL0 of the 1st layer (write order identifier 4). In this way, the first writes of WL-0 of the 0th layer and WL-0 of the 1st layer are both completed. Only then can the second write be performed on WL-0 of the 0th layer (write order identifier 5), and then all the write operations of WL-0 of the 0th layer are completed. The subsequent WLs on the current Layer (Layer-1) are performed in the above order. The reason for writing in this way is that the impact on the upper WL is more obvious during Program. After writing data to the lower WL, it is necessary to perform a second data write on the upper WL to increase the stability of the data.

[0058] To avoid ambiguous understanding, it is hereby stated that the data actually written for write order identifier 0 and write order identifier 5 is the same. The difference is that write order identifier 0 is the initial write of the word line to be disk dropped, which is equivalent to the primary data programming described in the previous text, and write order identifier 5 is the second write of the word line to be disk dropped, which is equivalent to the secondary data programming described in the previous text. By analogy, the data written for write order identifier 1 and write order identifier 7, write order identifier 2 and write order identifier 9, write order identifier 3 and write order identifier 11, write order identifier 4 and write order identifier 13, etc. is the same, and will not be elaborated here.

[0059] In the implementation of QLC SSD, data writing can be initiated by the algorithm layer, which sends the NAND address and data to the backend together. The backend completes the combination of NAND commands and data distribution, and finally completes the write operation.

[0060] The following elaborates on the detailed working principle of the data processing method of this application with examples.

[0061] Specifically, in this embodiment, the flash memory interaction module of the logic unit obtains the word lines to be written to the disk from the flash translation layer. The word lines to be written to the disk can be written into a preset buffer area of the flash memory interaction module, and data programming is performed on them once to serve as temporary word lines. The detailed working principle content can be illustrated by the examples in the previous steps S101 and S102, and will not be elaborated here.

[0062] Furthermore, the preset buffer area can include a preset number of sub-buffer areas, and the sub-buffer areas are used to store the word lines to be written to the disk. For example, a word line to be written to the disk can be written into one of the sub-buffer areas.

[0063] Optionally, the preset number can be one more than the target number. Wherein, the target number represents the number of word lines that the logic unit supports writing per layer. It is equivalent to automatically starting the second Program operation of the word lines in the upper layer after the first Program of the first WL in each layer starting from the first layer (equivalent to the second layer) is completed, and sending back the completion message of the current write after completion.

[0064] Thus, in this embodiment, it is possible to adapt to the working principle of performing secondary data programming on the characters to be written to the disk as described in the previous text, that is, when the word lines to be written to the disk in the second layer are written, secondary data programming is performed on the word lines to be written to the disk in the first layer of the WL area where they are written, so as to realize the automation of the secondary programming of the word lines to be written to the disk while reducing the situation of hoarding the word lines to be written to the disk, that is, reducing the number of word lines to be written to the disk temporarily stored in the preset buffer area, which is beneficial to the timeliness of the word lines to be written to the disk being written to the disk. At the same time, it is also beneficial to reduce the occupation of the storage space of the logic unit and ensure the performance of the logic unit.

[0065] Since the preset buffer area includes multiple sub-buffer areas, there are idle sub-buffer areas in the preset buffer area when initially obtaining the word lines to be written to the disk. Thus, in this embodiment, in response to the existence of idle sub-buffer areas in the preset buffer area, the word lines to be written to the disk can be written into the idle sub-buffer areas.

[0066] Optionally, in this process, the word lines to be written to the disk can be randomly allocated to the idle sub-buffer areas to improve the efficiency of writing the word lines to be written to the disk into the preset buffer area. Or, they can be written into each sub-buffer area in sequence according to the writing time of the word lines to be written to the disk, which is beneficial to improving the recognition efficiency of the initial word lines and also beneficial to improving the data orderliness of the preset buffer area.

[0067] Specifically, taking the example of writing the data to be written to the disk into each sub-buffer area in sequence as needed, the currently idle sub-buffer area can be obtained. Identify the starting idle area of the currently idle sub-buffer area. Among them, the starting idle area refers to the idle sub-buffer area whose current storage address is less than the storage addresses of other idle sub-buffer areas. Thus, the word lines to be written to the disk can be written into the starting idle area so that the word lines to be written to the disk are also stored in sequence in the preset buffer area.

[0068] As described in the foregoing embodiments, when a preset number of data to be written to disk are stored in the preset buffer, it can be considered that an initial word line can be selected for secondary data programming. Therefore, it is possible to identify whether the preset buffer currently stores a preset number of temporary word lines.

[0069] Specifically, it is possible to identify whether each sub-buffer in the preset buffer stores a temporary word line. Alternatively, it is possible to identify the writing order of the word lines to be written to disk written into the preset buffer.

[0070] For example, it is possible to obtain the order identifier of the word line to be written to disk. Among them, the order identifier can be the writing order identifier exemplified above, or it can be the writing order without subtracting one.

[0071] Here, taking the order identifier as the writing order without subtracting one as an example, the order identifier can be compared with the target quantity. Among them, the target quantity represents the number of word lines that a single layer of a logical unit supports writing. The preset quantity can be, as described above, the quantity value after adding one to the target quantity.

[0072] In response to the order identifier not being greater than the target quantity, when new data to be written to disk are obtained, the order identifier of the new data to be written to disk can be compared with the target quantity. Until the order identifier is greater than the target quantity, when new data to be written to disk are obtained again, its order identifier is not compared with the target quantity. In this way, in this embodiment, it is possible to implement the determination of the timing for starting to select the initial word line. When the preset buffer does not store a preset number of temporary word lines, the temporary word lines for secondary data programming are not selected. When the preset buffer stores a preset number of temporary word lines, it can be considered that it is possible to start secondary data programming for the data to be written to disk. That is, in response to the order identifier being greater than the target quantity, it can be determined that the preset buffer has stored a preset number of temporary word lines, that is, it can be considered that an initial word line can be selected.

[0073] Moreover, when writing new word lines to be written to disk to the preset buffer subsequently, it is also possible not to determine whether to select the initial word line, which is beneficial to reducing the verification of whether to perform secondary data programming, and further beneficial to simplifying the data processing flow to improve the data writing to disk efficiency and further optimize the flash memory performance.

[0074] Optionally, during this process, in response to the initial word line completing its primary data programming as a temporary word line, a completion message is sent to the flash translation layer. Among them, the completion message can be a CPL message, etc. The CPL message is a type of message used to indicate the completion status of a request. That is, before the initial word line performs secondary data programming, it is completed to feedback to the flash translation layer that the data writing to disk request for the initial word line has been completed.

[0075] In this embodiment, when the initial word line writes to its initial write preset buffer and completes a data programming operation, that is, when the initial word line serves as a temporary word line, a completion message can be sent to the flash translation layer. Thus, even when the initial word line, which serves as a temporary word line, has not yet undergone a second data programming operation, the flash translation layer can consider the initial word line that has not yet undergone a second data programming operation to have completed disk writing based on the completion message. As a result, the flash translation layer does not need to pay attention to the second data programming of the word line to be written to disk, achieving the transfer of the control of the second data programming of the word line to be written to disk from the flash translation layer to the flash interaction module.

[0076] Different from the related art, when performing a first data programming operation and a second data programming operation on the word line to be written to disk, it is usually necessary for the flash translation layer to send a programming request to the flash interaction module. And precisely because the flash translation layer needs to pay attention to and control the second data programming of the word line to be written to disk, a completion message needs to be sent to the flash exchange layer when the word line to be written to disk completes the second data programming operation. It should be noted that the completion message in this embodiment is similar to the completion message in the related art, both of which are used to feedback to the flash translation layer that the word line to be written to disk has completed disk writing. In this embodiment, precisely because it is desired to reduce the control and request of the flash translation layer for the second data programming operation, a completion message is fed back to the flash translation layer when the data to be written to disk completes its first data programming operation.

[0077] As described above, when the preset buffer has stored a preset number of temporary word lines, the stored temporary word lines can be subjected to a second data programming operation to achieve data disk writing. Specifically, in response to the preset buffer having stored a preset number of temporary word lines, an initial word line among them can be selected for a second data programming operation and written to the flash memory cell.

[0078] The following is an example of the identification process of the initial word line.

[0079] Optionally, the sequence identifier of the word line to be written to disk that was written to the preset buffer last time can be incremented to obtain a sequence factor.

[0080] The target quantity is incremented to obtain a comparison factor. Here, the target quantity represents the number of word lines that a single layer of a logical unit supports writing.

[0081] The sequence factor and the comparison factor are subjected to a remainder operation to obtain a remainder factor. The temporary word line stored in the sub-buffer that matches the remainder factor is used as the initial word line. Thus, although the write operation corresponding to the initial word line still requires a second data programming operation, it can be independently implemented by the backend module (i.e., the flash interaction module) without the participation of the flash translation layer. Therefore, the context corresponding to the initial word line can be released, and the buffer required for data storage does not need to be released. When the second data programming operation of the initial word line is completed, the backend module can release it to allow the flash translation layer to continue using the released buffer.

[0082] Generally speaking, the index information that can be used as the initial word line can be identified through the aforementioned working principle. The initial word line is obtained through the index information, and the initial word line is programmed with secondary data. Here, taking the target quantity as 4 and the sequence identifier as subtracting 1 from the writing sequence (i.e., as Figure 5 illustrated in the example shown) as an example, the specific calculation formula can be as follows:

[0083] index = (wl_idx + 1) MOD 5 Equation 1-1

[0084] Among them, index represents the remainder factor; wl_idx represents the sequence identifier; MOD represents the remainder function; 5 represents adding 1 to the target quantity 4.

[0085] As Figure 7 illustrated in the example shown, Figure 7 is a schematic flow chart of an embodiment of the working principle of the preset buffer area of the present application. req-1 to req-6 represent the request sequences for the word lines to be written to the disk sent by the flash translation layer. Taking req-5 as an example, that is, the fifth time the flash translation layer requests word line writing to the disk, the word line to be written to the disk requested is wl_idx = 4. After calculation by Equation 1-1, index = 0 is obtained. Therefore, the cached word line in the 0th sub-buffer is selected as the initial word line. At this time, the word line to be written to the disk requested by req-1 is stored in the 0th sub-buffer, and it is used as the initial word line for secondary data programming and written to the flash memory particles.

[0086] The initial word line of the preset buffer area can be overwritten with the new word line to be written to the disk. For example Figure 7 illustrated in the example shown, when the new word line to be written to the disk is obtained through req-6, the word line to be written to the disk carried by req-6 is written into the 0th sub-buffer to overwrite the word line to be written to the disk carried by req-1 (which has been written to the flash memory particles). And, the word line to be written to the disk carried by req-6 can be programmed with primary data to make it a new cached word line. That is, the new word line to be written to the disk is programmed with primary data to be a cached word line. At the same time, the selection of the initial word line, secondary data programming, and writing to the solid-state particles can be performed again to wait for the new word line to be written to the disk to overwrite it.

[0087] In an alternative embodiment, taking the sequence identifier, i.e., the writing sequence, as an example, the specific calculation formula can be as follows:

[0088] index = (wl_idx) MOD 5 Equation 2-1

[0089] Further, as illustrated by the examples in the foregoing text, there is at least one logic unit serving as a check storage unit. During the traditional data disk writing process, since the check data is calculated based on the previous word line to be written and then written into the check storage unit, and the two data programming controls of the word line to be written are controlled by the flash translation layer, both the first write and the second write of the check data require immediate calculation based on the previous word line to be written. In this process, the context information to be stored is extremely complex.

[0090] In this embodiment, the check storage unit may include a preset buffer area. Thus, when other logic units associated with the check storage unit first write the word line to be written, the first check data of the first write of the word line to be written is evaluated, and the check data is written into the check storage unit to achieve one data programming. When performing secondary data programming on the first written word line to be written, since the preset buffer area of the check storage unit has stored the first check data, if it is necessary to immediately evaluate the check data again, the first check data stored in the preset buffer area can be obtained and secondary data programming can be performed.

[0091] That is, the flash interaction module can pre-apply for buffers of N + 1 WLs during power-on initialization. When the current Parity data transfer to NAND is completed and Program starts, the data transfer module can be started to transfer the data to the pre-applied buffers. After the Program of the current WL is completed and the data has been transferred to the buffers, the Parity Program of the upper-layer WL is started to utilize the redundancy of a small number of buffers to solve the bottleneck problem of Parity calculation resources.

[0092] Thus, after receiving the check data write request, the flash interaction module can, while performing one data programming after transmitting the first check data to NAND, also start the data transfer module to transfer the data transmitted by the data transfer module to the flash interaction module to prepare data for secondary data programming.

[0093] Further, the data written in each page of QLC is 4 * 16K. Compared with 3 * 16K data written in each page of TLC NAND, it is possible to control TLC NAND to send 4 * 16K data each time to improve their compatibility, thereby further improving the data processing efficiency and flash performance of this embodiment.

[0094] In summary, the flash translation layer can be unaware of the need for secondary programming of QLC NAND. For each WL, only one write request needs to be sent for writing, significantly reducing the adaptation work of the FTL to QLC NAND. Although QLC performs two programs, the calculation of Parity can be done once, reducing the hardware's computing resource requirements by 50%. The data interaction between the FTL and the backend module can also be reduced by about 50% relatively, significantly reducing the situation of insufficient CPU load caused by data interaction and improving the backend work efficiency.

[0095] It should be noted that when the backend module stores a certain amount of data, it needs to occupy a certain amount of backend DRAM (Dynamic Random Access Memory) resources. As for the controller, its current redundant resources are sufficient for use, and there is no need to modify the original data structure to release the original DRAM resources additionally, so that the modification amount of the backend is controllable.

[0096] Moreover, through experimental tests, the data processing method of this application can improve the sequential write performance by about 8%. First, the limitation of the hardware resources for Parity calculation is solved; the FTL can achieve two data programming operations by sending only one write request, that is, the request for the Program operation between the FIL and the backend module can be reduced from two to one. At the same time, the demand bottleneck for the context of the FTL can also be solved, and it can reduce the adaptation and debugging work of the FTL caused by QLC NAND.

[0097] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0098] The embodiments of this application also provide an electronic device. Please refer to Figure 8 , Figure 8 which is a schematic structural diagram of an embodiment of the electronic device of this application.

[0099] The electronic device includes a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above data processing method embodiments.

[0100] For example, the electronic device can be a mobile phone, a server, a smart wearable device, etc., which is not limited here. Figure 8 Examples of the component modules of the server as an electronic device are given in

[0101] Embodiments of the present application also provide a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the above-described data processing method embodiments when running.

[0102] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM), random access memories (RAM), external hard drives, magnetic disks, or optical discs that can store computer programs.

[0103] Embodiments of the present application also provide a computer program product. The above computer program product includes a computer program that, when executed by a processor, implements the steps in any of the above-described data processing method embodiments.

[0104] Embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above-described data processing method embodiments.

[0105] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0106] The above has provided a detailed introduction to a data processing method, a data processing device, an electronic device, and a computer-readable storage medium provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A data processing method, characterized in that, The data processing method includes: A logic unit of a flash memory interaction module obtains word lines to be written to the disk from a flash translation layer; Write the word lines to be written to the disk into a preset buffer area of the logic unit, and perform a data programming on them to be used as temporary word lines; In response to the preset buffer area having stored a preset number of the temporary word lines, select initial word lines among them for secondary data programming and write them to the flash memory particles; wherein, the initial word lines represent the temporary word lines whose writing time is earlier than that of other temporary word lines; Use new word lines to be written to the disk to overwrite the initial word lines in the preset buffer area, and perform a data programming on the new word lines to be written to the disk to be used as temporary word lines.

2. The data processing method according to claim 1, characterized in that The preset buffer area includes the preset number of sub-buffer areas, and the preset number is the target number plus one; The target number represents the number of word lines that the logic unit supports writing in a single layer; The writing the word lines to be written to the disk into the preset buffer area of the logic unit includes: In response to there being an idle sub-buffer area in the preset buffer area, write the word lines to be written to the disk into the idle sub-buffer area.

3. The data processing method according to claim 2, wherein The writing the word lines to be written to the disk into the idle sub-buffer area includes: Obtain the currently idle sub-buffer area; Identify the starting idle area of the currently idle sub-buffer area; wherein, the starting idle area represents the idle sub-buffer area whose current storage address is less than the storage addresses of other idle sub-buffer areas; Write the word lines to be written to the disk into the starting idle area.

4. The data processing method according to claim 1, wherein Before the step of in response to the preset buffer area having stored a preset number of the temporary word lines, it includes: Obtain the sequence identifier of the word lines to be written to the disk; Compare the sequence identifier with the target number; wherein, the target number represents the number of word lines that the logic unit supports writing in a single layer; In response to the sequence identifier being greater than the target number, determine that the preset buffer area has stored a preset number of the temporary word lines.

5. The data processing method according to claim 4, wherein After the step of comparing the sequence identifier with the target number, it further includes: In response to the sequence identifier not being greater than the target number, when obtaining new word lines to be written to the disk, compare the sequence identifier of the new word lines to be written to the disk with the target number; Until the sequence identifier is greater than the target number, when obtaining new word lines to be written to the disk, do not compare its sequence identifier with the target number.

6. The data processing method according to claim 1, wherein The selecting the initial word lines among them includes: Increment the sequence identifier of the word lines to be written to the disk written to the preset buffer area last time by one to obtain a sequence factor; Increment the target number by one to obtain a comparison factor; wherein, the target number represents the number of word lines that the logic unit supports writing in a single layer; Perform a remainder operation on the sequence factor and the comparison factor to obtain a remainder factor; Use the temporary word lines stored in the sub-buffer area matching the remainder factor as the initial word lines.

7. The data processing method according to claim 1, wherein Before the step of selecting the initial word lines among them for secondary data programming, it includes: In response to the initial word lines having completed their data programming as the temporary word lines, send a completion message to the flash translation layer.

8. A data processing device, characterized in that, The data processing device includes: a flash memory interaction module for connecting to a flash translation layer and flash memory particles; The flash memory interaction module includes a preset buffer and a control unit. The preset buffer is used to temporarily store the word lines to be written to disk. The control unit is used to implement the steps of the data processing method described in any one of claims 1 to 7.

9. An electronic device, characterized in that, Comprising: A memory for storing a computer program; A processor for implementing the steps of the data processing method described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein the computer program, when executed by a processor, implements the steps of the data processing method described in any one of claims 1 to 7.

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