Cyclic redundancy check method and device and logic chip

Abstract

The invention provides a cyclic redundancy check method and device and a logic chip, and relates to the technical field of electronics. The cyclic redundancy check method comprises the following steps: acquiring to-be-processed data; splitting the to-be-processed data based on a preset bit width to generate N sub-data; performing CRC operation on the N sub-data according to a CRC matrix corresponding to a preset bit width to generate M first CRC values; and for the M first CRC values, selecting a corresponding CRC sub-matrix from the N CRC sub-matrixes according to the position of the sub-data corresponding to the current first CRC value in the data packet from the first first CRC value to the last first CRC value, performing CRC operation on the current first CRC value and the previous first CRC value to obtain M second CRC values, and performing XOR operation on the M second CRC values to determine a target CRC value. Through the method, the time sequence requirement of logic chip design can be met.

Description

Technical Field

[0001] This specification relates to the field of electronic technologies, and particularly to a cyclic redundancy check method, apparatus, and logic chip. Background Art

[0002] With the development of network technologies, the bandwidth of network devices has gradually increased, and the data to be processed has also gradually increased. Due to the demand for data processing speed, network devices have introduced a hardware forwarding method, that is, through a logic chip, such as an FPGA (Field Programmable Gate Array), to solidify the forwarding logic in the logic chip to improve the data processing and forwarding speed.

[0003] In a logic chip, data is processed beat by beat according to a clock signal. In the case of a large data bit width, a large amount of data needs to be processed in each beat. For CRC (Cyclic Redundancy Check) operations, when performing CRC operations on data with a large data bit width in one beat, the hardware logic is complex and it is difficult to meet the timing requirements of the operation module. Summary of the Invention

[0004] To overcome the problems existing in the related technologies, this specification provides a cyclic redundancy check method, apparatus, and logic chip.

[0005] According to a first aspect of an embodiment of this specification, a CRC method applied to a logic chip is provided, including:

[0006] Obtain data to be processed;

[0007] Based on a preset bit width, split the data to be processed to generate N sub-data, where N is a positive integer;

[0008] Perform CRC operations on the N sub-data respectively according to a CRC matrix corresponding to the preset bit width to generate M first CRC values, where M is a positive integer;

[0009] For the M first CRC values, from the first first CRC value to the last first CRC value, according to the position of the sub-data corresponding to the current first CRC value in the data packet, select a corresponding CRC sub-matrix from the N CRC sub-matrices, perform CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and perform an exclusive OR operation on the M second CRC values to determine a target CRC value;

[0010] Wherein, the Nth CRC sub-matrix is a default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

[0011] Optionally, after splitting the data to be processed based on a preset bit width to generate N sub-data, it includes:

[0012] Detect the validity of the N sub-data;

[0013] The step of respectively performing CRC operations on the N sub-data according to the CRC matrix corresponding to the preset bit width to generate M first CRC values includes:

[0014] Obtain the validity identifier of each sub-data;

[0015] For the valid sub-data, respectively perform CRC operations on the valid sub-data among the N sub-data according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0016] Optionally, after splitting the data to be processed based on a preset bit width to generate N sub-data, it further includes:

[0017] Record the position information of each sub-data in the data packet.

[0018] Optionally, the data to be processed contains at least two data packets;

[0019] The step of recording the position information of each sub-data in the data packet is specifically

[0020] Record the data packet identifier of the data packet to which each sub-data belongs and the position information in the data packet to which it belongs;

[0021] The step of performing an exclusive OR operation on the M second CRC values to determine the target CRC value is specifically:

[0022] According to the data packet identifier, respectively perform exclusive OR operations on the second CRC values belonging to the same data packet among the M second CRC values to determine at least two target CRC values.

[0023] According to the second aspect of the embodiments of the present specification, a CRC device is provided, which is applied to a logic chip and includes:

[0024] An acquisition unit, configured to acquire data to be processed;

[0025] A splitting unit, configured to split the data to be processed based on a preset bit width to generate N sub-data, where N is a positive integer;

[0026] A first CRC unit, configured to respectively perform CRC operations on the N sub-data according to the CRC matrix corresponding to the preset bit width to generate M first CRC values, where M is a positive integer and M ≤ N;

[0027] A second CRC unit, configured to, for M first CRC values, from the first first CRC value to the last first CRC value, select a corresponding CRC sub-matrix from N CRC sub-matrices according to the position of the sub-data corresponding to the current first CRC value in the data packet, perform CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and perform an exclusive OR operation on the M second CRC values to determine a target CRC value;

[0028] Wherein, the Nth CRC sub-matrix is a default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

[0029] Optionally, the splitting unit is further configured to detect the validity of N sub-data;

[0030] The first CRC unit is further configured to obtain a validity identifier for each sub-data; for valid sub-data, perform CRC operations on the valid sub-data in the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0031] Optionally, the splitting unit is further configured to record the position information of each sub-data in the data packet.

[0032] Optionally, the data to be processed includes at least two data packets;

[0033] The splitting unit is specifically configured to record the data packet identifier to which each sub-data belongs and the position information in the data packet to which it belongs;

[0034] During the process of performing an exclusive OR operation on the M second CRC values to determine a target CRC value, the second CRC unit is specifically configured to, according to the data packet identifier, perform an exclusive OR operation on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

[0035] According to a third aspect of the embodiments of the present specification, a logic chip is provided, including:

[0036] A first register, configured to obtain and record the data to be processed;

[0037] N second registers, configured to record the data to be processed according to a preset bit width, so that the data to be processed is split into N sub-data, where N is a positive integer;

[0038] N first CRC arithmetic units, each first CRC arithmetic unit is configured to calculate a first CRC value of a sub-data according to the CRC matrix corresponding to the preset bit width;

[0039] N second CRC calculators, where the second CRC calculation is used to select a corresponding CRC sub - matrix from N CRC sub - matrices according to the position of the sub - data corresponding to the current first CRC value in the data packet, perform a CRC calculation on the current first CRC value and the previous first CRC value to obtain a second CRC value, and perform an exclusive - OR operation on the calculated second CRC value to determine the target CRC value;

[0040] Among them, the Nth CRC sub - matrix is the default matrix, and the ith CRC sub - matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

[0041] Optionally, the second register is further configured to record the validity of N sub - data, where among the N sub - data, there are M valid sub - data, and M is a positive integer;

[0042] The first CRC calculator is further configured to obtain the effectiveness identifier of each sub - data; for the valid sub - data, perform a CRC calculation on the M valid sub - data among the N sub - data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0043] Optionally, the second register is further configured to record the position information of each sub - data in the data packet.

[0044] Optionally, the data to be processed includes at least two data packets;

[0045] The second register is specifically configured to record the data - packet identifier of the data packet to which each sub - data belongs and the position information in the data packet to which it belongs, and record the position information in the second register;

[0046] When performing an exclusive - OR operation on the M second CRC values to determine the target CRC value, the second CRC calculator is specifically configured to, according to the data - packet identifier, perform an exclusive - OR operation on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

[0047] The technical solutions provided by the embodiments of this specification may include the following beneficial effects:

[0048] In the embodiments of this specification, through the above method, data to be processed with a large bit width can be split into N sub-data by a preset bit width, and a first CRC value is obtained by performing CRC operations on the N sub-data based on a CRC matrix corresponding to the preset bit width. Thereafter, according to the positions of the sub-data corresponding to the first CRC value in the data packet, a CRC sub-matrix associated with the sub-data corresponding to the current first CRC value is selected from the N CRC sub-matrices, and a second CRC value is determined by performing CRC operations on the current first CRC value and the previous first CRC value, and the target CRC value is iteratively generated to reduce the data bit width during the CRC operation and meet the timing requirements of the logic chip design.

[0049] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit this specification. Brief Description of the Drawings

[0050] The drawings herein are incorporated into the specification and form a part of this specification, showing embodiments consistent with this specification, and are used together with the specification to explain the principles of this specification.

[0051] Figure 1 is a flowchart of a CRC method involved in this application;

[0052] Figure 2 is a schematic structural diagram of a logic chip involved in this application;

[0053] Figure 3 is a schematic structural diagram of a CRC device involved in this application. Detailed Embodiments

[0054] Here, the exemplary embodiments will be described in detail, and the examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this specification. On the contrary, they are merely examples of devices and methods consistent with some aspects of this specification as detailed in the appended claims.

[0055] The terms used in this specification are only for the purpose of describing specific embodiments and are not intended to limit this specification. The singular forms "a", "the", and "said" used in this specification and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0056] It should be understood that although the terms first, second, third, etc. may be used in this specification to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this specification, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "when" or "while" or "in response to a determination".

[0057] This application provides a CRC method, as Figure 1 shown, applied to a logic chip, including:

[0058] S100. Obtain data to be processed.

[0059] The data to be processed may be a data packet received by a network device, and the data packet has a certain data bit width. When the logic chip receives the data packet, it is written into the storage space of the logic chip. This storage space can be implemented by a first register. The space size of the first register can be set to be slightly more than 1024 bits, that is, at most 1024 bits of data can be processed in one clock signal beat. The extra bits are used to store relevant parameters of the data to be processed, such as validity identification, start identification, end identification, and the position of invalid data. In the case where the size of a data packet is small, multiple data packets can be written into the first register and processed in one beat. For example, if the size of a data packet is 256 bits, multiple data packets can be written into the first register for processing.

[0060] S101. Split the data to be processed based on a preset bit width to generate N sub-data.

[0061] Where N is a positive integer.

[0062] The preset bit width can be set according to actual needs. For example, if it is set to 64 bits, then in the case where the data to be processed is 1024 bits, 16 sub-data can be formed, that is, N = 16. The value of N can vary according to the preset bit width. For example, when the preset bit width is 128, then N = 8, and it can be set according to actual needs without limitation. The sub-data formed after splitting can be stored in another storage space of the logic chip. This storage space can be formed by a second register. Each second register can store data of 64 preset bit widths, that is, N second registers are set.

[0063] When splitting the data to be processed, it is also possible to detect the validity of the data to be processed, record the identification of the data packet, and generate the position of the sub-data in the data packet, etc., based on the identification of the data to be processed, and it can be set according to actual needs.

[0064] When writing multiple data packets into the first register, there may be invalid data between the data packets. When splitting, it is possible to determine whether the split data is valid and record the validity flag in the second register storing the partial sub-data. For example, the validity flag can be one bit. When the validity flag is set to the first value (such as 1), the sub-data can be considered valid data. When the validity flag is set to the second value (such as 0), the sub-data can be considered invalid data.

[0065] S102. Perform CRC operations on N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0066] A CRC matrix can be stored in the logic chip. When the selected CRC polynomial (such as CRC-32) and the data bit width (i.e., the preset bit width) are determined, a fixed CRC matrix can be determined for performing CRC operations on the sub-data.

[0067] Specifically, the CRC matrix for performing CRC operations on the split sub-data is

[0068]

[0069] wherein, dw represents the bit width of the sub-data, cq represents the length of the CRC value required by the CRC operation, and each element in the matrix is a fixed value 0 or 1 after the CRC polynomial (such as CRC-32) and the data bit width are determined, which can be obtained by calculation.

[0070] N first CRC calculators can be set in the logic chip to perform exclusive OR operations on the CRC matrix and each sub-data respectively. That is to say, the CRC operation can be understood as an exclusive OR operation to obtain M first CRC values, where M is a positive integer.

[0071] The quantity of M is related to N and the valid data in the data to be processed. When the data to be processed contains invalid data, the first CRC calculator can obtain the validity flag recorded in the second register. When it is determined that the validity flag is the second value, it is determined that the sub-data can not perform the CRC operation. Therefore, M < N. When all the data to be processed is valid data, the first CRC calculator can determine that the validity flag is the first value and determine that all sub-data need to perform the CRC operation. At this time, M = N. When it is possible to process multiple data packets, it may be necessary to divide into 2N second CRC calculators, which can be set according to actual needs without limitation.

[0072] S103. For the M first CRC values, from the first first CRC value to the last first CRC value, according to the position of the sub-data corresponding to the current first CRC value in the data packet, select the corresponding CRC sub-matrix from the N CRC sub-matrices, perform CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and perform an exclusive OR operation on the M second CRC values to determine the target CRC value.

[0073] Since the data to be processed is divided into N sub-data, after the logic chip calculates the M first CRC values, it is still necessary to process the M first CRC values to obtain the second CRC values and determine the target CRC value. This target CRC value can be understood as the complete CRC value of the data to be processed.

[0074] In the original implementation, when directly performing CRC operations on the complete data to be processed to obtain the target CRC value, when a data packet is too large to exceed the limit that can be processed in one cycle, an iteration of exclusive OR operations is required between multiple cycles of data to be processed, that is, an exclusive OR operation is performed based on the current data to be processed, the CRC value of the previous data to be processed, and the CRC matrix to obtain the CRC value of the current data to be processed.

[0075] Based on the same principle, in this application, since the data to be processed is split, the M first CRC values obtained for the sub-data need to be based on the first CRC value of the current sub-data, the previous first CRC value, and the influence of the split CRC sub-matrix to obtain the second CRC value, and an exclusive OR operation is performed on the obtained second CRC values to obtain the target CRC value of the current data to be processed.

[0076] In this process, if the object of the current CRC operation is not the first first CRC value, the previous first CRC value can be the first CRC value of the previous sub-data corresponding to the current first CRC value, that is, the previous first CRC value. If the object of the CRC operation is the first first CRC value, the previous first CRC value can be the default CRC value in the CRC operation. This default CRC value is a determined value when the CRC algorithm and bit width are determined.

[0077] In the process of calculating the second CRC value based on the first CRC value, it needs to be implemented through the CRC sub-matrix. For the data to be processed in one cycle, based on the position of each sub-data in the data packet, N different CRC sub-matrices need to be determined. These CRC sub-matrices are obtained by iterating the CRC matrix Ad.

[0078] Among them, the Nth CRC sub-matrix is the default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N. This CRC sub-matrix can be considered to be marked as Ac0 to Ac (N-1) There are N in total. These Ac0 to Ac (N-1) can be understood as being obtained by iterating the CRC matrix Ad from 0 to N - 1, and the last CRC sub-matrix does not need to be iterated.

[0079] When performing CRC operations, for the position information of each sub-data in the data packet, the corresponding CRC sub-matrix can be selected for calculation to obtain at most N second CRC values, and the target CRC value of the data to be processed is obtained through the exclusive OR operation of the obtained second CRC values.

[0080] The above method can be implemented by a logic chip, such as Figure 2 shown, including:

[0081] A first register for obtaining and recording the data to be processed;

[0082] N second registers for recording the data to be processed according to a preset bit width, so that the data to be processed is split into N sub-datas, where N is a positive integer;

[0083] N first CRC arithmetic units, storing a CRC matrix with a preset bit width, and performing an exclusive OR operation on the sub-data obtained from the second register to generate a first CRC value;

[0084] N second CRC arithmetic units, each of which stores a CRC sub-matrix corresponding to the position of the corresponding data packet, performs an exclusive OR operation on a first CRC value obtained from the first CRC arithmetic unit, the CRC sub-matrix corresponding to the first CRC value, and the previous first CRC value of the first CRC value to obtain a second CRC value, and performs an exclusive OR operation based on at most N second CRC values to obtain the target CRC value of the data to be processed.

[0085] In the second CRC arithmetic unit, a data packet selector and a position selector can be set, where the data packet selector is used to determine the data packet corresponding to the current first CRC value, and the position selector is used to determine the position of the sub-data corresponding to each first CRC value in the data packet.

[0086] The technical solutions provided by the embodiments of this specification may include the following beneficial effects:

[0087] In the embodiments of this specification, through the above method, the to-be-processed data with a large bit width can be split into N sub-data through a preset bit width, and the first CRC value is obtained by performing CRC operations on the N sub-data based on the CRC matrix corresponding to the preset bit width. After that, according to the positions of the sub-data corresponding to the first CRC value in the data packet, the CRC sub-matrix associated with the sub-data corresponding to the current first CRC value is selected from the N CRC sub-matrices, and the second CRC value is determined by performing CRC operations on the current first CRC value and the previous first CRC value, and the target CRC value is iteratively generated to reduce the data bit width during the CRC operation and meet the timing requirements of the logic chip design.

[0088] Optionally, after the step S101 of splitting the to-be-processed data based on a preset bit width to generate N sub-data, it includes:

[0089] S104. Detect the validity of the N sub-data.

[0090] The invalid position information of the position where the invalid data is located can also be recorded in the first register for recording the to-be-processed data. During the process of splitting the to-be-processed data and writing it into the N second registers, the validity of the sub-data written into a second register can be marked according to the invalid position information, that is, set as the validity identifier in this second register.

[0091] The step S102 of performing CRC operations on the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values includes:

[0092] S102A. Obtain the validity identifier of each sub-data.

[0093] S102B. For the valid sub-data, perform CRC operations on the valid sub-data among the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0094] During the process of the first CRC calculator calculating the first CRC value, the validity identifier can be used to determine whether the sub-data in the current second register is valid data. If it is valid, the CRC operation is performed; if it is invalid, the CRC operation is not performed.

[0095] After excluding the invalid data based on the above method, it is only necessary to generate the first CRC value for the M valid data to meet the requirements, reducing the CRC operation amount of the logic chip.

[0096] Optionally, after the step S101 of splitting the to-be-processed data based on a preset bit width to generate N sub-data, it further includes:

[0097] S105. Record the position information of each sub - data in the data packet.

[0098] By recording the position information of a sub - data in the data packet in the second register, the second CRC calculator can select the corresponding CRC sub - matrix according to this position information to calculate the second CRC value.

[0099] Furthermore, the data to be processed contains at least two data packets, that is, in one clock signal beat, CRC operations can be performed on the data of multiple data packets.

[0100] The step S105, recording the position information of each sub - data in the data packet, specifically is:

[0101] Record the data packet identifier of each sub - data's belonging data packet and the position information in the belonging data packet.

[0102] When calculating the first CRC value, it can be determined whether the sub - data belongs to the same data packet based on the start identifier (SOP) and end identifier (EOP) recorded in the second register. When storing the data to be processed, the start identifier and end identifier of the data to be processed are recorded. That is to say, the data between the start identifier and the end identifier can be considered as the data belonging to one data packet.

[0103] When the first CRC calculator calculates the first CRC value of the sub - data, it can determine whether the previous sub - data belongs to the same data packet according to whether there is an end identifier in the second register and mark them in sequence. That is, when the start identifier is detected, the subsequent sub - data is marked as pkt0 until the end identifier is detected. After detecting the next start identifier, the subsequent sub - data is marked as pkt1 until the end identifier is detected. And so on, to complete the calculation of the first CRC value of the sub - data within one beat.

[0104] The step S103, performing an exclusive - OR operation on M second CRC values to determine the target CRC value, specifically is:

[0105] According to the data packet identifier, perform an exclusive - OR operation on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

[0106] When calculating the second CRC value, perform an exclusive - OR operation on several second CRC values of the same data packet once to determine the target CRC value required for this data packet. In the case of multiple data packets, multiple target CRC values can be determined. These calculated target CRC values will be appended to the tail of the data packet for transmission, thus realizing the CRC verification process when data is transmitted between network devices.

[0107] Correspondingly, the present application further provides a CRC device, as Figure 3 shown, which is applied to a logic chip and includes:

[0108] An acquisition unit, configured to acquire data to be processed;

[0109] A splitting unit, configured to split the data to be processed based on a preset bit width to generate N sub-data, where N is a positive integer;

[0110] A first CRC unit, configured to perform CRC operations on the N sub-data respectively according to a CRC matrix corresponding to the preset bit width to generate M first CRC values, where M is a positive integer and M ≤ N;

[0111] A second CRC unit, configured to, for the M first CRC values, from the first first CRC value to the last first CRC value, select a corresponding CRC sub-matrix from N CRC sub-matrices according to the position of the sub-data corresponding to the current first CRC value in the data packet, perform CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and perform an exclusive OR operation on the M second CRC values to determine a target CRC value;

[0112] Wherein, the Nth CRC sub-matrix is a default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

[0113] Optionally, the splitting unit is further configured to detect the validity of the N sub-data;

[0114] The first CRC unit is further configured to obtain a validity identifier for each sub-data; for valid sub-data, perform CRC operations on the valid sub-data among the N sub-data respectively according to a CRC matrix corresponding to the preset bit width to generate M first CRC values.

[0115] Optionally, the splitting unit is further configured to record the position information of each sub-data in the data packet.

[0116] Further, the data to be processed includes at least two data packets;

[0117] The splitting unit is specifically configured to record the data packet identifier of each sub-data's belonging data packet and the position information in the belonging data packet;

[0118] During the process of performing an exclusive OR operation on the M second CRC values to determine a target CRC value, the second CRC unit is specifically configured to, according to the data packet identifier, perform exclusive OR operations on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

[0119] Correspondingly, the present application further provides a logic chip, as Figure 2 shown, including:

[0120] A first register for obtaining and recording data to be processed;

[0121] N second registers for recording data to be processed according to a preset bit width, so that the data to be processed is split into N sub-data, where N is a positive integer;

[0122] N first CRC calculators for calculating a first CRC value of a sub-data according to a CRC matrix corresponding to the preset bit width;

[0123] N second CRC calculators, where the second CRC calculation is used to select a corresponding CRC sub-matrix from N CRC sub-matrices according to the position of the sub-data corresponding to the current first CRC value in the data packet, perform a CRC operation on the current first CRC value and the previous first CRC value to obtain a second CRC value, and perform an exclusive OR operation on the calculated second CRC value to determine a target CRC value;

[0124] Among them, the Nth CRC sub-matrix is a default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

[0125] Optionally, the second register is further configured to record the validity of N sub-data, where N sub-data includes M valid sub-data, and M is a positive integer;

[0126] The first CRC calculator is further configured to obtain a validity identifier of each sub-data; for valid sub-data, perform a CRC operation on M valid sub-data among N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values; or,

[0127] The second register is further configured to record the position information of each sub-data in the data packet; or,

[0128] The data to be processed includes at least two data packets;

[0129] The second register is specifically configured to record the data packet identifier of each sub-data's belonging data packet and the position information in the belonging data packet, and record the position information in the second register;

[0130] The second CRC calculator is specifically configured to perform exclusive OR operations on the second CRC values belonging to the same data packet among the M second CRC values according to the data packet identifier to determine at least two target CRC values during the process of performing exclusive OR operations on the M second CRC values to determine the target CRC value.

[0131] The technical solutions provided by the embodiments of this specification may include the following beneficial effects:

[0132] In the embodiments of this specification, through the above method, the data to be processed with a larger bit width can be split into N sub-data by a preset bit width, and the first CRC value is obtained by performing CRC operations on the N sub-data based on the CRC matrix corresponding to the preset bit width. Thereafter, according to the position of the sub-data corresponding to the first CRC value in the data packet, the CRC sub-matrix associated with the sub-data corresponding to the current first CRC value is selected from the N CRC sub-matrices, and the second CRC value is determined by performing CRC operations on the current first CRC value and the previous first CRC value and iteratively generating the target CRC value, so as to reduce the data bit width during the CRC operation and meet the timing requirements of the logic chip design.

[0133] The implementation processes of the functions and roles of each module in the above device are specifically described in the implementation processes of the corresponding steps in the above method, and will not be repeated here.

[0134] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can refer to the partial descriptions of the method embodiments. The device embodiments described above are only illustrative. The modules described as separate components may or may not be physically separated, and the components shown as modules may or may not be physical modules, that is, they may be located in one place, or may be distributed to multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this specification. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0135] The specific embodiments of this specification are described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired results. Additionally, the processes depicted in the figures do not necessarily require the particular order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0136] Those skilled in the art will readily conceive of other embodiments of the present specification after considering the specification and practicing the invention claimed herein. The present specification is intended to cover any variations, uses, or adaptations of the present specification, which follow the general principles of the present specification and include common general knowledge or conventional technical means in the technical field not claimed in the present specification. The specification and examples are only regarded as exemplary, and the true scope and spirit of the present specification are pointed out by the following claims.

[0137] It should be understood that the present specification is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present specification is only limited by the appended claims.

[0138] The above are only the preferred embodiments of the present specification and are not intended to limit the present specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present specification shall be included within the scope of protection of the present specification.

Claims

1. A cyclic redundancy check (CRC) method, characterized in that, Applied to a logic chip, including: Obtain data to be processed; Split the data to be processed based on a preset bit width to generate N sub-data, where N is a positive integer; Perform CRC operations on the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values, where M is a positive integer; For the M first CRC values, from the first first CRC value to the last first CRC value, according to the position of the sub-data corresponding to the current first CRC value in the data packet, select the corresponding CRC sub-matrix from the N CRC sub-matrices, perform CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and perform an exclusive OR operation on the M second CRC values to determine the target CRC value; Among them, the Nth CRC sub-matrix is the default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

2. The method according to claim 1, characterized in that, After splitting the data to be processed based on the preset bit width to generate N sub-data, it includes: Detect the validity of the N sub-data; The step of performing CRC operations on the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values includes: Obtain the validity identifier of each sub-data; For the valid sub-data, perform CRC operations on the valid sub-data among the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

3. The method according to claim 1, wherein After splitting the data to be processed based on the preset bit width to generate N sub-data, it further includes: Record the position information of each sub-data in the data packet.

4. The method according to claim 3, characterized in that, The data to be processed contains at least two data packets; The step of recording the position information of each sub-data in the data packet is specifically Record the data packet identifier of the data packet to which each sub-data belongs and the position information in the belonging data packet; The step of performing an exclusive OR operation on the M second CRC values to determine the target CRC value is specifically: According to the data packet identifier, perform an exclusive OR operation on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

5. A CRC device, characterized in that, Applied to a logic chip, including: An acquisition unit for obtaining data to be processed; A splitting unit for splitting the data to be processed based on a preset bit width to generate N sub-data, where N is a positive integer; A first CRC unit for performing CRC operations on the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values, where M is a positive integer; A second CRC unit for, for the M first CRC values, from the first first CRC value to the last first CRC value, according to the position of the sub-data corresponding to the current first CRC value in the data packet, selecting the corresponding CRC sub-matrix from the N CRC sub-matrices, performing CRC operations on the current first CRC value and the previous first CRC value to obtain M second CRC values, and performing an exclusive OR operation on the M second CRC values to determine the target CRC value; Among them, the Nth CRC sub-matrix is the default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

6. The device according to claim 5, characterized in that, The splitting unit is further configured to detect the validity of N sub-data. The first CRC unit is further configured to obtain the validity identifier of each sub-data; for the valid sub-data, perform CRC operations on the valid sub-data among the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values.

7. The device according to claim 5, characterized in that The splitting unit is further configured to record the position information of each sub-data in the data packet.

8. The device according to claim 7, characterized in that, The data to be processed includes at least two data packets. Specifically, the splitting unit is configured to record the data packet identifier of the data packet to which each sub-data belongs and the position information in the data packet to which it belongs. In the process of performing an exclusive OR operation on the M second CRC values to determine the target CRC value, the second CRC unit is specifically configured to, according to the data packet identifier, perform an exclusive OR operation on the second CRC values belonging to the same data packet among the M second CRC values respectively to determine at least two target CRC values.

9. A logic chip, characterized in that, It includes: A first register for obtaining and recording the data to be processed. N second registers for recording the data to be processed according to the preset bit width, so that the data to be processed is split into N sub-data, where N is a positive integer. N first CRC calculators, each first CRC calculator is used to calculate the first CRC value of a sub-data according to the CRC matrix corresponding to the preset bit width. N second CRC calculators, the second CRC operation is used to select the corresponding CRC sub-matrix from the N CRC sub-matrices according to the position of the sub-data corresponding to the current first CRC value in the data packet, perform a CRC operation on the current first CRC value and the previous first CRC value to obtain a second CRC value, and perform an exclusive OR operation on the calculated second CRC values to determine the target CRC value. Among them, the Nth CRC sub-matrix is the default matrix, and the ith CRC sub-matrix is formed by iterating the CRC matrix N - i times, where i is a positive integer and i < N.

10. The logic chip according to claim 9, wherein The second register is further configured to record the validity of the N sub-data, where there are M valid sub-data among the N sub-data, and M is a positive integer and M ≤ N. The first CRC calculator is further configured to obtain the validity identifier of each sub-data; for the valid sub-data, perform CRC operations on the M valid sub-data among the N sub-data respectively according to the CRC matrix corresponding to the preset bit width to generate M first CRC values; or The second register is further configured to record the position information of each sub-data in the data packet; or The data to be processed includes at least two data packets. Specifically, the second register is configured to record the data packet identifier of the data packet to which each sub-data belongs and the position information in the data packet to which it belongs, and record the position information in the second register. The second CRC calculator is specifically configured to perform exclusive OR operations on the second CRC values belonging to the same data packet among the M second CRC values according to the data packet identifier to determine at least two target CRC values in the process of performing exclusive OR operations on the M second CRC values to determine the target CRC value.

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