A vector coprocessor and vector calculation method

Abstract

The present application discloses a vector coprocessor and a vector computing method, relating to the field of processor technology. The vector coprocessor includes: an arbitration module, a distributor module, a functional module, and a data path; the arbitration module is used to receive computing tasks from a main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks from the computing tasks; the distributor module is used to determine the parallelism and task queue of the vector tasks, and dispatch the vector tasks based on the parallelism and task queue; the functional module is used to decompose the vector task into multiple subtasks and determine the data path corresponding to each subtask; the subtasks are assigned to the data path, and the computing results corresponding to each data path are reduced to generate the target result corresponding to the vector task; the data path is used to calculate the subtasks and send the computing results to the functional module. This avoids redundant data storage and improves the processor's work efficiency in vector computing.

Description

Technical Field

[0001] The present application relates to the field of processor technology, and in particular to a vector coprocessor and a vector calculation method. Background Art

[0002] Current technology limits general-purpose processors when it comes to vector computing tasks. Integrating a vector computing unit in every core of a multi-core CPU architecture would significantly increase chip area and power consumption. For example, a 16-core system would require 16 sets of vector modules to be integrated, resulting in significant redundancy in hardware resources.

[0003] The architectural design of general-purpose processors is oriented towards versatility, and it is difficult to deeply optimize vector calculations (such as matrix operations, convolution, and large-scale data reduction), resulting in low computing efficiency. Especially in data-intensive scenarios such as AI training and scientific simulations, it is difficult to meet the requirements of high throughput and low latency. Summary of the Invention

[0004] The present application provides a vector coprocessor and a vector calculation method to solve the problems of hardware redundancy and low energy efficiency in traditional solutions.

[0005] In a first aspect, the present application provides a vector coprocessor, comprising an arbitration module, a distributor module, a functional module, and a data path;

[0006] The arbitration module is used to receive computing tasks from the main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks from the computing tasks;

[0007] The dispatcher module is used to determine the parallelism and task queue of vector tasks, and dispatch vector tasks according to the parallelism and task queue;

[0008] The functional module is used to decompose the vector task into multiple subtasks and determine the data path corresponding to each subtask; assign the subtasks to the data path and reduce the calculation results corresponding to each data path to generate the target result corresponding to the vector task;

[0009] The data path is used to calculate subtasks and send the calculation results to the functional modules.

[0010] In a second aspect, the present application provides a vector calculation method, which is applied to the vector coprocessor of the first aspect, including:

[0011] When receiving a vector task from the main processor, the coprocessor's corresponding dispatcher module determines the parallelism and task queue of the vector task;

[0012] Sending the vector task to the corresponding functional module of the coprocessor according to the task queue, so that the functional module decomposes the vector task into multiple subtasks according to a preset decomposition rule;

[0013] Determine the target path corresponding to the subtask based on the degree of parallelism and the real-time load of each data path;

[0014] And send the subtasks to the corresponding target path, so that the target path calculates the calculation results corresponding to each subtask;

[0015] Reduce each calculation result to the target result corresponding to the vector task;

[0016] Send the target result to the main processor.

[0017] This application significantly optimizes resource utilization and computing efficiency by decoupling vector computing tasks from the main processor core and designing independent coprocessor modules. This architecture not only supports wide-bitwidth or multi-channel parallel computing but also enables dynamic mounting and data consistency management of multiple coprocessors through the coordinated design of crossbar switches and L1 caches. This effectively addresses the hardware redundancy, energy inefficiency, and scalability issues inherent in traditional solutions, providing an efficient and flexible solution for data-intensive applications.

[0018] The further effects of the above-mentioned non-conventional preferred embodiment will be described below in conjunction with specific embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the existing technical solutions, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in this application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0020] Figure 1 A schematic diagram of the structure of a vector coprocessor provided in one embodiment of the present application;

[0021] Figure 2 A schematic structural diagram of an arbitration module in a vector coprocessor provided in one embodiment of the present application;

[0022] Figure 3 A schematic structural diagram of a distributor module in a vector coprocessor provided in one embodiment of the present application;

[0023] Figure 4 A schematic diagram of the structure of functional modules in a vector coprocessor provided in one embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of a data path in a vector coprocessor provided in one embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of a computing unit in a data path of a vector coprocessor provided in one embodiment of the present application;

[0026] Figure 7 A flowchart of a vector calculation method provided in one embodiment of the present application. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of this application more clear, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0028] Current technology limits general-purpose processors when it comes to vector computing tasks. Integrating a vector computing unit in every core of a multi-core CPU architecture would significantly increase chip area and power consumption. For example, a 16-core system would require 16 sets of vector modules to be integrated, resulting in significant redundancy in hardware resources.

[0029] The architectural design of general-purpose processors is oriented towards versatility, and it is difficult to deeply optimize vector calculations (such as matrix operations, convolution, and large-scale data reduction), resulting in low computing efficiency. Especially in data-intensive scenarios such as AI training and scientific simulations, it is difficult to meet the requirements of high throughput and low latency.

[0030] In view of this, the present application provides a vector coprocessor. Figure 1 1 is a specific embodiment of the vector coprocessor provided by the present application. In this embodiment, the vector coprocessor includes: an arbitration module 101 , a distributor module 102 , a functional module 103 and a data path 104 .

[0031] The arbitration module is used to receive computing tasks from the main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks from the computing tasks.

[0032] The dispatcher module is used to determine the parallelism and task queue of vector tasks and dispatch vector tasks according to the parallelism and task queue.

[0033] The functional module is used to decompose the vector task into multiple subtasks and determine the data path corresponding to each subtask; assign the subtasks to the data path and reduce the calculation results corresponding to each data path to generate the target result corresponding to the vector task.

[0034] The data path is used to calculate subtasks and send the calculation results to the functional modules.

[0035] The vector coprocessor can be connected to the main processor's L1 cache via a crossbar switch. The main processor is preferably a RISC-V architecture processor because RISC-V is an open-source processor. RISC-V's modular instruction set allows developers to directly optimize hardware interaction processes through custom extensions (such as adding coprocessor-specific instructions). For example, by extending vector memory access instructions or coprocessor control instructions, the main processor can dispatch tasks to the coprocessor with lower latency while reducing data transfer overhead.

[0036] like Figure 2 Figure 1 is a schematic diagram of the arbitration module in this embodiment. The arbitration module includes a parsing unit 1011 and a feedback unit 1012. The parsing unit is used to parse the computing task to identify whether it is a vector task. The feedback unit is used to send the vector task to the dispatcher module if the computing task is a vector task. If the computing task is not a vector task, it generates a rejection signal and returns the computing task to the main processor.

[0037] The arbitration module, serving as the entry point to the coprocessor, is responsible for receiving and classifying computing tasks issued by the main processor. The module's built-in parsing unit dynamically identifies task types by deeply analyzing the instruction stream issued by the main processor. For example, it determines whether a task is a vector calculation based on the instruction opcode, data format, and memory access pattern. If a scalar operation or control instruction is detected, it is classified as a non-vector task.

[0038] The feedback unit performs dynamic task allocation based on the parsing results. For identified vector tasks, the feedback unit pushes them to the dispatcher module via a dedicated channel. If a compute task is determined to be non-vector, the feedback unit generates a rejection signal and returns the task to the main processor via a crossbar switch, ensuring that the main core can promptly retrieve the task and redistribute it to other execution units.

[0039] like Figure 3 Figure 1 shows a schematic diagram of the dispatcher module in this embodiment. The dispatcher module includes a queue management unit 1021 and a parallelism decision unit 1022. The queue management unit is configured to receive vector tasks sent by the arbitration module and create a task queue based on preset priority rules. The parallelism decision unit is configured to analyze the task characteristics corresponding to the vector tasks and determine the corresponding parallelism based on the task characteristics.

[0040] The dispatcher module achieves efficient task allocation and resource optimization through a multi-level coordination mechanism. The queue management unit receives vector tasks from the arbitration module and sorts the tasks according to preset priority rules (such as task urgency, data dependency, or instruction type). For example, in an AI inference scenario, real-time inference requests may be marked as high priority and enter the queue before offline training tasks; for continuous tasks with data dependencies (such as multi-stage matrix decomposition), the queue management unit will ensure the execution order through a label association mechanism to avoid calculation errors caused by out-of-order processing. The queue scheduling strategy (such as FIFO, polling, or preemptive) can be dynamically configured according to the application scenario to adapt to different needs from low-latency real-time computing to high-throughput batch processing.

[0041] The parallelism decision unit dynamically determines the optimal degree of parallelism by analyzing the characteristic parameters of the vector task (such as data size, instruction complexity, and memory access pattern). For example, when processing a 2048-dimensional vector multiplication and addition operation, if the bit width of each data path is 128 bits, the parallelism decision unit can determine to apply 16 data paths for the operation. In addition, the parallelism decision unit can also monitor the load status of the data path in real time, and then make dynamic trade-offs based on the task characteristics. For example, in compute-intensive tasks, the parallelism is maximized to improve throughput, while in memory-intensive tasks, the parallelism is moderately reduced to reduce cache occupancy.

[0042] like Figure 4 Figure 1 is a schematic diagram of the functional modules in this embodiment. The functional modules include a reduction unit 1031 and a register control unit 1032. The reduction unit is used to decompose the vector task into subtasks and distribute the subtasks in parallel to each data path; perform a reduction operation on the calculation results corresponding to each data path to generate a target result; and the register control unit is used to temporarily store the calculation results corresponding to each data path model and send the target result to the main processor via the main processor's corresponding L1 cache.

[0043] The functional modules decompose vector tasks and integrate computational results. The reduction unit receives vector tasks from the distributor module and splits them into subtasks of appropriate granularity based on the datapath's bit width and parallelism. For example, when processing a large-scale matrix multiplication, the reduction unit might partition the tasks into blocks by row or column, assigning each subblock to a different datapath and marking dependencies between subtasks to maintain computational correctness.

[0044] After subtasks complete computation in the datapath, the reduction unit aggregates the scattered intermediate results using hardware-level reduction trees (such as addition trees and maximum trees) or software-configurable modes (such as accumulation, multiplication-accumulation, and multiply-add fusion). For example, during gradient descent in AI training, the reduction unit can accumulate local gradients output by multiple datapaths into a global gradient. This process achieves low latency through a multi-stage pipeline design and supports dynamic switching of reduction modes to adapt to different algorithm requirements.

[0045] The register control unit is responsible for data transfer and consistency. Upon completion, the calculation results of each data path are temporarily stored in the unit's distributed register bank. This design can adopt a double buffering mechanism. While one set of registers receives new results, the other set batches ready data into the main processor's L1 cache, thereby minimizing data transmission delays.

[0046] The register control unit also ensures the timing consistency of the results of multiple data paths through a tag matching mechanism. For example, in a reduction operation, the aggregation operation of the reduction unit is triggered only when the results of all related subtasks are ready, avoiding errors caused by missing data.

[0047] like Figure 5 Figure 1 is a schematic diagram of the data path structure in this embodiment. The data path includes a data controller unit 1041, a buffer unit 1042, a calculation unit 1043, and a write-back unit 1044. The data controller unit is used to receive calculation requests from functional modules and feedback a data-ready signal; the buffer unit is used to sequentially buffer subtasks and temporarily store intermediate data for multi-cycle calculations; the calculation unit is used to calculate the subtasks and generate calculation results; and the write-back unit is used to send the calculation results to the register control unit.

[0048] The datapath, as the actual execution unit of the computation, achieves efficient task execution and data flow management through a pipelined design. The data controller unit is responsible for receiving computation requests from functional modules and coordinating the data transmission rhythm through a two-way handshake protocol.

[0049] The front-end input buffer of the buffering unit sequentially arranges subtask data to address misalignment issues caused by differences in task distribution timing or data arrival speed. For example, in convolution operations, this ensures that sliding window data is fed into the computation unit block by block according to the computation cycle. The back-end has a multi-cycle temporary storage area for storing intermediate results of long-latency computations. For example, in iterative reduction tasks, partial sums are cyclically written to the buffer until the final result is generated.

[0050] The computing unit is composed of a vector multiplication subunit and a vector arithmetic logic subunit, which work together to cover the diverse needs of vector computing. Figure 6FIG2 is a schematic diagram of the structure of the computing unit in this embodiment. The computing unit includes a vector multiplication subunit 4301 and a vector arithmetic logic subunit 4302. The vector multiplication subunit is used to perform vector multiplication operations; the vector arithmetic logic subunit is used to perform vector addition, subtraction, shift, and logical operations.

[0051] The vector multiplication subunit is designed specifically for high-density multiplication operations. It supports massively parallel vector multiplication through hardware-level pipeline optimization. For example, in matrix multiplication or convolution calculations, it can simultaneously process vector multiplication operations on multiple data blocks, significantly improving computational throughput. Its architecture is tailored to the repetitive nature and data locality of multiplication. For example, Booth encoding or Wallace tree structures are used to accelerate the generation and accumulation of partial products, enabling low-latency, energy-efficient operations in AI training or scientific simulations.

[0052] The vector arithmetic logic subunit (VALU) specializes in vector addition and subtraction, shifting, and logical operations, providing flexible arithmetic and data manipulation capabilities. In vector addition and subtraction scenarios, the VALU supports parallel processing of multi-precision data and reduces critical path latency through carry chain optimization. Shifting can be used to quickly adjust data alignment or implement scaling operations, such as batch adjustment of pixel value ranges in image processing. The logical operation module serves tasks such as data mask generation and conditional screening, such as dynamically filtering out invalid elements in sparse matrix calculations.

[0053] The collaborative design of the vector multiplication subunit and the vector arithmetic logic subunit allows pipelined execution of complex instructions. For example, the displacement alignment of vector data is first completed by the vector arithmetic logic subunit, and then the vector multiplication subunit performs the multiplication operation, and finally the accumulation reduction is achieved by the vector arithmetic logic subunit. This type of hardware-level collaboration greatly reduces data handling overhead, and shows significant advantages in real-time signal processing or neural network inference.

[0054] The write-back unit is responsible for transferring computational results to the register control unit. The write-back unit can employ a transmission protocol with a checksum mechanism to ensure data integrity during high-speed transmission. For example, in floating-point operations used in scientific computing, the write-back unit separately checks the exponent and mantissa to detect and correct bit-flip errors caused by circuit noise. The write-back unit also supports result compression and format conversion. For example, it can concatenate scattered 128-bit intermediate results into 512-bit vectors and write them to registers in batches, reducing bus transaction overhead.

[0055] Through the above technical solution, it can be seen that the beneficial effects of this embodiment are:

[0056] A vector coprocessor includes an arbitration module, a distributor module, a functional module, and a data path. The arbitration module is used to receive computing tasks from a main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks from the computing tasks. The distributor module is used to determine the parallelism and task queue of the vector tasks and dispatch the vector tasks based on the parallelism and task queue. The functional module is used to decompose the vector tasks into multiple subtasks and determine the data path corresponding to each subtask. The subtasks are assigned to the data path and the computation results corresponding to each data path are reduced to generate the target result corresponding to the vector task. The data path is used to calculate the subtasks and send the computation results to the functional module. This avoids redundant data storage and improves the processor's efficiency in vector computing.

[0057] like Figure 7 The figure shows a specific embodiment of a vector calculation method of the present application. The method in this embodiment is applied to Figures 1-6 vector coprocessor.

[0058] Step 701: When a vector task is received from a main processor, the parallelism and task queue of the vector task are determined by the distributor module corresponding to the coprocessor.

[0059] The vector tasks are generated into a task queue according to a preset priority rule; the task features corresponding to the vector tasks are analyzed to determine the parallelism corresponding to the vector tasks according to the task features.

[0060] The dispatcher module sorts and caches tasks based on pre-defined dynamic priority rules, such as task deadlines, data dependency chains, or instruction types. For example, in real-time video processing scenarios, high-frame-rate rendering tasks might be marked as urgent and placed at the head of the queue. Meanwhile, offline data analysis tasks adopt a bandwidth-aware strategy, loading them in batches only when the cache is free.

[0061] During the task reception phase, tasks are classified and feature extracted based on metadata analysis (such as instruction type tags and data size descriptors). For example, in AI training scenarios, gradient update tasks are identified as requiring high parallelism because they involve large-scale matrix multiplication and addition operations. Parameter synchronization tasks, on the other hand, are classified as low priority because they rely on global communication.

[0062] Parallelism can be determined through static or dynamic mechanisms. The static mechanism generates initial parallelism recommendations based on preset hardware parameters, such as splitting a 2048-bit vector into 16 subtasks at 128-bit widths. The dynamic mechanism flexibly adjusts the degree of parallelism by monitoring the computational progress of each data path (such as instruction throughput and cache miss rate) in real time. If the system detects delays in some subtasks due to data dependencies or resource contention, it automatically reduces the degree of parallelism and reallocates redundant tasks to idle resources to avoid a decrease in overall efficiency.

[0063] Step 702: Send the vector task to the functional module corresponding to the coprocessor according to the task queue, so that the functional module decomposes the vector task into multiple subtasks according to a preset decomposition rule.

[0064] Analyze the data structure of the vector task to determine the data partitioning method corresponding to the vector task based on the data structure; determine the data granularity corresponding to the subtask based on the parallelism and the bit width limit of the data path; and decompose the vector task into multiple subtasks based on the data partitioning method and data granularity.

[0065] When vector tasks in the task queue are sent to functional modules, a multi-dimensional analysis of the task's data organization is required. For example, for two-dimensional matrix operations (such as convolution or matrix multiplication), row-based, column-based, or checkerboard-style blocking strategies are selected based on the memory layout (row-major or column-major) and data locality.

[0066] If the task involves high-dimensional tensors (such as the attention weight matrix in an AI model), slicing or hierarchical partitioning is used to ensure that the data blocks of each subtask are distributed continuously in memory and strictly aligned to cache line boundaries to minimize the performance loss caused by cross-row access. For irregular data structures (such as sparse matrices or graph data), the system dynamically partitions the blocks using tuple index partitioning or non-zero element clustering techniques. For example, the non-zero elements of a sparse matrix are split into balanced sub-blocks based on density distribution, reducing idle waiting of computing resources.

[0067] After determining the data partitioning method, the size of the subtasks needs to be dynamically adjusted based on the degree of parallelism and the datapath width limit. For example, if the coprocessor supports eight datapaths, each with a 128-bit width, a 1024-bit vector task will be split into eight subtasks, each processing 128 bits of data.

[0068] For floating-point operations, data granularity also needs to consider computational precision alignment. If the task requires FP32 precision (32-bit per element), each subtask contains 4 elements (128 / 32). If INT8 quantization is used, 16 elements (128 / 8) can be processed in parallel to maximize hardware utilization.

[0069] By integrating block partitioning with data granularity, a set of executable subtasks is generated. For example, in real-time object detection in image processing, an input image frame (e.g., 1080p resolution) is parsed into a two-dimensional pixel matrix. The matrix is ​​then divided into 16×16 pixel blocks (matching four FP32 pixels in a 128-bit datapath width). Based on the degree of parallelism (e.g., 16 datapaths), the subtasks are split into 256 subtasks (each processing 16 blocks). Each subtask carries metadata tags (e.g., block coordinates, reduction mode), and a dependency check module ensures timing constraints.

[0070] Step 703: Determine the target path corresponding to the subtask according to the degree of parallelism and the real-time load of each data path.

[0071] When subtasks are dispatched from functional modules to data paths, the system analyzes the current subtask decomposition scale and the upper limit of hardware resources. For example, if the initial parallelism is set to 16 subtasks, if it detects that some data paths are unavailable due to high load or hardware errors, the system will dynamically reduce the parallelism to 12 and reallocate redundant tasks to less-loaded data paths.

[0072] This process requires integrating a real-time load monitoring network to continuously collect key metrics from each data path (such as instruction throughput, cache hit rate, power consumption threshold, and error counters) to form a global view of resource status. For example, in an AI inference scenario, if a lane's temperature rises due to frequent multiplication and addition operations, the system will mark that data path as throttled and prioritize new tasks to lanes with better cooling conditions.

[0073] Step 704: Send the subtasks to the corresponding target pathways, so that the target pathways calculate the calculation results corresponding to the subtasks.

[0074] Parse the instruction type corresponding to the subtask; call the corresponding computing unit based on the instruction type; use the computing unit to process the subtask to determine the calculation result.

[0075] The opcode carried by the subtask needs to be decoded to dynamically identify the instruction type (such as vector multiplication, addition, shift, or logical operation). For example, if the subtask instruction is "VMUL-128-FP32", the system determines that it needs to call the vector multiplication subunit to perform single-precision floating-point multiplication. If the instruction is "VALU-AND-INT8", it needs to call the vector arithmetic logic subunit to perform the bitwise AND operation of 8-bit integers.

[0076] During the parsing process, the operand format (such as data bit width and memory address alignment information) can also be extracted to configure parameters for the computing unit (such as the Booth encoding mode of the multiplier and the carry chain structure of the ALU) to ensure that hardware resources are accurately matched to task requirements.

[0077] Step 705: Reduce each calculation result to the target result corresponding to the vector task.

[0078] In the vector coprocessor's computational flow, result reduction integrates the results of subtasks distributed across various data paths into the final target result of the vector task through a multi-level aggregation and consistency control mechanism. After all subtasks have completed computation in the target path, the reduction unit first verifies data integrity. For example, in a matrix multiplication task, the reduction operation is triggered only when the results of all row-column multiplication-addition subtasks are ready.

[0079] For accumulation tasks (such as parameter updates in gradient descent), the reduction unit merges the subtask results step by step through a pipelined adder hierarchy (such as a 4-stage pipeline adder tree), and can complete the parallel accumulation of dozens of data path outputs in a single cycle.

[0080] For extreme value screening tasks (such as maximum pooling in image filtering), extreme values ​​are propagated level by level through a comparator tree, ultimately outputting the global maximum or minimum. Reduction modes (such as accumulation, multiplication, and logical merging) are dynamically configured by task instructions. For example, in AI inference, the exponential sum reduction of the Softmax layer first accumulates the local sums of all subtasks before normalizing the probability distribution through a division tree.

[0081] Step 706: Send the target result to the main processor.

[0082] After the target results are integrated in the reduction unit, the register control unit writes the target results into the first-level cache in batches according to the cache line alignment principle.

[0083] To ensure data consistency, the system can employ a lightweight cache coherence protocol. When multiple coprocessors share the L1 cache, the protocol manages data ownership through status flags. For example, in a heterogeneous computing platform, if a GPU coprocessor and a vector coprocessor access the same cache line simultaneously, the protocol automatically coordinates access order to avoid data contention. Furthermore, L1 cache access rights are dynamically allocated through hardware locking mechanisms (such as atomic operation instructions), ensuring that the main processor always reads the latest version of the data.

[0084] Through the above technical solution, it can be seen that the beneficial effects of this embodiment are:

[0085] When a vector task is received from the main processor, the coprocessor's corresponding dispatcher module determines the vector task's parallelism and task queue. The coprocessor then sends the vector task to the coprocessor's corresponding functional module based on the task queue, which then decomposes the task into multiple subtasks according to pre-set decomposition rules. The coprocessor then determines the target paths corresponding to the subtasks based on the parallelism and the real-time load of each data path. The subtasks are then sent to the corresponding target paths, which then calculate the corresponding results for each subtask. These results are then reduced to the target result corresponding to the vector task, which is then sent to the main processor. This collaborative mechanism of dynamic task scheduling, flexible resource allocation, and efficient result reduction significantly improves the execution efficiency and system adaptability of vector computing.

[0086] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods or computer program products. Therefore, the present application may adopt a completely hardware embodiment, a completely software embodiment, or a combination of software and hardware.

[0087] The various embodiments in this application are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the device embodiments are generally similar to the method embodiments, so the description is relatively simple. For relevant parts, refer to the partial description of the method embodiments.

[0088] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0089] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A vector coprocessor, characterized in that: It includes arbitration module, distributor module, functional module and data path; The arbitration module is used to receive computing tasks from the main processor, filter out vector tasks from the computing tasks, and filter out non-vector tasks from the computing tasks; The distributor module is used to determine the parallelism and task queue of the vector task, and dispatch the vector task according to the parallelism and the task queue; The functional module is used to decompose the vector task into multiple subtasks and determine the data path corresponding to each subtask; Allocating the subtasks to the data paths and reducing the calculation results corresponding to the data paths to generate a target result corresponding to the vector task; The data path is used to calculate the subtask and send the calculation result to the functional module.

2. The vector coprocessor according to claim 1, wherein: The arbitration module includes: parsing unit and feedback unit; The parsing unit is configured to parse the computing task to identify whether the computing task is a vector task; The feedback unit is configured to send the vector task to the distributor module when the computing task is the vector task; and generate a rejection signal and return the computing task to the main processor when the computing task is the non-vector task.

3. The vector coprocessor according to claim 1, wherein: The distributor module includes: Queue management unit and parallelism decision unit; The queue management unit is configured to receive the vector tasks sent by the arbitration module and generate a task queue for the vector tasks according to a preset priority rule; The parallelism decision unit is configured to analyze task features corresponding to the vector task, so as to determine the parallelism corresponding to the vector task according to the task features.

4. The vector coprocessor according to claim 1, wherein: The functional modules include: Reduction unit and register control unit; The reduction unit is configured to decompose the vector task into the subtasks and distribute the subtasks to the data paths in parallel; perform a reduction operation on the calculation results corresponding to the data paths to generate the target result; The register control unit is used to temporarily store the calculation results corresponding to the data paths; and send the target results to the main processor through the first-level cache corresponding to the main processor.

5. The vector coprocessor according to claim 4, wherein: The data path includes: a data controller unit, a buffer unit, a calculation unit, and a write-back unit; The data controller unit is configured to receive the calculation request from the functional module and feed back a data ready signal; The buffer unit is used to sequentially buffer the subtasks and temporarily store intermediate data of multi-cycle calculations; The calculation unit is used to calculate the subtask to generate the calculation result; The write-back unit is used to send the calculation result to the register control unit.

6. The vector coprocessor according to claim 5, characterized in that The calculation unit includes: Vector multiplication subunit and vector arithmetic logic subunit; The vector multiplication subunit is used to perform vector multiplication operations; The vector arithmetic logic subunit is used to perform vector addition, subtraction, displacement and logical operations.

7. A vector calculation method, characterized in that: The method is applied to the vector coprocessor according to any one of claims 1 to 6, comprising: When receiving a vector task sent by the main processor, the dispatcher module corresponding to the coprocessor determines the parallelism and task queue of the vector task; Sending the vector task to a functional module corresponding to the coprocessor according to the task queue, so that the functional module decomposes the vector task into a plurality of subtasks according to a preset decomposition rule; Determining a target path corresponding to the subtask according to the parallelism and the real-time load of each of the data paths; and sending the subtasks to the corresponding target pathways, so that the target pathways calculate the calculation results corresponding to the subtasks; reducing each of the calculation results to a target result corresponding to the vector task; The target result is sent to the main processor.

8. The method according to claim 7, characterized in that The determining the parallelism and task queue of the vector task by the distributor module corresponding to the coprocessor includes: Generating the vector tasks into a task queue according to a preset priority rule; The task characteristics corresponding to the vector task are analyzed to determine the parallelism corresponding to the vector task according to the task characteristics.

9. The method according to claim 7, characterized in that The function module decomposes the vector task into a plurality of subtasks according to a preset decomposition rule, including: Parsing the data structure of the vector task to determine the data block mode corresponding to the vector task according to the data structure; Determining a data granularity corresponding to the subtask according to the parallelism and the bit width limitation of the data path; The vector task is decomposed into a plurality of subtasks according to the data block mode and the data granularity.

10. The method according to claim 7, characterized in that The target path calculates the calculation results corresponding to each of the subtasks including: Parsing the instruction type corresponding to the subtask; Calling a corresponding computing unit based on the instruction type; The subtask is processed using the computing unit to determine the computing result.

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