Instruction decoding pipeline construction method, electronic equipment and storage medium

Abstract

The invention relates to the technical field of chip design, in particular to an instruction decoding assembly line construction method, electronic equipment and a storage medium. Establishing a stage mapping relationship between an instruction execution step and an instruction decoding pipeline stage according to domain segment information in the instruction code and an operation configured in the clock configuration file; and on the basis of the instruction decoding assembly line template, searching a stage mapping relationship, filling instruction execution steps and distributing operation to obtain a constructed instruction decoding assembly line. When the instruction set changes, the instruction decoding assembly line can be automatically generated by inputting the changed instruction code, the clock configuration file and the instruction decoding assembly line template.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and particularly to a method for constructing an instruction decoding pipeline, an electronic device, and a storage medium. Background Art

[0002] In contemporary processor design, the instruction decoding pipeline architecture is the mainstream solution for improving performance. It processes instructions in multiple stages in parallel to increase the instruction issue throughput rate, and instruction decoding is a key link among them. To optimize performance, instruction decoding often subdivides the instruction decoding pipeline and specifies a specific number of stages to read operands. However, during project iteration and product evolution, instruction set optimization is inevitable. With the development of technology and the change of application requirements, the original instruction set may expose problems such as insufficient functions and low efficiency, and needs to be improved and extended.

[0003] The change of the instruction set will have a huge impact on the design of the instruction decoding pipeline. Because each stage of the instruction decoding pipeline is designed based on the characteristics and execution process of the original instruction set, the adjustment of the instruction set will change the instruction format, opcode, operands, etc. This requires the redesign and optimization of each stage of the instruction decoding pipeline, especially the instruction decoding stage, to adapt to the new instruction set. Taking a company's project as an example, the instruction set was planned and the corresponding instruction decoding pipeline was designed in the initial stage. However, it was found during the project evolution that the original instruction set could not meet the new scenarios and needed to be adjusted. After the instruction set was changed, all links of the instruction decoding pipeline, such as reading, decoding, and execution, had to be re-evaluated and designed. A large amount of code needed to be written to implement the new logic, and complex debugging and verification were also required to ensure stable and efficient operation. However, the redesign of the instruction decoding pipeline is cumbersome and time-consuming, and requires a large amount of manpower and material resources, resulting in low construction efficiency of the instruction decoding pipeline. Therefore, there is an urgent need for a method for constructing an instruction decoding pipeline that can improve efficiency. Summary of the Invention

[0004] In view of the above technical problems, the technical solution adopted by the present invention is: a method for constructing an instruction decoding pipeline, the method comprising the following steps: S100, read the input instruction encoding, parse all fields of each instruction in the instruction encoding, and obtain the field information of the instruction encoding.

[0005] S200, read the clock configuration file, and parse to obtain the operations of each clock cycle.

[0006] S300, read the instruction decoding pipeline template, and parse each stage in the instruction decoding pipeline.

[0007] S400, determine the instruction type according to the field information of the instruction encoding, and dynamically generate the instruction execution steps and the stage mapping relationship of the stages of the instruction decoding pipeline based on the instruction type and the operations.

[0008] The S500, based on the instruction decoding pipeline template, processes in the order of the instruction decoding pipeline stages, looks up the stage mapping relationship, fills the instruction execution steps found according to the current instruction decoding pipeline stage into the current instruction decoding pipeline stage, and assigns the operations to each instruction decoding pipeline stage to obtain a constructed instruction decoding pipeline.

[0009] In addition, the present invention also provides a non-transitory computer-readable storage medium, in which at least one instruction or at least one segment of program is stored, and the at least one instruction or the at least one segment of program is loaded and executed by a processor to implement the above method.

[0010] In addition, the present invention also provides an electronic device, including a processor and the above non-transitory computer-readable storage medium.

[0011] The present invention has at least the following beneficial effects: The present invention provides a method for constructing an instruction decoding pipeline. By reading the input instruction encoding, clock configuration file, and instruction decoding pipeline template, a constructed instruction decoding pipeline is obtained through a series of processing steps. When the instruction set changes, the instruction decoding pipeline can be generated by inputting the changed instruction encoding, clock configuration file, and instruction decoding pipeline template, avoiding the problem of low efficiency in constructing the instruction decoding pipeline caused by the need to rewrite the instruction decoding pipeline code when the instruction set changes in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0013] Figure 1 It is a flowchart of a method for constructing an instruction decoding pipeline provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of an instruction decoding pipeline provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0015] Unless otherwise defined, all technical and scientific terms used in the embodiments of the present invention have the same meaning as commonly understood by those skilled in the art.

[0016] Please refer to Figure 1 , which shows a method for constructing an instruction decoding pipeline. The method includes the following steps: S100, read the input instruction encoding, parse all fields of each instruction in the instruction encoding, and obtain the field information of the instruction encoding.

[0017] Among them, the instruction encoding is the binary representation of the instructions in the instruction set. The instruction set is a set of instructions supported by the computer, and different fields of the instructions are defined in the instruction set, which is the basic specification for the interaction between software and hardware. The fields are used to distinguish different parts of the instruction, and each field has its specific function and meaning. For example, the opcode field, the operand field, the addressing mode field, etc.

[0018] In one embodiment, the instruction includes an opcode field and an operand field. The opcode specifies the type of operation. The operand is the data participating in the operation.

[0019] In one embodiment, the opcode is the opcode of the addition instruction or the opcode of the subtraction instruction. Other types of opcodes also fall within the protection scope of the present invention.

[0020] In one embodiment, the operand is an immediate operand, a register operand, or a memory operand. Other types of operands also fall within the protection scope of the present invention.

[0021] S200, read the clock configuration file, and parse to obtain the clock operations of each clock cycle.

[0022] Among them, the clock cycle is the basic time unit in the computer system, which is the time required for the clock signal to complete a full cycle change. Within one clock cycle, the computer can perform certain operations.

[0023] Among them, the configuration file records the field information configured for each clock cycle in the decoding execution stage, which is used to guide the fields to be decoded during the corresponding clock cycle in the decoding stage, can more effectively utilize hardware resources, and improve the decoding efficiency. For example, if the decoding operation of some fields is more complex and requires more time and resources, more clock cycles are allocated to them; while for some simple fields, the decoding can be completed within a shorter clock cycle. Reasonable configuration can avoid decoding conflicts between different fields and ensure the correctness and stability of the decoding process.

[0024] In one embodiment, L operations are configured within the q-th clock cycle in the clock profile, where L ≥ 0 and q > 1. That is, when L is greater than 1, more than two operations are allowed to be configured in the q-th clock cycle.

[0025] In one embodiment, the profile includes ten clock cycles in the decode execution stage and the operations for each clock cycle. Among them, the first clock cycle is configured for preparing decoding; the second clock cycle is configured for reading the first field segment and the second field segment; the third clock cycle is configured for reading the operands; the fourth clock cycle is configured for calculating the first address; the fifth clock cycle is configured for reading the third field segment and the fourth field segment; the sixth clock cycle is configured for calculating the second address; the seventh clock cycle is configured for reading the hardware configuration; the eighth and ninth clock cycles are respectively configured for calculation; the tenth clock cycle is configured for updating the result. Please refer to Figure 2 , and the clock configuration in this profile corresponds to the first configuration in the instruction decode pipeline. In one embodiment, the first field segment and the second field segment are address offsets or constant encodings. In one embodiment, the third field segment and the fourth field segment are the result write-back positions. Other configuration types of the profile also fall within the protection scope of the present invention.

[0026] In another embodiment, more clock cycles are allocated for processing computationally intensive operations. The profile includes ten clock cycles in the decode execution stage and the operations for each clock cycle. Among them, the first clock cycle is configured for preparing decoding; the second clock cycle is configured for reading the first operand; the third clock cycle is configured for reading the second operand; the fourth clock cycle is configured for reading the hardware configuration; the fifth clock cycle is configured for reading the second field segment for operand judgment; the sixth to ninth clock cycles are configured for computational operations; the tenth clock cycle is configured for updating the result. Please refer to Figure 2 , and the clock configuration in this profile corresponds to the second configuration in the instruction decode pipeline.

[0027] In one embodiment, the profile is a file pre-configured according to the instruction architecture in the instruction set.

[0028] S300, read the instruction decode pipeline template and parse each stage in the instruction decode pipeline.

[0029] Among them, the instruction decode pipeline divides the execution process of an instruction into multiple relatively independent and sequentially connected stages. Each stage completes a specific function and is implemented by a dedicated component in hardware.

[0030] In one embodiment, the stages of the instruction decode pipeline include instruction fetching, scheduling, resource checking, and decode execution stage.

[0031] Among them, the instruction decoding pipeline template is used to define the basic structure and interfaces of the functional modules in each stage of the instruction decoding pipeline, including input interfaces, output interfaces, and basic logic frameworks, for generating a specific instruction decoding pipeline.

[0032] S400 determines the instruction type according to the field segment information of the instruction encoding, and dynamically generates the instruction execution steps and the stage mapping relationship of the instruction decoding pipeline stages based on the instruction type and the operation.

[0033] It should be noted that the stage mapping relationship is used to disassemble the instruction execution steps and correspond them to the corresponding stages of the instruction decoding pipeline, and a series of clock operations are performed within each stage to complete the corresponding steps. Among them, the instruction execution steps focus on the logical execution order of the instructions. For example, for arithmetic operation instructions, its execution steps include obtaining operands, performing operations, and processing results, etc. There is a strong correspondence between the instruction execution steps and the instruction decoding pipeline stages. For example, the step of obtaining operands may correspond to the instruction fetching and decoding stages of the instruction decoding pipeline, and the step of performing operations may correspond to the execution stage of the instruction decoding pipeline.

[0034] In one implementation, S400 further includes a step of obtaining the instruction type: extracting the opcode field segment in the instruction encoding, determining the instruction type according to the opcode field segment, and defining a template for the instruction execution steps for each type of instruction. As an example, the template for the instruction execution steps of a branch instruction is: calculating the destination address and updating the next jump instruction. As another example, the template for the instruction execution steps of a LOAD instruction is: calculating the address, accessing memory, and writing back.

[0035] S500, based on the instruction decoding pipeline template, processes in the order of the instruction decoding pipeline stages, searches for the stage mapping relationship, fills the instruction execution steps found according to the current instruction decoding pipeline stage into the current instruction decoding pipeline stage, and allocates the operation to each instruction decoding pipeline stage to obtain a constructed instruction decoding pipeline.

[0036] It should be noted that when the instruction set changes, the instruction encoding will change synchronously. The present invention can automatically generate an instruction decoding pipeline according to the changed instruction encoding, avoiding the problem of low efficiency in constructing the instruction decoding pipeline caused by the need to rewrite the instruction decoding pipeline code when the instruction set changes in the prior art.

[0037] In summary, the present invention provides a method for constructing an instruction decoding pipeline. By reading the input instruction encoding, clock configuration file, and instruction decoding pipeline template, a stage mapping relationship between the instruction execution steps and the stages of the instruction decoding pipeline is established according to the field segment information in the instruction encoding and the operations configured in the clock configuration file. Based on the instruction decoding pipeline template, the stage mapping relationship is searched, the instruction execution steps are filled, and operations are allocated to obtain the constructed instruction decoding pipeline. When the instruction set changes, the instruction decoding pipeline can be generated by inputting the changed instruction encoding, clock configuration file, and instruction decoding pipeline template, avoiding the problem of low efficiency in constructing the instruction decoding pipeline caused by the need to rewrite the instruction decoding pipeline code when the instruction set changes in the prior art.

[0038] An embodiment of the present invention also provides a non-transitory computer-readable storage medium, which can be set in an electronic device to store at least one instruction or at least one segment of a program related to a method in the method embodiment. The at least one instruction or the at least one segment of the program is loaded and executed by the processor to implement the method provided in the above embodiment.

[0039] An embodiment of the present invention also provides an electronic device, including a processor and the aforementioned non-transitory computer-readable storage medium.

[0040] An embodiment of the present invention also provides a computer program product, which includes program code. When the program product runs on an electronic device, the program code is used to cause the electronic device to execute the steps in the method according to various exemplary embodiments of the present invention described above in this specification.

[0041] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the above-mentioned division of each functional unit and module is used as an example. In practical applications, the above functions can be allocated to different functional units and modules according to needs, that is, the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above.

[0042] Although some specific embodiments of the present invention have been described in detail by way of examples, those skilled in the art should understand that the above examples are only for illustration purposes and not for limiting the scope of the present invention. Those skilled in the art should also understand that various modifications can be made to the embodiments without departing from the scope and spirit of the present invention. The scope disclosed by the present invention is defined by the appended claims.

Claims

1. A method for constructing an instruction decoding pipeline, characterized in that The method includes the following steps: S100, read the input instruction encoding, parse all fields of each instruction in the instruction encoding to obtain the field information of the instruction encoding; S200, read the clock configuration file, and parse to obtain the operations of each clock cycle; S300, read the instruction decoding pipeline template, and parse each stage in the instruction decoding pipeline; S400, determine the instruction type according to the field information of the instruction encoding, and dynamically generate the instruction execution steps and the stage mapping relationship of the stages of the instruction decoding pipeline based on the instruction type and the operations; S500, based on the instruction decoding pipeline template, process in the order of the stages of the instruction decoding pipeline, search for the stage mapping relationship, fill the instruction execution steps found according to the current stage of the instruction decoding pipeline into the current stage of the instruction decoding pipeline, and allocate the operations to each stage of the instruction decoding pipeline to obtain the constructed instruction decoding pipeline.

2. The method according to claim 1, wherein In the clock configuration file, L operations are configured in the q-th clock cycle, where L≥0 and q>1.

3. The method according to claim 1, characterized in that The configuration file includes ten clock cycles of the decoding execution stage and the operations of each clock cycle; among them, the first clock cycle is configured for preparing decoding; the second clock cycle is configured for reading the first field and the second field; the third clock cycle is configured for reading the operands; the fourth clock cycle is configured for calculating the first address; the fifth clock cycle is configured for reading the third field and the fourth field; the sixth clock cycle is configured for calculating the second address; the seventh clock cycle is configured for reading the hardware configuration; the eighth and ninth clock cycles are respectively configured for calculation; the tenth clock cycle is configured for updating the result.

4. The method according to claim 1, wherein S400 further includes a step of obtaining the instruction type: extract the opcode field in the instruction encoding, determine the instruction type according to the opcode field, and define a template for the instruction execution steps for each type of instruction.

5. The method according to claim 1, characterized in that, The stages of the instruction decoding pipeline include instruction fetching, scheduling, resource checking, and decoding execution stages.

6. A non-transitory computer-readable storage medium storing at least one instruction or at least one program segment, characterized in that, The at least one instruction or the at least one program segment is loaded and executed by a processor to implement the method according to any one of claims 1-5.

7. An electronic device, characterized in that, It includes a processor and the non-transitory computer-readable storage medium according to claim 6.

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