Memory management system, method, device, medium and product

Abstract

The invention discloses a memory management system, method and device, a medium and a product, and relates to the technical field of computers, a processor is used for performing hardware initialization through a basic input and output system by reading hardware component information of each hardware component, therefore, different memory spaces can be allocated to each hardware component according to the obtained address bus width supported by each hardware component under the condition that the fact that any preset bus link does not comprise a switch is determined according to the hardware component information; the first hardware component may be made assignable to a first memory space that supports a first address bus width. And for the second hardware component capable of expanding the address range, the second hardware component is allocated to the second memory space supporting the second address bus width, so that each hardware component can be ensured to have an independent address range, the utilization rate of memory resources is optimized, and the system stability is improved.

Description

Technical Field

[0001] This application relates to the field of computer technologies, and in particular, to a memory management system, method, device, medium, and product. Background Art

[0002] With the increasing complexity and integration of server hardware components, the deployment scale of high-performance peripherals such as intelligent network adapters, storage controllers, and smart network cards has increased significantly, resulting in continuous intensification of competition for internal bus resources in the server. In particular, traditional memory address resources (up to 4 gigabytes) are facing severe allocation pressure.

[0003] Currently, for the allocation of traditional memory address resources in a server, direct allocation is performed on hardware components. After the memory address resources are exhausted, memory address allocation for subsequent hardware components is stopped, resulting in the failure of hardware component functions and further affecting the stability of the server. Summary of the Invention

[0004] This application provides a memory management system, method, device, medium, and product to at least solve the problem in the related art that for the allocation of traditional memory address resources in a server, direct allocation is performed on hardware components. After the memory address resources are exhausted, memory address allocation for subsequent hardware components is stopped, resulting in the failure of hardware component functions and further affecting the stability of the server.

[0005] In a first aspect, this application provides a memory management system. The system includes a processor and multiple hardware components; the processor is connected to each hardware component through a preset bus; among the hardware components, there are a first hardware component and a second hardware component;

[0006] The processor is configured to, during the process of hardware initialization through the basic input / output system, read the hardware component information of each hardware component; and when it is determined that a switch is not included in any preset bus link based on the hardware component information, determine the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address within the first memory space, and the second hardware component allocates a memory address within the second memory space. The first memory space is a memory space supporting the first address bus width, and the second memory space is a memory space supporting the second address bus width.

[0007] In a second aspect, this application provides a memory management method. The method includes:

[0008] During the process of hardware initialization through the basic input / output system, the hardware component information of each hardware component is read; and when it is determined based on the hardware component information that a switch is not included in any preset bus link, the memory space corresponding to each hardware component is determined based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space, and the second hardware component allocates a memory address in the second memory space. The first memory space is a memory space that supports the first address bus width, and the second memory space is a memory space that supports the second address bus width.

[0009] In a third aspect, the present application provides a memory management device, including:

[0010] A reading module, configured to read the hardware component information of each hardware component during the process of hardware initialization through the basic input / output system;

[0011] A determining module, configured to, when it is determined based on the hardware component information that a switch is not included in any preset bus link, determine the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space, and the second hardware component allocates a memory address in the second memory space. The first memory space is a memory space that supports the first address bus width, and the second memory space is a memory space that supports the second address bus width.

[0012] In a fourth aspect, the present application further provides an electronic device, including: a memory, configured to store a computer program; a processor, configured to implement the steps of the memory management method provided in the second aspect above when executing the computer program.

[0013] In a fifth aspect, the present application further provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of the memory management method provided in the second aspect above are implemented.

[0014] In a sixth aspect, the present application further provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of the memory management method provided in the second aspect above are implemented.

[0015] With the memory management system, method, device, medium and product provided by this application, since the processor is connected to multiple hardware components through a preset bus, in order to ensure the normal operation of each hardware component, it is necessary to allocate addresses to each hardware component. Among them, the preset bus is a high-speed serial expansion bus. The space of the first memory space is smaller than that of the second memory space. To avoid insufficient allocation of memory resources in the first memory space, during the process of hardware initialization by the processor through the basic input / output system, by reading the hardware component information of each hardware component, when it is determined that a switch is not included in any preset bus link according to the hardware component information, different memory spaces can be allocated to each hardware component according to the address bus width supported by each hardware component obtained, so that the first hardware component can be allocated the first memory space that supports the first address bus width. For the second hardware component that can perform address range expansion, the second hardware component is allocated to the second memory space that supports the second address bus width, so as to ensure that each hardware component has an independent address range. And compared with allocating all hardware components to the first memory space, which causes the space resources of the first memory space to be tense, by allocating the second hardware component that can perform memory range expansion to the second memory space, the utilization rate of memory resources can be optimized, thereby reducing the memory management burden during system operation and improving system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0017] Figure 1 Hardware architecture diagram of the memory management system provided by the embodiment of the present application;

[0018] Figure 2 Hardware architecture diagram of the data processing unit provided by the embodiment of the present application;

[0019] Figure 3 Schematic diagram of a preset bus link including a switch provided by the embodiment of the present application;

[0020] Figure 4 Schematic diagram of a preset bus link including a switch provided by another embodiment of the present application;

[0021] Figure 5 Hardware architecture diagram of the memory management system provided by another embodiment of the present application;

[0022] Figure 6 Flow chart of the memory management method provided by an embodiment of the present application;

[0023] Figure 7 Flow schematic diagram of the memory management method provided in another embodiment of the present application;

[0024] Figure 8 Flow schematic diagram of the memory management method provided in yet another embodiment of the present application;

[0025] Figure 9 Physical link connection schematic diagram of the server motherboard provided in yet another embodiment of the present application;

[0026] Figure 10 Structural schematic diagram of the memory management device provided in an embodiment of the present application;

[0027] Figure 11 Structural schematic diagram of the electronic device provided in an embodiment of the present application. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0029] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and not to describe a specific order or sequence.

[0030] Here, the exemplary embodiments will be described in detail, and the examples are shown in the accompanying drawings. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent the embodiments consistent with the present invention. On the contrary, they are only examples of the devices and methods consistent with some aspects of the present invention as detailed in the appended claims.

[0031] Next, the technical solutions of the present invention will be described in detail with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. Next, the embodiments of the present invention will be described in conjunction with the accompanying drawings.

[0032] The hardware architecture of modern servers is evolving towards higher integration and more complex functionality. The large-scale deployment of high-performance peripherals such as intelligent network adapters, storage controllers, and data processing units has significantly improved data processing efficiency but also increased the competition pressure on the internal bus resources of the server. In particular, the traditional memory address resources (up to 4 gigabytes) are facing severe allocation pressure. Currently, the server adopts a static allocation strategy during the startup phase and directly allocates memory address resources according to the enumeration order of hardware components. However, with the introduction of complex components such as multi-level switches and data processors, the demand for memory address resources far exceeds the 4-gigabyte limit. Once the resources are exhausted, subsequent devices will not be able to obtain address allocation, resulting in the failure of the functions of hardware components and further affecting the stability of the server.

[0033] Therefore, in the face of the above technical problems, instead of statically allocating memory address resources to hardware components directly, dynamic allocation is adopted. Specifically, a memory management system can be designed to determine the address bus width supported by hardware components, allocate addresses for the second memory space to hardware components that support address expansion, and allocate addresses for the first memory space to hardware components that only support the first address bus width, thereby reducing the address allocation pressure in the first memory space, optimizing the utilization rate of memory resources, and further improving the stability of the system.

[0034] To enable those skilled in the art of this technology to better understand the solution of this application, the following further details the application in combination with the accompanying drawings and specific implementation manners.

[0035] Combined with the specific application environment architecture or specific hardware architecture on which the execution of the memory management system, method, device, medium, and product depends, the specific application environment architecture or specific hardware architecture is described herein. Figure 1 This is the hardware architecture diagram of the memory management system provided by the embodiment of this application. The system includes a processor and multiple hardware components, and the processor is connected to each hardware component through a preset bus.

[0036] The processor is used to read the hardware component information of each hardware component during the process of hardware initialization through the basic input / output system; and when it is determined that a preset bus link does not include a switch based on the hardware component information, determine the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates memory addresses in the first memory space, and the second hardware component allocates memory addresses in the second memory space. The first memory space is the memory space that supports the first address bus width, and the second memory space is the memory space that supports the second address bus width.

[0037] Among them, the processor is a Central Processing Unit (CPU).

[0038] Among them, the preset bus is a high-speed serial expansion bus. The preset bus link is a Peripheral Component Interconnect Express (PCIe) link.

[0039] Among them, as Figure 1 shown, the processor is connected to the hardware components through the high-speed serial expansion bus.

[0040] It can be understood that when the computer is powered on, the system will perform a series of initialization operations. During this process, the central processing unit will read and execute the basic input / output system code from the memory on the motherboard that stores the basic input / output system.

[0041] It can be understood that when the computer starts up, the basic input / output system identifies and initializes all the hardware components connected to the motherboard, including the processor, memory, storage devices, Peripheral Component Interconnect Express (PCIe) devices, etc. These hardware components usually exist in a hierarchical structure, such as a device tree or a topology.

[0042] Among them, the hardware component information is used to identify devices, allocate resources, configure drivers, and ensure the normal operation of devices.

[0043] Among them, the switch is used to expand the number of Peripheral Component Interconnect Express interfaces, allowing a single Peripheral Component Interconnect Express port to connect multiple devices to form a hierarchical topology.

[0044] Among them, the address bus width is the number of binary digits for transmitting memory addresses.

[0045] Among them, the first address bus width is a 32-bit address bus, and the second address bus width is a 64-bit address bus. The first memory space is the memory space corresponding to the first address bus width, with a maximum addressable memory space of 4 gigabytes. The maximum addressable memory space of the second memory space is greater than that of the first memory space.

[0046] Among them, the first hardware component is the component that presets and allocates the first memory space, and the second hardware component is the component that can expand the address range.

[0047] Among them, the depth-first search algorithm is an algorithm used to traverse a tree structure.

[0048] Specifically, in this embodiment, during the hardware initialization process by the processor through the Basic Input / Output System (BIOS), the BIOS will use a preset algorithm to enumerate from the root node, traverse the hardware components layer by layer downward until all the hardware components are traversed, read the configuration space of each hardware component, so as to obtain the hardware component information. The BIOS determines whether a hardware component is a switch by reading the hardware component information. In the case where it is determined that a switch is not included in any preset bus link, it reads the memory type flag bits of the base address registers in each hardware component, and determines the address bus width supported by each hardware component through the memory type flag bits. Therefore, it can allocate memory addresses for each hardware component in the corresponding memory space according to the supported address bus width, allocate a memory address for the first hardware component that only supports the first address bus width in the first memory space, and allocate a memory address for the second hardware component that can perform an address range in the second memory space.

[0049] Among them, if the value of the memory type flag bit of the base address register corresponding to a hardware component is 00, it indicates that the hardware component supports a 32-bit address bus. If the value of the memory type flag bit of the base address register corresponding to a hardware component is 10, it indicates that the hardware component supports a 64-bit address bus extension.

[0050] Among them, the configuration space of a hardware component is a fixed-size memory area in the hardware component, which contains hardware component identification information and hardware component information such as the base address register. Among them, the Base Address Register (BAR) is the core register in the hardware component configuration space, which is used to declare to the system the type and size of the memory or input / output resources required by the device.

[0051] Optionally, the hardware component information may include hardware component identification information, hardware component configuration information, etc., which are not limited in this embodiment.

[0052] The memory management system provided in this embodiment includes a processor and multiple hardware components; the processor is connected to each hardware component through a preset bus; among the hardware components, there are a first hardware component and a second hardware component; the processor is configured to read the hardware component information of each hardware component during the process of hardware initialization through the basic input / output system; and when it is determined based on the hardware component information that a switch is not included in any preset bus link, determine the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space, and the second hardware component allocates a memory address in the second memory space. The first memory space is a memory space that supports the first address bus width, and the second memory space is a memory space that supports the second address bus width. The memory management system achieves the following technical effects: Since the processor is connected to multiple hardware components through a preset bus, to ensure the normal operation of each hardware component, it is necessary to allocate a memory address for each hardware component. Among them, the preset bus is a high-speed serial expansion bus. The space of the first memory space is smaller than that of the second memory space. To avoid insufficient allocation of memory resources in the first memory space, the processor is configured to, during the process of hardware initialization through the basic input / output system, read the hardware component information of each hardware component, so that when it is determined based on the hardware component information that a switch is not included in any preset bus link, according to the obtained address bus width supported by each hardware component, allocate different memory spaces for each hardware component, so that the first hardware component can be allocated the first memory space that supports the first address bus width. For the second hardware component that can perform address range expansion, the second hardware component is allocated to the second memory space that supports the second address bus width, so as to ensure that each hardware component has an independent address range. And compared with allocating all hardware components to the first memory space, which causes the space resources of the first memory space to be tense, by allocating the second hardware component that can perform memory range expansion to the second memory space, the utilization rate of memory resources can be optimized, thereby reducing the memory management burden during system operation and improving system stability.

[0053] As an alternative embodiment, on the basis of the above embodiment, when the processor determines the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space and the second hardware component allocates a memory address in the second memory space, it is specifically configured to:

[0054] If it is determined based on the hardware component information that any hardware component is a preset hardware component, then determine that any hardware component is the first hardware component, and the memory space for allocating a memory address to the first hardware component is the first memory space; the preset hardware component only supports the first address bus width;

[0055] If it is determined based on the information of each hardware component that any hardware component is a component capable of address bus width expansion and supports the first address bus width and the second address bus width, then determine that any hardware component is the second hardware component, and the memory space for allocating the memory address for the second hardware component is the second memory space.

[0056] Wherein, the preset hardware component is a component that is preset to be allocated to the first memory space.

[0057] It can be understood that the program of the basic input / output system itself is stored in the motherboard, but when the computer starts, it is the central processing unit that is responsible for reading and executing the code of the basic input / output system.

[0058] Specifically, in this embodiment, during the hardware initialization process by the processor through the basic input / output system, the basic input / output system determines whether any hardware component is a preset hardware component according to the hardware component information of each hardware component and using the first preset configuration information. If it is determined that any hardware component is a preset hardware component, then determine the hardware component determined as the preset hardware component as the first hardware component, allocate an address for the first hardware component in the first memory space corresponding to the first address bus width, and after allocating the address, update the configuration space of the first hardware component, and save the allocated memory address in the configuration register of the first hardware component configuration space. If it is determined that any hardware component is a component capable of address bus width expansion, then determine the component capable of address bus width expansion as the second hardware component, allocate an address for the second hardware component in the second memory space corresponding to the second address bus width, and after allocating the address, update the configuration space of the second hardware component, and save the allocated memory address in the configuration register of the second hardware component configuration space.

[0059] It can be understood that a component capable of address range expansion can support the first address bus width or the second address bus width.

[0060] Wherein, the preset hardware component is a component that only supports the first address bus width.

[0061] Optionally, the preset hardware component can be a data processing unit, etc., which is not limited in this embodiment.

[0062] It can be understood that the preset hardware component can be a hardware component that only supports the first address bus width and has a high priority. There are multiple hardware components that only support the first address bus width among the hardware components, and the preset hardware component is the component with a high priority among them. When allocating memory addresses, the memory address of the first address bus width is preferentially allocated to the preset hardware component, so as to avoid the situation that the preset hardware component cannot be used due to insufficient memory addresses.

[0063] Among them, if a hardware component supports both a first address bus width and a second address bus width, a memory address with the second address bus width is allocated to the hardware component.

[0064] Specifically, by allocating a memory address in the first memory space to a first hardware component that only supports the first address bus width, it is ensured that the first hardware component can operate within a compatible address range, and a memory address in the second memory space is allocated to a second hardware component that supports address expansion, so that the second hardware component can make full use of system resources and improve resource utilization.

[0065] As an alternative implementation, based on any of the above embodiments, the hardware component information includes hardware component identification information;

[0066] The processor, when determining that any hardware component is a preset hardware component based on the hardware component information, is specifically configured to:

[0067] Obtain first preset configuration information; the first preset configuration information includes preset hardware component identification information;

[0068] Compare the hardware component identification information of each hardware component with the first preset configuration information respectively;

[0069] If the first preset configuration information includes the same hardware component identification information as the hardware component, the hardware component corresponding to the same hardware component identification information is determined as the preset hardware component.

[0070] Among them, the hardware component identification information is used to uniquely identify the hardware component.

[0071] Among them, the hardware component identification information may include the model identification information of the hardware component and the source identification information of the hardware component.

[0072] Among them, the model identification information of the hardware component is used to distinguish different models of similar devices and may be a device identification code (DID). The source identification information of the hardware component may be a vendor identification code (VID).

[0073] Among them, the first preset configuration information is pre-configured configuration information including preset hardware component identification information. The preset hardware component identification information is the identification information of the preset hardware component.

[0074] Optionally, the preset hardware component can be set independently according to actual needs and is not limited in this embodiment.

[0075] Specifically, in this embodiment, the basic input / output system reads the first preset configuration information stored in the preset database. Since the first preset configuration information includes the preset hardware component identification information, the hardware component identification information corresponding to each hardware component is respectively compared with the preset hardware component identification information stored in the first preset configuration information. If there is a hardware component identification information that is the same as the preset hardware component identification information existing in the first preset configuration information, the hardware component is determined as a preset hardware component.

[0076] Specifically, by pre-configuring the preset hardware components and storing them in the first preset configuration information, and comparing the hardware component identification information that uniquely identifies the hardware components with the preset hardware component identification information in the first preset configuration information, the preset hardware components can be quickly and accurately identified.

[0077] As an alternative implementation, based on any of the above embodiments, the processor is further configured to:

[0078] If it is determined that any hardware component is a non-preset hardware component and only supports the first address bus width based on the information of each hardware component, then determine that any hardware component is a third hardware component, and the memory space for allocating the memory address for the third hardware component is the first memory space.

[0079] Wherein, the third hardware component is a component that is a non-preset hardware component and only supports the first address bus width.

[0080] Specifically, in this embodiment, the basic input / output system determines the address bus width supported by the hardware component according to the configuration space of the read hardware component. If the hardware component only supports the first address bus width, the hardware component identification information corresponding to the hardware component is compared with the preset hardware component identification information stored in the first preset configuration information. If there is no preset hardware component identification information in the first preset configuration information that is the same as the hardware component identification information of the hardware component, it indicates that the hardware component is a third hardware component, and a memory address is allocated for the third hardware component in the first memory space.

[0081] Specifically, by identifying the hardware components that only support the first address bus and are non-preset hardware components and determining them as third hardware components, a memory address is allocated for the third hardware components in the first memory space, realizing the dynamic allocation of memory addresses.

[0082] As an alternative implementation, based on any of the above embodiments, the hardware components are distributed in different preset bus links; the preset bus link is a channel for data transmission in the preset bus; the first preset configuration information further includes the mapping relationship between the preset hardware component identification information and the preset address reservation information; the preset address reservation information is used to indicate whether the preset hardware component needs to reserve a memory address;

[0083] The processor is further configured to:

[0084] Determine whether a preset hardware component needs to reserve a memory address based on first preset configuration information;

[0085] If it is determined that the preset hardware component needs to reserve a memory address, reserve a memory area of a first preset size for the preset hardware component in the first memory space;

[0086] Enable the hot-plug function of the bridge device corresponding to the first link; the first link is the preset bus link where the preset hardware component that needs to reserve a memory address is located; the bridge device is used to manage the preset bus link.

[0087] Wherein, the bridge device is a hub device used to connect different links in a high-speed serial computer expansion bus standard system, responsible for address routing and protocol conversion. The hot-plug function refers to the ability to dynamically insert or remove hardware devices during system operation without restarting the system.

[0088] Wherein, the first preset size is the memory size that needs to be reserved corresponding to the preset hardware component.

[0089] Optionally, the first preset size corresponding to each hardware component may be different, which is not limited in this embodiment.

[0090] It can be understood that the bridge devices corresponding to different preset bus links are link bridges. The link bridge is a relay device for managing the preset bus link, used for address routing, protocol conversion, and topology expansion. There is only one link bridge on each preset bus link.

[0091] Wherein, if a memory address needs to be reserved, the preset address reservation information further includes the memory size that needs to be reserved.

[0092] Specifically, in this embodiment, the processor reads the preset address reservation information corresponding to each preset hardware component in the first configuration space through the basic input / output system. If the preset address reservation information corresponding to any one preset hardware component is for reservation, it indicates that the preset hardware component needs to reserve a memory address. Then, reserve a memory area of the first preset size for the preset hardware component in the first memory space according to the first preset size stored in the preset address reservation information of the preset hardware component, and write the reserved memory area of the first preset size into the base address register of the hardware component. Further, the basic input / output system reads the hot-plug control register in the configuration space of the bridge device corresponding to the first link, and enables the hot-plug enable bit in the hot-plug register, thereby enabling the hot-plug function of the bridge device corresponding to the first link.

[0093] Exemplarily, if the preset hardware component is a Data Processing Unit (DPU), memory addresses need to be reserved for the data processing unit. The data processing unit is a hardware device for data processing. Refer to Figure 2 as shown in Figure 2 the hardware architecture diagram of the data processing unit provided by an embodiment of the present application. As Figure 2 shown, the data processing unit includes a central processing unit. The hot-plug function of the central processing unit is in an enabled state. The lower end of the central processing unit is connected to a hard disk 0 and a switch through a high-speed serial expansion bus. Among them, the hot-plug function of the switch is in an enabled state. A network interface card 0, a network interface card 1, and a network interface card 2 are connected to the switch. External devices communicate with the central processing unit through a universal serial bus interface for data transmission and power supply. It can be seen from the figure that the data processing unit includes a central processing unit and a switch, and the hot-plug functions of the central processing unit and the switch are enabled. Therefore, memory addresses need to be reserved for the data processing unit.

[0094] Specifically, by using the first preset configuration information to determine whether the preset hardware component needs to reserve memory addresses, and reserving corresponding sizes of memory addresses for the preset hardware components that need to reserve memory addresses, so that the preset hardware components can obtain sufficient memory resources, and turning on the hot-plug function of the bridge device of the first link, so that the system can sense the addition and removal of hardware components and dynamically release or allocate the reserved memory addresses.

[0095] As an alternative implementation manner, based on any one of the above embodiments, the processor is further configured to:

[0096] If it is determined that the hardware component is a second hardware component, turn on the hot-plug function of the bridge device corresponding to the second link; the second link is the preset bus link where the second hardware component is located.

[0097] Specifically, in this embodiment, the Basic Input / Output System reads the hot-plug control register in the configuration space of the bridge device corresponding to the second link, and turns on the hot-plug enable bit in the hot-plug register, thereby turning on the hot-plug function of the bridge device corresponding to the second link.

[0098] Specifically, by turning on the hot-plug function of the bridge device corresponding to the second link, the system can dynamically insert or remove the second hardware component during operation and reallocate the memory addresses corresponding to the second hardware component, improving the flexibility of the system. Since the second hardware component supports memory address expansion, the second address bus width provides a huge addressing range, which can meet the memory address requirements of various hardware components. By combining the hot-plug function, the system can flexibly allocate and release the memory addresses of the second memory space according to the actual needs of the hardware components.

[0099] As an alternative implementation, based on any of the above embodiments, the processor is further configured to:

[0100] If it is determined that the hardware component is the third hardware component, then the hot-plug function of the bridge device corresponding to the third link is turned off; the third link is the preset bus link where the third hardware component is located.

[0101] Specifically, in this embodiment, the basic input / output system reads the hot-plug control register in the configuration space of the bridge device corresponding to the third link, and turns off the hot-plug enable bit in the hot-plug register, thereby turning off the hot-plug function of the bridge device corresponding to the third link.

[0102] Specifically, by turning off the hot-plug function of the bridge device corresponding to the third link, it is possible to avoid fragmentation or conflict of the memory address space caused by dynamic hardware changes in the system.

[0103] As an alternative implementation, based on any of the above embodiments, the processor is further configured to:

[0104] If it is determined based on the information of each hardware component that any hardware component is a bridge device and there is no hardware component connected under the bridge device, then it is determined that any hardware component is the fourth hardware component;

[0105] Determine whether the fourth hardware component needs to reserve a memory address based on the second preset configuration information;

[0106] If it is determined that the fourth hardware component needs to reserve a memory address, then a memory area of a second preset size is reserved for the fourth hardware component in the first memory space, and the hot-plug function of the fourth hardware component is turned on.

[0107] Wherein, in this embodiment, that any hardware component is a bridge device and there is no hardware component connected under the bridge device can be understood as that the bridge device supports the hot-plug function, but there is no hardware component connected currently.

[0108] Wherein, the fourth hardware component is a component that is a bridge device and is not connected to any hardware component currently.

[0109] Optionally, in this embodiment, when it is determined based on the information of each hardware component that a switch is not included in any preset bus link, the bridge device can be a root port, etc., which is not limited in this embodiment. It can be understood that the physical interfaces on the motherboard, such as physical slots, must be connected to an upstream bridge device, and the upstream bridge device is such as a root port.

[0110] Wherein, the second preset configuration information includes the identification information corresponding to the bridge device that needs to reserve a memory address and the configuration information for the bridge device to reserve a corresponding preset memory size.

[0111] Among them, the second preset size is the memory size to be reserved corresponding to the fourth hardware component, and different fourth hardware components may correspond to different second preset sizes.

[0112] Optionally, the second preset size can be set according to requirements and is not limited in this embodiment.

[0113] Specifically, in this embodiment, the processor reads the hardware component information of each hardware component through the input / output system, determines whether the hardware component is a bridge device according to the type code and the hardware component identification information in the hardware component. If it is determined that the hardware component is a bridge device, the secondary bus of the hardware component is accessed. If there is no response device on the secondary bus, it means that there is no lower-level hardware component connected under the bridge device. Therefore, the hardware component that is determined to be a bridge device and has no lower-level hardware component connected under it is used as the fourth hardware component. Further, the preset second preset configuration information is read, and the identification information of the hardware component determined to be the fourth hardware component is compared with the identification information of the bridge device that needs to reserve the memory address included in the second preset configuration information. If the identification information of the fourth hardware component exists in the second preset configuration information, it is determined that the fourth hardware component needs to reserve the memory address. Then, a memory area with the second preset size is reserved for the fourth hardware component in the first memory space, and the hot-plug control bit of the configuration space of the fourth hardware component is enabled, so as to enable the hot-plug function of the fourth hardware component.

[0114] Specifically, by identifying the fourth hardware component, determining whether the fourth hardware component needs to reserve the memory address, reserving the corresponding second preset size of the memory area for the fourth hardware component that needs to reserve the memory address, and enabling the hot-plug function of the fourth hardware component, the scalability of the system is improved, and it can be ensured that when a hardware component is inserted in the future, the processor can immediately allocate the preset memory resources without the need for system restart.

[0115] As an alternative implementation manner, on the basis of any of the above embodiments, the processor is further configured to: when it is determined based on the hardware component information that a switch is included in any preset bus link, read the preset memory address allocation policy from the switch firmware, and allocate a memory address for the switch based on the preset memory address allocation policy.

[0116] Among them, the switch firmware is used to control the hardware functions of the switch, implement network protocols, and manage data forwarding logic, including the preset memory address allocation policy. The preset memory address allocation policy is the memory address allocation policy preset for each switch.

[0117] Among them, different switches correspond to different preset memory address allocation policies.

[0118] Optionally, the preset memory address allocation policy can be set according to actual requirements, and no limitation is made in this embodiment.

[0119] Specifically, in this embodiment, if the basic input / output system determines whether a hardware component is a switch by reading the hardware component information, and it is determined that a switch is included in any preset bus link, then the preset memory address allocation policy stored in the firmware of the switch is read, and the memory address is allocated to the switch according to the setting in the preset memory address allocation policy.

[0120] Specifically, if a switch is included in any preset bus link, by allocating memory to the switch according to the preset memory address allocation policy, the calculation time for the basic input / output system to allocate the memory address to the switch is reduced, and the memory address allocation efficiency is optimized.

[0121] As an alternative implementation manner, on the basis of any of the above embodiments, a switch includes a plurality of downstream ports; the preset memory address allocation policy includes the preset memory capacity corresponding to each downstream port on the switch;

[0122] When the processor allocates a memory address to the switch based on the preset memory address allocation policy, it is specifically used for:

[0123] Determine the address bus width supported by each downstream port in the switch;

[0124] If the downstream port supports the first address bus width, allocate a memory address with the corresponding preset memory capacity for the downstream port in the first memory space based on the preset memory address allocation policy;

[0125] If the downstream port supports the second address bus width, allocate a memory address with the corresponding preset memory capacity for the downstream port in the second memory space based on the preset memory address allocation policy.

[0126] Wherein, the downstream port is a connection port facing a terminal device (such as a network card) or a lower-level switch.

[0127] Wherein, the preset memory capacity is the size of the memory space to be allocated corresponding to each downstream port on the switch preset in advance.

[0128] Specifically, in this embodiment, the processor reads the memory type flag bits in the base address registers of each downstream port in the switch through the basic input / output system, and determines the address bus width supported by each downstream port in the switch based on the memory type flag bits. If it is determined that a downstream port supports the first address bus width, the preset memory capacity corresponding to the downstream port in the preset memory allocation policy is read, and the basic input / output system allocates a memory address with the corresponding preset memory capacity for the downstream port in the first memory space. If it is determined that a downstream port supports the second address bus width, the preset memory capacity corresponding to the corresponding downstream port in the preset memory allocation policy is read, and the basic input / output system allocates a memory address with the corresponding preset memory capacity for the corresponding downstream port in the second memory space.

[0129] Optionally, the preset memory capacity corresponding to each downstream port in the switch may be different, and this is not limited in this embodiment.

[0130] Among them, whether each downstream port supports the hot plug function is also pre-configured in the firmware of the switch.

[0131] Exemplarily, referring to Figure 3 shown, Figure 3 is a schematic diagram of a preset bus link including a switch provided by an embodiment of the present application. As Figure 3 shown, the figure includes a switch 1. The switch 1 is connected to the switch firmware through a serial peripheral interface, and the preset memory address allocation policy is stored in the firmware. The switch 1 has 4 downstream ports, namely DP0, DP1, DP2, and DP3. DP is the downstream port (Downstream Port). The preset memory allocation policy stored in the firmware of the switch 1 includes the memory addresses corresponding to the preset memory capacity that needs to be allocated for each downstream port and the configuration of the hot plug function of each downstream port. Among them, DP0 is allocated 16 megabytes and the hot plug is enabled; DP1 is allocated 8 megabytes and the hot plug is enabled; DP2 is allocated 32 megabytes and the hot plug is enabled; DP3 is allocated 0 megabytes and the hot plug is disabled. DP0 is connected to the hardware component 1 through the physical slot 1, and the hardware component 1 supports memory address expansion. DP1 is connected to the hardware component 2 through the physical slot 2, and the hardware component 2 does not support memory address expansion. DP2 is connected to the hardware component 3 through the physical slot 3, and the hardware component 3 does not support memory address expansion. The physical slot 0 under DP3 is not connected to a hardware component. Therefore, the basic input / output system can, according to the read preset memory allocation policy, allocate a 16-megabyte memory address for DP0 in the second memory space, allocate an 8-megabyte memory address for DP1 in the first memory space, allocate a 32-megabyte memory address for DP2 in the first memory space, and allocate a 0-megabyte memory address for DP3 in the first memory space.

[0132] It can be understood that the arrow above the switch 1 is used to indicate that the upstream port of the switch can be connected to the hardware component through a high-speed serial expansion bus. The hot-plug function of the upstream port of the switch 1 is enabled.

[0133] Among them, the hot-plug function on the switch 1 does not require basic input / output system settings and is managed by the switch 1 firmware.

[0134] It can be understood that the hardware component supporting memory expansion means that the hardware component supports both the first address bus width and the second address bus width. The hardware component not supporting memory expansion means that the hardware component only supports the first address bus width.

[0135] Among them, the serial peripheral interface is a synchronous serial bus for firmware to communicate with the switch. The physical slot is a physical interface for installing the hardware component.

[0136] Exemplarily, refer to Figure 4 as shown Figure 4 This is a schematic diagram of a preset bus link including a switch provided by another embodiment of the present application. As Figure 4As shown in the figure, the figure contains 3 switches, namely switch a, switch b, and switch N. The switches are connected through the Serial Peripheral Interface and switch firmware, and a preset memory address allocation policy is stored in the firmware. Switch a has 4 downstream ports, namely DP4, DP5, DP6, and DP7, where DP stands for Downstream Port. Switch b has 4 downstream ports, namely DP10, DP11, DP12, and DP13. Switch N has 4 downstream ports, namely DP N, DP N+1, DP N+2, and DP N+3. The preset memory allocation policy stored in the switch firmware includes the memory addresses corresponding to the preset memory capacities to be allocated for each downstream port and the configuration of the hot-plug function for each downstream port. Among them, for DP4 of switch a, 16 megabytes are allocated, and the hot-plug is enabled; for DP5, 128 megabytes are allocated, and the hot-plug is enabled; for DP6, 32 megabytes are allocated, and the hot-plug is enabled; for DP7, 0 megabytes are allocated, and the hot-plug is disabled. DP4 is connected to hardware component 11 through physical slot 11, and hardware component 11 supports memory address expansion. DP6 is connected to hardware component 12 through physical slot 12, and hardware component 12 does not support memory address expansion. The physical slot 13 under DP7 is not connected to any hardware component. DP5 is connected to switch b, and switch b has 4 downstream ports, namely DP10, DP11, DP12, and DP13. For DP10 of switch b, 16 megabytes are allocated, and the hot-plug is enabled; for DP11, 32 megabytes are allocated, and the hot-plug is enabled; for DP12, 0 megabytes are allocated, and the hot-plug is disabled; for DP13, 80 megabytes are allocated, and the hot-plug is enabled. DP10 is connected to hardware component 21 through physical slot 21, and hardware component 21 does not support memory address expansion. DP11 is connected to hardware component 22 through physical slot 22, and hardware component 12 does not support memory address expansion. The physical slot 23 under DP12 is not connected to any hardware component. DP13 is connected to switch N, and switch N has 4 downstream ports, namely DP N, DP N+1, DP N+2, and DP N+3. For DP N of switch N, 0 megabytes are allocated, and the hot-plug is disabled; for DP N+1, 32 megabytes are allocated, and the hot-plug is enabled; for DP N+2, 48 megabytes are allocated, and the hot-plug is enabled; for DP N+3, 0 megabytes are allocated, and the hot-plug is disabled. There are no hardware components connected under DP N and DP N+3. DP N+1 is connected to hardware component N+1, and DP N+2 is connected to hardware component N+2. Therefore, the Basic Input / Output System can respectively read the preset memory allocation policies corresponding to switch a, switch b, and switch N. For switch a, it allocates a memory address of 16 megabytes for DP4 in the second memory space, a memory address of 128 megabytes for DP5 in the first memory space, a memory address of 32 megabytes for DP6 in the second memory space, and does not reserve a memory address for DP7.For switch b, allocate 16 megabytes of memory addresses for DP10 in the first memory space, allocate 32 megabytes of memory addresses for DP11 in the first memory space, do not reserve memory addresses for DP12, and allocate 80 megabytes of memory addresses for DP13 in the first memory space. For switch N, do not reserve memory addresses for DP N, allocate 32 megabytes of memory addresses for DP N+1 in the first memory space, do not reserve memory addresses for DP N+3, and allocate 48 megabytes of memory addresses for DP N+2 in the first memory space.

[0137] It can be understood that the downstream interface of switch N can also be connected to other switches for expansion.

[0138] Among them, the dotted line indicates whether the corresponding hardware component supports memory address expansion.

[0139] It can be understood that the arrow above switch a is used to indicate that the upstream port of the switch can be connected to a hardware component. The hot-swap function of the upstream port of switch a is enabled.

[0140] Specifically, the basic input / output system identifies the port characteristics of each downstream port in the switch through the memory type flag bit, and reads the preset memory capacity corresponding to each downstream port in the switch from the preset policy, so as to achieve precise allocation of memory addresses. By allocating memory addresses according to port capabilities, the performance of each port can be maximized.

[0141] As an alternative implementation, based on any of the above embodiments, the processor is further configured to:

[0142] Enable the hot-swap function of the bridge device corresponding to the fourth link; the fourth link is the preset bus link where the switch is located.

[0143] Among them, the switch also includes an upstream port. The upstream port is a connection port facing the system core. The system core can be (such as the CPU root port or the upper-level Switch). Connect to the root port (Root Port) of the CPU or the downstream port of the upper-level Switch.

[0144] Among them, the bridge device corresponding to the fourth link can be the processor root port or the upstream port of the switch.

[0145] Specifically, in this embodiment, the basic input / output system reads the hot-swap control register in the configuration space of the bridge device corresponding to the fourth link, and enables the hot-swap enable bit in the hot-swap register, thereby enabling the hot-swap function of the bridge device corresponding to the fourth link.

[0146] Specifically, by enabling the hot-plug function of the fourth link, the hot-plug capability of the fourth link is ensured. After enabling the hot-plug function of the bridge device corresponding to the fourth link, the system can dynamically adjust the memory resource allocation policy when a hardware component is inserted, avoiding the situation where a new device cannot be recognized or the existing device operates abnormally due to resource conflicts.

[0147] Reference Figure 5 , Figure 5 is the hardware architecture diagram of the memory management system provided by another embodiment of the present application. As Figure 5 shown, as an alternative implementation, based on any of the above embodiments, the system further includes a client device; the client device includes an operation interface;

[0148] The client device is used to obtain the preset operation parameter information configured by the user through the operation interface and save it in the preset database;

[0149] The processor is used to, after hardware initialization through the basic input / output system, read the preset operation parameter information from the preset database and determine whether to reallocate the memory address result already allocated during the hardware initialization process based on the preset operation parameter information;

[0150] If it is determined not to reallocate the memory address result already allocated during the hardware initialization process, then maintain the memory address result already allocated during the hardware initialization process;

[0151] If it is determined to reallocate the memory address result already allocated during the hardware initialization process, then reallocate the memory address result already allocated during the hardware initialization process based on the preset reallocation policy.

[0152] Among them, the preset operation parameter information is used to guide the kernel to start and enter the operating system.

[0153] Among them, the operation interface can be a GRand Unified Bootloader (GRUB) interface.

[0154] Among them, the GRand Unified Bootloader is responsible for loading the operating system kernel into memory and passing necessary startup parameters when the system starts.

[0155] Among them, as Figure 5 shown, the client device can be connected to the processor through an interface, and the processor is connected to the hardware components through a high-speed serial expansion bus.

[0156] Specifically, in this embodiment, the user can modify the parameters in the preset operating parameter information on the operation interface. After the user finishes the modification, the preset operating parameter information modified by the user is saved in the preset database. When the processor enters the operating system, it reads the preset operating parameter information in the preset database, parses the preset operating parameter information, and determines whether to reallocate the memory address result already allocated during the hardware initialization process according to the parsing result of the preset operating parameter information. If it is determined not to reallocate the memory address result already allocated during the hardware initialization process, the processor maintains the memory address result already allocated during the hardware initialization process through the operating system. If it is determined to reallocate the memory address result already allocated during the hardware initialization process, the processor reallocates the memory address result already allocated during the hardware initialization process through the operating system based on the preset reallocation policy.

[0157] Among them, after the processor allocates memory during the hardware initialization process through the basic input / output system, the basic input / output system stores the memory address result already allocated during the hardware initialization process in the Advanced Configuration and Power Interface (ACPI) table of the hardware configuration and power management.

[0158] It can be understood that if the processor does not reallocate the memory address result already allocated during the hardware initialization process, it can read the Advanced Configuration and Power Interface table of the hardware configuration and power management to obtain the memory address result already allocated during the hardware initialization process.

[0159] Specifically, the user can modify the preset operating parameter information through the operation interface according to the actual situation, so as to control whether to reallocate the memory addresses of each hardware component, thereby improving the user experience.

[0160] As an alternative embodiment, based on any of the above embodiments, when the processor determines whether to reallocate the memory address result already allocated during the hardware initialization process based on the preset operating parameter information, it is specifically used for:

[0161] Determine whether the preset operating parameter information includes a target parameter, where the target parameter is a parameter used to indicate reallocation;

[0162] If the preset operating parameter information includes the target parameter, it is determined to reallocate the memory address result already allocated during the hardware initialization process;

[0163] If the preset operating parameter information does not include the target parameter, it is determined not to reallocate the memory address result already allocated during the hardware initialization process.

[0164] Among them, the target parameter is used to indicate whether the processor performs reallocation.

[0165] Optionally, the target parameter can be set independently by the user, which is not limited in this embodiment.

[0166] Specifically, in this embodiment, the processor reads the preset operation parameter information and determines whether the target parameter is included in the preset operation parameter information. If the target parameter is included, the processor determines to reallocate the memory address result already allocated during the hardware initialization process. If the target parameter is not included, the processor determines not to reallocate the memory address result already allocated during the hardware initialization process.

[0167] Specifically, by determining whether the target parameter is included in the preset operation parameter information, the processor can quickly and accurately decide whether to reallocate the memory address, simplifying system management.

[0168] As an alternative implementation manner, based on any of the above embodiments, when the processor reallocates the memory address result already allocated during the hardware initialization process based on the preset reallocation policy, it is specifically used for:

[0169] Read the initial resource configuration information to obtain the memory address result already allocated by the processor during the hardware initialization process;

[0170] Traverse the hardware components in sequence. If it is determined that a switch is not included in any of the preset bus links, determine whether the hot-plug function of the bridge device in any of the preset bus links is enabled;

[0171] If the hot-plug function of the bridge device in the preset bus link is enabled, determine whether any of the hardware components connected under the bridge device is a first hardware component or a second hardware component;

[0172] If it is determined that any of the hardware components is a first hardware component or a second hardware component, maintain the memory address allocation result for the first hardware component or the second hardware component during the hardware initialization process.

[0173] Among them, the initial resource configuration information includes the hardware component information of each hardware component by the processor during the hardware initialization stage through the basic input / output system, as well as the memory allocation and hot-plug function setting results for each hardware component. The open standard table for hardware configuration and power management includes the initial resource configuration information.

[0174] Specifically, in this embodiment, the processor reads the initial resource configuration information through the operating system, and can obtain the topology structure on the preset bus. The operating system traverses the hardware components, and determines whether a switch is included in any preset bus link through the initial resource configuration information. If it is determined that no switch is included in any preset bus link, the configuration space of the bridge device in any preset bus link without a switch is read, and whether the hot-plug function of the bridge device is enabled is determined according to the hot-plug flag bit in the configuration space. If the hot-plug function of the bridge device in the preset bus link is enabled, it is determined whether any hardware component connected under the bridge device is a first hardware component or a second hardware component according to the first preset configuration information. If it is determined that any hardware component is a first hardware component or a second hardware component, memory reallocation is not performed on the first hardware component or the second hardware component, and the memory address allocation result for the first hardware component or the second hardware component during the hardware initialization process is maintained.

[0175] Optionally, if the hot-plug function of the bridge device in the preset bus link is disabled, it is read whether a terminal device is connected under the bridge device. If a terminal device is connected, the memory type flag bit in the base address register of the configuration space of the terminal device is read, and the address bus width supported by the terminal device is determined through the memory type flag bit. If the address bus width supported by the terminal device is the first address bus width, a memory address is allocated for the terminal device in the first memory space. If the address bus width supported by the terminal device is the second address bus width, a memory address is allocated for the terminal device in the second memory space.

[0176] Specifically, since the first hardware component is a preset hardware component and is a component that needs to ensure that a memory address is allocated, the second hardware component is a component with address expansion capabilities and has sufficient memory space. The hot-plug function allows hardware components to be inserted or removed during system operation without affecting the normal operation of the system. Therefore, in the case where it is determined that no switch is included in any preset bus link, if the hot-plug function of the bridge device is enabled, it is determined whether any hardware component connected under the bridge device is a first hardware component or a second hardware component. If it is determined that any hardware component is a first hardware component or a second hardware component, the memory address allocation result for the first hardware component or the second hardware component during the hardware initialization process is maintained, thereby ensuring the stable operation of the first hardware component or the second hardware component and further improving the stability of the system.

[0177] As an alternative implementation manner, based on any of the above embodiments, when the processor reallocates the memory address results already allocated during the hardware initialization process based on a preset reallocation strategy, it is further used for:

[0178] If it is determined that at least one switch is included in any preset bus link, it is determined whether the hot-plug function of the at least one switch is enabled;

[0179] If all are enabled, maintain the memory address allocation result for at least one switch in the preset bus link during the hardware initialization process;

[0180] If not all are enabled, obtain the hardware component information corresponding to at least one switch with the hot plug function disabled, and re-allocate the memory address for at least one switch with the hot plug function disabled based on the hardware component information corresponding to at least one switch with the hot plug function disabled.

[0181] Specifically, in this embodiment, the processor reads the initial resource configuration information through the operating system, can obtain the topology structure on the high-speed serial expansion bus. The operating system traverses the hardware components, and determines whether a switch is included in any preset bus link through the initial resource configuration information. If it is determined that a switch is included in any preset bus link, the configuration space of each switch is read, and whether the hot plug function of each switch is enabled is determined according to the hot plug flag bit in the configuration space. If the hot plug functions of at least one switch connected in any preset bus link are all enabled, maintain the memory address allocation result for at least one switch in the preset bus link during the hardware initialization process. If the hot plug functions of at least one switch connected in any preset bus link are not all enabled, read the hardware component information corresponding to the switch with the hot plug function disabled, and the operating system re-allocates the memory address for the switch with the hot plug function disabled.

[0182] It can be understood that the operating system allocates the memory address for each hardware component according to the actual requirements of the switch with the hot plug function disabled and the hardware components connected under the switch.

[0183] Specifically, if it is determined that at least one switch is included in any preset bus link, by determining whether the hot plug functions of at least one switch are all enabled, the dynamic change ability of the entire preset bus link can be evaluated. If all are enabled, it means that the preset bus link is dynamically variable. Therefore, maintaining the memory address allocation result for at least one switch in the preset bus link during the hardware initialization process can avoid system anomalies caused by frequent memory address re-allocation. If not all are enabled, it means that there are static or less dynamically changing parts in the preset bus link. For this part, re-allocating the memory address can more accurately match the actual requirements of the hardware components and optimize the memory usage efficiency.

[0184] As an optional implementation manner, based on any of the above embodiments, when the processor re-allocates the memory address for at least one switch with the hot plug function disabled based on the hardware component information corresponding to at least one switch with the hot plug function disabled, it is specifically used for:

[0185] Determine whether the downstream port of a switch with hot plug function turned off is connected to a terminal device;

[0186] If it is connected to a terminal device, determine the address bus width supported by the terminal device based on the hardware component information of the terminal device;

[0187] If the address bus width supported by the terminal device is the first address bus width, allocate a memory address for the terminal device in the first memory space;

[0188] If the address bus width supported by the terminal device is the second address bus width, allocate a memory address for the terminal device in the second memory space.

[0189] Wherein, the terminal device is a terminal node in a high-speed serial expansion bus topology.

[0190] Specifically, in this embodiment, the processor reads the configuration space of the switch with hot plug function turned off through the operating system to determine whether the downstream port included in the switch is connected to a terminal device. If it is connected to a terminal device, read the memory type flag bit in the base address register of the configuration space of the terminal device, and determine the address bus width supported by the terminal device through the memory type flag bit. If the address bus width supported by the terminal device is the first address bus width, allocate a memory address for the terminal device in the first memory space. If the address bus width supported by the terminal device is the second address bus width, allocate a memory address for the terminal device in the second memory space.

[0191] Specifically, by determining whether the downstream port of the switch with hot plug function turned off is connected to a terminal device, it can be determined whether memory addresses need to be allocated. If it is connected to a terminal device, then by determining the memory address bus supported by the terminal device, allocate a memory address for the terminal device in the corresponding memory space, so that the system can accurately match the actual requirements of the hardware components and optimize the memory usage efficiency.

[0192] Figure 6 It is a schematic flow chart of a memory management method provided by an embodiment of the present application, as Figure 6 shown. This embodiment provides a memory management method, and the method includes:

[0193] S701: During the process of hardware initialization through the basic input / output system, read the hardware component information of each hardware component.

[0194] Specifically, the processor runs the basic input / output system, and the basic input / output system enumerates each hardware component, reads the configuration space of each hardware component, and obtains the hardware component information of each hardware component.

[0195] S702: When it is determined based on the information of each hardware component that a switch is not included in any preset bus link, determine the memory space corresponding to each hardware component based on the information of each hardware component and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space and the second hardware component allocates a memory address in the second memory space.

[0196] Among them, the preset bus is a high-speed serial expansion bus. The preset bus link is a Peripheral Component Interconnect Express (PCIe) link. Among them, the first memory space is a memory space that supports the first address bus width, and the second memory space is a memory space that supports the second address bus width.

[0197] Specifically, the basic input / output system determines whether a hardware component is a switch by reading the information of the hardware component. When it is determined that a switch is not included in any preset bus link, read the memory type flag bits of the base address registers in each hardware component, and determine the address bus width supported by each hardware component through the memory type flag bits, and allocate memory addresses for the first hardware component and the second hardware component in the corresponding memory spaces respectively.

[0198] Figure 7 It is a flowchart of the memory management method provided by another embodiment of the present application, as Figure 7 shown. This embodiment provides a memory management method, which is applied in the process of hardware initialization by the processor through the basic input / output system. The method includes:

[0199] S801: During the hardware initialization process, the basic input / output system reads the hardware component information of each hardware component, and confirms whether a switch is included in any preset bus link according to the hardware component identification information of each hardware component.

[0200] S802: If a switch is not included in any preset bus link, read the hardware component identification information of each hardware component and use the first preset configuration information to determine whether any hardware component is a preset hardware component.

[0201] S803: If any hardware component is determined to be a preset hardware component, allocate a memory address for the preset hardware component in the first memory space, and reserve a memory address of the first preset size in the first memory space for the preset hardware component that needs to reserve a memory address.

[0202] S804: Turn on the hot plug function of the bridge device corresponding to the first link.

[0203] S805: If any hardware component is a non - preset hardware component, determine whether any hardware component is a second hardware component.

[0204] Wherein, the second hardware component is a component that supports address bus expansion and supports the first address bus width and the second address bus width.

[0205] S806: If it is determined that any hardware component is a second hardware component, allocate a memory address for the second hardware component in the second memory space.

[0206] S807: If it is determined that any hardware component is a non - preset hardware component and only supports the first address bus width, determine that any hardware component is a third hardware component, and allocate a memory address for the third hardware component in the first memory space.

[0207] S808: If it is determined that any hardware component is a bridge device and there is no hardware component connected under the bridge device, determine that any hardware component is a fourth hardware component.

[0208] S809, Determine whether the fourth hardware component needs to reserve a memory address based on the second preset configuration information.

[0209] S810: If it is determined that the fourth hardware component needs to reserve a memory address, reserve a memory area of the second preset size for the fourth hardware component in the first memory space, and turn on the hot - plug function of the fourth hardware component.

[0210] S811: If it is determined that the fourth hardware component does not need to reserve a memory address, turn off the hot - plug function of the fourth hardware component.

[0211] S812: If any preset bus link includes a switch, read the preset memory address allocation policy from the switch firmware.

[0212] S813: Obtain the address bus width supported by each downstream port in the switch.

[0213] S814: If the downstream port supports the first address bus width, allocate a memory address with the corresponding preset memory capacity for the downstream port in the first memory space based on the preset memory address allocation policy.

[0214] S815: If the downstream port supports the second address bus width, allocate a memory address with the corresponding preset memory capacity for the downstream port in the second memory space based on the preset memory address allocation policy.

[0215] S816: Turn on the hot - plug function of the bridge device corresponding to the fourth link.

[0216] Among them, during the hardware initialization process, if the bridge device corresponding to any preset bus link has not been fully traversed, continue to traverse the bridge device corresponding to any preset bus link until the bridge device corresponding to any preset bus link has been fully traversed, and then the processor runs the operating system.

[0217] Figure 8 A flowchart of a memory management method provided by another embodiment of the present application is shown in Figure 8 As shown. This embodiment provides a memory management method, which is applied to the process of the processor entering the operating system after hardware initialization through the basic input / output system. The method includes:

[0218] S901, obtain preset operation parameter information;

[0219] S902, determine whether to reallocate the memory address result allocated during the hardware initialization process based on the preset operation parameter information;

[0220] Among them, the operating system reads the initial resource configuration information to obtain the memory address result allocated by the processor during the hardware initialization process;

[0221] S903, if it is determined not to reallocate the memory address result allocated during the hardware initialization process, keep the memory address result allocated during the hardware initialization process.

[0222] S904, traverse the hardware components in sequence to determine whether any preset bus link includes a switch;

[0223] S905, traverse the hardware components in sequence. If it is determined that any preset bus link does not include a switch, determine whether the hot-plug function of the bridge device in any preset bus link is enabled;

[0224] S906, if it is determined that the hot-plug function of the bridge device in the preset bus link is enabled, determine whether any hardware component connected under the bridge device is a first hardware component or a second hardware component;

[0225] S907, if it is determined that any hardware component is a first hardware component or a second hardware component, keep the memory address allocation result for the first hardware component or the second hardware component during the hardware initialization process;

[0226] S908, if it is determined that any hardware component is not a first hardware component or a second hardware component, perform memory allocation according to actual requirements.

[0227] S909, if it is determined that any preset bus link includes at least one switch, determine whether the hot-plug function of the at least one switch is enabled;

[0228] S910, if all are enabled, maintain the memory address allocation result for at least one switch in the preset bus link during the hardware initialization process;

[0229] S911, if not all are enabled, obtain the hardware component information corresponding to at least one switch with the hot plug function turned off, and determine whether the downstream port of the switch with the hot plug function turned off is connected to a terminal device;

[0230] S912, if it is connected to a terminal device, determine the address bus width supported by the terminal device based on the hardware component information of the terminal device;

[0231] S913, allocate memory addresses for the terminal device according to the address bus width supported by the terminal device.

[0232] S914, if it is not connected to a terminal device, do not perform memory address allocation.

[0233] Exemplarily, refer to Figure 9 as shown in Figure 9 is a schematic diagram of the physical link connection of the server motherboard provided by another embodiment of the present application. As Figure 9As shown in the figure, the figure contains two central processing units, namely central processing unit 0 and central processing unit 1. Under central processing unit 0, there are 4 root complexes (RCs), namely RC0, RC1, RC2, and RC3. Among them, the root complex is the starting point of the high-speed serial expansion bus standard topology, managing device enumeration and configuration. Under RC0, a switch 20 is connected through the high-speed serial expansion bus, and under the switch, terminal devices 0, terminal device 1, and terminal device 2 are connected through the high-speed serial expansion bus. Among them, the hot-swap function of RC0 is turned off. Under RC1, a disk array card is connected. Among them, the disk array card is a hardware device used to implement the redundant array of independent disks (RAID) function. Under RC3, a memory is connected. Under RC3, a switch 21 is connected, and under switch 21, terminal device 8 and switch 22 are connected. Under switch 22, terminal device 9 is connected. Switch 21 and switch 22 form a multi-level switch network with a level of 2. The hot-swap function of RC3 is turned on. On central processing unit 1, there are a universal serial bus interface, a serial advanced technology attachment interface, RC4, and RC5. Among them, the serial advanced technology attachment interface (SATA) is an industry-standard serial hardware drive interface. The universal serial bus (USB) interface is a universal, hot-swap interface standard that allows users to easily connect and disconnect external devices. Under RC4, a data processing unit is connected, and the hot-swap function of RC4 is turned off. Under RC5, there is a switch 31. Under switch 31, terminal devices 10, terminal device 11, terminal device 12, and the lower-level switch 32 of switch 31 are connected. Under switch 32, terminal devices 3, terminal device 4, and the lower-level switch 33 of switch 32 are connected. Switch 33 is connected to the lower-level switch 34, and the lower-level switch 34 is connected to terminal devices 5, terminal device 6, and terminal device 7. The hot-swap function of RC5 is turned on. The hot-swap function of switch 32 is turned on. The hot-swap function of switch 33 is turned on. The hot-swap function of switch 34 is turned on. The basic input / output system can be connected to central processing unit 0 through a low pin count bus (LPC), a serial peripheral interface (SPI), or a four-wire serial peripheral interface for data transmission. Among them, the low pin count bus is a low-bandwidth, low-pin-count bus protocol. The serial peripheral interface is a synchronous full-duplex serial communication protocol. The four-wire serial peripheral interface is a high-speed expansion interface based on the SPI protocol.

[0234] Specifically, from Figure 9As shown, assuming that the data processing unit and the memory are preset hardware components, if it is determined to reallocate the memory address results already allocated during the hardware initialization process, then each hardware component under each root union is traversed in sequence, and RC1, RC2, and RC4 can be obtained. If there is no switch included, then it is determined whether the hardware components connected under each root union are preset hardware components. Since the hardware components connected to RC1 and RC4 are preset hardware components, the memory address allocation results for the preset hardware components during the hardware initialization process are maintained. The memory of RC2 is read, and the operating system determines the actual requirements of RC2, and allocates memory resources for RC2 in the memory space corresponding to the supported address bus width. Further, it is obtained that switches are included in RC0, RC3, and RC5. First, the switch levels included in RC0, RC3, and RC5 are scanned. It is determined that a 4-level switch network is included under RC5, a 2-level switch network is included under RC3, and RC0 is a single-level switch network. After the scanning of the levels is completed, the processor, through the operating system, reallocates the memory resources of the switch networks of the scanned levels. First, it is determined whether the hot-plug function of the switches under each level is fully enabled. The hot-plug function of the 4-level switch network connected under RC5 is fully enabled, so the memory address allocation results for the preset hardware components during the hardware initialization process are maintained. The hot-plug function of RC0 is turned off, and the hot-plug function of switch 20 is turned off, but there are 3 terminal devices connected under switch 20. Therefore, the memory addresses of switch 20 and terminal devices 0, 1, and 2 are reallocated. If there is a reserved memory range, the excess memory range is released after the memory addresses are allocated for the terminal devices. The hot-plug function of switch 21 connected under RC1 is turned off, but there is 1 terminal device connected under switch 21. Therefore, the memory address of terminal device 8 of switch 21 is reallocated, and it is determined whether there is a lower-level switch connected. Since there is a lower-level switch 22 connected, it is determined whether the hot-plug function of the lower-level switch 22 is enabled. Since the hot-plug function of the lower-level switch 22 is turned off, it is determined whether there is a terminal device connected under switch 22. Since there is a terminal device 9 connected under switch 22, the memory address of terminal device 9 of switch 22 is reallocated. Among them, the double-headed arrow indicates that communication and data transmission can be carried out bidirectionally.

[0235] Among them, during the allocation process, the memory size of the first allocated memory space is calculated. If the memory of the first memory space has been fully allocated, then the memory address allocation of the switches and the connected hardware components in the subsequent levels in the first memory space is abandoned.

[0236] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0237] Figure 10 FIG. is a schematic structural diagram of a memory management device provided by an embodiment of the present application. As Figure 10 shown, the execution subject of the above memory management method is a memory management device, and the memory management device can be implemented by a computer program; it can also be implemented by a medium storing relevant computer programs, such as a USB flash drive and / or an optical disc, etc., or it can also be implemented by an entity device integrated or installed with relevant computer programs, such as an electronic device, etc. The electronic device can be a computer or a server, etc. If the memory management device provided in this embodiment is located in an electronic device, then the memory management device 50 provided in this embodiment includes: a reading module 51 and a determining module 52.

[0238] Specifically, the reading module 51 is configured to read the hardware component information of each hardware component during the process of hardware initialization through the basic input / output system; the determining module 52 is configured to, when it is determined that a switch is not included in any preset bus link based on the hardware component information, determine the memory space corresponding to each hardware component based on the hardware component information and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address in the first memory space, and the second hardware component allocates a memory address in the second memory space; the first memory space is a memory space supporting the first address bus width, and the second memory space is a memory space supporting the second address bus width.

[0239] For the description of the features in the embodiments corresponding to the memory management device, reference can be made to the relevant descriptions in the embodiments corresponding to the memory management method, which will not be elaborated here one by one.

[0240] Figure 11 FIG. is a schematic structural diagram of an electronic device provided by an embodiment of the present application. As Figure 11 shown, the electronic device 60 provided in the embodiment of the present application includes: a memory 62 and a processor 61.

[0241] The memory 62 stores a computer program, and the processor 61 is configured to run the computer program to execute the steps in any of the above embodiments of the memory management method.

[0242] For the specific implementation process of the processor 61, reference can be made to the above method embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0243] In the above embodiments, it should be understood that the processor is a Central Processing Unit (CPU for short). The steps of the method disclosed in combination with the application can be directly embodied as being executed by a hardware processor, or executed by a combination of hardware and software modules in the processor.

[0244] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.

[0245] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, the bus in the drawings of this application is not limited to only one bus or one type of bus.

[0246] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored. Among them, the computer program is set to execute the steps in any of the above embodiments of the memory management method when running.

[0247] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (Read-Only Memory, abbreviated as ROM), random access memories (Random Access Memory, abbreviated as RAM), mobile hard disks, magnetic disks, or optical discs, etc., various media that can store computer programs.

[0248] The embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the memory management method.

[0249] The embodiments of the present application also provide another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it implements the steps in any of the above embodiments of the memory management method.

[0250] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered as exceeding the scope of this application.

[0251] The above has introduced in detail a memory management method provided by this application. Specific examples are used herein to elaborate on the principle and implementation manner of this application. The description of the above embodiments is only used to help understand the method and its core idea of this application. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of this application, several improvements and modifications can be made to this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A memory management system, characterized in that, The system includes a processor and multiple hardware components; the processor is connected to each of the hardware components through a preset bus; among the hardware components, there are a first hardware component and a second hardware component; The processor is configured to, during the process of initializing the hardware through the basic input / output system, read the hardware component information of each of the hardware components; and when it is determined based on the hardware component information that a switch is not included in any preset bus link, determine the memory space corresponding to each of the hardware components based on the hardware component information and the address bus width supported by each of the hardware components, so that the first hardware component allocates a memory address within the first memory space, and the second hardware component allocates a memory address within the second memory space, where the first memory space is a memory space supporting the first address bus width, and the second memory space is a memory space supporting the second address bus width.

2. The memory management system according to claim 1, characterized in that When the processor determines the memory space corresponding to each of the hardware components based on the hardware component information and the address bus width supported by each of the hardware components, so that the first hardware component allocates a memory address within the first memory space, and the second hardware component allocates a memory address within the second memory space, it is specifically configured to: If it is determined based on the hardware component information that any one of the hardware components is a preset hardware component, then determine that any one of the hardware components is the first hardware component, and the memory space for allocating the memory address for the first hardware component is the first memory space; the preset hardware component only supports the first address bus width; If it is determined based on the hardware component information that any one of the hardware components is a component capable of address bus width expansion and supports both the first address bus width and the second address bus width, then determine that any one of the hardware components is the second hardware component, and the memory space for allocating the memory address for the second hardware component is the second memory space.

3. The memory management system according to claim 2, wherein The hardware component information includes hardware component identification information; When the processor determines that any one of the hardware components is a preset hardware component based on the hardware component information, it is specifically configured to: Obtain first preset configuration information; the first preset configuration information includes preset hardware component identification information; Compare the hardware component identification information of each of the hardware components with the first preset configuration information respectively; If the first preset configuration information includes the hardware component identification information identical to that of the hardware component, then determine the hardware component corresponding to the identical hardware component identification information as the preset hardware component.

4. The memory management system according to claim 2, wherein The processor is further configured to: If it is determined based on the hardware component information that any one of the hardware components is not the preset hardware component and only supports the first address bus width, then determine that any one of the hardware components is the third hardware component, and the memory space for allocating the memory address for the third hardware component is the first memory space.

5. The memory management system according to claim 3, wherein The hardware components are distributed in different preset bus links; the preset bus link is a channel for data transmission in the preset bus; The first preset configuration information further includes the mapping relationship between the preset hardware component identification information and the preset address reservation information; the preset address reservation information is used to indicate whether the preset hardware component needs to reserve a memory address; The processor is further configured to: Determine whether the preset hardware component needs to reserve a memory address based on the first preset configuration information; If it is determined that the preset hardware component needs to reserve a memory address, reserve a memory area of a first preset size for the preset hardware component in the first memory space; Enable the hot pluggable function of the bridge device corresponding to the first link; The first link is the preset bus link where the preset hardware component that needs to reserve a memory address is located; The bridge device is used to manage the preset bus link.

6. The memory management system according to claim 1, wherein The processor is further configured to: If it is determined that the hardware component is the second hardware component, enable the hot pluggable function of the bridge device corresponding to the second link; the second link is the preset bus link where the second hardware component is located.

7. The memory management system according to claim 4, wherein The processor is further configured to: If it is determined that the hardware component is the third hardware component, disable the hot pluggable function of the bridge device corresponding to the third link; the third link is the preset bus link where the third hardware component is located.

8. The memory management system according to claim 2, wherein The processor is further configured to: If it is determined based on each hardware component information that any one of the hardware components is a bridge device and no hardware component is connected under the bridge device, determine that any one of the hardware components is a fourth hardware component; Determine whether the fourth hardware component needs to reserve a memory address based on the second preset configuration information; If it is determined that the fourth hardware component needs to reserve a memory address, reserve a memory area of a second preset size for the fourth hardware component in the first memory space, and enable the hot pluggable function of the fourth hardware component.

9. The memory management system according to claim 1, wherein The processor is further configured to: If it is determined based on each hardware component information that a switch is included in any one of the preset bus links, read a preset memory address allocation policy from the switch firmware, and allocate a memory address for the switch based on the preset memory address allocation policy.

10. The memory management system according to claim 9, wherein A plurality of downstream ports are included on the switch; the preset memory address allocation policy includes the preset memory capacity corresponding to each of the downstream ports on the switch; When the processor allocates a memory address for the switch based on the preset memory address allocation policy, specifically: Determine the address bus width supported by each of the downstream ports in the switch; If the downstream port supports the first address bus width, allocate a memory address of a corresponding preset memory capacity for the downstream port in the first memory space based on the preset memory address allocation policy; If the downstream port supports the second address bus width, allocate a memory address of a corresponding preset memory capacity for the downstream port in the second memory space based on the preset memory address allocation policy.

11. The memory management system according to claim 10, characterized in that, The processor is further configured to: Enable the hot pluggable function of the bridge device corresponding to the fourth link; the fourth link is the preset bus link where the switch is located.

12. The memory management system according to claim 2, wherein The system further includes a client device; the client device includes an operation interface; The client device is configured to obtain preset operation parameter information configured by a user through the operation interface and store the information in a preset database; The processor is configured to, after performing hardware initialization through the basic input / output system, read the preset operation parameter information from the preset database and determine whether to reallocate the memory address result allocated during the hardware initialization process based on the preset operation parameter information; If it is determined not to reallocate the memory address result allocated during the hardware initialization process, the memory address result allocated during the hardware initialization process is maintained; If it is determined to reallocate the memory address result allocated during the hardware initialization process, the memory address result allocated during the hardware initialization process is reallocated based on a preset reallocation policy.

13. The memory management system according to claim 12, characterized in that, When determining whether to reallocate the memory address result allocated during the hardware initialization process based on the preset operation parameter information, the processor is specifically configured to: Determine whether the preset operation parameter information includes a target parameter, where the target parameter is a parameter used to indicate reallocation; If the preset operation parameter information includes the target parameter, it is determined to reallocate the memory address result allocated during the hardware initialization process; If the preset operation parameter information does not include the target parameter, it is determined not to reallocate the memory address result allocated during the hardware initialization process.

14. The memory management system according to claim 12, wherein When reallocating the memory address result allocated during the hardware initialization process based on the preset reallocation policy, the processor is specifically configured to: Read initial resource configuration information to obtain the memory address result allocated by the processor during the hardware initialization process; Traverse the hardware components in sequence. If it is determined that any of the preset bus links does not include the switch, determine whether the hot plug function of the bridge device in any of the preset bus links is enabled; If the hot plug function of the bridge device in the preset bus link is enabled, determine whether any of the hardware components connected under the bridge device is the first hardware component or the second hardware component; If it is determined that any of the hardware components is the first hardware component or the second hardware component, maintain the memory address allocation result for the first hardware component or the second hardware component during the hardware initialization process.

15. The memory management system according to claim 14, wherein When reallocating the memory address result allocated during the hardware initialization process based on the preset reallocation policy, the processor is further configured to: If it is determined that any of the preset bus links includes at least one switch, determine whether the hot plug function of at least one switch is enabled; If all are enabled, maintain the memory address allocation result for at least one switch in the preset bus link during the hardware initialization process; If not all are enabled, obtain the hardware component information corresponding to at least one of the switches with the hot-plug function turned off, and re-allocate memory addresses for at least one of the switches with the hot-plug function turned off based on the hardware component information corresponding to at least one of the switches with the hot-plug function turned off.

16. The memory management system according to claim 15, characterized in that, When re-allocating memory addresses for at least one of the switches with the hot-plug function turned off based on the hardware component information corresponding to at least one of the switches with the hot-plug function turned off, the processor is specifically configured to: Determine whether the downstream port of the switch with the hot-plug function turned off is connected to a terminal device; If it is connected to the terminal device, determine the address bus width supported by the terminal device based on the hardware component information of the terminal device; If the address bus width supported by the terminal device is the first address bus width, allocate a memory address for the terminal device within the first memory space; If the address bus width supported by the terminal device is the second address bus width, allocate a memory address for the terminal device within the second memory space.

17. A memory management method, characterized in that, Includes: During the process of hardware initialization through the basic input / output system, read the hardware component information of each hardware component; And when it is determined that any preset bus link does not include a switch based on the hardware component information of each hardware component, determine the memory space corresponding to each hardware component based on the hardware component information of each hardware component and the address bus width supported by each hardware component, so that the first hardware component allocates a memory address within the first memory space, and the second hardware component allocates a memory address within the second memory space. The first memory space is a memory space that supports the first address bus width, and the second memory space is a memory space that supports the second address bus width.

18. An electronic device, characterized in that, Includes: A memory for storing a computer program; A processor for implementing the steps of the memory management method as described in claim 17 when executing the computer program.

19. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, it implements the steps of the memory management method as described in claim 17.

20. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the memory management method as described in claim 17.

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